OSDN Git Service
David Green [Fri, 28 Jun 2019 11:17:38 +0000 (11:17 +0000)]
[ARM] Mark math routines as non-legal for MVE
This adds handling and tests for a number of floating point math routines,
which have no MVE instructions.
Differential Revision: https://reviews.llvm.org/D63725
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364641
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David Green [Fri, 28 Jun 2019 10:25:35 +0000 (10:25 +0000)]
[ARM] MVE patterns for VABS and VNEG
This simply adds the required patterns for fp neg and abs.
Differential Revision: https://reviews.llvm.org/D63861
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364640
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Fangrui Song [Fri, 28 Jun 2019 10:10:10 +0000 (10:10 +0000)]
[DebugInfo] Fix setStartAddress after r364637
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364638
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Fangrui Song [Fri, 28 Jun 2019 10:06:11 +0000 (10:06 +0000)]
[DebugInfo] Simplify GSYM::AddressRange and GSYM::AddressRanges
Delete unnecessary getters of AddressRange.
Simplify AddressRange::size(): Start <= End check should be checked in an upper layer.
Delete isContiguousWith() that doesn't make sense.
Simplify AddressRanges::insert. Delete commented code. Fix it when more than 1 ranges are to be deleted.
Delete trailing newline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364637
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David Green [Fri, 28 Jun 2019 09:47:55 +0000 (09:47 +0000)]
[ARM] Widening loads and narrowing stores
MVE has instructions to widen as it loads, and narrow as it stores. This adds
the required patterns and legalisation to make them work including specifying
that they are legal, patterns to select them and test changes.
Patch by David Sherwood.
Differential Revision: https://reviews.llvm.org/D63839
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364636
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Simon Tatham [Fri, 28 Jun 2019 09:28:39 +0000 (09:28 +0000)]
[ARM] Fix integer UB in MVE load/store immediate handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364635
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Fangrui Song [Fri, 28 Jun 2019 08:58:05 +0000 (08:58 +0000)]
[DebugInfo] GSYM cleanups after D63104/r364427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364634
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David Green [Fri, 28 Jun 2019 08:41:40 +0000 (08:41 +0000)]
[ARM] MVE loads and stores
This fills in the gaps for basic MVE loads and stores, allowing unaligned
access and adding far too many tests. These will become important as
narrowing/expanding and pre/post inc are added. Big endian might still not be
handled very well, because we have not yet added bitcasts (and I'm not sure how
we want it to work yet). I've included the alignment code anyway which maps
with our current patterns. We plan to return to that later.
Code written by Simon Tatham, with additional tests from Me and Mikhail Maltsev.
Differential Revision: https://reviews.llvm.org/D63838
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364633
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Dylan McKay [Fri, 28 Jun 2019 08:35:21 +0000 (08:35 +0000)]
[AVR] Don't look for the TargetFrameLowering in the FrameLowering implementation
c.f. r364349
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364632
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David Green [Fri, 28 Jun 2019 08:18:55 +0000 (08:18 +0000)]
[ARM] Mark div and rem as expand for MVE
We don't have vector operations for these, so they need to be expanded for both
integer and float.
Differential Revision: https://reviews.llvm.org/D63595
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364631
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David Green [Fri, 28 Jun 2019 07:41:09 +0000 (07:41 +0000)]
[ARM] Select MVE fp add and sub
The same as integer arithmetic, we can add simple floating point MVE addition and
subtraction patterns.
Initial code by David Sherwood
Differential Revision: https://reviews.llvm.org/D63257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364629
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Sam Parker [Fri, 28 Jun 2019 07:38:16 +0000 (07:38 +0000)]
[HardwareLoops] Loop counter guard intrinsic
Introduce llvm.test.set.loop.iterations which sets the loop counter
and also produces an i1 after testing that the count is not zero.
Differential Revision: https://reviews.llvm.org/D63809
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364628
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David Green [Fri, 28 Jun 2019 07:21:11 +0000 (07:21 +0000)]
[ARM] Select MVE add and sub
This adds the first few patterns for MVE code generation, adding simple integer
add and sub patterns.
Initial code by David Sherwood
Differential Revision: https://reviews.llvm.org/D63255
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364627
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David Green [Fri, 28 Jun 2019 07:08:42 +0000 (07:08 +0000)]
[ARM] MVE vector shuffles
This patch adds necessary shuffle vector and buildvector support for ARM MVE.
It essentially adds support for VDUP, VREVs and some VMOVs, which are often
required by other code (like upcoming patches).
This mostly uses the same code from Neon that already generated
NEONvdup/NEONvduplane/NEONvrev's. These have been renamed to ARMvdup/etc and
moved to ARMInstrInfo as they are common to both architectures. Most of the
selection code seems to be applicable to both, but NEON does have some more
instructions making some parts specific.
Most code originally by David Sherwood.
Differential Revision: https://reviews.llvm.org/D63567
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364626
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Craig Topper [Fri, 28 Jun 2019 06:58:50 +0000 (06:58 +0000)]
[X86] Connect the output chain properly when combining vzext_movl+load into vzext_load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364625
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Mikael Holmen [Fri, 28 Jun 2019 06:45:20 +0000 (06:45 +0000)]
Silence gcc warning in testcase [NFC]
Without the fix gcc (7.4.0) complains with
../unittests/ADT/APIntTest.cpp: In member function 'virtual void {anonymous}::APIntTest_MultiplicativeInverseExaustive_Test::TestBody()':
../unittests/ADT/APIntTest.cpp:2510:36: error: comparison between signed and unsigned integer expressions [-Werror=sign-compare]
for (unsigned Value = 0; Value < (1 << BitWidth); ++Value) {
~~~~~~^~~~~~~~~~~~~~~~~
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364624
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Craig Topper [Fri, 28 Jun 2019 05:03:47 +0000 (05:03 +0000)]
[X86] Remove some duplicate patterns that already exist as part of their instruction definition. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364623
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Alex Brachet [Fri, 28 Jun 2019 04:07:13 +0000 (04:07 +0000)]
[Support] Fix add fs::getUmask() patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364622
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Alex Brachet [Fri, 28 Jun 2019 03:21:00 +0000 (03:21 +0000)]
[Support] Add fs::getUmask() function and change fs::setPermissions
Summary: This patch changes fs::setPermissions to optionally set permissions while respecting the umask. It also adds the function fs::getUmask() which returns the current umask.
Reviewers: jhenderson, rupprecht, aprantl, lhames
Reviewed By: jhenderson, rupprecht
Subscribers: sanaanajjar231288, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63583
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364621
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Zi Xuan Wu [Fri, 28 Jun 2019 02:51:03 +0000 (02:51 +0000)]
[NFC][PowerPC] Move XS*QP series instruction apart from XS*QPO series in position of td file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364620
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Stanislav Mekhanoshin [Fri, 28 Jun 2019 01:52:13 +0000 (01:52 +0000)]
[AMDGPU] Packed thread ids in function call ABI
Differential Revision: https://reviews.llvm.org/D63851
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364619
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Matt Arsenault [Fri, 28 Jun 2019 01:47:44 +0000 (01:47 +0000)]
GlobalISel: Use Register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364618
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Kai Luo [Fri, 28 Jun 2019 01:38:42 +0000 (01:38 +0000)]
[PowerPC][NFC] Use `|=` to update `Simplified` flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364617
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Matt Arsenault [Fri, 28 Jun 2019 01:16:46 +0000 (01:16 +0000)]
AMDGPU/GlobalISel: Convert to using Register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364616
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Matt Arsenault [Fri, 28 Jun 2019 01:16:41 +0000 (01:16 +0000)]
GlobalISel: Convert rest of MachineIRBuilder to using Register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364615
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Amara Emerson [Thu, 27 Jun 2019 23:56:34 +0000 (23:56 +0000)]
[GlobalISel][IRTranslator] Fix some PHI bugs related to jump tables when optimizations are used.
The new switch lowering code that tries to generate jump tables and range checks
were tested at -O0 on arm64, but on -O3 the generic switch lowering code goes to
town on trying to generate optimized lowerings, e.g. multiple jump tables, range
checks etc. This exposed bugs in the way PHI nodes are handled because the CFG
looks even stranger after all of this is done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364613
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Fedor Sergeev [Thu, 27 Jun 2019 23:41:03 +0000 (23:41 +0000)]
[InlineCost] make InlineCost assignable
Summary:
Current InlineCost is not assignable because of const members Cost and Threshold.
I dont see practical benefits from having them const (access to these members is
private and internal interactions are rather simple). On other hand that makes
it hard to use as a member in some other data structure where assignability is necessary.
I'm going to use InlineCost in a downstream inliner that maintains a complex queue
of candidate call-sites and thus keeping and recalculating InlineCost is necessary.
This patch just removes 'const' from both members, making InlineCost assignable.
Reviewers: eraman, greened, chandlerc, yrouban, apilipenko
Reviewed By: apilipenko
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63823
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364612
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Rumeet Dhindsa [Thu, 27 Jun 2019 23:37:04 +0000 (23:37 +0000)]
Fix ASAN error caused by commit r364512.
This patch intends to fix ASAN stack-use-after-scope error.
This is at least a short-term fix to unbreak LLVM's mainline.
Differential Revision: https://reviews.llvm.org/D63905
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364611
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Amara Emerson [Thu, 27 Jun 2019 23:33:05 +0000 (23:33 +0000)]
[LangRef] Clarify codegen expectations for intrinsics with fp/integer-only overloads.
This change is a result of discussions on list: "GlobalISel: Ambiguous intrinsic semantics problem"
Differential Revision: https://reviews.llvm.org/D59657
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364610
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Peter Collingbourne [Thu, 27 Jun 2019 23:24:07 +0000 (23:24 +0000)]
hwasan: Use llvm.read_register intrinsic to read the PC on aarch64 instead of taking the function's address.
This shaves an instruction (and a GOT entry in PIC code) off prologues of
functions with stack variables.
Differential Revision: https://reviews.llvm.org/D63472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364608
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Lang Hames [Thu, 27 Jun 2019 23:00:30 +0000 (23:00 +0000)]
Revert "[JITLink][MachO/x86-64] Add a testcase for X86_64_RELOC_GOT."
Reverts commit r364600 while I investigate bot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364606
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Roman Lebedev [Thu, 27 Jun 2019 21:52:10 +0000 (21:52 +0000)]
[CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 3)
Summary:
I'm submitting a new revision since i don't understand how to reclaim/reopen/take over the existing one, D50222.
There is no such action in "Add Action" menu...
This implements an optimization described in Hacker's Delight 10-17: when `C` is constant,
the result of `X % C == 0` can be computed more cheaply without actually calculating the remainder.
The motivation is discussed here: https://bugs.llvm.org/show_bug.cgi?id=35479.
This is a recommit, the original commit rL364563 was reverted in rL364568
because test-suite detected miscompile - the new comparison constant 'Q'
was being computed incorrectly (we divided by `D0` instead of `D`).
Original patch D50222 by @hermord (Dmytro Shynkevych)
Notes:
- In principle, it's possible to also handle the `X % C1 == C2` case, as discussed on bugzilla.
This seems to require an extra branch on overflow, so I refrained from implementing this for now.
- An explicit check for when the `REM` can be reduced to just its LHS is included:
the `X % C` == 0 optimization breaks `test1` in `test/CodeGen/X86/jump_sign.ll` otherwise.
I hadn't managed to find a better way to not generate worse output in this case.
- The `test/CodeGen/X86/jump_sign.ll` regresses, and is being fixed by a followup patch D63390.
Reviewers: RKSimon, craig.topper, spatel, hermord, xbolva00
Reviewed By: RKSimon, xbolva00
Subscribers: dexonsmith, kristina, xbolva00, javed.absar, llvm-commits, hermord
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364600
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Roman Lebedev [Thu, 27 Jun 2019 21:51:54 +0000 (21:51 +0000)]
[NFC][APInt] Add (exhaustive) test for multiplicativeInverse()
Else there is no direct test coverage at all.
The function should either return '0' or precise answer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364599
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Lang Hames [Thu, 27 Jun 2019 21:50:29 +0000 (21:50 +0000)]
[JITLink][MachO/x86-64] Add a testcase for X86_64_RELOC_GOT.
This is the data-section counterpart to X86_64_RELOC_GOTPCREL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364598
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Cameron McInally [Thu, 27 Jun 2019 21:23:07 +0000 (21:23 +0000)]
[NFC][GVNSink] Pre-commit unary FNeg test to fpmath.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364597
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Heejin Ahn [Thu, 27 Jun 2019 21:22:04 +0000 (21:22 +0000)]
[WebAssembly] Enable an atomic.notify MC test
Summary:
Assembly of atomic.notify has been fixed in r364576, so we can enable
it.
Reviewers: aardappel
Subscribers: dschuff, sbc100, jgravelle-google, sunfish, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63898
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364596
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Cameron McInally [Thu, 27 Jun 2019 21:05:02 +0000 (21:05 +0000)]
[GVN] Add support for unary FNeg to GVN pass
Differential Revision: https://reviews.llvm.org/D63896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364592
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Reid Kleckner [Thu, 27 Jun 2019 20:56:04 +0000 (20:56 +0000)]
[compiler-rt] Rename lit.*.cfg.* -> lit.*.cfg.py.*
These lit configuration files are really Python source code. Using the
.py file extension helps editors and tools use the correct language
mode. LLVM and Clang already use this convention for lit configuration,
this change simply applies it to all of compiler-rt.
Reviewers: vitalybuka, dberris
Differential Revision: https://reviews.llvm.org/D63658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364591
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Alexandre Ganea [Thu, 27 Jun 2019 20:46:11 +0000 (20:46 +0000)]
Convert line endings to LF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364590
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Sanjay Patel [Thu, 27 Jun 2019 20:37:12 +0000 (20:37 +0000)]
[x86] remove whitespace; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364588
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Cameron McInally [Thu, 27 Jun 2019 20:33:44 +0000 (20:33 +0000)]
[NFC][GVN] Pre-commit unary FNeg tests to fpmath.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364587
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Sanjay Patel [Thu, 27 Jun 2019 20:16:58 +0000 (20:16 +0000)]
[x86] prevent crashing from select narrowing with AVX512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364585
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Vitaly Buka [Thu, 27 Jun 2019 19:55:22 +0000 (19:55 +0000)]
[GN] Update build file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364583
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Vitaly Buka [Thu, 27 Jun 2019 19:55:21 +0000 (19:55 +0000)]
[GN] Set exit code to 1 if changes are needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364582
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Jinsong Ji [Thu, 27 Jun 2019 19:35:11 +0000 (19:35 +0000)]
[PowerPC][NFC] Remove unused (and unsupported) fusion feature bits.
FeatureFusion bits was first introduced in
https://reviews.llvm.org/rL253724. for add/load integer fusion for P8.
The only use of `hasFusion` was https://reviews.llvm.org/rL255319.
However, this was removed later in https://reviews.llvm.org/rL280440.
So, there is NO any reference to fusion in code now.
Leaving it there is misleading and confusing, so remove it for now.
We can alwasy add back if we ever support fusion in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364581
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Johannes Doerfert [Thu, 27 Jun 2019 19:29:48 +0000 (19:29 +0000)]
Use "willreturn" in isGuaranteedToTransferExecutionToSuccessor
The `willreturn` function attribute guarantees that a function call will
come back to the call site if the call is also known not to throw.
Therefore, this attribute can be used in
`isGuaranteedToTransferExecutionToSuccessor`.
Patch by Hideto Ueno (@uenoku)
Reviewers: jdoerfert, sstefan1
Reviewed By: jdoerfert
Subscribers: hiraditya, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63372
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364580
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Philip Reames [Thu, 27 Jun 2019 19:22:43 +0000 (19:22 +0000)]
Update -analyze -scalar-evolution output for multiple exit loops w/computable exit values
The previous output was next to useless if *any* exit was not computable. If we have more than one exit, show the exit count for each so that it's easier to see what's going from with SCEV analysis when debugging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364579
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Roman Lebedev [Thu, 27 Jun 2019 19:09:51 +0000 (19:09 +0000)]
[NFC][CodeGen] Add negative test for X u% C == 0 fold (D63391)
The fold (D63391) uses multiplicativeInverse(),
but it is not guaranteed to always succeed,
and '100' appears to be one of the problematic values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364578
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Michael Liao [Thu, 27 Jun 2019 19:05:46 +0000 (19:05 +0000)]
Correct the file path. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364577
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Wouter van Oortmerssen [Thu, 27 Jun 2019 18:58:26 +0000 (18:58 +0000)]
[WebAssembly] AsmParser: better atomic inst detection
Summary:
Previously missed atomic.notify.
Fixes https://bugs.llvm.org/show_bug.cgi?id=40728
Reviewers: aheejin
Subscribers: sbc100, jgravelle-google, sunfish, jfb, llvm-commits, dschuff
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63747
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364576
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Yuanfang Chen [Thu, 27 Jun 2019 18:39:34 +0000 (18:39 +0000)]
[llvm-objdump] Update the doc for --disassemble-functions.
Update the doc after llvm-svn: 364121 is landed.
With two more trivial fixes that are not related to
--disassemble-functions but still about llvm-objdump.
Reviewers: jhenderson, grimar, MaskRay, rupprecht, peter.smith
Reviewed by: jhenderson, MaskRay
Differential Revision: https://reviews.llvm.org/D63787
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364573
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Djordje Todorovic [Thu, 27 Jun 2019 18:12:04 +0000 (18:12 +0000)]
Revert "[LiveDebugValues] Emit the debug entry values"
Appears that the 'test/DebugInfo/MIR/X86/dbginfo-entryvals.mir'
does not pass on Windows.
This reverts commit rL364553.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364571
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Wouter van Oortmerssen [Thu, 27 Jun 2019 18:11:15 +0000 (18:11 +0000)]
[WebAssembly] Fix p2align in assembler.
Summary:
- Match the syntax output by InstPrinter.
- Fix it always emitting 0 for align. Had to work around fact that
opcode is not available for GetDefaultP2Align while parsing.
- Updated tests that were erroneously happy with a p2align=0
Fixes https://bugs.llvm.org/show_bug.cgi?id=40752
Reviewers: aheejin, sbc100
Subscribers: jgravelle-google, sunfish, jfb, llvm-commits, dschuff
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63633
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364570
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Simon Pilgrim [Thu, 27 Jun 2019 17:30:51 +0000 (17:30 +0000)]
[X86] combineX86ShufflesRecursively - merge shuffles with more than 2 inputs
We already had the infrastructure for this, but were waiting for the fix for a number of regressions which were handled by the recent shuffle(extract_subvector(),extract_subvector()) -> extract_subvector(shuffle()) shuffle combines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364569
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Roman Lebedev [Thu, 27 Jun 2019 17:22:31 +0000 (17:22 +0000)]
Revert "[CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 2)"
*Appears* to break test-suite on
http://lab.llvm.org:8011/builders/clang-cmake-x86_64-sde-avx512-linux/builds/23790
FAIL: burg.execution_time
FAIL: spiff.execution_time
FAIL: employ.execution_time
FAIL: llu.execution_time
FAIL: gramschmidt.execution_time
FAIL: fdtd-apml.execution_time
This reverts commit r364563.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364568
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Nicolai Haehnle [Thu, 27 Jun 2019 16:56:44 +0000 (16:56 +0000)]
AMDGPU: Make fixing i1 copies robust against re-ordering
Summary:
The new test case led to incorrect code.
Change-Id: Ief48b227e97aa662dd3535c9bafb27d4a184efca
Reviewers: arsenm, david-salinas
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63871
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364566
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David Green [Thu, 27 Jun 2019 16:56:41 +0000 (16:56 +0000)]
[ARM] Move low overhead loop codegen tests into a separate file. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364565
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Simon Pilgrim [Thu, 27 Jun 2019 16:46:00 +0000 (16:46 +0000)]
Use getConstantOperandAPInt instead of getConstantOperandVal for comparisons.
getConstantOperandAPInt avoids any large integer issues - these are unlikely but the fuzzers do like to mess around.....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364564
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Roman Lebedev [Thu, 27 Jun 2019 16:45:42 +0000 (16:45 +0000)]
[CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 2)
Summary:
I'm submitting a new revision since i don't understand how to reclaim/reopen/take over the existing one, D50222.
There is no such action in "Add Action" menu...
Original patch D50222 by @hermord (Dmytro Shynkevych)
This implements an optimization described in Hacker's Delight 10-17: when `C` is constant,
the result of `X % C == 0` can be computed more cheaply without actually calculating the remainder.
The motivation is discussed here: https://bugs.llvm.org/show_bug.cgi?id=35479.
Original patch author: @hermord (Dmytro Shynkevych)!
Notes:
- In principle, it's possible to also handle the `X % C1 == C2` case, as discussed on bugzilla.
This seems to require an extra branch on overflow, so I refrained from implementing this for now.
- An explicit check for when the `REM` can be reduced to just its LHS is included:
the `X % C` == 0 optimization breaks `test1` in `test/CodeGen/X86/jump_sign.ll` otherwise.
I hadn't managed to find a better way to not generate worse output in this case.
- The `test/CodeGen/X86/jump_sign.ll` regresses, and is being fixed by a followup patch D63390.
Reviewers: RKSimon, craig.topper, spatel, hermord, xbolva00
Reviewed By: RKSimon, xbolva00
Subscribers: xbolva00, javed.absar, llvm-commits, hermord
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364563
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Simon Pilgrim [Thu, 27 Jun 2019 16:33:44 +0000 (16:33 +0000)]
[X86] getTargetVShiftByConstNode - reduce variable scope. NFCI.
Fixes cppcheck warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364561
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Sam Tebbs [Thu, 27 Jun 2019 16:28:28 +0000 (16:28 +0000)]
[ARM] Fix formatting issue in ARMISelLowering.cpp
Fix a formatting error in ARMISelLowering.cpp::Expand64BitShift. My test
commit after receiving write access.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364560
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Chris Jackson [Thu, 27 Jun 2019 16:27:53 +0000 (16:27 +0000)]
[llvm-nm] Fix for BZ41711 - Class character for a symbol with undefined
binding does not match class assigned by GNU nm
Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=41711
Differential Revision: https://reviews.llvm.org/D63340
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364559
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Roland Froese [Thu, 27 Jun 2019 16:20:24 +0000 (16:20 +0000)]
Recommit [PowerPC] Update P9 vector costs for insert/extract element
Recommit patch D60160 after regression fix patch D63463.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364557
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Paul Robinson [Thu, 27 Jun 2019 15:53:07 +0000 (15:53 +0000)]
[debug-info] Make a couple of tests more robust.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364556
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Johannes Doerfert [Thu, 27 Jun 2019 15:51:40 +0000 (15:51 +0000)]
[Attr] Add "willreturn" function attribute
This patch introduces a new function attribute, willreturn, to indicate
that a call of this function will either exhibit undefined behavior or
comes back and continues execution at a point in the existing call stack
that includes the current invocation.
This attribute guarantees that the function does not have any endless
loops, endless recursion, or terminating functions like abort or exit.
Patch by Hideto Ueno (@uenoku)
Reviewers: jdoerfert
Subscribers: mehdi_amini, hiraditya, steven_wu, dexonsmith, lebedev.ri, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62801
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364555
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Djordje Todorovic [Thu, 27 Jun 2019 15:35:48 +0000 (15:35 +0000)]
[LiveDebugValues] Emit the debug entry values
Emit replacements for clobbered parameters location if the parameter
has unmodified value throughout the funciton. This is basic scenario
where we can use the debug entry values.
([12/13] Introduce the debug entry values.)
Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>
Differential Revision: https://reviews.llvm.org/D58042
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364553
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James Henderson [Thu, 27 Jun 2019 15:18:15 +0000 (15:18 +0000)]
[docs][llvm-nm][llvm-objdump] Improve "See Also" section
The "See Also" section for llvm-nm didn't actually contain any links,
and the tools referred to didn't make much sense (referring to non-LLVM
tools, when we have equivalents, or tools that aren't really to do with
symbol dumping). llvm-objdump's didn't refer to llvm-readelf.
Reviewed by: grimar
Differential Revision: https://reviews.llvm.org/D63875
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364552
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Tim Northover [Thu, 27 Jun 2019 14:46:51 +0000 (14:46 +0000)]
Bitcode: derive all types used from records instead of Values.
There is existing bitcode that we need to support where the structured nature
of pointer types is used to derive the result type of some operation. For
example a GEP's operation and result will be based on its input Type.
When pointers become opaque, the BitcodeReader will still have access to this
information because it's explicitly told how to construct the more complex
types used, but this information will not be attached to any Value that gets
looked up. This changes BitcodeReader so that in all places which use type
information in this manner, it's derived from a side-table rather than from the
Value in question.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364550
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Djordje Todorovic [Thu, 27 Jun 2019 14:31:52 +0000 (14:31 +0000)]
[LiveRangeEdit] Fix build failure caused by the rL364536
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364549
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Simon Pilgrim [Thu, 27 Jun 2019 14:25:54 +0000 (14:25 +0000)]
[TargetLowering] SimplifyDemandedVectorElts - add shift/rotate support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364548
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Sanjay Patel [Thu, 27 Jun 2019 14:20:10 +0000 (14:20 +0000)]
[InstCombine] remove 'tmp' names and regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364546
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Jinsong Ji [Thu, 27 Jun 2019 14:11:31 +0000 (14:11 +0000)]
[PowerPC][HTM] Fix disassembling buffer overflow for tabortdc and others
This was reported in https://bugs.llvm.org/show_bug.cgi?id=41751
llvm-mc aborted when disassembling tabortdc.
This patch try to clean up TM related DAGs.
* Fixes the problem by remove explicit output of cr0, and put it as implicit def.
* Update int_ppc_tbegin pattern to accommodate the implicit def of cr0.
* Update the TCHECK operand and int_ppc_tcheck accordingly.
* Add some builtin test and disassembly tests.
* Remove unused CRRC0/crrc0
Differential Revision: https://reviews.llvm.org/D61935
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364544
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Hans Wennborg [Thu, 27 Jun 2019 13:55:02 +0000 (13:55 +0000)]
Revert r363658 "[SVE][IR] Scalable Vector IR Type with pr42210 fix"
We saw a 70% ThinLTO link time increase in Chromium for Android, see
crbug.com/978817. Sounds like more of PR42210.
> Recommit of D32530 with a few small changes:
> - Stopped recursively walking through aggregates in
> the verifier, so that we don't impose too much
> overhead on large modules under LTO (see PR42210).
> - Changed tests to match; the errors are slightly
> different since they only report the array or
> struct that actually contains a scalable vector,
> rather than all aggregates which contain one in
> a nested member.
> - Corrected an older comment
>
> Reviewers: thakis, rengolin, sdesmalen
>
> Reviewed By: sdesmalen
>
> Differential Revision: https://reviews.llvm.org/D63321
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364543
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Djordje Todorovic [Thu, 27 Jun 2019 13:52:34 +0000 (13:52 +0000)]
[DWARF] Handle the DW_OP_entry_value operand
Add the IR and the AsmPrinter parts for handling of the DW_OP_entry_values
DWARF operation.
([11/13] Introduce the debug entry values.)
Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>
Differential Revision: https://reviews.llvm.org/D60866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364542
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Simon Pilgrim [Thu, 27 Jun 2019 13:48:43 +0000 (13:48 +0000)]
[TargetLowering] SimplifyDemandedBits - use DemandedElts to better identify partial splat shift amounts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364541
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Simon Atanasyan [Thu, 27 Jun 2019 13:41:30 +0000 (13:41 +0000)]
[mips] Mark pseudo select instructions by the `hasNoSchedulingInfo` tag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364540
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Simon Atanasyan [Thu, 27 Jun 2019 13:41:23 +0000 (13:41 +0000)]
[mips] Add new items to the list of features unsupported by P5600
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364539
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James Henderson [Thu, 27 Jun 2019 13:24:46 +0000 (13:24 +0000)]
[docs][tools] Add missing "program" tags to rst files
Sphinx allows for definitions of command-line options using
`.. option <name>` and references to those options via `:option:<name>`.
However, it looks like there is no scoping of these options by default,
meaning that links can end up pointing to incorrect documents. See for
example the llvm-mca document, which contains references to -o that,
prior to this patch, pointed to a different document. What's worse is
that these links appear to be non-deterministic in which one is picked
(on my machine, some references end up pointing to opt, whereas on the
live docs, they point to llvm-dwarfdump, for example).
The fix is to add the .. program <name> tag. This essentially namespaces
the options (definitions and references) to the named program, ensuring
that the links are kept correct.
Reviwed by: andreadb
Differential Revision: https://reviews.llvm.org/D63873
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364538
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Djordje Todorovic [Thu, 27 Jun 2019 13:10:29 +0000 (13:10 +0000)]
[Backend] Keep call site info valid through the backend
Handle call instruction replacements and deletions in order to preserve
valid state of the call site info of the MachineFunction.
NOTE: If the call site info is enabled for a new target, the assertion from
the MachineFunction::DeleteMachineInstr() should help to locate places
where the updateCallSiteInfo() should be called in order to preserve valid
state of the call site info.
([10/13] Introduce the debug entry values.)
Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>
Differential Revision: https://reviews.llvm.org/D61062
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364536
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Simon Tatham [Thu, 27 Jun 2019 12:41:12 +0000 (12:41 +0000)]
[ARM] Fix bogus assertions in copyPhysReg v8.1-M cases.
The code to generate register move instructions in and out of VPR and
FPSCR_NZCV had assertions checking that the other register involved
was a GPR _pair_, instead of a single GPR as it should have been.
Reviewers: miyuki, ostannard
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63865
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364534
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Simon Tatham [Thu, 27 Jun 2019 12:41:07 +0000 (12:41 +0000)]
[ARM] Fix handling of zero offsets in LOB instructions.
The BF and WLS/WLSTP instructions have various branch-offset fields
occupying different positions and lengths in the instruction encoding,
and all of them were decoded at disassembly time by the function
DecodeBFLabelOffset() which returned SoftFail if the offset was zero.
In fact, it's perfectly fine and not even a SoftFail for most of those
offset fields to be zero. The only one that can't be zero is the 4-bit
field labelled `boff` in the architecture spec, occupying bits {26-23}
of the BF instruction family. If that one is zero, the encoding
overlaps other instructions (WLS, DLS, LETP, VCTP), so it ought to be
a full Fail.
Fixed by adding an extra template parameter to DecodeBFLabelOffset
which controls whether a zero offset is accepted or rejected. Adjusted
existing tests (only in error messages for bad disassemblies); added
extra tests to demonstrate zero offsets being accepted in all the
right places, and a few demonstrating rejection of zero `boff`.
Reviewers: DavidSpickett, ostannard
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63864
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364533
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Simon Tatham [Thu, 27 Jun 2019 12:40:55 +0000 (12:40 +0000)]
[ARM] Make coprocessor number restrictions consistent.
Different versions of the Arm architecture disallow the use of generic
coprocessor instructions like MCR and CDP on different sets of
coprocessors. This commit centralises the check of the coprocessor
number so that it's consistent between assembly and disassembly, and
also updates it for the new restrictions in Arm v8.1-M.
New tests added that check all the coprocessor numbers; old tests
updated, where they used a number that's now become illegal in the
context in question.
Reviewers: DavidSpickett, ostannard
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63863
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364532
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Simon Tatham [Thu, 27 Jun 2019 12:40:40 +0000 (12:40 +0000)]
[ARM] Tighten restrictions on use of SP in v8.1-M CSEL.
In the `CSEL Rd,Rm,Rn` instruction family (also including CSINC, CSINV
and CSNEG), the architecture lists it as CONSTRAINED UNPREDICTABLE
(i.e. SoftFail) to use SP in the Rd or Rm slot, but outright illegal
to use it in the Rn slot, not least because some encodings of that
form are used by MVE instructions such as UQRSHLL.
MC was treating all three slots the same, as SoftFail. So the only
reason UQRSHLL was disassembled correctly at all was because the MVE
decode table is separate from the Thumb2 one and takes priority; if
you turned off MVE, then encodings such as `[0x5f,0xea,0x0d,0x83]`
would disassemble as spurious CSELs.
Fixed by inventing another version of the `GPRwithZR` register class,
which disallows SP completely instead of just SoftFailing it.
Reviewers: DavidSpickett, ostannard
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63862
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364531
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Simon Pilgrim [Thu, 27 Jun 2019 12:35:52 +0000 (12:35 +0000)]
[X86] getFauxShuffle - add DemandedElts as a filter
This is currently benign but will be used in the future based on the elements referenced by the parent shuffle(s).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364530
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Simon Atanasyan [Thu, 27 Jun 2019 12:08:17 +0000 (12:08 +0000)]
[mips] Add GPR_64 predicate to some mov[zn] instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364527
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Simon Atanasyan [Thu, 27 Jun 2019 12:08:10 +0000 (12:08 +0000)]
[mips] Fix indentation and split long lines. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364526
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Simon Atanasyan [Thu, 27 Jun 2019 12:08:03 +0000 (12:08 +0000)]
[mips] Reformat MSA instruction definitions. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364525
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Jeremy Morse [Thu, 27 Jun 2019 11:52:03 +0000 (11:52 +0000)]
Add triple to a test I just added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364524
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Tim Northover [Thu, 27 Jun 2019 11:44:45 +0000 (11:44 +0000)]
IR: compare type attributes deeply when looking into functions.
FunctionComparator attempts to produce a stable comparison of two Function
instances by looking at all available properties. Since ByVal attributes now
contain a Type pointer, they are not trivially ordered and FunctionComparator
should use its own Type comparison logic to sort them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364523
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George Rimar [Thu, 27 Jun 2019 11:31:43 +0000 (11:31 +0000)]
[Object/invalid.test] - Convert most of the sub tests to YAML.
Object/invalid.test is a test case that is used to check the behavior of tools
when broken inputs are used.
The most often tool tested there is llvm-readobj. I think we might want to move
such tests to test\tools\llvm-readobj. For now this patch converts
many sub-tests to use YAML and removes 12 binaries from the inputs.
Differential revision: https://reviews.llvm.org/D63762
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364522
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Stefan Stipanovic [Thu, 27 Jun 2019 11:27:54 +0000 (11:27 +0000)]
[Attributor] Deducing existing nounwind attribute.
Adding nounwind deduction in new attributor framework.
Reviewers: jdoerfert, uenoku
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D63379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364521
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Simon Pilgrim [Thu, 27 Jun 2019 11:22:23 +0000 (11:22 +0000)]
[X86][SSE] Regenerate v48 shuffle test on a variety of targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364520
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Simon Pilgrim [Thu, 27 Jun 2019 11:16:03 +0000 (11:16 +0000)]
[X86][AVX] SimplifyDemandedVectorElts - combine PERMPD(x) -> EXTRACTF128(X)
If we only use the bottom lane, see if we can simplify this to extract_subvector - which is always at least as quick as PERMPD/PERMQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364518
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George Rimar [Thu, 27 Jun 2019 11:08:42 +0000 (11:08 +0000)]
[yaml2obj] - Allow overriding e_shentsize, e_shoff, e_shnum and e_shstrndx fields in the YAML.
This allows setting different values for e_shentsize, e_shoff, e_shnum
and e_shstrndx fields and is useful for producing broken inputs for various
test cases.
Differential revision: https://reviews.llvm.org/D63771
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364517
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Djordje Todorovic [Thu, 27 Jun 2019 10:51:15 +0000 (10:51 +0000)]
[ISEL][X86] Tracking of registers that forward call arguments
While lowering calls, collect info about registers that forward arguments
into following function frame. We store such info into the MachineFunction
of the call. This is used very late when dumping DWARF info about
call site parameters.
([9/13] Introduce the debug entry values.)
Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>
Differential Revision: https://reviews.llvm.org/D60715
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364516
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Jeremy Morse [Thu, 27 Jun 2019 10:20:27 +0000 (10:20 +0000)]
[DebugInfo] Avoid register coalesing unsoundly changing DBG_VALUE locations
Once MIR code leaves SSA form and the liveness of a vreg is considered,
DBG_VALUE insts are able to refer to non-live vregs, because their
debug-uses do not contribute to liveness. This non-liveness becomes
problematic for optimizations like register coalescing, as they can't
``see'' the debug uses in the liveness analyses.
As a result registers get coalesced regardless of debug uses, and that can
lead to invalid variable locations containing unexpected values. In the
added test case, the first vreg operand of ADD32rr is merged with various
copies of the vreg (great for performance), but a DBG_VALUE of the
unmodified operand is blindly updated to the modified operand. This changes
what value the variable will appear to have in a debugger.
Fix this by changing any DBG_VALUE whose operand will be resurrected by
register coalescing to be a $noreg DBG_VALUE, i.e. give the variable no
location. This is an overapproximation as some coalesced locations are
safe (others are not) -- an extra domination analysis would be required to
work out which, and it would be better if we just don't generate non-live
DBG_VALUEs.
This fixes PR40010.
Differential Revision: https://reviews.llvm.org/D56151
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364515
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Diana Picus [Thu, 27 Jun 2019 09:49:07 +0000 (09:49 +0000)]
[GlobalISel] Remove [un]packRegs from IRTranslator
Remove the last use of packRegs from IRTranslator and delete
pack/unpackRegs. This introduces a fallback to DAGISel for intrinsics
with aggregate arguments, since we don't have a testcase for them so
it's hard to tell how we'd want to handle them.
Discussed in https://reviews.llvm.org/D63551
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364514
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Diana Picus [Thu, 27 Jun 2019 09:24:30 +0000 (09:24 +0000)]
[AArch64 GlobalISel] Cleanup CallLowering. NFCI
Now that lowerCall and lowerFormalArgs have been refactored, we can
simplify splitToValueTypes.
Differential Revision: https://reviews.llvm.org/D63552
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364513
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Diana Picus [Thu, 27 Jun 2019 09:18:03 +0000 (09:18 +0000)]
[GlobalISel] Accept multiple vregs for lowerCall's args
Change the interface of CallLowering::lowerCall to accept several
virtual registers for each argument, instead of just one. This is a
follow-up to D46018.
CallLowering::lowerReturn was similarly refactored in D49660 and
lowerFormalArguments in D63549.
With this change, we no longer pack the virtual registers generated for
aggregates into one big lump before delegating to the target. Therefore,
the target can decide itself whether it wants to handle them as separate
pieces or use one big register.
ARM and AArch64 have been updated to use the passed in virtual registers
directly, which means we no longer need to generate so many
merge/extract instructions.
NFCI for AMDGPU, Mips and X86.
Differential Revision: https://reviews.llvm.org/D63551
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364512
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Diana Picus [Thu, 27 Jun 2019 09:15:53 +0000 (09:15 +0000)]
[GlobalISel] Accept multiple vregs for lowerCall's result
Change the interface of CallLowering::lowerCall to accept several
virtual registers for the call result, instead of just one. This is a
follow-up to D46018.
CallLowering::lowerReturn was similarly refactored in D49660 and
lowerFormalArguments in D63549.
With this change, we no longer pack the virtual registers generated for
aggregates into one big lump before delegating to the target. Therefore,
the target can decide itself whether it wants to handle them as separate
pieces or use one big register.
ARM and AArch64 have been updated to use the passed in virtual registers
directly, which means we no longer need to generate so many
merge/extract instructions.
NFCI for AMDGPU, Mips and X86.
Differential Revision: https://reviews.llvm.org/D63550
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364511
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