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Hiroshi Yamauchi [Mon, 21 Dec 2015 22:06:23 +0000 (14:06 -0800)]
Treat thread state kWaitingWeakGcRootRead as kJavaRunnable.
Like kSuspended, kWaitingWeakGcRootRead means temporarily waiting for
GC's purpose rather than the thread is waiting on a monitor.
This may fix some jsr166 test failures.
Bug:
25883050
Bug:
12687968
Change-Id: Ib53e18c0fb2ff95aa0491b1531201e583288684e
Alex Light [Fri, 18 Dec 2015 17:57:40 +0000 (17:57 +0000)]
Merge "Make use of new method iterators."
Roland Levillain [Fri, 18 Dec 2015 17:54:01 +0000 (17:54 +0000)]
Merge "MIPS64: Fuse long and FP compare & condition in Optimizing."
Roland Levillain [Fri, 18 Dec 2015 17:21:25 +0000 (17:21 +0000)]
Merge "Disable jsr166.LinkedTransferQueueTest#testTransfer2 again."
Roland Levillain [Fri, 18 Dec 2015 16:55:35 +0000 (16:55 +0000)]
Disable jsr166.LinkedTransferQueueTest#testTransfer2 again.
This test is failing (again) on the concurrent collector
configuration. Disable it while we investigate.
Bug:
25883050
Change-Id: I54e59a43b730c286e370b5ae01bc5713fe816b61
Nicolas Geoffray [Fri, 18 Dec 2015 14:57:19 +0000 (14:57 +0000)]
Merge "ART: Fix bug in LSE"
David Brazdil [Mon, 14 Dec 2015 16:58:08 +0000 (16:58 +0000)]
ART: Fix bug in LSE
LSE will not remove a load if the type of the heap value does not
match the type of the load. This was a workaround for b/
22538329 but
backfires for integers. For example, 'IntConstant 0' has type int
but can be retrieved from a boolean field. The corresponding store is
removed but not the load, loading uninitialized memory. This fixes the
issue until the workaround is not needed any more.
Change-Id: I2a47783e8d5f93104854e5216b69b6c220832c76
Roland Levillain [Fri, 18 Dec 2015 12:56:47 +0000 (12:56 +0000)]
Merge "Disable the UnsafeCASObject intrinsic with read barriers."
Roland Levillain [Fri, 18 Dec 2015 11:43:38 +0000 (11:43 +0000)]
Disable the UnsafeCASObject intrinsic with read barriers.
The current implementations of the UnsafeCASObject
intrinsics are missing a read barrier. Temporarily disable
them when read barriers are enabled.
Also re-enable the jsr166.LinkedTransferQueueTest tests that
were failing on the concurrent collector configuration, as
the UnsafeCASObject JNI implementation now correctly
implements the read barrier which was missing.
Bug:
25883050
Bug:
26205973
Change-Id: Iaf5d515532949662d0ac6702c9452a00aa0a23e6
Aart Bik [Thu, 17 Dec 2015 23:28:06 +0000 (23:28 +0000)]
Merge "Revert "Revert "X86: Use locked add rather than mfence"""
Alex Light [Thu, 17 Dec 2015 21:55:59 +0000 (13:55 -0800)]
Make use of new method iterators.
Change-Id: I1f82f17951339b2054a1dac87bde79f9e803fc4a
Alexey Frunze [Wed, 9 Dec 2015 00:08:02 +0000 (16:08 -0800)]
MIPS64: Fuse long and FP compare & condition in Optimizing.
Bug:
25559148
Change-Id: I2d14ac75460a76848c71c08cffff6d7a18f5f580
Andreas Gampe [Thu, 17 Dec 2015 18:55:58 +0000 (18:55 +0000)]
Merge "ART: Refactor CommonRuntimeTest::SetUp"
Andreas Gampe [Thu, 17 Dec 2015 00:54:35 +0000 (16:54 -0800)]
ART: Refactor CommonRuntimeTest::SetUp
Factor out finishing up the runtime. This code will execute the
interpreter to initialize important classes etc., which is not
necessary for testing RuntimeMethod sizes and trampoline entrypoints,
in fact it may violate pointer-size invariants.
Also add InstructionSet parsing tests to the ParsedOptions test.
Change-Id: I75cd00c6d358e1bc962c8f1845244f6400c1cd6c
Andreas Gampe [Thu, 17 Dec 2015 18:35:41 +0000 (18:35 +0000)]
Merge "ART: Recognize cortex-a53.a57 for ARM features"
Alex Light [Thu, 17 Dec 2015 18:33:57 +0000 (18:33 +0000)]
Merge "Revert "Revert "Combine direct_methods_ and virtual_methods_ fields of mirror::Class"""
Vladimir Marko [Thu, 17 Dec 2015 16:46:19 +0000 (16:46 +0000)]
Merge "Revert "Revert "ART: Reduce the instructions generated by packed switch."""
Nicolas Geoffray [Thu, 17 Dec 2015 15:27:16 +0000 (15:27 +0000)]
Merge "Fix braino in parallel move resolver."
Nicolas Geoffray [Thu, 17 Dec 2015 15:26:44 +0000 (15:26 +0000)]
Merge "Revert "Tweak inlining heuristics.""
Nicolas Geoffray [Thu, 17 Dec 2015 15:26:21 +0000 (15:26 +0000)]
Revert "Tweak inlining heuristics."
This reverts commit
fcb7613d3aaa9a6802800b6e957aaad51cedf6dc.
Change-Id: Idc0df6a2f68e8b5aa740bb1259f19c2953811510
Vladimir Marko [Thu, 17 Dec 2015 15:23:13 +0000 (15:23 +0000)]
Revert "Revert "ART: Reduce the instructions generated by packed switch.""
This reverts commit
b4c137630fd2226ad07dfd178ab15725374220f1.
The underlying issue was fixed by https://android-review.googlesource.com/188271 .
Bug:
26121945
Change-Id: I58b08eb1a9f0a5c861f8cda93522af64bcf63920
Vladimir Marko [Thu, 17 Dec 2015 15:14:59 +0000 (15:14 +0000)]
Merge "Optimizing/ARM: Fix AddConstant() to adhere to set_cc."
Vladimir Marko [Thu, 17 Dec 2015 12:08:08 +0000 (12:08 +0000)]
Optimizing/ARM: Fix AddConstant() to adhere to set_cc.
And improve it to use shorter code sequences.
Bug:
26121945
Change-Id: Ia4f1688652c195a7ca19af36d919388a550e2841
Nicolas Geoffray [Thu, 17 Dec 2015 14:28:35 +0000 (14:28 +0000)]
Fix braino in parallel move resolver.
Reiterating over the moves needs to set i to -1, not 0.
bug:
26241132
Change-Id: Iaae7eac5b421b0ee1b1ce89577c8b951b2d4dae8
Nicolas Geoffray [Thu, 17 Dec 2015 13:59:47 +0000 (13:59 +0000)]
Merge "Tweak inlining heuristics."
Nicolas Geoffray [Thu, 17 Dec 2015 12:43:00 +0000 (12:43 +0000)]
Tweak inlining heuristics.
go/lem driven:
Performance:
Richards +41%
CaffeineMethod +43%
ReversiBench: +52%
Towers: +73%
Tak: +85%
Memory use: 7% less memory
CompileTime: 14% increase
CodeSize: 8% increase
Last three measures are now more acceptable given we JIT.
Change-Id: Ic4aa6535d2b76cf3545ef00e9b2ae32330f10745
Nicolas Geoffray [Thu, 17 Dec 2015 12:02:19 +0000 (12:02 +0000)]
Merge "Change DCHECK into CHECK to diagnose sporadic crash."
Nicolas Geoffray [Thu, 17 Dec 2015 11:56:01 +0000 (11:56 +0000)]
Change DCHECK into CHECK to diagnose sporadic crash.
bug:
26221227
bug:
25942183
Change-Id: I1325af40098dd336b6c85df8d4fcb7fe26aeac97
Nicolas Geoffray [Thu, 17 Dec 2015 11:34:37 +0000 (11:34 +0000)]
Merge "Add some dumping when SIGQUIT for the JIT."
Hiroshi Yamauchi [Thu, 17 Dec 2015 08:08:12 +0000 (08:08 +0000)]
Merge "Fix (non-intrinsic) UnsafeCASObject for the read barrier config."
Andreas Gampe [Thu, 17 Dec 2015 01:27:30 +0000 (17:27 -0800)]
ART: Recognize cortex-a53.a57 for ARM features
Add cortex-a53.a57 to the hardware-divide recognized set. Add all
ARMv8 Cortex-A variants to the LPAE list.
Bug:
26221616
Change-Id: I0fd577e84952ce23f8a5577ae5061a841240d602
Mark P Mendell [Wed, 16 Dec 2015 19:15:59 +0000 (19:15 +0000)]
Revert "Revert "X86: Use locked add rather than mfence""
This reverts commit
0da3b9117706760e8722029f407da6d0297cc943.
Fix a compilation failure that slipped in somehow.
Change-Id: Ide8681cdc921febb296ea47aa282cc195f154049
Alex Light [Thu, 17 Dec 2015 00:10:38 +0000 (00:10 +0000)]
Merge "Ensure that ClassTable has correct alignment in image."
Alex Light [Wed, 16 Dec 2015 23:52:51 +0000 (15:52 -0800)]
Ensure that ClassTable has correct alignment in image.
Change-Id: I645b44fae1ec129364449af552c745bf32486b1a
Alex Light [Tue, 15 Dec 2015 23:02:47 +0000 (15:02 -0800)]
Revert "Revert "Combine direct_methods_ and virtual_methods_ fields of mirror::Class""
This reverts commit
ae358c1d5cef227b44d6f4971b79e1ab91aa26eb.
Bug:
24618811
Change-Id: I8becf9bae3258450b90cfef5e79589db7c535a4d
Hiroshi Yamauchi [Fri, 11 Dec 2015 23:51:04 +0000 (15:51 -0800)]
Fix (non-intrinsic) UnsafeCASObject for the read barrier config.
Make sure the field contains a to-space reference before attempting the
CAS with a special read barrier to avoid an incorrect CAS failure.
This is only about the non-intrinsic UnsafeCASObject.
This seems to fix some jsr166 test failures.
Also, remove the unused template parameter kMaybeDuringStartup.
Bug:
25883050
Bug:
12687968
Change-Id: Ia6f0d882fa3d90c42f14968672d547babcdf6309
Aart Bik [Wed, 16 Dec 2015 19:11:38 +0000 (19:11 +0000)]
Merge "Revert "X86: Use locked add rather than mfence""
Aart Bik [Wed, 16 Dec 2015 19:06:17 +0000 (19:06 +0000)]
Revert "X86: Use locked add rather than mfence"
This reverts commit
7b3e4f99b25c31048a33a08688557b133ad345ab.
Reason: build error on sdk (linux) in git_mirror-aosp-master-with-vendor , please fix first
art/compiler/optimizing/code_generator_x86_64.cc:4032:7: error: use of
undeclared identifier 'codegen_'
codegen_->MemoryFence();
Change-Id: I91f8542cfd944b7425d1981c35872dcdcb901e18
Dimitry Ivanov [Wed, 16 Dec 2015 19:00:55 +0000 (19:00 +0000)]
Merge "Remove references to dlmalloc specific functions"
Aart Bik [Wed, 16 Dec 2015 18:47:07 +0000 (18:47 +0000)]
Merge "X86: Use locked add rather than mfence"
Andreas Gampe [Wed, 16 Dec 2015 17:08:53 +0000 (17:08 +0000)]
Merge "Make the 008-exceptions test print everything to stdout"
Roland Levillain [Wed, 16 Dec 2015 17:08:26 +0000 (17:08 +0000)]
Merge "Remove spurious references to kEmitCompilerReadBarrier in MIPS."
Roland Levillain [Wed, 16 Dec 2015 17:06:47 +0000 (17:06 +0000)]
Remove spurious references to kEmitCompilerReadBarrier in MIPS.
We do not support read barriers on MIPS code generators yet.
Also, wrap some long lines in the MIPS64 code generator.
Change-Id: Ia2755590afa60eb9c8fb547e059146ab6518372b
Roland Levillain [Wed, 16 Dec 2015 15:45:29 +0000 (15:45 +0000)]
Merge "MIPS32: Fuse long and FP compare & condition in Optimizing."
Roland Levillain [Wed, 16 Dec 2015 15:25:49 +0000 (15:25 +0000)]
Merge "Adjust tests blacklisted for heap poisoning and read barriers."
Roland Levillain [Wed, 16 Dec 2015 15:23:06 +0000 (15:23 +0000)]
Merge "Disable LinkedTransferQueueTest tests failing on the CC."
Roland Levillain [Wed, 16 Dec 2015 15:21:25 +0000 (15:21 +0000)]
Merge "Revert "Revert "Introduce support for hardware simulators, starting with ARM64"""
Roland Levillain [Wed, 16 Dec 2015 15:15:17 +0000 (15:15 +0000)]
Disable LinkedTransferQueueTest tests failing on the CC.
The following libcore tests randomly fail on the
concurrent collector (CC) configuration:
- jsr166.LinkedTransferQueueTest#testTransfer2
- jsr166.LinkedTransferQueueTest#testWaitingConsumer
It seems that it is due to
SR166TestCase.waitForThreadToEnterWaitState timing out.
Disable those tests while we investigate.
Bug:
25883050
Change-Id: I4f310c677869d9e2701738e9734a1f53b5939f18
Kevin Brodsky [Mon, 14 Dec 2015 10:15:04 +0000 (10:15 +0000)]
Make the 008-exceptions test print everything to stdout
Printing to different streams (stderr and stdout) may cause the
messages to be interleaved, making the test fail. Without this patch,
this kind of outcome has been observed:
--- expected.txt 2015-12-09 08:13:50.
583294910 +0000
+++ output.txt 2015-12-09 08:55:35.
635185771 +0000
@@ -1,15 +1,15 @@
Got an NPE: second throw
java.lang.NullPointerException: second throw
- at Main.catchAndRethrow(Main.java:77)
+Static Init
+BadError: This is bad by convention: BadInit
+java.lang.NoClassDefFoundError: BadInit at Main.catchAndRethrow(Main.java:77)
at Main.exceptions_007(Main.java:59)
at Main.main(Main.java:67)
Caused by: java.lang.NullPointerException: first throw
at Main.throwNullPointerException(Main.java:84)
at Main.catchAndRethrow(Main.java:74)
... 2 more
-Static Init
-BadError: This is bad by convention: BadInit
-java.lang.NoClassDefFoundError: BadInit
+
BadError: This is bad by convention: BadInit
Static BadInitNoStringInit
BadErrorNoStringInit: This is bad by convention
Change-Id: Iaabf5ed593d100abf157adf46c1761338227d2cf
Roland Levillain [Wed, 16 Dec 2015 14:21:33 +0000 (14:21 +0000)]
Adjust tests blacklisted for heap poisoning and read barriers.
Bug:
12687968
Change-Id: I7b504661c04d35d10f66a3893a33db8c9db128a1
Nicolas Geoffray [Wed, 16 Dec 2015 12:31:26 +0000 (12:31 +0000)]
Merge "Add test case for bad arm code generation."
Nicolas Geoffray [Wed, 16 Dec 2015 12:31:14 +0000 (12:31 +0000)]
Merge "Revert "ART: Reduce the instructions generated by packed switch.""
Nicolas Geoffray [Wed, 16 Dec 2015 12:16:43 +0000 (12:16 +0000)]
Add test case for bad arm code generation.
Bug:
26121945
Change-Id: Ibaedeca24d4208a0bc6b650e549cb68619fd8f64
Nicolas Geoffray [Wed, 16 Dec 2015 12:06:39 +0000 (12:06 +0000)]
Revert "ART: Reduce the instructions generated by packed switch."
This reverts commit
59f054d98f519a3efa992b1c688eb97bdd8bbf55.
bug:
26121945
Change-Id: I8a5ad7ef1f1de8d44787c27528fa3f7f5c2e9cd3
Vladimir Marko [Wed, 16 Dec 2015 10:50:52 +0000 (10:50 +0000)]
Merge "ART: Compile run-tests with Java 7."
Vladimir Marko [Tue, 15 Dec 2015 16:36:24 +0000 (16:36 +0000)]
ART: Compile run-tests with Java 7.
This fixes run-tests with EXPERIMENTAL_USE_JAVA8=true.
Change-Id: I269664fc65a1d6c244c3f6191e332eb2751b5c0e
Nicolas Geoffray [Wed, 16 Dec 2015 09:34:39 +0000 (09:34 +0000)]
Merge "Revert "ART: Set RTI of Arm64IntermediateAddress""
Nicolas Geoffray [Wed, 16 Dec 2015 09:34:21 +0000 (09:34 +0000)]
Revert "ART: Set RTI of Arm64IntermediateAddress"
This reverts commit
e36ae9435da21542891ceeebb3328f5066c8301e.
Change-Id: If675b02db04bee78cc95da4ed58e545da5085da1
Nicolas Geoffray [Wed, 16 Dec 2015 08:35:46 +0000 (08:35 +0000)]
Merge "Revert "ART: Refactor SsaBuilder for more precise typing info""
Alex Light [Wed, 16 Dec 2015 01:30:30 +0000 (17:30 -0800)]
Revert "ART: Refactor SsaBuilder for more precise typing info"
This reverts commit
d9510dfc32349eeb4f2145c801f7ba1d5bccfb12.
Bug:
26208284
Bug:
24252151
Bug:
24252100
Bug:
22538329
Bug:
25786318
Change-Id: I5f491becdf076ff51d437d490405ec4e1586c010
Alexey Frunze [Fri, 4 Dec 2015 00:46:38 +0000 (16:46 -0800)]
MIPS32: Fuse long and FP compare & condition in Optimizing.
This also does a minor clean-up in the assembler and
its test.
Bug:
25559148
Change-Id: I9bad3c500b592a09013b56745f70752eb284a842
Alex Light [Tue, 15 Dec 2015 22:17:21 +0000 (22:17 +0000)]
Merge "Revert "Combine direct_methods_ and virtual_methods_ fields of mirror::Class""
Alex Light [Tue, 15 Dec 2015 22:15:26 +0000 (22:15 +0000)]
Revert "Combine direct_methods_ and virtual_methods_ fields of mirror::Class"
This reverts commit
6286a97bea0f584342803a215550038852b24776.
Change-Id: I5b00f6d1350e9c587acd4b185367dc815ea707de
Aart Bik [Tue, 15 Dec 2015 20:50:49 +0000 (20:50 +0000)]
Merge "Various induction/range analysis improvements."
Mark Mendell [Thu, 19 Nov 2015 19:08:40 +0000 (14:08 -0500)]
X86: Use locked add rather than mfence
Java semantics for memory ordering can be satisfied using
lock addl $0,0(SP)
rather than mfence. The locked add synchronizes the memory caches, but
doesn't affect device memory.
Timing on a micro benchmark with a mfence or lock add $0,0(sp) in a loop
with
600000000 iterations:
time ./mfence
real 0m5.411s
user 0m5.408s
sys 0m0.000s
time ./locked_add
real 0m3.552s
user 0m3.550s
sys 0m0.000s
Implement this as an instruction-set-feature lock_add. This is off by
default (uses mfence), and enabled for atom & silvermont variants.
Generation of mfence can be forced by a parameter to MemoryFence.
Change-Id: I5cb4fded61f4cbbd7b7db42a1b6902e43e458911
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
Aart Bik [Wed, 9 Dec 2015 22:39:48 +0000 (14:39 -0800)]
Various induction/range analysis improvements.
Rationale: this change list improves analysis of triangular loops
both by changing loop order for induction analysis
(enabling range analysis in inner loops) and by
some symbolic improvements during range analysis;
also, a mul/div bug has been fixed (with pass/fail
unit tests); lastly this change list prepares some
follow up optimizations.
Change-Id: I84a03e848405009541c3fa8e3d3c2f430e100087
Alex Light [Tue, 15 Dec 2015 18:11:08 +0000 (18:11 +0000)]
Merge "Combine direct_methods_ and virtual_methods_ fields of mirror::Class"
Nicolas Geoffray [Tue, 15 Dec 2015 17:04:50 +0000 (17:04 +0000)]
Merge "Remove reference of deleted file."
Nicolas Geoffray [Tue, 15 Dec 2015 17:04:05 +0000 (17:04 +0000)]
Remove reference of deleted file.
Change-Id: Ib6d03a8c57a746e738fc849deee800d28da82485
Nicolas Geoffray [Tue, 15 Dec 2015 16:39:44 +0000 (16:39 +0000)]
Add some dumping when SIGQUIT for the JIT.
Change-Id: Iad68bdc8a4ab53e810feb3bc8507b7f42e79b1f7
Nicolas Geoffray [Tue, 15 Dec 2015 16:45:34 +0000 (16:45 +0000)]
Merge "Remove test given its flakiness."
Nicolas Geoffray [Tue, 15 Dec 2015 16:03:48 +0000 (16:03 +0000)]
Remove test given its flakiness.
Change-Id: I7b746bd93cfd3f7eca71f1a7b9dcc799d30dd971
David Srbecky [Tue, 15 Dec 2015 15:29:17 +0000 (15:29 +0000)]
Merge "Refactor DexFile::DecodeDebugInfo."
David Srbecky [Thu, 10 Dec 2015 13:15:00 +0000 (13:15 +0000)]
Refactor DexFile::DecodeDebugInfo.
Split the method into two - one for locals and one for positions.
All uses of the method request only one of the two and it makes the
code slightly cleaner. The position variant requires fewer parameters.
Expose additional line table information which was previously ignored
by the decode method (prologue, epilogue, source file).
Change-Id: Idf8ba98fa58ea0d2103932b5cc0af81365885107
Roland Levillain [Tue, 15 Dec 2015 13:55:13 +0000 (13:55 +0000)]
Merge "x86-64 Baker's read barrier fast path implementation."
Roland Levillain [Tue, 15 Dec 2015 12:39:34 +0000 (12:39 +0000)]
Merge "x86 Baker's read barrier fast path implementation."
Calin Juravle [Tue, 15 Dec 2015 12:20:13 +0000 (12:20 +0000)]
Merge "Lower jitthreshold for jit profile test."
Nicolas Geoffray [Tue, 15 Dec 2015 12:14:14 +0000 (12:14 +0000)]
Merge "Fix --inline-max-code-units option."
Nicolas Geoffray [Tue, 15 Dec 2015 12:09:43 +0000 (12:09 +0000)]
Fix --inline-max-code-units option.
Change-Id: I73d99904a9eed69eb89efb6fb764db4a5d199f20
Calin Juravle [Tue, 15 Dec 2015 12:02:50 +0000 (12:02 +0000)]
Lower jitthreshold for jit profile test.
The test still proves to be flacky on the build bots. Lowering the
threshold will trigger compilation earlier.
Change-Id: Iacabf88d9fbd2a15fd3456f817402c9aaf3ec766
Nicolas Geoffray [Tue, 15 Dec 2015 11:51:51 +0000 (11:51 +0000)]
Merge "Revert "Make the JIT the default in ART.""
Nicolas Geoffray [Tue, 15 Dec 2015 11:51:37 +0000 (11:51 +0000)]
Revert "Make the JIT the default in ART."
Few tests failing: oat_file_assistant_test and jit run tests.
This reverts commit
0a9b6826bc6e71d799eb3fe8829981597b890dee.
Change-Id: Ibbf73c191d244ebb9517b6ae97971dd9a9d37d7c
Roland Levillain [Tue, 15 Dec 2015 10:54:19 +0000 (10:54 +0000)]
x86-64 Baker's read barrier fast path implementation.
Introduce an x86-64 fast path implementation in Optimizing
for Baker's read barriers (for both heap reference loads and
GC root loads). The marking phase of the read barrier is
performed by a slow path, invoking the runtime entry point
artReadBarrierMark.
Other read barrier algorithms continue to use the original
slow path based implementation, which has been renamed as
GenerateReadBarrierSlow/GenerateReadBarrierForRootSlow.
Bug:
12687968
Change-Id: I9329293ddca7f9bcb512132bde6675aa202b98b2
Roland Levillain [Tue, 15 Dec 2015 10:55:36 +0000 (10:55 +0000)]
x86 Baker's read barrier fast path implementation.
Introduce an x86 fast path implementation in Optimizing for
Baker's read barriers (for both heap reference loads and GC
root loads). The marking phase of the read barrier is
performed by a slow path, invoking a new runtime entry point
(artReadBarrierMark).
Other read barrier algorithms continue to use the original
slow path based implementation, which has been renamed as
GenerateReadBarrierSlow/GenerateReadBarrierForRootSlow.
Bug:
12687968
Change-Id: Ie610c4befc19ff22378a8cba38b422dcacb54320
Nicolas Geoffray [Tue, 15 Dec 2015 09:38:55 +0000 (09:38 +0000)]
Merge "Make the JIT the default in ART."
Dimitry Ivanov [Tue, 15 Dec 2015 02:55:02 +0000 (18:55 -0800)]
Remove references to dlmalloc specific functions
Remove references to internal libc dlmalloc_* functions
so that we can hide them for lp64
Change-Id: I13977bea63d900e1819052140e3bd6bc1f2fc759
Shinichiro Hamaji [Tue, 15 Dec 2015 04:42:20 +0000 (04:42 +0000)]
Merge "Get DCHECK back to EncodedStaticFieldValueIterator"
Alex Light [Fri, 4 Dec 2015 01:38:56 +0000 (17:38 -0800)]
Combine direct_methods_ and virtual_methods_ fields of mirror::Class
This makes several parts of the overall runtime simpler and reduces
the size of a class object by 32-bits.
Bug:
24618811
Change-Id: I36129b52189e26898ea56fa2b7b45652e06af236
Dimitry Ivanov [Mon, 14 Dec 2015 18:04:02 +0000 (18:04 +0000)]
Merge "Temporary disable linker-namespaces"
Calin Juravle [Mon, 14 Dec 2015 18:03:55 +0000 (18:03 +0000)]
Merge "Increase the sleep time in 554-jit-profile-file"
Calin Juravle [Mon, 14 Dec 2015 18:01:21 +0000 (18:01 +0000)]
Increase the sleep time in 554-jit-profile-file
The previous sleep time wasn't enough. Some tests failed because not
all the methods managed to be compiled in time.
Change-Id: I4d63b6c3602c72dfa608f62c55e0f484bbfcf900
Dimitry Ivanov [Mon, 14 Dec 2015 17:57:56 +0000 (09:57 -0800)]
Temporary disable linker-namespaces
Bug: http://b/
26178910
Bug: http://b/
26165097
Change-Id: I858c70dc72ec164ea7a79ad625ddda91367dae06
Calin Juravle [Mon, 14 Dec 2015 16:48:10 +0000 (16:48 +0000)]
Merge "Disable 554-jit-profile-file for the READ_BARRIER mode."
Calin Juravle [Mon, 14 Dec 2015 16:29:06 +0000 (16:29 +0000)]
Disable 554-jit-profile-file for the READ_BARRIER mode.
Change-Id: I98f5c0aeb0d68b42a587b1f7261d3fe998ca7f8b
Calin Juravle [Mon, 14 Dec 2015 15:15:08 +0000 (15:15 +0000)]
Merge "Print more info on why the code_cache test fails in 115-native-bridge."
Calin Juravle [Mon, 14 Dec 2015 14:38:38 +0000 (14:38 +0000)]
Merge "Revert "Revert "Enable profiled guided compilation in dex2oat"""
Calin Juravle [Mon, 14 Dec 2015 14:35:17 +0000 (14:35 +0000)]
Print more info on why the code_cache test fails in 115-native-bridge.
Change-Id: Ib30893e53a5ed616ae4f6b6bc4d657b0fca846c8
David Brazdil [Mon, 14 Dec 2015 14:28:32 +0000 (14:28 +0000)]
Merge "ART: Set RTI of Arm64IntermediateAddress"
David Brazdil [Mon, 14 Dec 2015 14:25:44 +0000 (14:25 +0000)]
ART: Set RTI of Arm64IntermediateAddress
Fixes the arm64 build after I7a3aee1ff66c82d64b4846611c547af17e91d260.
Change-Id: Ic2c72df59e0ddbdf2edc8519a6954d078a5ef596
David Brazdil [Mon, 14 Dec 2015 13:38:20 +0000 (13:38 +0000)]
Merge "ART: Refactor SsaBuilder for more precise typing info"