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Sanjay Patel [Tue, 1 May 2018 15:43:36 +0000 (15:43 +0000)]
[DAG] add test to show FMF mismatch between IR and DAG; NFC
D45710 proposes to change this, but we have no test coverage
for the first step in this process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331271
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Daniel Neilson [Tue, 1 May 2018 15:35:08 +0000 (15:35 +0000)]
[LV] Preserve inbounds on created GEPs
Summary:
This is a fix for PR23997.
The loop vectorizer is not preserving the inbounds property of GEPs that it creates.
This is inhibiting some optimizations. This patch preserves the inbounds property in
the case where a load/store is being fed by an inbounds GEP.
Reviewers: mkuper, javed.absar, hsaito
Reviewed By: hsaito
Subscribers: dcaballe, hsaito, llvm-commits
Differential Revision: https://reviews.llvm.org/D46191
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331269
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Wei Mi [Tue, 1 May 2018 14:47:24 +0000 (14:47 +0000)]
Fix the issue that ComputeValueKnownInPredecessors only handles the case when
phi is on lhs of a comparison op.
For the following testcase,
L1:
%t0 = add i32 %m, 7
%t3 = icmp eq i32* %t2, null
br i1 %t3, label %L3, label %L2
L2:
%t4 = load i32, i32* %t2, align 4
br label %L3
L3:
%t5 = phi i32 [ %t0, %L1 ], [ %t4, %L2 ]
%t6 = icmp eq i32 %t0, %t5
br i1 %t6, label %L4, label %L5
We know if we go through the path L1 --> L3, %t6 should always be true. However
currently, if the rhs of the eq comparison is phi, JumpThreading fails to
evaluate %t6 to true. And we know that Instcombine cannot guarantee always
canonicalizing phi to the left hand side of the comparison operation according
to the operand priority comparison mechanism in instcombine. The patch handles
the case when rhs of the comparison op is a phi.
Differential Revision: https://reviews.llvm.org/D46275
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331266
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Omer Paparo Bivas [Tue, 1 May 2018 14:27:10 +0000 (14:27 +0000)]
[InstCombine] new testcases for OverflowingBinaryOperators and PossiblyExactOperators transformations; NFC
instcombine should transform the relevant cases if the OverflowingBinaryOperator/PossiblyExactOperator can be proven to be safe.
Change-Id: I7aec62a31a894e465e00eb06aed80c3ea0c9dd45
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331265
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Simon Pilgrim [Tue, 1 May 2018 14:25:01 +0000 (14:25 +0000)]
[X86] Split WriteFShuffle into XMM and YMM/ZMM scheduler classes
Removes more WriteFShuffle InstRW overrides
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331264
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Simon Pilgrim [Tue, 1 May 2018 14:14:42 +0000 (14:14 +0000)]
[X86] Convert all uses of WriteFShuffle to X86SchedWriteWidths.
In preparation of splitting WriteFShuffle by vector width.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331262
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Sander de Smalen [Tue, 1 May 2018 13:36:03 +0000 (13:36 +0000)]
[AArch64][SVE] Asm: Support for contiguous ST1 (scalar+scalar) store instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D46121
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331260
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Simon Dardis [Tue, 1 May 2018 13:06:49 +0000 (13:06 +0000)]
Reland r331175: "[mips] Fix the predicates of jump and branch and link instructions"
The previous version of this patch restricted the 'jal' instruction to MIPS and
microMIPSr3. microMIPS32r6 does not have this instruction and instead uses jal
as an alias for balc.
Original commit message:
> Reviewers: smaksimovic, atanasyan, abeserminji
>
> Differential Revision: https://reviews.llvm.org/D46114
>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331259
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Simon Pilgrim [Tue, 1 May 2018 12:39:17 +0000 (12:39 +0000)]
[X86] Split WriteVecLogic into XMM and YMM/ZMM scheduler classes
This removes all the WriteVecLogic InstRW overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331258
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Omer Paparo Bivas [Tue, 1 May 2018 12:25:46 +0000 (12:25 +0000)]
[InstCombine] Adjusting bswap pattern matching to hold for And/Shift mixed case
Differential Revision: https://reviews.llvm.org/D45731
Change-Id: I85d4226504e954933c41598327c91b2d08192a9d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331257
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Simon Pilgrim [Tue, 1 May 2018 12:15:29 +0000 (12:15 +0000)]
[X86] Convert all uses of WriteFLogic/WriteVecLogic to X86SchedWriteWidths.
In preparation of splitting WriteVecLogic by vector width.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331256
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Florian Hahn [Tue, 1 May 2018 11:18:31 +0000 (11:18 +0000)]
[MC] Add llvm_unreachable to toString to fix compile time warning.
Without this change, GCC 7 raises the warning below:
control reaches end of non-void function
Reviewers: sbc100, andreadb
Reviewed By: andreadb
Differential Revision: https://reviews.llvm.org/D46304
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331255
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Simon Pilgrim [Tue, 1 May 2018 11:05:42 +0000 (11:05 +0000)]
[X86] Tag PSLLDQ/PSRLDQ as WriteShuffle scheduler classes instead of shifts.
Although they are encoded similar to bit shifts, the byte shifts behave like shuffles from a scheduling point of view.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331253
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Andrea Di Biagio [Tue, 1 May 2018 10:29:38 +0000 (10:29 +0000)]
[X86] Correct spill slot size.
This patch fixes a bug introduced by revision 330778 (originally reviewed at:
https://reviews.llvm.org/D44782), where function isFrameLoadOpcode returned
the wrong number of bytes read for opcodes VMOVSSrm and VMOVSDrm.
This corrects that mistake, and extends the regression test to catch cases where
the dead stores should be removed.
Patch by Jeremy Morse.
Differential Revision: https://reviews.llvm.org/D46256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331252
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Gabor Buella [Tue, 1 May 2018 10:21:10 +0000 (10:21 +0000)]
NFC, Avoid a warning in WasmObjectWriter
The warning was (introduced in r331220):
lib/MC/WasmObjectWriter.cpp:51:1: warning: control reaches end of non-void function [-Wreturn-type]
}
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331251
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Gabor Buella [Tue, 1 May 2018 10:01:16 +0000 (10:01 +0000)]
[X86] movdiri and movdir64b instructions
Reviewers: spatel, craig.topper, RKSimon
Reviewed By: craig.topper, RKSimon
Differential Revision: https://reviews.llvm.org/D45983
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331248
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Chandler Carruth [Tue, 1 May 2018 09:54:39 +0000 (09:54 +0000)]
[PM/LoopUnswitch] Remove the last manual domtree update code from loop
unswitch and replace it with the amazingly simple update API code.
This addresses piles of FIXMEs around the update logic here and makes
everything substantially simpler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331247
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Chandler Carruth [Tue, 1 May 2018 09:42:09 +0000 (09:42 +0000)]
[PM/LoopUnswitch] Add back a successor set that was removed based on
code review.
It turns out this *is* necessary, and I read the comment on the API
correctly the first time. ;]
The `applyUpdates` routine requires that updates are "balanced". This is
in order to cleanly handle cycles like inserting, removing, nad then
re-inserting the same edge. This precludes inserting the same edge
multiple times in a row as handling that would cause the insertion logic
to become *ordered* instead of *unordered* (which is what the API
provides).
It happens that in this specific case nothing (other than an assert and
contract violation) goes wrong because we're never inserting and
removing the same edge. The implementation *happens* to do the right
thing to eliminate redundant insertions in that case.
But the requirement is there and there is an assert to catch it.
Somehow, after the code review I never did another asserts-clang build
testing loop-unswich for a long time. As a consequence, I didn't notice
this despite a bunch of testing going on, but it shows up immediately
with an asserts build of clang itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331246
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Craig Topper [Tue, 1 May 2018 04:42:00 +0000 (04:42 +0000)]
[X86] Remove 'opaque ptr' from the intel syntax parser and printer.
Previously for instructions like fxsave we would print "opaque ptr" as part of the memory operand. Now we print nothing.
We also no longer accept "opaque ptr" in the parser. We still accept any size to be specified for these instructions, but we may want to consider only parsing when no explicit size is specified. This what gas does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331243
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Eric Christopher [Tue, 1 May 2018 00:10:13 +0000 (00:10 +0000)]
Temporarily revert "[DEBUG] Initial adaptation of NVPTX target for debug info emission."
This appears to have some issues associated with the file directive output
causing multiple global symbols with the name "file" to be emitted into a
startup section. I'm investigating more specific causes and working with the
original author.
This reverts commit r330271.
Also Revert "[DEBUGINFO, NVPTX] Add the test for the debug info of the local"
This reverts commit r330592 and the follow up of 330779 as the testcase is dependent upon r330271.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331237
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Sanjay Patel [Mon, 30 Apr 2018 21:28:18 +0000 (21:28 +0000)]
[InstCombine] fix test to restore intent
This test had values that differed in only in capitalization,
and that causes problems for the auto-generating check line
script. So I changed that in rL331226, but I accidentally
forgot to change a subsequent use of a param.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331228
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Sanjay Patel [Mon, 30 Apr 2018 21:03:36 +0000 (21:03 +0000)]
[InstCombine] add tests, update checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331226
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Nico Weber [Mon, 30 Apr 2018 20:19:48 +0000 (20:19 +0000)]
Stop setting LLVM_ON_WIN32 in config.h and llvm-config.h.
See thread "Replacing LLVM_ON_WIN32 with just _WIN32" on llvm-dev and cfe-dev.
I replaced all uses of LLVM_ON_WIN32 with _WIN32 in r331127 (llvm),
r331069 (clang), r329697 (lldb), r329696 (lld), r329696 (clang-tools-extra).
If your out-of-tree program used LLVM_ON_WIN32, just use _WIN32 instead, which
is set at exactly the same time to exactly the same value.
https://reviews.llvm.org/D46264
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331224
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Alina Sbirlea [Mon, 30 Apr 2018 20:11:13 +0000 (20:11 +0000)]
[ModRefInfo] Rename local variable IsMustAlias to avoid shadowing MustAlias enum entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331222
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Florian Hahn [Mon, 30 Apr 2018 20:10:53 +0000 (20:10 +0000)]
[SimplifyCFG] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).
This patch updates some code responsible the skip debug info to use
BasicBlock::instructionsWithoutDebug. I think this makes things slightly
simpler and more direct.
Reviewers: aprantl, vsk, hans, danielcdh
Reviewed By: hans
Differential Revision: https://reviews.llvm.org/D46252
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331221
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Sam Clegg [Mon, 30 Apr 2018 19:40:57 +0000 (19:40 +0000)]
[WebAssembly] MC: Improve debug output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331220
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Krzysztof Parzyszek [Mon, 30 Apr 2018 19:38:47 +0000 (19:38 +0000)]
[LivePhysRegs] Remove registers clobbered by regmasks from the live set
Dead defs were being removed from the live set (in stepForward), but
registers clobbered by regmasks weren't (more specifically, they were
actually removed by removeRegsInMask, but then they were added back in).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331219
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Nirav Dave [Mon, 30 Apr 2018 19:22:40 +0000 (19:22 +0000)]
[MC] Change AsmParser to leverage Assembler during evaluation
Teach AsmParser to check with Assembler for when evaluating constant
expressions. This improves the handing of preprocessor expressions
that must be resolved at parse time. This idiom can be found as
assembling-time assertion checks in source-level assemblers. Note that
this relies on the MCStreamer to keep sufficient tabs on Section /
Fragment information which the MCAsmStreamer does not. As a result the
textual output may fail where the equivalent object generation would
pass. This can most easily be resolved by folding the MCAsmStreamer
and MCObjectStreamer together which is planned for in a separate
patch.
Currently, this feature is only enabled for assembly input, keeping IR
compilation consistent between assembly and object generation.
Reviewers: echristo, rnk, probinson, espindola, peter.smith
Reviewed By: peter.smith
Subscribers: eraman, peter.smith, arichardson, jyknight, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D45164
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331218
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Florian Hahn [Mon, 30 Apr 2018 19:19:36 +0000 (19:19 +0000)]
[LoopSimplify] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).
This patch updates some code responsible the skip debug info to use
BasicBlock::instructionsWithoutDebug. I think this makes things slightly
simpler and more direct.
Reviewers: aprantl, vsk, chandlerc
Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D46253
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331217
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Matt Arsenault [Mon, 30 Apr 2018 19:08:16 +0000 (19:08 +0000)]
AMDGPU: Add Vega12 and Vega20
Changes by
Matt Arsenault
Konstantin Zhuravlyov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331215
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Roman Tereshin [Mon, 30 Apr 2018 18:58:57 +0000 (18:58 +0000)]
[MIR] Reset unique MBB numbering in MachineFunction::reset()
No need to waste space nor number MBBs differently if MF gets recreated.
Reviewers: qcolombet, stoklund, t.p.northover, bogner, javed.absar
Reviewed By: qcolombet
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331213
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Sanjay Patel [Mon, 30 Apr 2018 18:20:33 +0000 (18:20 +0000)]
[DAGCombiner] rename function attribute for disabling ftrunc transform
This is the matching name change for the Clang patch at:
D46236
rL331209
Differential Revision: https://reviews.llvm.org/D46237
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331210
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Simon Pilgrim [Mon, 30 Apr 2018 18:18:38 +0000 (18:18 +0000)]
[X86] Introduce X86SchedWriteWidths schedule wrapper for different vector widths.
We need to split most of the scheduler classes by vector width to remove more of the InstRW overrides, this patch should make this easier/tidier by allowing us to pass the X86SchedWriteWidths wrapper to multi-width multiclasses and then split as required.
I've included fields for Scl (scalar float/double), MMX (MMX integer), XMM, YMM and ZMM widths. These fields mostly share the same classes but it should give us the flexibility that we may need in the future.
This patch has replaced a set of example SSE/AVX512 instruction cases but isn't exhaustive as it gets very noisy before we really need the functionality.
Differential Revision: https://reviews.llvm.org/D46266
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331208
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Roman Lebedev [Mon, 30 Apr 2018 17:59:33 +0000 (17:59 +0000)]
[InstCombine] Unfold masked merge with constant mask
Summary:
As discussed in D45733, we want to do this in InstCombine.
https://rise4fun.com/Alive/LGk
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: chandlerc, xbolva00, llvm-commits
Differential Revision: https://reviews.llvm.org/D45867
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331205
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Roman Lebedev [Mon, 30 Apr 2018 17:59:26 +0000 (17:59 +0000)]
[InstCombine][NFC] Add tests for unfolding masked merge with constant mask
Summary: As discussed in D45733, we want to do this in InstCombine.
Differential Revision: https://reviews.llvm.org/D45866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331204
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Ulrich Weigand [Mon, 30 Apr 2018 17:54:28 +0000 (17:54 +0000)]
[SystemZ] Handle SADDO et.al. and ADD/SUBCARRY
This provides an optimized implementation of SADDO/SSUBO/UADDO/USUBO
as well as ADDCARRY/SUBCARRY on top of the new CC implementation.
In particular, multi-word arithmetic now uses UADDO/ADDCARRY instead
of the old ADDC/ADDE logic, which means we no longer need to use
"glue" links for those instructions. This also allows making full
use of the memory-based instructions like ALSI, which couldn't be
recognized due to limitations in the DAG matcher previously.
Also, the llvm.sadd.with.overflow et.al. intrinsincs now expand to
directly using the ADD instructions and checking for a CC 3 result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331203
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Ulrich Weigand [Mon, 30 Apr 2018 17:52:32 +0000 (17:52 +0000)]
[SystemZ] Do not use glue to represent condition code dependencies
Currently, an instruction setting the condition code is linked to
the instruction using the condition code via a "glue" link in the
SelectionDAG. This has a number of drawbacks; in particular, it
means the same CC cannot be used by multiple users. It also makes
it more difficult to efficiently implement SADDO et. al.
This patch changes the back-end to represent CC dependencies as
normal values during SelectionDAG matching, along the lines of
how this is handled in the X86 back-end already.
In addition to the core mechanics of updating all relevant patterns,
this requires a number of additional changes:
- We now need to be able to spill/restore a CC value into a GPR
if necessary. This means providing a copyPhysReg implementation
for moves involving CC, and defining getCrossCopyRegClass.
- Since we still prefer to avoid such spills, we provide an override
for IsProfitableToFold to avoid creating a merged LOAD / ICMP if
this would result in multiple users of the CC.
- combineCCMask no longer requires a single CC user, and no longer
need to be careful about preventing invalid glue/chain cycles.
- emitSelect needs to be more careful in marking CC live-in to
the basic block it generates. Also, we can now optimize the
case of multiple subsequent selects with the same condition
just like X86 does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331202
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Daniel Sanders [Mon, 30 Apr 2018 17:20:01 +0000 (17:20 +0000)]
Fix infinite loop after r331115
There are two separate fixes here:
* The lowering code for non-extending loads should report UnableToLegalize instead of emitting the same instruction.
* The target should not be requesting lowering of non-extending loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331201
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Jonas Devlieghere [Mon, 30 Apr 2018 17:02:41 +0000 (17:02 +0000)]
[DebugInfo] Prevent infinite recursion for malformed DWARF
This prevents infinite recursion in DWARFDie::findRecursively for
malformed DWARF where a DIE references itself.
This fixes PR36257.
Differential revision: https://reviews.llvm.org/D43092
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331200
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Davide Italiano [Mon, 30 Apr 2018 16:57:33 +0000 (16:57 +0000)]
[SLPVectorizer] Debug info shouldn't impact spill cost computation.
<rdar://problem/
39794738>
(Also, PR32761).
Differential Revision: https://reviews.llvm.org/D46199
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331199
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Simon Pilgrim [Mon, 30 Apr 2018 16:51:13 +0000 (16:51 +0000)]
[X86][Atom] Remove unnecessary x87 load/move instrw overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331198
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Tom Stellard [Mon, 30 Apr 2018 16:28:02 +0000 (16:28 +0000)]
AMDGPU: Remove some dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331196
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Andrea Di Biagio [Mon, 30 Apr 2018 15:55:04 +0000 (15:55 +0000)]
[llvm-mca] Correctly handle zero-latency stores that consume pipeline resources.
This fixes PR37293.
We can have scheduling classes with no write latency entries, that still consume
processor resources. We don't want to treat those instructions as zero-latency
instructions; they still have to be issued to the underlying pipelines, so they
still consume resource cycles.
This is likely to be a regression which I have accidentally introduced at
revision 330807. Now, if an instruction has a non-empty set of write processor
resources, we conservatively treat it as a normal (i.e. non zero-latency)
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331193
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Ulrich Weigand [Mon, 30 Apr 2018 15:52:28 +0000 (15:52 +0000)]
[SystemZ] Refactor some VT casts in DAG match patterns
In patterns where we need to specify a result VT, prefer
[(set (tr.vt tr.op:$V1), (operator ...))]
over
[(set tr.op:$V1, (tr.vt (operator ...)))]
This is NFC now, but simplifies some future changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331192
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Ulrich Weigand [Mon, 30 Apr 2018 15:49:27 +0000 (15:49 +0000)]
[SystemZ] Improve handling of Select pseudo-instructions
If we have LOCR instructions, select them directly from SelectionDAG
instead of first going through a pseudo instruction and then using
the custom inserter to emit the LOCR.
Provide Select pseudo-instructions for VR32/VR64 if we have vector
instructions, to avoid having to go through the first 16 FPRs
unnecessarily.
If we do not have LOCFHR, prefer using LOCR followed by a move
over a conditional branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331191
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Nico Weber [Mon, 30 Apr 2018 15:26:01 +0000 (15:26 +0000)]
IWYU for llvm-config.h, removals. Also see r331184.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331190
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Simon Pilgrim [Mon, 30 Apr 2018 15:18:33 +0000 (15:18 +0000)]
[X86] Drop unnecessary VPORrm InstrRW override in SkylakeServer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331188
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Simon Pilgrim [Mon, 30 Apr 2018 15:17:16 +0000 (15:17 +0000)]
[X86] Fix SkylakeServer typo in WritePSADBW class - it only uses 1 resource.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331187
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Tom Stellard [Mon, 30 Apr 2018 15:15:23 +0000 (15:15 +0000)]
AMDGPU/GlobalISel: Don't try to lower geometry shaders
Summary: The AMDGPU_GS calling convention is not supported yet.
Reviewers: arsenm, nhaehnle
Reviewed By: nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D46041
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331186
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Nico Weber [Mon, 30 Apr 2018 14:59:11 +0000 (14:59 +0000)]
IWYU for llvm-config.h in llvm, additions.
See r331124 for how I made a list of files missing the include.
I then ran this Python script:
for f in open('filelist.txt'):
f = f.strip()
fl = open(f).readlines()
found = False
for i in xrange(len(fl)):
p = '#include "llvm/'
if not fl[i].startswith(p):
continue
if fl[i][len(p):] > 'Config':
fl.insert(i, '#include "llvm/Config/llvm-config.h"\n')
found = True
break
if not found:
print 'not found', f
else:
open(f, 'w').write(''.join(fl))
and then looked through everything with `svn diff | diffstat -l | xargs -n 1000 gvim -p`
and tried to fix include ordering and whatnot.
No intended behavior change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331184
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Bjorn Pettersson [Mon, 30 Apr 2018 14:37:46 +0000 (14:37 +0000)]
[BranchFolding] Salvage DBG_VALUE instructions from empty blocks
Summary:
This patch will introduce copying of DBG_VALUE instructions
from an otherwise empty basic block to predecessor/successor
blocks in case the empty block is eliminated/bypassed. It
is currently only done in one identified situation in the
BranchFolding pass, before optimizing on empty block.
It can be seen as a light variant of the propagation done
by the LiveDebugValues pass, which unfortunately is executed
after the BranchFolding pass.
We only propagate (copy) DBG_VALUE instructions in a limited
number of situations:
a) If the empty BB is the only predecessor of a successor
we can copy the DBG_VALUE instruction to the beginning of
the successor (because the DBG_VALUE instruction is always
part of the flow between the blocks).
b) If the empty BB is the only successor of a predecessor
we can copy the DBG_VALUE instruction to the end of the
predecessor (because the DBG_VALUE instruction is always
part of the flow between the blocks). In this case we add
the DBG_VALUE just before the first terminator (assuming
that the terminators do not impact the DBG_VALUE).
A future solution, to handle more situations, could perhaps
be to run the LiveDebugValues pass before branch folding?
This fix is related to PR37234. It is expected to resolve
the problem seen, when applied together with the fix in
SelectionDAG from here: https://reviews.llvm.org/D46129
Reviewers: #debug-info, aprantl, rnk
Reviewed By: #debug-info, aprantl
Subscribers: ormris, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D46184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331183
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Bjorn Pettersson [Mon, 30 Apr 2018 14:37:39 +0000 (14:37 +0000)]
[SelectionDAG] Improve selection of DBG_VALUE using a PHI node result
Summary:
When building the selection DAG at ISel all PHI nodes are
selected and lowered to Machine Instruction PHI nodes before
we start to create any SDNodes. So there are no SDNodes for
values produced by the PHI nodes.
In the past when selecting a dbg.value intrinsic that uses
the value produced by a PHI node we have been handling such
dbg.value intrinsics as "dangling debug info". I.e. we have
not created a SDDbgValue node directly, because there is
no existing SDNode for the PHI result, instead we deferred
the creationg of a SDDbgValue until we found the first use
of the PHI result.
The old solution had a couple of flaws. The position of the
selected DBG_VALUE instruction would end up quite late in a
basic block, and for example not directly after the PHI node
as in the LLVM IR input. And in case there were no use at all
in the basic block the dbg.value could be dropped completely.
This patch introduces a new VREG kind of SDDbgValue nodes.
It is similar to a SDNODE kind of node, but it refers directly
to a virtual register and not a SDNode. When we do selection
for a dbg.value that is using the result of a PHI node we
can do a lookup of the virtual register directly (as it already
is determined for the PHI node) and create a SDDbgValue node
immediately instead of delaying the selection until we find a
use.
This should fix a problem with losing debug info at ISel
as seen in PR37234 (https://bugs.llvm.org/show_bug.cgi?id=37234).
It does not resolve PR37234 completely, because the debug info
is dropped later on in the BranchFolder (see D46184).
Reviewers: #debug-info, aprantl
Reviewed By: #debug-info, aprantl
Subscribers: rnk, gbedwell, aprantl, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D46129
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331182
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Gabor Buella [Mon, 30 Apr 2018 14:21:28 +0000 (14:21 +0000)]
NFC, Avoid a warning on pointer casting in PassPlugin.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331179
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Simon Dardis [Mon, 30 Apr 2018 14:03:35 +0000 (14:03 +0000)]
Revert "[mips] Fix the predicates of jump and branch and link instructions"
That commit broke one of the LLD builders, reverting while I investigate.
This patch reverts r331175.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331178
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Simon Dardis [Mon, 30 Apr 2018 13:37:42 +0000 (13:37 +0000)]
[mips] Fix the predicates of jump and branch and link instructions
Reviewers: smaksimovic, atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D46114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331175
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Florian Hahn [Mon, 30 Apr 2018 13:28:08 +0000 (13:28 +0000)]
[LV] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).
This patch updates some code responsible the skip debug info to use
BasicBlock::instructionsWithoutDebug. I think this makes things
slightly simpler and more direct.
Reviewers: mkuper, rengolin, dcaballe, aprantl, vsk
Reviewed By: rengolin
Differential Revision: https://reviews.llvm.org/D46254
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331174
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Benjamin Kramer [Mon, 30 Apr 2018 12:48:45 +0000 (12:48 +0000)]
[bindings] Fix dibuilder go bindings after r331114.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331171
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Andrea Di Biagio [Mon, 30 Apr 2018 12:13:04 +0000 (12:13 +0000)]
[llvm-mca] Regenerate test Atom/resources-sse3.s. NFC
Before this change, it wrongly specified -mcpu=slm instead of -mcpu=atom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331170
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Andrea Di Biagio [Mon, 30 Apr 2018 12:05:34 +0000 (12:05 +0000)]
[llvm-mca] Support for in-order CPU for -instruction-tables testing.
Added Intel Atom tests to verify that the tool correctly generates instruction
tables even if the CPU is in-order.
Fixes PR37282.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331169
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Simon Pilgrim [Mon, 30 Apr 2018 10:46:35 +0000 (10:46 +0000)]
[X86] Fix typo in skylake-avx512 model for PMAXSD/PMINSD instructions
The PMAXSD/PMINSD instregexs had been written as PMAX(C?)SD - looks like this was a search+replace error when matching float MAXSD/MINSD commutative instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331167
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Gabor Buella [Mon, 30 Apr 2018 10:18:11 +0000 (10:18 +0000)]
NFC - Typo fixes lib/VMCore -> lib/IR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331166
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Simon Dardis [Mon, 30 Apr 2018 09:44:44 +0000 (09:44 +0000)]
[mips] Fix microMIPS loads and stores.
Previously these instructions were unselectable and instead were generated
through the instruction mapping tables.
Reviewers: atanasyan, smaksimovic, abeserminji
Differential Revision: https://reviews.llvm.org/D46055
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331165
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Sander de Smalen [Mon, 30 Apr 2018 07:24:38 +0000 (07:24 +0000)]
[AArch64][SVE] Asm: Improve diagnostics for gather loads.
This patch extends the 'isSVEVectorRegWithShiftExtend' function to
improve diagnostics for SVE's gather load (scalar + vector) addressing
modes. Instead of always suggesting the 'unscaled' addressing mode,
the use of DiagnosticPredicate enables a more specific error message
in the context where the scaling is incorrect. For example:
ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
^
shift amount should be '1'
Instead of suggesting the packed, unscaled addressing mode:
expected 'z[0..31].d, (uxtw|sxtw)'
the assembler now suggests using the proper scaling:
expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D46124
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331162
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Craig Topper [Mon, 30 Apr 2018 06:21:24 +0000 (06:21 +0000)]
[X86] Add a Requires<[In64BitMode]> to FARJMP64
Otherwise we can try to assemble it in 32-bit mode and throw an assert in the encoder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331161
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Craig Topper [Mon, 30 Apr 2018 06:21:23 +0000 (06:21 +0000)]
[X86] Hide another instruction from the assembly matcher table to avoid a duplicate entry. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331160
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Craig Topper [Mon, 30 Apr 2018 06:21:22 +0000 (06:21 +0000)]
[X86] Remove some InstAliases aren't needed because a MnemonicAlias makes them unreachable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331159
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Craig Topper [Mon, 30 Apr 2018 06:21:21 +0000 (06:21 +0000)]
[X86] Remove some instructions from the Intel assembly matcher table as there are equivalent mode aware InstAliases that conflict.
The instructions have predicates of Not64BitMode, but there are identical strings in InstAliases that have Mode32Bit and Mode16Bit. But the ordering is uncontrolled and the less specific Not64BitMode was ordered first.
This patch hides the Not64BitMode from the table so there is no conflict anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331158
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Craig Topper [Mon, 30 Apr 2018 06:21:19 +0000 (06:21 +0000)]
[X86] Use a MnemonicAlias instead of an InstAlias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331157
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Craig Topper [Mon, 30 Apr 2018 01:53:12 +0000 (01:53 +0000)]
[X86] Remove support for accepting 'fnstsw %eax' and 'fnstsw %al'.
I assume this was done because gas accepted it at one point, but current versions of gas don't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331154
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Craig Topper [Mon, 30 Apr 2018 01:53:10 +0000 (01:53 +0000)]
[X86] Mark some more InstAliases as 'att' syntax only.
These aliases are used to default the memory forms of call and jmp to the size of the operating mode. This doesn't work for Intel syntax. We have a different hack in the AsmParser code itself to force a size on unsized memory operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331153
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Nico Weber [Mon, 30 Apr 2018 00:08:06 +0000 (00:08 +0000)]
Remove a dead #ifdef.
Unix/Threading.inc should never be included on _WIN32. See also
https://reviews.llvm.org/D30526#
1082292
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331151
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Craig Topper [Sun, 29 Apr 2018 22:55:54 +0000 (22:55 +0000)]
[X86] Make 64-bit sysret/sysexit not ambiguous in Intel assembly syntax.
This also makes it default to the 32-bit non REX.W version in 64-bit mode. This seems to be more consistent with gas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331149
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Simon Pilgrim [Sun, 29 Apr 2018 18:18:51 +0000 (18:18 +0000)]
[X86] Remove unnecessary BT InstRW overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331147
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Sander de Smalen [Sun, 29 Apr 2018 18:18:21 +0000 (18:18 +0000)]
[AArch64][AsmParser] NFC: Cleanup of addOperands functions
Most of the add<operandname>Operands() functions are the same
and can be replaced by using a single 'RenderMethod' in
the AArch64InstrFormats.td file. Since many of the scaled
immediates (with different scaling/bits) are the same, most of
these can reuse the same AsmOperandClass.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: samparker
Differential Revision: https://reviews.llvm.org/D46122
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331146
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Sander de Smalen [Sun, 29 Apr 2018 17:33:38 +0000 (17:33 +0000)]
[AArch64][SVE] Asm: Support for gather LD1/LDFF1 (vector + imm) load instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46120
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331145
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Simon Pilgrim [Sun, 29 Apr 2018 15:45:31 +0000 (15:45 +0000)]
[llvm-mca][X86] Add BT resource tests to all models
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331144
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Simon Pilgrim [Sun, 29 Apr 2018 15:33:15 +0000 (15:33 +0000)]
[X86] Merge more instregex single matches to reduce InstrRW compile time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331143
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Simon Pilgrim [Sun, 29 Apr 2018 14:16:17 +0000 (14:16 +0000)]
[X86] Remove unnecessary add/adc+sub/sbb InstRW overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331142
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Simon Pilgrim [Sun, 29 Apr 2018 11:03:25 +0000 (11:03 +0000)]
[llvm-mca][X86] Add add/adc + sub/sbb resource tests to all models
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331140
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Hideki Saito [Sun, 29 Apr 2018 07:26:18 +0000 (07:26 +0000)]
[NFC][LV][LoopUtil] Move LoopVectorizationLegality to its own file
Summary:
This is a follow up to D45420 (included here since it is still under review and this change is dependent on that) and D45072 (committed).
Actual change for this patch is LoopVectorize* and cmakefile. All others are all from D45420.
LoopVectorizationLegality is an analysis and thus really belongs to Analysis tree. It is modular enough and it is reusable enough ---- we can further improve those aspects once uses outside of LV picks up.
Hopefully, this will make it easier for people familiar with vectorization theory, but not necessarily LV itself to contribute, by lowering the volume of code they should deal with. We probably should start adding some code in LV to check its own capability (i.e., vectorization is legal but LV is not ready to handle it) and then bail out.
Reviewers: rengolin, fhahn, hfinkel, mkuper, aemerson, mssimpso, dcaballe, sguggill
Reviewed By: rengolin, dcaballe
Subscribers: egarcia, rogfer01, mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D45552
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331139
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Craig Topper [Sun, 29 Apr 2018 06:24:09 +0000 (06:24 +0000)]
[X86] Add suffixes to the LGDT/LIDT/SGDT/SIDT mnemonics in Intel syntax. Add aliases based on 16/32-bit mode to choose the default.
This allows the instruction selection to follow mode in Intel syntax. And allows a suffix to be used to change size.
This matches gas behavior from what I could tell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331138
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Craig Topper [Sun, 29 Apr 2018 04:50:53 +0000 (04:50 +0000)]
[X86] Remove SLDT64m instruction.
It doesn't really exist. The instruction always writes 16-bits of memory. Putting a REX.w on it won't change anything.
While I was touching the encoding tests to remove it, I added some other missing register form test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331135
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Craig Topper [Sun, 29 Apr 2018 04:06:02 +0000 (04:06 +0000)]
[X86] Remove unnecessary InstAliases. NFCI
These used to disambiguate MOV16ms/MOV16sm from other size instructions that no longer exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331134
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whitequark [Sun, 29 Apr 2018 02:01:34 +0000 (02:01 +0000)]
[LLVM-C] Eliminate an unused variable in a test.
This was introduced in r331123 and broke -Werror bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331132
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Rafael Espindola [Sun, 29 Apr 2018 01:13:57 +0000 (01:13 +0000)]
Update my email address and description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331131
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Craig Topper [Sun, 29 Apr 2018 00:53:10 +0000 (00:53 +0000)]
[X86] Use getX86SubSuperRegister in addGR32orGR64Operands in the AsmParser instead of duplicating its functionality. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331128
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Nico Weber [Sun, 29 Apr 2018 00:45:03 +0000 (00:45 +0000)]
s/LLVM_ON_WIN32/_WIN32/, llvm
LLVM_ON_WIN32 is set exactly with MSVC and MinGW (but not Cygwin) in
HandleLLVMOptions.cmake, which is where _WIN32 defined too. Just use the
default macro instead of a reinvented one.
See thread "Replacing LLVM_ON_WIN32 with just _WIN32" on llvm-dev and cfe-dev.
No intended behavior change.
This moves over all uses of the macro, but doesn't remove the definition
of it in (llvm-)config.h yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331127
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Robert Widmann [Sat, 28 Apr 2018 22:32:07 +0000 (22:32 +0000)]
[LLVM-C] Add DIBuilder bindings to create import declarations
Summary: Add bindings to create import declarations for modules, functions, types, and other entities. This wraps the conveniences available in the existing DIBuilder API, but these seem C++-specific.
Reviewers: whitequark, harlanhaskins, deadalnix
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46167
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331123
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Craig Topper [Sat, 28 Apr 2018 18:46:11 +0000 (18:46 +0000)]
[X86] Restrict many of the InstAliases to either to only att or intel syntax. NFCI
Many of these aliases exist to give one syntax or the other a slightly different mnemonic and the other variant gets a duplicate of its normal mnemonic
This patch restricts a lot of these to only one variant so we don't get the duplication.
This removes a lot of duplicate entries from the matcher table. It also reduces the number of warnings printed when you enable the ambiguous match warning in tablegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331117
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Simon Pilgrim [Sat, 28 Apr 2018 18:45:16 +0000 (18:45 +0000)]
[X86] Remove unnecessary rotate-carry folded InstRW overrides.
Merge some remaining instregex entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331116
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Daniel Sanders [Sat, 28 Apr 2018 18:14:50 +0000 (18:14 +0000)]
[globalisel][legalizerinfo] Introduce dedicated extending loads and add lowerings for them
Summary:
Previously, a extending load was represented at (G_*EXT (G_LOAD x)).
This had a few drawbacks:
* G_LOAD had to be legal for all sizes you could extend from, even if
registers didn't naturally hold those sizes.
* All sizes you could extend from had to be allocatable just in case the
extend went missing (e.g. by optimization).
* At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we
improve optimization of extends and truncates, this legality requirement
would spread without considerable care w.r.t when certain combines were
permitted.
* The SelectionDAG importer required some ugly and fragile pattern
rewriting to translate patterns into this style.
This patch begins changing the representation to:
* (G_[SZ]EXTLOAD x)
* (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits()
which resolves these issues by allowing targets to work entirely in their
native register sizes, and by having a more direct translation from
SelectionDAG patterns.
This patch introduces the new generic instructions and new variation on
G_LOAD and adds lowering for them to convert back to the existing
representations.
Depends on D45466
Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, aemerson, javed.absar
Reviewed By: aemerson
Subscribers: aemerson, kristof.beyls, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D45540
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331115
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Robert Widmann [Sat, 28 Apr 2018 18:13:39 +0000 (18:13 +0000)]
[LLVM-C] Miscellaneous Cleanups in DIBuilder Bindings
Summary:
* rL328953 does not include bindings for LLVMDIBuilderCreateClassType and LLVMDIBuilderCreateBitFieldMemberType despite declaring their prototypes. Provide these bindings now.
* Switch to more precise types with specific numeric limits matching the DIBuilder's C++ API.
Reviewers: harlanhaskins, whitequark, deadalnix
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46168
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331114
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Roman Lebedev [Sat, 28 Apr 2018 15:45:07 +0000 (15:45 +0000)]
[InstCombine] Canonicalize variable mask in masked merge
Summary:
Masked merge has a pattern of: `((x ^ y) & M) ^ y`.
But, there is no difference between `((x ^ y) & M) ^ y` and `((x ^ y) & ~M) ^ x`,
We should canonicalize the pattern to non-inverted mask.
https://rise4fun.com/Alive/Yol
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45664
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331112
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Roman Lebedev [Sat, 28 Apr 2018 15:45:00 +0000 (15:45 +0000)]
[InstCombine][NFC] Add tests for variable mask canonicalization in masked merge
Summary:
Masked merge has a pattern of: `((x ^ y) & M) ^ y`.
But, there is no difference between `((x ^ y) & M) ^ y` and `((x ^ y) & ~M) ^ x`,
We should canonicalize the pattern to non-inverted mask.
Differential Revision: https://reviews.llvm.org/D45663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331111
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Simon Pilgrim [Sat, 28 Apr 2018 15:32:19 +0000 (15:32 +0000)]
[X86] Remove unnecessary shift/rotate folded InstRW overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331110
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Simon Pilgrim [Sat, 28 Apr 2018 15:18:49 +0000 (15:18 +0000)]
[llvm-mca][X86] Add double shift resource tests to all relevant models
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331109
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Simon Pilgrim [Sat, 28 Apr 2018 14:56:18 +0000 (14:56 +0000)]
[llvm-mca][X86] Add shift/rotate resource tests to all relevant models
I intend to add further instruction tests to the resources-x86_64.s test file as required, but this initial commit is to help remove a load of unnecessary InstRW overrides in a future patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331108
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Simon Pilgrim [Sat, 28 Apr 2018 14:08:51 +0000 (14:08 +0000)]
[X86][SSE] Stop hard coding some instruction scheduler classes.
Make these arguments to the multiclass to allow easier specialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331107
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Simon Pilgrim [Sat, 28 Apr 2018 14:06:28 +0000 (14:06 +0000)]
[X86][HW] Cleanup Haswell model. NFCI.
Moved LAHF/SAHF to instrs instead of instregex.
Removed some unnecessary instregex entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331106
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Craig Topper [Sat, 28 Apr 2018 06:58:27 +0000 (06:58 +0000)]
[X86] Remove mayLoad flag from BNDMK/BNDCL/BNDCN/BNDCU.
The instruction documentation specifically says that these instruction don't access memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331105
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