OSDN Git Service
Laurent Vivier [Fri, 12 Mar 2021 21:41:43 +0000 (22:41 +0100)]
m68k: add an interrupt controller
A (generic) copy of the GLUE device we already have for q800 to use with
the m68k-virt machine.
The q800 one would disappear in the future as q800 uses actually the djMEMC
controller.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210312214145.
2936082-4-laurent@vivier.eu>
Laurent Vivier [Fri, 12 Mar 2021 21:41:42 +0000 (22:41 +0100)]
hw/intc: add goldfish-pic
Implement the goldfish pic device as defined in
https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210312214145.
2936082-3-laurent@vivier.eu>
Laurent Vivier [Fri, 12 Mar 2021 21:41:41 +0000 (22:41 +0100)]
hw/char: add goldfish-tty
Implement the goldfish tty device as defined in
https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT
and based on the kernel driver code:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/tty/goldfish.c
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210312214145.
2936082-2-laurent@vivier.eu>
Peter Maydell [Mon, 15 Mar 2021 16:59:55 +0000 (16:59 +0000)]
Merge remote-tracking branch 'remotes/philmd/tags/avr-
20210315' into staging
AVR patches queue
- Only reset 'interrupt_request' mask once all interrupts executed
- Documentation and typo fixes
# gpg: Signature made Sun 14 Mar 2021 23:45:34 GMT
# gpg: using RSA key
FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd/tags/avr-
20210315:
target/avr: Fix interrupt execution
target/avr: Fix some comment spelling errors
hw/avr/arduino: List board schematic links
hw/misc/led: Add yellow LED
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Mon, 15 Mar 2021 15:34:27 +0000 (15:34 +0000)]
Merge remote-tracking branch 'remotes/bkoppelmann2/tags/pull-tricore-
20210314' into staging
- Added triboard with tc27x_soc
- Cleaned up get_physical_address()
- Fixed corner case bugs in OPC2_32_RRPW_IMASK and OPC2_32_RRPW_IMASK
insns
# gpg: Signature made Sun 14 Mar 2021 13:53:11 GMT
# gpg: using RSA key
6E636A7E83F2DD0CFA6E6E370AD2C6396B69CA14
# gpg: issuer "kbastian@mail.uni-paderborn.de"
# gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" [full]
# Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E 6E37 0AD2 C639 6B69 CA14
* remotes/bkoppelmann2/tags/pull-tricore-
20210314:
target/tricore: Fix OPC2_32_RRPW_EXTR for width=0
target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2
tricore: fixed faulty conditions for extr and imask
target/tricore: Remove unused definitions
target/tricore: Pass MMUAccessType to get_physical_address()
target/tricore: Replace magic value by MMU_DATA_LOAD definition
tricore: added triboard with tc27x_soc
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Ivanov Arkasha [Fri, 12 Mar 2021 16:47:54 +0000 (19:47 +0300)]
target/avr: Fix interrupt execution
Only one interrupt is in progress at the moment.
It is only necessary to set to reset interrupt_request
after all interrupts have been executed.
Signed-off-by: Ivanov Arkasha <ivanovrkasha@gmail.com>
Message-Id: <
20210312164754.18437-1-arkaisp2021@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
Lichang Zhao [Fri, 9 Oct 2020 06:44:46 +0000 (14:44 +0800)]
target/avr: Fix some comment spelling errors
I found that there are many spelling errors in the comments of qemu/target/avr.
I used spellcheck to check the spelling errors and found some errors in the folder.
Signed-off-by: Lichang Zhao <zhaolichang@huawei.com>
Reviewed-by: David Edmondson <david.edmondson@oracle.com>
Reviewed-by: Philippe Mathieu-Daude<f4bug@amsat.org>
Message-Id: <
20201009064449.2336-12-zhaolichang@huawei.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
Philippe Mathieu-Daudé [Sat, 13 Mar 2021 15:18:19 +0000 (16:18 +0100)]
hw/avr/arduino: List board schematic links
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
Message-Id: <
20210313165445.
2113938-3-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sat, 13 Mar 2021 15:18:34 +0000 (16:18 +0100)]
hw/misc/led: Add yellow LED
Add the yellow "lime" LED.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
Message-Id: <
20210313165445.
2113938-2-f4bug@amsat.org>
Peter Maydell [Sun, 14 Mar 2021 19:16:11 +0000 (19:16 +0000)]
Merge remote-tracking branch 'remotes/philmd/tags/mips-
20210313' into staging
MIPS patches queue
- Tidy up the GT64120 north bridge
- Move XBurst Media eXtension Unit code to mxu_translate.c
- Convert TX79 to decodetree
# gpg: Signature made Sat 13 Mar 2021 22:44:44 GMT
# gpg: using RSA key
FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd/tags/mips-
20210313: (27 commits)
target/mips/tx79: Salvage instructions description comment
target/mips: Remove 'C790 Multimedia Instructions' dead code
target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree
target/mips/tx79: Move PCPYH opcode to decodetree
target/mips/translate: Simplify PCPYH using deposit_i64()
target/mips/translate: Make gen_rdhwr() public
target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree
target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree
target/mips: Use gen_load_gpr[_hi]() when possible
target/mips: Extract MXU code to new mxu_translate.c file
target/mips: Introduce mxu_translate_init() helper
target/mips: Simplify decode_opc_mxu() ifdef'ry
target/mips: Convert decode_ase_mxu() to decodetree prototype
target/mips: Rename decode_opc_mxu() as decode_ase_mxu()
target/mips: Move MUL opcode check from decode_mxu() to decode_legacy()
target/mips: Use OPC_MUL instead of OPC__MXU_MUL
target/mips: Pass instruction opcode to decode_opc_mxu()
target/mips: Remove unused CPUMIPSState* from MXU functions
target/mips: Remove XBurst Media eXtension Unit dead code
target/mips: Rewrite complex ifdef'ry
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Sun, 14 Mar 2021 17:47:49 +0000 (17:47 +0000)]
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-6.0-pull-request' into staging
linux-user pull request
20210313
- fix elfload
- fix executable page of /proc/self/maps
- add preserve-arg[0] support for binfmt_misc
# gpg: Signature made Sat 13 Mar 2021 09:47:23 GMT
# gpg: using RSA key
CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg: issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier2/tags/linux-user-for-6.0-pull-request:
linux-user/elfload: fix address calculation in fallback scenario
linux-user/elfload: do not assume MAP_FIXED_NOREPLACE kernel support
linux-user/elfload: munmap proper address in pgd_find_hole_fallback
linux-user: manage binfmt-misc preserve-arg[0] flag
linux-user: Fix executable page of /proc/self/maps
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Sun, 14 Mar 2021 15:13:53 +0000 (15:13 +0000)]
Merge remote-tracking branch 'remotes/thuth-gitlab/tags/pull-request-2021-03-12' into staging
* Move unit and bench tests into separate directories
* Clean-up and improve gitlab-ci jobs
* Drop the non-working "check-speed" makefile target
* Minor documentation updates
# gpg: Signature made Fri 12 Mar 2021 17:18:45 GMT
# gpg: using RSA key
27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* remotes/thuth-gitlab/tags/pull-request-2021-03-12:
README: Add Documentation blurb
MAINTAINERS: Merge the Gitlab-CI section into the generic CI section
tests: remove "make check-speed" in favor of "make bench"
gitlab-ci.yml: Merge check-crypto-old jobs into the build-crypto-old jobs
gitlab-ci.yml: Merge one of the coroutine jobs with the tcg-disabled job
gitlab-ci.yml: Add some missing dependencies to the jobs
gitlab-ci.yml: Move build-tools-and-docs-debian to a better place
tests: Move benchmarks into a separate folder
tests: Move unit tests into a separate directory
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Bastian Koppelmann [Fri, 5 Mar 2021 13:06:38 +0000 (14:06 +0100)]
target/tricore: Fix OPC2_32_RRPW_EXTR for width=0
if width was 0 we would run into the assertion:
qemu-system-tricore: tcg/tcg-op.c:217: tcg_gen_sari_i32: Assertion `arg2 >= 0 && arg2 < 32' failed.o
The instruction manual specifies undefined behaviour for this case. So
we bring this in line with the golden Infineon simlator 'tsim', which
simply writes 0 to the result in case of width=0.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Bastian Koppelmann [Fri, 5 Mar 2021 13:03:51 +0000 (14:03 +0100)]
target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2
if r3+1 and r2 are the same then we would overwrite r2 with our first
move and use the wrong result for the shift. Thus we store the result
from the mov in a temp.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Andreas Konopik [Thu, 11 Feb 2021 11:53:29 +0000 (12:53 +0100)]
tricore: fixed faulty conditions for extr and imask
According to the TC 1.3.1. Architecture Manual [1; page 174], results are
undefined, if pos + width > 32 and not 31 or if width = 0.
We found this error because of a different behavior between qemu-tricore
and the real tricore processor. For pos + width = 32, qemu-tricore did not
generate any intermediate code and ran into a different state compared to
the real hardware.
[1] https://www.infineon.com/dgdl/tc_v131_instructionset_v138.pdf?fileId=
db3a304412b407950112b409b6dd0352
[BK: Add the why to the commit message]
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de>
Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
Signed-off-by: David Brenken <david.brenken@efs-auto.de>
Message-Id: <
20210211115329.8984-2-david.brenken@efs-auto.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Philippe Mathieu-Daudé [Wed, 27 Jan 2021 22:42:55 +0000 (23:42 +0100)]
target/tricore: Remove unused definitions
Remove these confusing and unused definitions.
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210127224255.
3505711-4-f4bug@amsat.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Philippe Mathieu-Daudé [Wed, 27 Jan 2021 22:42:54 +0000 (23:42 +0100)]
target/tricore: Pass MMUAccessType to get_physical_address()
'int access_type' and ACCESS_INT are unused, drop them.
Provide the mmu_idx argument to match other targets.
'int rw' is actually the MMUAccessType, rename it.
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210127224255.
3505711-3-f4bug@amsat.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Philippe Mathieu-Daudé [Wed, 27 Jan 2021 22:42:53 +0000 (23:42 +0100)]
target/tricore: Replace magic value by MMU_DATA_LOAD definition
cpu_get_phys_page_debug() uses 'DATA LOAD' MMU access type.
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210127224255.
3505711-2-f4bug@amsat.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Andreas Konopik [Mon, 9 Nov 2020 16:50:55 +0000 (17:50 +0100)]
tricore: added triboard with tc27x_soc
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de>
Signed-off-by: David Brenken <david.brenken@efs-auto.de>
Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de>
Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de>
Message-Id: <
20201109165055.10508-2-david.brenken@efs-auto.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Peter Maydell [Sun, 14 Mar 2021 13:18:49 +0000 (13:18 +0000)]
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-
20210314' into staging
target-arm queue:
* versal: Support XRAMs and XRAM controller
* smmu: Various minor bug fixes
* SVE emulation: fix bugs handling odd vector lengths
* allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC register value
* tests/acceptance: fix orangepi-pc acceptance tests
* hw/timer/sse-timer: Propagate eventual error in sse_timer_realize()
* hw/arm/virt: KVM: The IPA lower bound is 32
* npcm7xx: support MFT module
* pl110, pxa2xx_lcd: tidy up template headers
# gpg: Signature made Sun 14 Mar 2021 13:17:43 GMT
# gpg: using RSA key
E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-
20210314: (39 commits)
hw/display/pxa2xx: Inline template header
hw/display/pxa2xx: Apply whitespace-only coding style fixes to template header
hw/display/pxa2xx: Apply brace-related coding style fixes to template header
hw/display/pxa2xx: Remove use of BITS in pxa2xx_template.h
hw/display/pxa2xx_lcd: Remove dest_width state field
hw/display/pxa2xx_lcd: Remove dead code for non-32-bpp surfaces
hw/display/pl110: Remove use of BITS from pl110_template.h
hw/display/pl110: Pull included-once parts of template header into pl110.c
hw/display/pl110: Remove dead code for non-32-bpp surfaces
tests/qtest: Test PWM fan RPM using MFT in PWM test
hw/arm: Connect PWM fans in NPCM7XX boards
hw/arm: Add MFT device to NPCM7xx Soc
hw/misc: Add NPCM7XX MFT Module
hw/misc: Add GPIOs for duty in NPCM7xx PWM
hw/arm/virt: KVM: The IPA lower bound is 32
accel: kvm: Fix kvm_type invocation
hw/timer/sse-timer: Propagate eventual error in sse_timer_realize()
tests/acceptance: drop ARMBIAN_ARTIFACTS_CACHED condition for orangepi-pc, cubieboard tests
tests/acceptance: update sunxi kernel from armbian to 5.10.16
tests/acceptance/boot_linux_console: change URL for test_arm_orangepi_bionic_20_08
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Thu, 11 Feb 2021 14:15:15 +0000 (14:15 +0000)]
hw/display/pxa2xx: Inline template header
The template header is now included only once; just inline its contents
in hw/display/pxa2xx_lcd.c.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id:
20210211141515.8755-10-peter.maydell@linaro.org
Peter Maydell [Thu, 11 Feb 2021 14:15:14 +0000 (14:15 +0000)]
hw/display/pxa2xx: Apply whitespace-only coding style fixes to template header
We're about to move code from the template header into pxa2xx_lcd.c.
Before doing that, make coding style fixes so checkpatch doesn't
complain about the patch which moves the code. This commit is
whitespace changes only:
* avoid hard-coded tabs
* fix ident on function prototypes
* no newline before open brace on array definitions
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id:
20210211141515.8755-9-peter.maydell@linaro.org
Peter Maydell [Thu, 11 Feb 2021 14:15:13 +0000 (14:15 +0000)]
hw/display/pxa2xx: Apply brace-related coding style fixes to template header
We're about to move code from the template header into pxa2xx_lcd.c.
Before doing that, make coding style fixes so checkpatch doesn't
complain about the patch which moves the code. This commit fixes
missing braces in the SKIP_PIXEL() macro definition and in if()
statements.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id:
20210211141515.8755-8-peter.maydell@linaro.org
Peter Maydell [Thu, 11 Feb 2021 14:15:12 +0000 (14:15 +0000)]
hw/display/pxa2xx: Remove use of BITS in pxa2xx_template.h
Now that BITS is always 32, expand out all its uses in the template
header, including removing now-useless uses of the glue() macro.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id:
20210211141515.8755-7-peter.maydell@linaro.org
Peter Maydell [Thu, 11 Feb 2021 14:15:11 +0000 (14:15 +0000)]
hw/display/pxa2xx_lcd: Remove dest_width state field
Since the dest_width is now always 4 because the output surface is
32bpp, we can replace the dest_width state field with a constant.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id:
20210211141515.8755-6-peter.maydell@linaro.org
Peter Maydell [Thu, 11 Feb 2021 14:15:10 +0000 (14:15 +0000)]
hw/display/pxa2xx_lcd: Remove dead code for non-32-bpp surfaces
For a long time now the UI layer has guaranteed that the console
surface is always 32 bits per pixel. Remove the legacy dead code
from the pxa2xx_lcd display device which was handling the possibility
that the console surface was some other format.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id:
20210211141515.8755-5-peter.maydell@linaro.org
Peter Maydell [Thu, 11 Feb 2021 14:15:09 +0000 (14:15 +0000)]
hw/display/pl110: Remove use of BITS from pl110_template.h
BITS is always 32, so remove all uses of it from the template header,
by dropping the trailing '32' from the draw function names and
not constructing the name of rgb_to_pixel32() via the glue() macro.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id:
20210211141515.8755-4-peter.maydell@linaro.org
Peter Maydell [Thu, 11 Feb 2021 14:15:08 +0000 (14:15 +0000)]
hw/display/pl110: Pull included-once parts of template header into pl110.c
The pl110_template.h header has a doubly-nested multiple-include pattern:
* pl110.c includes it once for each host bit depth (now always 32)
* every time it is included, it includes itself 6 times, to account
for multiple guest device pixel and byte orders
Now we only have to deal with 32-bit host bit depths, we can move the
code corresponding to the outer layer of this double-nesting to be
directly in pl110.c and reduce the template header to a single layer
of nesting.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id:
20210211141515.8755-3-peter.maydell@linaro.org
Peter Maydell [Thu, 11 Feb 2021 14:15:07 +0000 (14:15 +0000)]
hw/display/pl110: Remove dead code for non-32-bpp surfaces
For a long time now the UI layer has guaranteed that the console
surface is always 32 bits per pixel. Remove the legacy dead
code from the pl110 display device which was handling the
possibility that the console surface was some other format.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id:
20210211141515.8755-2-peter.maydell@linaro.org
Philippe Mathieu-Daudé [Sat, 13 Feb 2021 11:19:10 +0000 (12:19 +0100)]
target/mips/tx79: Salvage instructions description comment
This comment describing the tx79 opcodes is helpful. As we
will implement these instructions in tx79_translate.c, move
the comment there.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210214175912.732946-15-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sat, 13 Feb 2021 11:08:28 +0000 (12:08 +0100)]
target/mips: Remove 'C790 Multimedia Instructions' dead code
We have almost 400 lines of code full of /* TODO */ comments
which end calling gen_reserved_instruction().
As we are not going to implement them, and all the caller's
switch() default cases already call gen_reserved_instruction(),
we can remove this altogether.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210214175912.732946-14-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sat, 13 Feb 2021 11:04:43 +0000 (12:04 +0100)]
target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree
Move PCPYLD (Parallel Copy Lower Doubleword) and PCPYUD
(Parallel Copy Upper Doubleword) to decodetree. Remove
unnecessary code / comments.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210214175912.732946-13-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sat, 13 Feb 2021 10:57:56 +0000 (11:57 +0100)]
target/mips/tx79: Move PCPYH opcode to decodetree
Move the existing PCPYH opcode (Parallel Copy Halfword) to decodetree.
Remove unnecessary code / comments.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210214175912.732946-12-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sat, 13 Feb 2021 00:09:57 +0000 (01:09 +0100)]
target/mips/translate: Simplify PCPYH using deposit_i64()
Simplify the PCPYH (Parallel Copy Halfword) instruction by using
multiple calls to deposit_i64() which can be optimized by some
TCG backends.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210214175912.732946-11-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sat, 13 Feb 2021 14:09:18 +0000 (15:09 +0100)]
target/mips/translate: Make gen_rdhwr() public
We will use gen_rdhwr() outside of translate.c, make it public.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210214175912.732946-28-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 14 Feb 2021 16:20:19 +0000 (17:20 +0100)]
target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210214175912.732946-10-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 14 Feb 2021 16:57:24 +0000 (17:57 +0100)]
target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree
Introduce decodetree structure to decode the tx79 opcodes.
Start it by moving the existing MFHI1 and MFLO1 opcodes.
Remove unnecessary comments.
As the TX79 share opcodes with the TX19/TX39/TX49 CPUs,
we introduce the decode_ext_txx9() dispatcher where we
will add the other decoders later.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210214175912.732946-9-f4bug@amsat.org>
Philippe Mathieu-Daudé [Mon, 8 Mar 2021 12:18:06 +0000 (13:18 +0100)]
target/mips: Use gen_load_gpr[_hi]() when possible
Use gen_load_gpr[_hi]() instead of open coding it.
Patch generated using the following spatch script:
@gen_load_gpr@
identifier reg_idx;
expression tcg_reg;
@@
-if (reg_idx == 0) {
- tcg_gen_movi_tl(tcg_reg, 0);
-} else {
- tcg_gen_mov_tl(tcg_reg, cpu_gpr[reg_idx]);
-}
+gen_load_gpr(tcg_reg, reg_idx);
@gen_load_gpr_hi@
identifier reg_idx;
expression tcg_reg;
@@
-if (reg_idx == 0) {
- tcg_gen_movi_i64(tcg_reg, 0);
-} else {
- tcg_gen_mov_i64(tcg_reg, cpu_gpr_hi[reg_idx]);
-}
+gen_load_gpr_hi(tcg_reg, reg_idx);
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210308131604.460693-1-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 17 Feb 2021 20:23:49 +0000 (21:23 +0100)]
target/mips: Extract MXU code to new mxu_translate.c file
Extract 1600+ lines from the big translate.c into a new file.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210226093111.
3865906-14-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 17 Feb 2021 20:21:17 +0000 (21:21 +0100)]
target/mips: Introduce mxu_translate_init() helper
Extract the MXU register initialization code from mips_tcg_init()
as a new mxu_translate_init() helper. Make it public and replace
!TARGET_MIPS64 ifdef'ry by the 'TARGET_LONG_BITS == 32' check to
elide this code at preprocessing time.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210226093111.
3865906-13-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 24 Feb 2021 17:58:26 +0000 (18:58 +0100)]
target/mips: Simplify decode_opc_mxu() ifdef'ry
By making the prototype public and checking
'TARGET_LONG_BITS == 32' we let the compiler
elide the decode_opc_mxu() call.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210226093111.
3865906-12-f4bug@amsat.org>
Philippe Mathieu-Daudé [Thu, 18 Feb 2021 08:45:44 +0000 (09:45 +0100)]
target/mips: Convert decode_ase_mxu() to decodetree prototype
To easily convert MXU code to decodetree, making it return a boolean.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210226093111.
3865906-11-f4bug@amsat.org>
Philippe Mathieu-Daudé [Thu, 18 Feb 2021 08:45:44 +0000 (09:45 +0100)]
target/mips: Rename decode_opc_mxu() as decode_ase_mxu()
Use "decode_{isa,ase,ext}_$name()" function name pattern for
public decodetree entrypoints.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210226093111.
3865906-10-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 24 Feb 2021 17:51:00 +0000 (18:51 +0100)]
target/mips: Move MUL opcode check from decode_mxu() to decode_legacy()
Move the check for MUL opcode from decode_opc_mxu() callee
to decode_opc_legacy() caller, so we can simplify the ifdef'ry
and elide the call in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210226093111.
3865906-9-f4bug@amsat.org>
Philippe Mathieu-Daudé [Thu, 18 Feb 2021 09:19:27 +0000 (10:19 +0100)]
target/mips: Use OPC_MUL instead of OPC__MXU_MUL
We already have a macro and definition to extract / check
the Special2 MUL opcode. Use it instead of the unnecessary
OPC__MXU_MUL macro.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210226093111.
3865906-8-f4bug@amsat.org>
Philippe Mathieu-Daudé [Thu, 18 Feb 2021 08:41:43 +0000 (09:41 +0100)]
target/mips: Pass instruction opcode to decode_opc_mxu()
In the next commit we'll make decode_opc_mxu() match decodetree
prototype by returning a boolean. First pass ctx->opcode as an
argument.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210226093111.
3865906-7-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 17 Feb 2021 19:52:14 +0000 (20:52 +0100)]
target/mips: Remove unused CPUMIPSState* from MXU functions
None of these MXU functions use their CPUMIPSState* env argument,
remove it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210226093111.
3865906-6-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 17 Feb 2021 18:44:50 +0000 (19:44 +0100)]
target/mips: Remove XBurst Media eXtension Unit dead code
All these unimplemented MXU opcodes end up calling
gen_reserved_instruction() which is the default switch
case in decode_opc_mxu().
The translate.c file is already big enough and hard to maintain,
remove 1300 lines of unnecessary code and /* TODO */ comments.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210226093111.
3865906-5-f4bug@amsat.org>
Philippe Mathieu-Daudé [Thu, 18 Feb 2021 09:16:35 +0000 (10:16 +0100)]
target/mips: Rewrite complex ifdef'ry
No need for this obfuscated ifdef'ry, KISS.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210226093111.
3865906-4-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sat, 16 Jan 2021 12:46:09 +0000 (13:46 +0100)]
target/mips/meson: Restrict mips-semi.c to TCG
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210226093111.
3865906-3-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 24 Feb 2021 17:37:27 +0000 (18:37 +0100)]
target/mips/meson: Introduce mips_tcg source set
Introduce the 'mips_tcg' source set to collect TCG specific files.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210226093111.
3865906-2-f4bug@amsat.org>
Philippe Mathieu-Daudé [Thu, 4 Mar 2021 18:02:56 +0000 (19:02 +0100)]
hw/mips/gt64xxx: Trace accesses to ISD registers
Trace all accesses to Internal Space Decode (ISD) registers.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <
20210309142630.728014-6-f4bug@amsat.org>
Philippe Mathieu-Daudé [Tue, 2 Mar 2021 23:10:01 +0000 (00:10 +0100)]
hw/mips/gt64xxx: Rename trace events related to interrupt registers
We want to trace all register accesses. First rename the current
gt64120_read / gt64120_write events with '_intreg' suffix, as they
are restricted to interrupt registers.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <
20210309142630.728014-5-f4bug@amsat.org>
Philippe Mathieu-Daudé [Tue, 2 Mar 2021 23:20:21 +0000 (00:20 +0100)]
hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats
Fix the following typos:
- GT_PCI1_CFGDATA is not a timer register but a PCI one,
- zero-padding flag is out of the format
Fixes:
641ca2bfcd5 ("hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of debug printf()")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <
20210309142630.728014-4-f4bug@amsat.org>
Philippe Mathieu-Daudé [Thu, 4 Mar 2021 18:25:11 +0000 (19:25 +0100)]
hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers
The ISD MemoryRegion is implemented for 32-bit accesses.
Simplify it by setting the MemoryRegionOps::impl min/max
access size fields.
Since the region is registered with a size of 0x1000 bytes,
we can remove the hwaddr mask.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <
20210309142630.728014-3-f4bug@amsat.org>
Philippe Mathieu-Daudé [Tue, 2 Mar 2021 22:39:06 +0000 (23:39 +0100)]
hw/mips/gt64xxx: Initialize ISD I/O memory region in DeviceRealize()
The ISD I/O region belongs to the TYPE_GT64120_PCI_HOST_BRIDGE,
so initialize it before it is realized, not after.
Rename the region as 'gt64120-isd' so it is clearer to realize
it belongs to the GT64120 in the memory tree view.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <
20210309142630.728014-2-f4bug@amsat.org>
Vincent Fazio [Sun, 31 Jan 2021 06:19:48 +0000 (00:19 -0600)]
linux-user/elfload: fix address calculation in fallback scenario
Previously, guest_loaddr was not taken into account when returning an
address from pgb_find_hole when /proc/self/maps was unavailable which
caused an improper guest_base address to be calculated.
This could cause a SIGSEGV later in load_elf_image -> target_mmap for
ET_EXEC type images since the mmap MAP_FIXED flag is specified which
could clobber existing mappings at the address returnd by g2h().
mmap(0xd87000,
16846912, PROT_NONE, MAP_PRIVATE|MAP_ANONYMOUS|MAP_NORESERVE|0x100000, -1, 0) = 0xd87000
munmap(0xd87000,
16846912) = 0
write(2, "Locating guest address space @ 0"..., 40Locating guest address space @ 0xd87000) = 40
mmap(0x1187000,
16850944, PROT_NONE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS|MAP_NORESERVE, -1, 0) = 0x1187000
--- SIGSEGV {si_signo=SIGSEGV, si_code=SEGV_ACCERR, si_addr=0x2188310} ---
+++ killed by SIGSEGV +++
Now, pgd_find_hole accounts for guest_loaddr in this scenario.
Fixes:
ad592e37dfcc ("linux-user: provide fallback pgd_find_hole for bare chroots")
Signed-off-by: Vincent Fazio <vfazio@gmail.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <
20210131061948.15990-1-vfazio@xes-inc.com>
[lv: updated it to check if ret == -1]
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Vincent Fazio [Sun, 31 Jan 2021 06:19:30 +0000 (00:19 -0600)]
linux-user/elfload: do not assume MAP_FIXED_NOREPLACE kernel support
Previously, pgd_find_hole_fallback assumed that if the build host's libc
had MAP_FIXED_NOREPLACE defined that the address returned by mmap would
match the requested address. This is not a safe assumption for Linux
kernels prior to 4.17
Now, we always compare mmap's resultant address with the requested
address and no longer short-circuit based on MAP_FIXED_NOREPLACE.
Fixes:
2667e069e7b5 ("linux-user: don't use MAP_FIXED in pgd_find_hole_fallback")
Signed-off-by: Vincent Fazio <vfazio@gmail.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <
20210131061930.14554-1-vfazio@xes-inc.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Vincent Fazio [Sun, 31 Jan 2021 06:18:49 +0000 (00:18 -0600)]
linux-user/elfload: munmap proper address in pgd_find_hole_fallback
Previously, if the build host's libc did not define MAP_FIXED_NOREPLACE
or if the running kernel didn't support that flag, it was possible for
pgd_find_hole_fallback to munmap an incorrect address which could lead to
SIGSEGV if the range happened to overlap with the mapped address of the
QEMU binary.
mmap(0x1000,
22261224, PROT_NONE, MAP_PRIVATE|MAP_ANONYMOUS|MAP_NORESERVE, -1, 0) = 0x7f889d331000
munmap(0x1000,
22261224) = 0
--- SIGSEGV {si_signo=SIGSEGV, si_code=SEGV_MAPERR, si_addr=0x84b817} ---
++ killed by SIGSEGV +++
Now, always munmap the address returned by mmap.
Fixes:
2667e069e7b5 ("linux-user: don't use MAP_FIXED in pgd_find_hole_fallback")
Signed-off-by: Vincent Fazio <vfazio@gmail.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <
20210131061849.12615-1-vfazio@xes-inc.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Laurent Vivier [Mon, 22 Feb 2021 10:50:04 +0000 (11:50 +0100)]
linux-user: manage binfmt-misc preserve-arg[0] flag
Add --preserve-argv0 in qemu-binfmt-conf.sh to configure the preserve-argv0
flag.
This patch allows to use new flag in AT_FLAGS to detect if
preserve-argv0 is configured for this interpreter:
argv[0] (the full pathname provided by binfmt-misc) is removed and
replaced by argv[1] (the original argv[0] provided by binfmt-misc when
'P'/preserve-arg[0] is set)
For instance with this patch and kernel support for AT_FLAGS:
$ sudo chroot m68k-chroot sh -c 'echo $0'
sh
without this patch:
$ sudo chroot m68k-chroot sh -c 'echo $0'
/usr/bin/sh
The new flag is available in kernel (v5.12) since:
2347961b11d4 ("binfmt_misc: pass binfmt_misc flags to the interpreter")
This can be tested with something like:
# cp ..../qemu-ppc /chroot/powerpc/jessie
# qemu-binfmt-conf.sh --qemu-path / --systemd ppc --credential yes \
--persistent no --preserve-argv0 yes
# systemctl restart systemd-binfmt.service
# cat /proc/sys/fs/binfmt_misc/qemu-ppc
enabled
interpreter //qemu-ppc
flags: POC
offset 0
magic
7f454c4601020100000000000000000000020014
mask
ffffffffffffff00fffffffffffffffffffeffff
# chroot /chroot/powerpc/jessie sh -c 'echo $0'
sh
# qemu-binfmt-conf.sh --qemu-path / --systemd ppc --credential yes \
--persistent no --preserve-argv0 no
# systemctl restart systemd-binfmt.service
# cat /proc/sys/fs/binfmt_misc/qemu-ppc
enabled
interpreter //qemu-ppc
flags: OC
offset 0
magic
7f454c4601020100000000000000000000020014
mask
ffffffffffffff00fffffffffffffffffffeffff
# chroot /chroot/powerpc/jessie sh -c 'echo $0'
/bin/sh
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <
20210222105004.
1642234-1-laurent@vivier.eu>
Nicolas Surbayrole [Mon, 8 Mar 2021 09:19:59 +0000 (10:19 +0100)]
linux-user: Fix executable page of /proc/self/maps
The guest binary and libraries are not always map with the
executable bit in the host process. The guest may read a
/proc/self/maps with no executable address range. The
perm fields should be based on the guest permission inside
Qemu.
Signed-off-by: Nicolas Surbayrole <nsurbayrole@quarkslab.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <
20210308091959.986540-1-nsurbayrole@quarkslab.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Peter Maydell [Fri, 12 Mar 2021 18:56:56 +0000 (18:56 +0000)]
Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-6.0-pull-request' into staging
Prepare MacOS ROM support:
- add RTR instruction
- fix unaligned access requirement
- fix ATC bit (68040 MMU)
# gpg: Signature made Thu 11 Mar 2021 22:18:11 GMT
# gpg: using RSA key
CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg: issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier/tags/m68k-for-6.0-pull-request:
target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature
target/m68k: reformat m68k_features enum
target/m68k: don't set SSW ATC bit for physical bus errors
target/m68k: implement rtr instruction
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
John Snow [Wed, 4 Nov 2020 19:30:32 +0000 (14:30 -0500)]
README: Add Documentation blurb
Add it in a prominent place: Right after figuring out what QEMU is,
users may wish to know how to use it more than they want to know how to
build their own version of it.
Signed-off-by: John Snow <jsnow@redhat.com>
Message-Id: <
20201104193032.
1319248-1-jsnow@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Tue, 9 Mar 2021 11:23:56 +0000 (12:23 +0100)]
MAINTAINERS: Merge the Gitlab-CI section into the generic CI section
The status of the gitlab-CI files is currently somewhat confusing, and
it is often not quite clear whether a patch should go via my tree or
via the testing tree of Alex. That situation has grown historically...
Initially, I was the only one using the gitlab-CI, just for my private
repository there. But in the course of time, the gitlab-CI switched to
use the containers from tests/docker/ (which is not part of the gitlab-CI
section in the MAINTAINERS file), and QEMU now even switched to gitlab.com
completely for the repository and will soon use it as its gating CI, too,
so it makes way more sense if the gitlab-ci.yml files belong to the people
who are owning the qemu-project on gitlab.com and take care of the gitlab
CI there. Thus let's merge the gitlab-ci section into the common "test and
build automation" section.
And while we're at it, I'm also removing the line with Fam there for now,
since he was hardly active during the last years in this area anymore.
If he ever gets more time for this part again in the future, we surely
can add the line back again. I'm also removing the Patchew URL from this
section now since Patchew's files are not tracked in the main QEMU repo
and it is also not maintained by Alex, Philippe and myself.
The maintainers of Patchew are still listed more accurately in the wiki on
https://wiki.qemu.org/AdminContacts & https://wiki.qemu.org/Testing/CI/Patchew
instead.
Now to avoid that Alex is listed here in this section alone, Philippe and
I agreed to help as backup maintainers here, too. And Willian volunteered
to be an additional reviewer.
Message-Id: <
20210309112356.737266-1-thuth@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Acked-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Acked-by: Fam Zheng <fam@euphon.net>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Paolo Bonzini [Wed, 10 Mar 2021 16:46:12 +0000 (17:46 +0100)]
tests: remove "make check-speed" in favor of "make bench"
"make check-speed" has been broken since the removal of ninja2make
last October. It was just a backwards-compatibility alias for
"make bench-speed", which in turn is in principle a subset of
"make bench". Advertise the latter and drop "make check-speed"
completely since no one has noticed.
Reported-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <
20210310164612.285362-1-pbonzini@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Thu, 11 Mar 2021 14:22:11 +0000 (15:22 +0100)]
gitlab-ci.yml: Merge check-crypto-old jobs into the build-crypto-old jobs
Both, the build-crypto-old and the check-crypto-old jobs finish reasonably
fast, and the build artifacts are only used for the single corresponding
check jobs, so there is no reason for doing the check step in a separate
job here. Thus let's stop wasting artifacts space and job scheduler over-
head by simply merging the test step into the build jobs.
Message-Id: <
20210311142211.
1547864-5-thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Thu, 11 Mar 2021 14:22:10 +0000 (15:22 +0100)]
gitlab-ci.yml: Merge one of the coroutine jobs with the tcg-disabled job
Our gitlab-ci got quite slow in the past weeks, due to the immense amount
of jobs that we have, so we should try to reduce the number of jobs.
Since we already have a job that builds without TCG, we can merge
one of the "build-coroutine" jobs with it to get rid of at least one
job.
Message-Id: <
20210311142211.
1547864-4-thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Thu, 11 Mar 2021 14:22:09 +0000 (15:22 +0100)]
gitlab-ci.yml: Add some missing dependencies to the jobs
Let's make sure that all jobs have proper "needs:" statements so that
they can start as soon as possible, without having to wait for the
previous pipeline stage to finish.
Message-Id: <
20210311142211.
1547864-3-thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Thu, 11 Mar 2021 14:22:08 +0000 (15:22 +0100)]
gitlab-ci.yml: Move build-tools-and-docs-debian to a better place
The "build-tools-and-docs-debian" job had been added in between
the "check-system-debian" and the "accepance-system-debian" jobs
and thus separates the jobs that belong together. Move it away,
to the end of the file, next to the "pages" job that depends on it.
And while we're at it, also add a proper "needs:" line to the
job so that it can be started as soon as possible instead of always
waiting for the previous stage to finish.
Message-Id: <
20210311142211.
1547864-2-thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Fri, 12 Mar 2021 09:22:38 +0000 (10:22 +0100)]
tests: Move benchmarks into a separate folder
Make it clear that these files are related to benchmarks by moving
them into a new folder called "bench".
Message-Id: <
20210312092238.79509-1-thuth@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Wed, 10 Mar 2021 06:33:14 +0000 (07:33 +0100)]
tests: Move unit tests into a separate directory
The main tests directory still looks very crowded, and it's not
clear which files are part of a unit tests and which belong to
a different test subsystem. Let's clean up the mess and move the
unit tests to a separate directory.
Message-Id: <
20210310063314.
1049838-1-thuth@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Peter Maydell [Fri, 12 Mar 2021 13:53:44 +0000 (13:53 +0000)]
Merge remote-tracking branch 'remotes/kraxel/tags/ui-
20210311-pull-request' into staging
ui: mostly cocoa fixes
# gpg: Signature made Thu 11 Mar 2021 12:33:51 GMT
# gpg: using RSA key
A0328CFFB93A17A79901FE7D4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* remotes/kraxel/tags/ui-
20210311-pull-request:
ui/cocoa: Fix mouse association state
ui/cocoa: Mark variables static
ui/cocoa: Clear modifiers whenever possible
ui/cocoa: Do not rely on the first argument
ui/cocoa: Show QEMU icon in the about window
docs: Fix removal text of -show-cursor
ui/cocoa: Use kCGColorSpaceSRGB
ui/gtk: Remove NULL checks in gd_switch
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Hao Wu [Thu, 11 Mar 2021 18:08:55 +0000 (10:08 -0800)]
tests/qtest: Test PWM fan RPM using MFT in PWM test
This patch adds testing of PWM fan RPMs in the existing npcm7xx pwm
test. It tests whether the MFT module can measure correct fan values
for a PWM fan in NPCM7XX boards.
Reviewed-by: Doug Evans <dje@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
20210311180855.149764-6-wuhaotsh@google.com
[PMM: fixed format strings for printing uint64_t]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Hao Wu [Thu, 11 Mar 2021 18:08:54 +0000 (10:08 -0800)]
hw/arm: Connect PWM fans in NPCM7XX boards
This patch adds fan_splitters (split IRQs) in NPCM7XX boards. Each fan
splitter corresponds to 1 PWM output and can connect to multiple fan
inputs (MFT devices).
In NPCM7XX boards(NPCM750 EVB and Quanta GSJ boards), we initializes
these splitters and connect them to their corresponding modules
according their specific device trees.
Reviewed-by: Doug Evans <dje@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
20210311180855.149764-5-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Hao Wu [Thu, 11 Mar 2021 18:08:53 +0000 (10:08 -0800)]
hw/arm: Add MFT device to NPCM7xx Soc
This patch adds the recently implemented MFT device to the NPCM7XX
SoC file.
Reviewed-by: Doug Evans <dje@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id:
20210311180855.149764-4-wuhaotsh@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Hao Wu [Thu, 11 Mar 2021 18:08:52 +0000 (10:08 -0800)]
hw/misc: Add NPCM7XX MFT Module
This patch implements Multi Function Timer (MFT) module for NPCM7XX.
This module is mainly used to configure PWM fans. It has just enough
functionality to make the PWM fan kernel module work.
The module takes two input, the max_rpm of a fan (modifiable via QMP)
and duty cycle (a GPIO from the PWM module.) The actual measured RPM
is equal to max_rpm * duty_cycle / NPCM7XX_PWM_MAX_DUTY. The RPM is
measured as a counter compared to a prescaled input clock. The kernel
driver reads this counter and report to user space.
Refs:
https://github.com/torvalds/linux/blob/master/drivers/hwmon/npcm750-pwm-fan.c
Reviewed-by: Doug Evans <dje@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id:
20210311180855.149764-3-wuhaotsh@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Hao Wu [Thu, 11 Mar 2021 18:08:51 +0000 (10:08 -0800)]
hw/misc: Add GPIOs for duty in NPCM7xx PWM
This patch adds GPIOs in NPCM7xx PWM module for its duty values.
The purpose of this is to connect it to the MFT module to provide
an input for measuring a PWM fan's RPM. Each PWM module has
NPCM7XX_PWM_PER_MODULE of GPIOs, each one corresponds to
one PWM instance and can connect to multiple fan instances in MFT.
Reviewed-by: Doug Evans <dje@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
20210311180855.149764-2-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Andrew Jones [Wed, 10 Mar 2021 13:52:18 +0000 (14:52 +0100)]
hw/arm/virt: KVM: The IPA lower bound is 32
The virt machine already checks KVM_CAP_ARM_VM_IPA_SIZE to get the
upper bound of the IPA size. If that bound is lower than the highest
possible GPA for the machine, then QEMU will error out. However, the
IPA is set to 40 when the highest GPA is less than or equal to 40,
even when KVM may support an IPA limit as low as 32. This means KVM
may fail the VM creation unnecessarily. Additionally, 40 is selected
with the value 0, which means use the default, and that gets around
a check in some versions of KVM, causing a difficult to debug fail.
Always use the IPA size that corresponds to the highest possible GPA,
unless it's lower than 32, in which case use 32. Also, we must still
use 0 when KVM only supports the legacy fixed 40 bit IPA.
Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Message-id:
20210310135218.255205-3-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Andrew Jones [Wed, 10 Mar 2021 13:52:17 +0000 (14:52 +0100)]
accel: kvm: Fix kvm_type invocation
Prior to commit
f2ce39b4f067 a MachineClass kvm_type method
only needed to be registered to ensure it would be executed.
With commit
f2ce39b4f067 a kvm-type machine property must also
be specified. hw/arm/virt relies on the kvm_type method to pass
its selected IPA limit to KVM, but this is not exposed as a
machine property. Restore the previous functionality of invoking
kvm_type when it's present.
Fixes:
f2ce39b4f067 ("vl: make qemu_get_machine_opts static")
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id:
20210310135218.255205-2-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Fri, 12 Mar 2021 00:18:45 +0000 (01:18 +0100)]
hw/timer/sse-timer: Propagate eventual error in sse_timer_realize()
If the SSECounter link is absent, we set an error message
in sse_timer_realize() but forgot to propagate this error.
Add the missing 'return'.
Fixes: CID
1450755 (Null pointer dereferences)
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id:
20210312001845.
1562670-1-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Niek Linnenbank [Wed, 10 Mar 2021 19:58:20 +0000 (20:58 +0100)]
tests/acceptance: drop ARMBIAN_ARTIFACTS_CACHED condition for orangepi-pc, cubieboard tests
Previously the ARMBIAN_ARTIFACTS_CACHED pre-condition was added to allow running
tests that have already existing armbian.com artifacts stored in the local avocado cache,
but do not have working URLs to download a fresh copy.
At this time of writing the URLs for artifacts on the armbian.com server are updated and working.
Any future broken URLs will result in a skipped acceptance test, for example:
(1/5) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi:
CANCEL: Missing asset https://apt.armbian.com/pool/main/l/linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb (0.53 s)
This commits removes the ARMBIAN_ARTIFACTS_CACHED pre-condition such that
the acceptance tests for the orangepi-pc and cubieboard machines can run.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Message-id:
20210310195820.21950-6-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Niek Linnenbank [Wed, 10 Mar 2021 19:58:19 +0000 (20:58 +0100)]
tests/acceptance: update sunxi kernel from armbian to 5.10.16
The linux kernel 4.20.7 binary for sunxi has been removed from apt.armbian.com:
$ ARMBIAN_ARTIFACTS_CACHED=yes AVOCADO_ALLOW_LARGE_STORAGE=yes avocado --show=app,console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
Fetching asset from tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi
...
(1/6) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi:
CANCEL: Missing asset https://apt.armbian.com/pool/main/l/linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb (0.55 s)
This commit updates the sunxi kernel to 5.10.16 for the acceptance
tests of the orangepi-pc and cubieboard machines.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Message-id:
20210310195820.21950-5-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Niek Linnenbank [Wed, 10 Mar 2021 19:58:18 +0000 (20:58 +0100)]
tests/acceptance/boot_linux_console: change URL for test_arm_orangepi_bionic_20_08
Update the download URL of the Armbian 20.08 Bionic image for
test_arm_orangepi_bionic_20_08 of the orangepi-pc machine.
The archive.armbian.com URL contains more images and should keep stable
for a longer period of time than dl.armbian.com.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Message-id:
20210310195820.21950-4-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Niek Linnenbank [Wed, 10 Mar 2021 19:58:17 +0000 (20:58 +0100)]
tests/acceptance/boot_linux_console: remove Armbian 19.11.3 bionic test for orangepi-pc machine
The image for Armbian 19.11.3 bionic has been removed from the armbian server.
Without the image as input the test arm_orangepi_bionic_19_11 cannot run.
This commit removes the test completely and merges the code of the generic function
do_test_arm_orangepi_uboot_armbian back with the 20.08 test.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Message-id:
20210310195820.21950-3-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Niek Linnenbank [Wed, 10 Mar 2021 19:58:16 +0000 (20:58 +0100)]
hw/net/allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC register value
Currently the emulated EMAC for sun8i always traverses the transmit queue
from the head when transferring packets. It searches for a list of consecutive
descriptors whichs are flagged as ready for processing and transmits their payloads
accordingly. The controller stops processing once it finds a descriptor that is not
marked ready.
While the above behaviour works in most situations, it is not the same as the actual
EMAC in hardware. Actual hardware uses the TX_CUR_DESC register value to keep track
of the last position in the transmit queue and continues processing from that position
when software triggers the start of DMA processing. The currently emulated behaviour can
lead to packet loss on transmit when software fills the transmit queue with ready
descriptors that overlap the tail of the circular list.
This commit modifies the emulated EMAC for sun8i such that it processes
the transmit queue using the TX_CUR_DESC register in the same way as hardware.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id:
20210310195820.21950-2-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 9 Mar 2021 15:53:05 +0000 (07:53 -0800)]
target/arm: Update sve reduction vs simd_desc
With the reduction operations, we intentionally increase maxsz to
the next power of 2, so as to fill out the reduction tree correctly.
Since
e2e7168a214b, oprsz must equal maxsz, with exceptions for small
vectors, so this triggers an assertion for vector sizes > 32 that are
not themselves a power of 2.
Pass the power-of-two value in the simd_data field instead.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210309155305.11301-9-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 9 Mar 2021 15:53:04 +0000 (07:53 -0800)]
target/arm: Update WHILE for PREDDESC
Since
b64ee454a4a0, all predicate operations should be
using these field macros for predicates.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210309155305.11301-8-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 9 Mar 2021 15:53:03 +0000 (07:53 -0800)]
target/arm: Update CNTP for PREDDESC
Since
b64ee454a4a0, all predicate operations should be
using these field macros for predicates.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210309155305.11301-7-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 9 Mar 2021 15:53:02 +0000 (07:53 -0800)]
target/arm: Update BRKA, BRKB, BRKN for PREDDESC
Since
b64ee454a4a0, all predicate operations should be
using these field macros for predicates.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210309155305.11301-6-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 9 Mar 2021 15:53:01 +0000 (07:53 -0800)]
target/arm: Update find_last_active for PREDDESC
Since
b64ee454a4a0, all predicate operations should be
using these field macros for predicates.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210309155305.11301-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 9 Mar 2021 15:53:00 +0000 (07:53 -0800)]
target/arm: Fix sve_punpk_p vs odd vector lengths
Wrote too much with punpk1 with vl % 512 != 0.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210309155305.11301-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 9 Mar 2021 15:52:59 +0000 (07:52 -0800)]
target/arm: Fix sve_zip_p vs odd vector lengths
Wrote too much with low-half zip (zip1) with vl % 512 != 0.
Adjust all of the x + (y << s) to x | (y << s) as a style fix.
We only ever have exact overlap between D, M, and N. Therefore
we only need a single temporary, and we do not need to check for
partial overlap.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210309155305.11301-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 9 Mar 2021 15:52:58 +0000 (07:52 -0800)]
target/arm: Fix sve_uzp_p vs odd vector lengths
Missed out on compressing the second half of a predicate
with length vl % 512 > 256.
Adjust all of the x + (y << s) to x | (y << s) as a
general style fix. Drop the extract64 because the input
uint64_t are known to be already zero-extended from the
current size of the predicate.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210309155305.11301-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Eric Auger [Tue, 9 Mar 2021 10:27:42 +0000 (11:27 +0100)]
hw/arm/smmuv3: Uniformize sid traces
Convert all sid printouts to sid=0x%x.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id:
20210309102742.30442-8-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Eric Auger [Tue, 9 Mar 2021 10:27:41 +0000 (11:27 +0100)]
hw/arm/smmuv3: Fix SMMU_CMD_CFGI_STE_RANGE handling
If the whole SID range (32b) is invalidated (SMMU_CMD_CFGI_ALL),
@end overflows and we fail to handle the command properly.
Once this gets fixed, the current code really is awkward in the
sense it loops over the whole range instead of removing the
currently cached configs through a hash table lookup.
Fix both the overflow and the lookup.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
20210309102742.30442-7-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Eric Auger [Tue, 9 Mar 2021 10:27:40 +0000 (11:27 +0100)]
hw/arm/smmuv3: Enforce invalidation on a power of two range
As of today, the driver can invalidate a number of pages that is
not a power of 2. However IOTLB unmap notifications and internal
IOTLB invalidations work with masks leading to erroneous
invalidations.
In case the range is not a power of 2, split invalidations into
power of 2 invalidations.
When looking for a single page entry in the vSMMU internal IOTLB,
let's make sure that if the entry is not found using a
g_hash_table_remove() we iterate over all the entries to find a
potential range that overlaps it.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id:
20210309102742.30442-6-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Eric Auger [Tue, 9 Mar 2021 10:27:39 +0000 (11:27 +0100)]
hw/arm/smmu-common: Fix smmu_iotlb_inv_iova when asid is not set
If the asid is not set, do not attempt to locate the key directly
as all inserted keys have a valid asid.
Use g_hash_table_foreach_remove instead.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id:
20210309102742.30442-5-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Eric Auger [Tue, 9 Mar 2021 10:27:38 +0000 (11:27 +0100)]
virtio-iommu: Handle non power of 2 range invalidations
Unmap notifiers work with an address mask assuming an
invalidation range of a power of 2. Nothing mandates this
in the VIRTIO-IOMMU spec.
So in case the range is not a power of 2, split it into
several invalidations.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Message-id:
20210309102742.30442-4-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Eric Auger [Tue, 9 Mar 2021 10:27:37 +0000 (11:27 +0100)]
dma: Introduce dma_aligned_pow2_mask()
Currently get_naturally_aligned_size() is used by the intel iommu
to compute the maximum invalidation range based on @size which is
a power of 2 while being aligned with the @start address and less
than the maximum range defined by @gaw.
This helper is also useful for other iommu devices (virtio-iommu,
SMMUv3) to make sure IOMMU UNMAP notifiers only are called with
power of 2 range sizes.
Let's move this latter into dma-helpers.c and rename it into
dma_aligned_pow2_mask(). Also rewrite the helper so that it
accomodates UINT64_MAX values for the size mask and max mask.
It now returns a mask instead of a size. Change the caller.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Message-id:
20210309102742.30442-3-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Eric Auger [Tue, 9 Mar 2021 10:27:36 +0000 (11:27 +0100)]
intel_iommu: Fix mask may be uninitialized in vtd_context_device_invalidate
With -Werror=maybe-uninitialized configuration we get
../hw/i386/intel_iommu.c: In function ‘vtd_context_device_invalidate’:
../hw/i386/intel_iommu.c:1888:10: error: ‘mask’ may be used
uninitialized in this function [-Werror=maybe-uninitialized]
1888 | mask = ~mask;
| ~~~~~^~~~~~~
Add a g_assert_not_reached() to avoid the error.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id:
20210309102742.30442-2-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>