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Simon Pilgrim [Wed, 13 Jun 2018 16:52:02 +0000 (16:52 +0000)]
[CostModel] Recognise BROADCAST shuffle mask if the elements come from the second src
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334620
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Andrea Di Biagio [Wed, 13 Jun 2018 16:33:52 +0000 (16:33 +0000)]
Revert: [llvm-mca] Flush the output stream before we start the analysis of a new code region. NFC
Not sure why, but it breaks buildbot clang-cmake-armv8-full.
It causes a failure in TEST 'Xray-armhf-linux :: TestCases/Posix/profiling-single-threaded.cc'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334617
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Simon Pilgrim [Wed, 13 Jun 2018 16:33:42 +0000 (16:33 +0000)]
[CostModel][X86] Test showing failure to recognise BROADCAST shuffle mask if the elements come from the second src
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334616
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Andrea Di Biagio [Wed, 13 Jun 2018 15:43:56 +0000 (15:43 +0000)]
[llvm-mca] Flush the output stream before we start the analysis of a new code region. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334610
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Dmitry Preobrazhensky [Wed, 13 Jun 2018 15:32:46 +0000 (15:32 +0000)]
[AMDGPU][MC][GFX8][GFX9] Allow LDS direct reads for BUFFER_LOAD_DWORDX2/X3/X4
See bug 37653: https://bugs.llvm.org/show_bug.cgi?id=37653
Reviewers: artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D47885
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334609
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Sanjay Patel [Wed, 13 Jun 2018 15:22:48 +0000 (15:22 +0000)]
[DAGCombiner] remove hasOneUse() check from fadd constants transform
We're constant folding here, so we shouldn't check uses. This matches
the IR optimizer behavior.
The x86 test shows the expected win. The AArch64 test shows something
else. This only seems to happen if the "generic" AArch64 CPU model is
used by MachineCombiner, so I'll file a bug report to follow-up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334608
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Tom Stellard [Wed, 13 Jun 2018 15:06:37 +0000 (15:06 +0000)]
AMDGPU: Move isSDNodeSourceOfDivergence() implementation to SITargetLowering
Summary:
The code that handles ISD:Register and ISD::CopyFromReg assumes
the target is amdgcn, so this is broken on r600. We don't
need this analysis on r600 anyway so we can safely move
it to SITargetLowering.
Reviewers: alex-t, arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: msearles, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D46298
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334607
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Sanjay Patel [Wed, 13 Jun 2018 15:01:07 +0000 (15:01 +0000)]
[x86] add test for fadd with more than one use; NFC
The equivalent AArch64 test added at rL334556 isn't showing
the expected output from the DAGCombiner code change that
would fix this example. That's a machine combiner bug from
what I see.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334605
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Cameron McInally [Wed, 13 Jun 2018 14:32:12 +0000 (14:32 +0000)]
[FPEnv] Expand constrained FP operations
Add a helper function to expand constrained FP operations as needed.
Note that the Strict POWI operation is not handled in this patch since
the format is slightly different from the others.
Differential Revision: https://reviews.llvm.org/D47491
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334603
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Hans Wennborg [Wed, 13 Jun 2018 14:29:26 +0000 (14:29 +0000)]
Do not enforce absolute path argv0 in windows
Even if we support no-canonical-prefix on
clang-cl(https://reviews.llvm.org/D47480), argv0 becomes absolute path
in clang-cl and that embeds absolute path in /showIncludes.
This patch removes such full path normalization from InitLLVM on
windows, and that removes absolute path from clang-cl output
(obj/stdout/stderr) when debug flag is disabled.
Patch by Takuto Ikuta!
Differential Revision https://reviews.llvm.org/D47578
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334602
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Guillaume Chatelet [Wed, 13 Jun 2018 14:07:36 +0000 (14:07 +0000)]
[llvm-exegesis] Fix buildbot - power was using native target for X86.
Reviewers: courbet
Reviewed By: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48125
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334601
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Guillaume Chatelet [Wed, 13 Jun 2018 13:53:56 +0000 (13:53 +0000)]
[llvm-exegesis] Fix failing assert when creating Snippet for LAHF.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48123
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334599
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Krzysztof Parzyszek [Wed, 13 Jun 2018 13:49:06 +0000 (13:49 +0000)]
Revert "Improve handling of COPY instructions with identical value numbers"
This reverts r334594, it breaks buildbots and fails with expensive checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334598
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Guillaume Chatelet [Wed, 13 Jun 2018 13:24:41 +0000 (13:24 +0000)]
[llvm-exegesis] Cleaner design without mutable data.
Summary: Previous design was relying on the 'mutate' keyword and was quite confusing. This version separate mutable from immutable data and makes it clearer what changes and what doesn't.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48020
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334596
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Zoran Jovanovic [Wed, 13 Jun 2018 12:51:37 +0000 (12:51 +0000)]
[mips][microMIPS] Extending size reduction pass with LWP and SWP
Author: milena.vujosevic.janicic
Reviewers: sdardis
The patch extends size reduction pass for MicroMIPS.
It introduces reduction of two instructions into one instruction:
Two SW instructions are transformed into one SWP instrucition.
Two LW instructions are transformed into one LWP instrucition.
Differential Revision: https://reviews.llvm.org/D39115
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334595
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Krzysztof Parzyszek [Wed, 13 Jun 2018 12:47:17 +0000 (12:47 +0000)]
Improve handling of COPY instructions with identical value numbers
Differential Revision: https://reviews.llvm.org/D48102
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334594
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Sanjay Patel [Wed, 13 Jun 2018 12:28:32 +0000 (12:28 +0000)]
[x86] eliminate even more sign-bit tests with vector select
This shortcoming was noted in D47330, and the test diffs show we already
had other examples where we failed to fold to a SHRUNKBLEND:
/// Dynamic (non-constant condition) vector blend where only the sign bits
/// of the condition elements are used. This is used to enforce that the
/// condition mask is not valid for generic VSELECT optimizations.
This patch implements an idea from D48043 and would obsolete that patch
because it catches more cases (notable the AVX1 case that was missed there).
All we're doing is allowing the existing transform to fire more often by
removing the post-legalize constraint. All of the relevant feature checks
and other predicates are left as-is.
Differential Revision: https://reviews.llvm.org/D48078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334592
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Alex Bradbury [Wed, 13 Jun 2018 12:04:51 +0000 (12:04 +0000)]
[RISCV] Add codegen support for atomic load/stores with RV32A
Fences are inserted according to table A.6 in the current draft of version 2.3
of the RISC-V Instruction Set Manual, which incorporates the memory model
changes and definitions contributed by the RISC-V Memory Consistency Model
task group.
Instruction selection failures will now occur for 8/16/32-bit atomicrmw and
cmpxchg operations when targeting RV32IA until lowering for these operations
is added in a follow-on patch.
Differential Revision: https://reviews.llvm.org/D47589
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334591
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Alex Bradbury [Wed, 13 Jun 2018 11:58:46 +0000 (11:58 +0000)]
[RISCV] Codegen support for atomic operations on RV32I
This patch adds lowering for atomic fences and relies on AtomicExpandPass to
lower atomic loads/stores, atomic rmw, and cmpxchg to __atomic_* libcalls.
test/CodeGen/RISCV/atomic-* are modelled on the exhaustive
test/CodeGen/PPC/atomics-regression.ll, and will prove more useful once RV32A
codegen support is introduced.
Fence mappings are taken from table A.6 in the current draft of version 2.3 of
the RISC-V Instruction Set Manual, which incorporates the memory model changes
and definitions contributed by the RISC-V Memory Consistency Model task group.
Differential Revision: https://reviews.llvm.org/D47587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334590
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Simon Pilgrim [Wed, 13 Jun 2018 10:49:24 +0000 (10:49 +0000)]
[SLPVectorizer] getSameOpcode - remove useless cast [NFC]
There's no need to cast the base Value to an Instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334588
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Simon Pilgrim [Wed, 13 Jun 2018 10:14:27 +0000 (10:14 +0000)]
[SLPVectorizer] getSameOpcode - remove unusued alternate code [NFC]
We early-out for the case where we don't use alternate opcodes, so no need to check for it later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334587
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Clement Courbet [Wed, 13 Jun 2018 09:41:49 +0000 (09:41 +0000)]
[TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.
Summary:
For targets I'm not familiar with, I've automatically made the "default to 1 for each resource" behaviour explicit in the td files.
For more obvious cases, I've ventured a fix.
Some notes:
- Exynos is especially fishy.
- AArch64SchedThunderX2T99.td had some truncated entries. If I understand correctly, the person who wrote that interpreted the ResourceCycle as a range. I made the decision to use the upper/lower bound for consistency with the 'Latency' value. I'm sure there is a better choice.
- The change to X86ScheduleBtVer2.td is an NFC, it just makes values more explicit.
Also see PR37310.
Reviewers: RKSimon, craig.topper, javed.absar
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D46356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334586
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Hans Wennborg [Wed, 13 Jun 2018 09:11:10 +0000 (09:11 +0000)]
GettingStarted.rst: Fix 'If you you' typo (PR37787)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334584
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Hiroshi Inoue [Wed, 13 Jun 2018 08:54:13 +0000 (08:54 +0000)]
[PowerPC] fix trivial typos in comment, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334583
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Hans Wennborg [Wed, 13 Jun 2018 08:43:03 +0000 (08:43 +0000)]
Fix -DLLVM_ENABLE_THREADS=OFF build after r334537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334582
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Pavel Labath [Wed, 13 Jun 2018 08:29:19 +0000 (08:29 +0000)]
Fix "Optional" is ambiguous error on some bots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334580
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Hiroshi Inoue [Wed, 13 Jun 2018 08:25:14 +0000 (08:25 +0000)]
[PowerPC] avoid verification failure due to PowerPC VSX Swap Removal pass
This patch fixes a failure in lnt tests with -verify-machineinstrs option.
When VSX Swap Removal pass swaps two register operands, it did not maintain kill flags associated with operands. This patch swaps flags as well as register number to avoid inconsistent kill flags information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334579
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Pavel Labath [Wed, 13 Jun 2018 08:14:27 +0000 (08:14 +0000)]
[DWARF/AccelTable] Remove getDIESectionOffset for DWARF v5 entries
Summary:
This method was not correct for entries in DWO files as it assumed it
could just add up the CU and DIE offsets to get the absolute DIE offset.
This is not correct for the DWO files, as here the CU offset will
reference the skeleton unit, whereas the DIE offset will be the offset
in the full unit in the DWO file.
Unfortunately, this means that we are not able to determine the absolute
DIE offset using the information in the .debug_names section alone,
which means we have to offload some of this work to the users of this
class.
To demonstrate how this can be done, I've added/fixed the ability to
lookup entries using accelerator tables in DWO files in llvm-dwarfdump.
To make this happen, I've needed to make two extra changes in other
classes:
- made the DWARFContext method to lookup a CU based on the section
offset public. I've needed this functionality to lookup a CU, and this
seems like a useful thing in general.
- made DWARFUnit::getDWOId call extractDIEsIfNeeded. Before this, the
DWOId was filled in only if the root DIE happened to be parsed
before we called the accessor. Since the lazy parsing is supposed to
happen under the hood, calling extractDIEsIfNeeded seems appropriate.
Reviewers: JDevlieghere, aprantl, dblaikie
Subscribers: mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D48009
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334578
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Craig Topper [Wed, 13 Jun 2018 07:19:21 +0000 (07:19 +0000)]
[X86] Remove masking from avx512vbmi2 concat and shift by immediate intrinsics. Use select in IR instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334576
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Bill Wendling [Wed, 13 Jun 2018 05:53:59 +0000 (05:53 +0000)]
Set the code model when specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334571
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Tom Stellard [Wed, 13 Jun 2018 05:14:10 +0000 (05:14 +0000)]
utils/release: Add merge-git.sh
Summary:
This script allows you to use git to backport a commit to a stable
branch while generating the exact same commit message (ignoring
whitespace) that you would get from using the merge.sh script with svn.
Reviewers: hansw
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47760
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334568
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Max Kazantsev [Wed, 13 Jun 2018 02:25:32 +0000 (02:25 +0000)]
[SimplifyIndVars] Ignore dead users
IndVarSimplify sometimes makes transforms basing on users that are trivially dead. In particular,
if DCE wasn't run before it, there may be a dead `sext/zext` in loop that will trigger widening
transforms, however it makes no sense to do it.
This patch teaches IndVarsSimplify ignore the mist trivial cases of that.
Differential Revision: https://reviews.llvm.org/D47974
Reviewed By: sanjoy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334567
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Ahmed Bougacha [Wed, 13 Jun 2018 02:16:01 +0000 (02:16 +0000)]
Revert "Fix how LLVMOPTIONALCOMPONENTS is passed to llvm-build"
This reverts commit r334543.
My understanding is, that commit is intended to make the llvm-build
invocation have a correct "--enable-optional-components" value, but:
- it already has a value: it's quoted in the command line a few lines
below, and, if I hack llvm-build to print sys.argv, it does look correct:
-- llvm-build output: ['.../utils/llvm-build/llvm-build',
'--native-target', 'X86', '--enable-targets', 'X86;ARM;AArch64',
'--enable-optional-components', '',
'--write-library-table',
'.../build/tools/llvm-config/LibraryDependencies.inc',
'--write-cmake-fragment', '.../build/LLVMBuild.cmake']
- the " " string seems to evaluate to TRUE in CMake (*sigh*), so this
basically force-enables LLVM_USE_INTEL_JITEVENTS, regardless of the
value of the option.
On Darwin, JITEvents is not supported, so this bypasses that OS check
but is guaranteed to fail later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334566
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Craig Topper [Wed, 13 Jun 2018 00:04:08 +0000 (00:04 +0000)]
[X86] Mark all instructions that have masked store semantics with NotMemoryFoldable. Remove dependency on SchedRW from memory table autogenerator.
Previously we were whitelisting in instructions based on their SchedRW value. With the masked store instructions explicitly removed via NotMemoryFoldable, we don't seem to need this check anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334563
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Craig Topper [Wed, 13 Jun 2018 00:04:04 +0000 (00:04 +0000)]
[X86] Remove VPCOMPRESSB/W from the autogenerated load folding table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334562
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Stanislav Mekhanoshin [Tue, 12 Jun 2018 23:50:37 +0000 (23:50 +0000)]
[AMDGPU] DAG combine to produce V_PERM_B32
Differential Revision: https://reviews.llvm.org/D48099
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334559
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Sanjay Patel [Tue, 12 Jun 2018 22:50:37 +0000 (22:50 +0000)]
[AArch64] add tests for fadd with more than one use; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334556
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Raphael Isemann [Tue, 12 Jun 2018 22:40:20 +0000 (22:40 +0000)]
Added missing include to AMDHSAKernelDescriptor.h
We use size_t in this header, so we also need to include
cstddef to make it compile. Fixes the module builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334555
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Krzysztof Parzyszek [Tue, 12 Jun 2018 21:51:49 +0000 (21:51 +0000)]
[DAGCombiner] Recognize more patterns for ABS
Differential Revision: https://reviews.llvm.org/D47831
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334553
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Craig Topper [Tue, 12 Jun 2018 21:42:42 +0000 (21:42 +0000)]
[X86] add avx512 tests for potentially miscompiling cvttp2si/cvttp2ui (PR37751).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334551
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Reid Kleckner [Tue, 12 Jun 2018 21:15:27 +0000 (21:15 +0000)]
Remove malloc.h include from Intel JIT events code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334547
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Reid Kleckner [Tue, 12 Jun 2018 20:54:11 +0000 (20:54 +0000)]
Add null check to Intel JIT event listener
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334544
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Reid Kleckner [Tue, 12 Jun 2018 20:53:46 +0000 (20:53 +0000)]
Fix how LLVMOPTIONALCOMPONENTS is passed to llvm-build
Patch by Force.Charlie-I
If LLVM_USE_INTEL_JITEVENTS and LLVM_USE_OPROFILE not set,
"${LLVMOPTIONALCOMPONENTS}" is empty, but
**--enable-optional-components** need arg, Cause
**--write-library-table** to be skipped parsed.
Differential Revision: https://reviews.llvm.org/D47982
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334543
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Lang Hames [Tue, 12 Jun 2018 20:43:18 +0000 (20:43 +0000)]
[ORC] Add a fallback definition generator for VSOs.
If a VSO has a fallback definition generator attached it will be called during
lookup (and lookupFlags) for any unresolved symbols. The definition generator
can add new definitions to the VSO for any unresolved symbol. This allows VSOs
to generate new definitions on demand.
The immediate use case for this code is supporting VSOs that can import
definitions found via dlsym on demand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334538
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Lang Hames [Tue, 12 Jun 2018 20:43:17 +0000 (20:43 +0000)]
[ORC] Refactor blocking lookup logic into the blockingLookup function, and
implement existing blocking lookups (the lookup function) and
JITSymbolResolverAdapter on top of that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334537
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Lang Hames [Tue, 12 Jun 2018 20:43:17 +0000 (20:43 +0000)]
[RuntimeDyld] Add an assert to catch misbehaving symbol resolvers.
Resolvers are required to find results for all requested symbols or return an
error, but if a resolver fails to adhere to this contract (by returning results
for only a subset of the requested symbols) then this code will infinite loop.
This assertion catches resolvers that fail to adhere to the contract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334536
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Lang Hames [Tue, 12 Jun 2018 20:43:15 +0000 (20:43 +0000)]
[MCJIT] Call materializeAll on modules before compiling them in MCJIT.
This only affects modules with lazy GVMaterializers attached (usually modules
read off disk using the lazy bitcode reader). For such modules, materializing
before compiling prevents crashes due to missing function bodies /
initializers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334535
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Petr Hosek [Tue, 12 Jun 2018 20:00:50 +0000 (20:00 +0000)]
[AArch64] Support reserving x20 register
Register x20 is a callee-saved register which may be used for other
purposes in certain contexts, for example to hold special variables
within the kernel. This change adds support for reserving this register
both to frontend and backend to make this register usable for these
purposes.
Differential Revision: https://reviews.llvm.org/D46552
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334531
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Craig Topper [Tue, 12 Jun 2018 19:59:10 +0000 (19:59 +0000)]
[X86] Remove unnecessary include from one of the tblgen emitters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334530
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Craig Topper [Tue, 12 Jun 2018 19:59:08 +0000 (19:59 +0000)]
[X86] Remove mayLoad flag from AVX512 truncating store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334529
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Reid Kleckner [Tue, 12 Jun 2018 18:56:05 +0000 (18:56 +0000)]
[MS][ARM64] Hoist __ImageBase handling into TargetLoweringObjectFileCOFF
All COFF targets should use @IMGREL32 relocations for symbol differences
against __ImageBase. Do the same for getSectionForConstant, so that
immediates lowered to globals get merged across TUs.
Patch by Chris January
Differential Revision: https://reviews.llvm.org/D47783
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334523
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Konstantin Zhuravlyov [Tue, 12 Jun 2018 18:33:51 +0000 (18:33 +0000)]
AMDHSA/NFC: Code object v3 updates (additional):
- Move section selection and alignment to AMDGPUAsmPrinter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334521
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Roman Tereshin [Tue, 12 Jun 2018 18:30:37 +0000 (18:30 +0000)]
[MIR][MachineCSE] Implementing proper MachineInstr::getNumExplicitDefs()
Apparently, MachineInstr class definition as well as pretty much all of
the machine passes assume that the only kind of MachineInstr's operands
that is variadic for variadic opcodes is explicit non-definitions.
In particular, this assumption is made by MachineInstr::defs(), uses(),
and explicit_uses() methods, as well as by MachineCSE pass.
The assumption is incorrect judging from at least TableGen backend
implementation, that recognizes variable_ops in OutOperandList, and the
very existence of G_UNMERGE_VALUES generic opcode, or ARM load multiple
instructions, all of which have variadic defs.
In particular, MachineCSE pass breaks MIR with CSE'able G_UNMERGE_VALUES
instructions in it.
This commit implements MachineInstr::getNumExplicitDefs() similar to
pre-existing MachineInstr::getNumExplicitOperands(), fixes
MachineInstr::defs(), uses(), and explicit_uses(), and fixes MachineCSE
pass.
As the issue addressed seems to affect only machine passes that could be
ran mid-GlobalISel pipeline at the moment, the other passes aren't fixed
by this commit, like MachineLICM: that could be done on per-pass basis
when (if ever) they get adopted for GlobalISel.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D45640
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334520
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Konstantin Zhuravlyov [Tue, 12 Jun 2018 18:02:46 +0000 (18:02 +0000)]
AMDHSA: Code object v3 updates
- Do not emit following assembler directives:
- .hsa_code_object_version
- .hsa_code_object_isa
- .amd_amdgpu_isa
- .amd_amdgpu_hsa_metadata
- .amd_amdgpu_pal_metadata
- Do not emit .note entries
- Cleanup and bring in sync kernel descriptor header file
- Emit kernel descriptor into .rodata with appropriate relocations and
alignments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334519
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Zachary Turner [Tue, 12 Jun 2018 17:43:52 +0000 (17:43 +0000)]
Refactor ExecuteAndWait to take StringRefs.
This simplifies some code which had StringRefs to begin with, and
makes other code more complicated which had const char* to begin
with.
In the end, I think this makes for a more idiomatic and platform
agnostic API. Not all platforms launch process with null terminated
c-string arrays for the environment pointer and argv, but the api
was designed that way because it allowed easy pass-through for
posix-based platforms. There's a little additional overhead now
since on posix based platforms we'll be takign StringRefs which
were constructed from null terminated strings and then copying
them to null terminate them again, but from a readability and
usability standpoint of the API user, I think this API signature
is strictly better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334518
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Fangrui Song [Tue, 12 Jun 2018 16:20:44 +0000 (16:20 +0000)]
[MC] [X86] Teach leaq _GLOBAL_OFFSET_TABLE(%rip), %r15 to use R_X86_64_GOTPC32 instead of R_X86_64_PC32
Summary:
This is similar to D46319 (ARM). x86-64 psABI p40 gives an example:
leaq _GLOBAL_OFFSET_TABLE(%rip), %r15 # GOTPC32 reloc
GNU as creates R_X86_64_GOTPC32. However, MC currently emits R_X86_64_PC32.
Reviewers: javed.absar, echristo
Subscribers: kristof.beyls, llvm-commits, peter.smith, grimar
Differential Revision: https://reviews.llvm.org/D47507
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334515
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Michael Berg [Tue, 12 Jun 2018 16:13:11 +0000 (16:13 +0000)]
Utilize new SDNode flag functionality to expand current support for fmul
Summary: This patch originated from D46562 and is a proper subset, with some issues addressed for fmul.
Reviewers: spatel, hfinkel, wristow, arsenm
Reviewed By: spatel
Subscribers: nhaehnle, wdng
Differential Revision: https://reviews.llvm.org/D47911
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334514
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Simon Pilgrim [Tue, 12 Jun 2018 16:12:29 +0000 (16:12 +0000)]
[CostModel] Replace ShuffleKind::SK_Alternate with ShuffleKind::SK_Select (PR33744)
As discussed on PR33744, this patch relaxes ShuffleKind::SK_Alternate which requires shuffle masks to only match an alternating pattern from its 2 sources:
e.g. v4f32: <0,5,2,7> or <4,1,6,3>
This seems far too restrictive as most SIMD hardware which will implement it using a general blend/bit-select instruction, so replaces it with SK_Select, permitting elements from either source as long as they are inline:
e.g. v4f32: <0,5,2,7>, <4,1,6,3>, <0,1,6,7>, <4,1,2,3> etc.
This initial patch just updates the name and cost model shuffle mask analysis, later patch reviews will update SLP to better utilise this - it still limits itself to SK_Alternate style patterns.
Differential Revision: https://reviews.llvm.org/D47985
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334513
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Paul Robinson [Tue, 12 Jun 2018 16:09:03 +0000 (16:09 +0000)]
[DWARFv5] llvm-mc -dwarf-version does not imply -g.
Don't provide the assembler source as the "root file" unless the user
asked to have debug info for the assembler source (with -g).
If the source doesn't provide an explicit ".file 0" then (a) use the
compilation directory as directory #0, and (b) use the file #1 info
for file #0 also.
Differential Revision: https://reviews.llvm.org/D48055
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334512
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Craig Topper [Tue, 12 Jun 2018 15:48:03 +0000 (15:48 +0000)]
[X86] Remove TB_ALIGN_16 from VEXTRACTF128/VEXTRACTI128 in the memory folding table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334511
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Simon Pilgrim [Tue, 12 Jun 2018 15:14:34 +0000 (15:14 +0000)]
Fix signed/unsigned warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334509
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Krzysztof Parzyszek [Tue, 12 Jun 2018 15:12:50 +0000 (15:12 +0000)]
[Hexagon] Make floating point operations expensive for vectorization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334508
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Simon Pilgrim [Tue, 12 Jun 2018 14:47:13 +0000 (14:47 +0000)]
[CostModel] Treat Identity shuffle masks as zero cost
As discussed on D47985, identity shuffle masks should probably be free.
I've limited this to the case where the input and output types all match - but we could probably accept all cases.
Differential Revision: https://reviews.llvm.org/D47986
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334506
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Sanjay Patel [Tue, 12 Jun 2018 14:21:51 +0000 (14:21 +0000)]
[x86] move shrunkblend transform to helper function; NFCI
We should be able to obsolete D48043 by easing the constraints
on this existing code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334504
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Clement Courbet [Tue, 12 Jun 2018 13:28:37 +0000 (13:28 +0000)]
[llvm-exegesis] Sum counter values when several counters are specified for a ProcRes.
Summary: This allows handling memory ports on SNB.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334502
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Guillaume Chatelet [Tue, 12 Jun 2018 13:07:16 +0000 (13:07 +0000)]
[llvm-exegesis] Move libpfm linking to LLVMExegesis.
Summary: This patch moves linking of libpfm from different places to a single one.
Reviewers: courbet
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48075
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334499
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Krzysztof Parzyszek [Tue, 12 Jun 2018 12:49:36 +0000 (12:49 +0000)]
[SelectionDAG] Provide default expansion for rotates
Implement default legalization of rotates: either in terms of the rotation
in the opposite direction (if legal), or in terms of shifts and ors.
Implement generating of rotate instructions for Hexagon. Hexagon only
supports rotates by an immediate value, so implement custom lowering of
ROTL/ROTR on Hexagon. If a rotate is not legal, use the default expansion.
Differential Revision: https://reviews.llvm.org/D47725
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334497
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Florian Hahn [Tue, 12 Jun 2018 11:16:56 +0000 (11:16 +0000)]
Use SmallPtrSet explicitly for SmallSets with pointer types (NFC).
Currently SmallSet<PointerTy> inherits from SmallPtrSet<PointerTy>. This
patch replaces such types with SmallPtrSet, because IMO it is slightly
clearer and allows us to get rid of unnecessarily including SmallSet.h
Reviewers: dblaikie, craig.topper
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D47836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334492
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Simon Dardis [Tue, 12 Jun 2018 10:28:06 +0000 (10:28 +0000)]
[mips] Guard some floating point instructions correctly
Reviewers: smaksimovic, atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D47636
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334491
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Aleksandar Beserminji [Tue, 12 Jun 2018 10:23:49 +0000 (10:23 +0000)]
[mips] Extend LONG_BRANCH_LUi/ADDiu with extra parameter
Extend LONG_BRANCH_LUi and LONG_BRANCH_ADDiu pseudo instructions with
additional flag, so instead of always lowering to lui %hi(...),
addiu %lo(...) or addiu %hi(...), now they can lower to either %lo, %hi,
%higher or %highest depending on the added flag.
Differential Revision: https://reviews.llvm.org/D47941
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334490
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Luke Geeson [Tue, 12 Jun 2018 09:35:20 +0000 (09:35 +0000)]
[AArch64] Audit on rL333879 to fix FP16 64bit bitpatterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334488
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Simon Pilgrim [Tue, 12 Jun 2018 09:18:13 +0000 (09:18 +0000)]
[CostModel][X86] Add extra Identity shuffle mask cost tests (D47986)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334486
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Craig Topper [Tue, 12 Jun 2018 07:32:19 +0000 (07:32 +0000)]
[X86] Add NotMemoryFoldable to the VPCOMPRESS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334481
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Craig Topper [Tue, 12 Jun 2018 07:32:18 +0000 (07:32 +0000)]
[X86] Don't add stores to the autogenerated load folding tables if the register and memory operands have different widths.
This can cause the amount of the memory written to be changed which would be bad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334480
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Craig Topper [Tue, 12 Jun 2018 07:32:17 +0000 (07:32 +0000)]
[X86] Add NotMemoryFoldable to more instructions.
These include PUSH/POP instructions that don't match the manual table. This also includes CMPXCHG which we never emit in non-locked form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334479
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Craig Topper [Tue, 12 Jun 2018 07:32:15 +0000 (07:32 +0000)]
[X86] Update folding table generator to properly detect RMW arithmetic instructions.
The RMW instructions are detected by reading the SchedRW data, but the RMW instructions have had their SchedRW changed in recent months. This broke the expectation.
We probably should fix this to use the mayLoad/mayStore flags if possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334478
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Wei Mi [Tue, 12 Jun 2018 05:53:49 +0000 (05:53 +0000)]
[NFC] Change sample profile format enum name SPF_Raw_Binary to SPF_Binary.
Some out-of-tree targets depend on the enum name SPF_Binary. Keep the name
can avoid unnecessary churn to those targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334476
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Wei Mi [Tue, 12 Jun 2018 04:43:09 +0000 (04:43 +0000)]
Fix a typo in rL334447.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334475
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Craig Topper [Tue, 12 Jun 2018 04:34:59 +0000 (04:34 +0000)]
[X86] Add NotMemoryFoldable to a bunch of instructions to suppress them from the autogenerated load folding table.
Most of these are system instructions or other instructions we don't use in CodeGen. No point wasting space for them in the table. Removing them from the autogenerated table makes it easier to review the manual table.
A few are real opcode collisions where the memory and register forms are completely different instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334474
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Craig Topper [Tue, 12 Jun 2018 04:34:58 +0000 (04:34 +0000)]
[X86] Enforce agreement of AdSize field when autogenerating load folding table entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334473
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Michael Berg [Tue, 12 Jun 2018 00:52:43 +0000 (00:52 +0000)]
NFC, some additional tests added and some renaming for planned fma support changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334461
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Craig Topper [Tue, 12 Jun 2018 00:48:57 +0000 (00:48 +0000)]
[X86] Add isel patterns for folding loads when creating ROUND instructions from ffloor/fnearbyint/fceil/frint/ftrunc.
We were missing packed isel folding patterns for all of sse41, avx, and avx512.
For some reason avx512 had scalar load folding patterns under optsize(due to partial/undef reg update), but we didn't have the equivalent sse41 and avx patterns.
Sometimes we would get load folding due to peephole pass anyway, but we're also missing avx512 instructions from the load folding table. I'll try to fix that in another patch.
Some of this was spotted in the review for D47993.
This patch adds all the folds to isel, adds a few spot tests, and disables the peephole pass on a few tests to ensure we're testing some of these patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334460
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Mark Searles [Tue, 12 Jun 2018 00:41:26 +0000 (00:41 +0000)]
[AMDGPU] prevent hitting Assertion `isReg() && "Wrong MachineOperand accessor"'
The use iterator, used within findMaskOperands(), can return anything which is
not a def. isUse() requires a register, so check isReg() before calling isUse().
Differential Revision: https://reviews.llvm.org/D48047
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334459
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Wei Mi [Mon, 11 Jun 2018 23:39:02 +0000 (23:39 +0000)]
Fix a buildbot error reported by sanitizer-x86_64-linux-fast:
Function::getGUID may complain if its input is an empty StringRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334455
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Wei Mi [Mon, 11 Jun 2018 23:09:04 +0000 (23:09 +0000)]
Fix a warning issued by clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334453
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Justin Bogner [Mon, 11 Jun 2018 23:05:28 +0000 (23:05 +0000)]
[CMake] Fix dropped dependency in install-llvm-headers
This dependency was accidentally dropped in r319480, causing
install-distribution and install-llvm-headers to install an incomplete
set of headers (the generated Intrinsics and Attributes would be
missing).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334452
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George Burgess IV [Mon, 11 Jun 2018 22:58:32 +0000 (22:58 +0000)]
Simplify; NFC
Not shown in the diff: AQ is a `vector<SUnit *>`, and SU is a `SUnit *`
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334451
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Wei Mi [Mon, 11 Jun 2018 22:51:28 +0000 (22:51 +0000)]
Fix a warning reported by clang but not by gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334449
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Wei Mi [Mon, 11 Jun 2018 22:40:43 +0000 (22:40 +0000)]
[SampleFDO] Add a new compact binary format for sample profile.
Name table occupies a big chunk of size in current binary format sample profile.
In order to reduce its size, the patch changes the sample writer/reader to
save/restore MD5Hash of names in the name table. Sample annotation phase will
also use MD5Hash of name to query samples accordingly.
Experiment shows compact binary format can reduce the size of sample profile by
2/3 compared with binary format generally.
Differential Revision: https://reviews.llvm.org/D47955
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334447
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David Blaikie [Mon, 11 Jun 2018 22:14:43 +0000 (22:14 +0000)]
TableGen: Change some pointer parameters to references since they're never null anyway
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334446
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Konstantin Zhuravlyov [Mon, 11 Jun 2018 21:37:57 +0000 (21:37 +0000)]
AMDGPU: Add 64-bit relative variant kind
Differential Revision: https://reviews.llvm.org/D47601
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334443
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Matt Arsenault [Mon, 11 Jun 2018 21:27:41 +0000 (21:27 +0000)]
DAG: Fix extract_subvector combine for a single element
This would fail before because 1x vectors aren't legal,
so instead just use the scalar type.
Avoids regressions in a future AMDGPU commit to add
v4i16/v4f16 as legal types.
Test update is just the one test that this triggers
on in tree now. It wasn't checking anything before.
The result is completely changed since the selects
are eliminated. Not sure if it's considered better
or not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334440
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Craig Topper [Mon, 11 Jun 2018 20:50:58 +0000 (20:50 +0000)]
[X86] Push some variable declarations down into the individual switch cases that need them. NFC
All of the cases are already wrapped in curly braces so declaring a variable there isn't an issue. And the variables aren't assigned or used in the larger scope.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334436
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Farhana Aleen [Mon, 11 Jun 2018 20:29:31 +0000 (20:29 +0000)]
[SLP] Add testcases of min/max reduction pattern for AMDGPU.
Author: FarhanaAleen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334435
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Tim Shen [Mon, 11 Jun 2018 19:56:12 +0000 (19:56 +0000)]
Fix incorrect CHECK-LABEL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334434
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Craig Topper [Mon, 11 Jun 2018 19:20:15 +0000 (19:20 +0000)]
[X86] Reorder some type constraints to force things to be vectors and integer/fp before forcing them to be the same size.
This may be needed by another patch that I'm working on. It should have no effect on any of the generated outputs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334430
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Justin Lebar [Mon, 11 Jun 2018 18:57:58 +0000 (18:57 +0000)]
[SCEV] Add transform zext((A * B * ...)<nuw>) --> (zext(A) * zext(B) * ...)<nuw>.
Reviewers: sanjoy
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D48041
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334429
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Justin Lebar [Mon, 11 Jun 2018 18:57:42 +0000 (18:57 +0000)]
[SCEV] Add nuw/nsw to mul ops in StrengthenNoWrapFlags where safe.
Summary:
Previously we would add them for adds, but not multiplies.
Reviewers: sanjoy
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D48038
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334428
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Justin Lebar [Mon, 11 Jun 2018 18:57:27 +0000 (18:57 +0000)]
Fix indentation in ScalarEvolution.cpp.
Whitespace-only change. (clang-formatted the whole block.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334427
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Krzysztof Parzyszek [Mon, 11 Jun 2018 18:45:52 +0000 (18:45 +0000)]
[Hexagon] Late predicate producers cannot be used as dot-new sources
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334426
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