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Juergen Ributzka [Fri, 17 Oct 2014 17:39:00 +0000 (17:39 +0000)]
[Stackmaps] Enable invoking the patchpoint intrinsic.
Patch by Kevin Modzelewski
Reviewers: atrick, ributzka
Reviewed By: ributzka
Subscribers: llvm-commits, reames
Differential Revision: http://reviews.llvm.org/D5634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220055
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Andrea Di Biagio [Fri, 17 Oct 2014 17:27:06 +0000 (17:27 +0000)]
[X86] Fix missed selection of non-temporal store of zero vector.
When the input to a store instruction was a zero vector, the backend
always selected a normal vector store regardless of the non-temporal
hint. This is fixed by this patch.
This fixes PR19370.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220054
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James Molloy [Fri, 17 Oct 2014 17:06:31 +0000 (17:06 +0000)]
[AArch64] Fix a silent codegen fault in BUILD_VECTOR lowering.
We should be talking about the number of source elements, not the number of destination elements, given we know at this point that the source and dest element numbers are not the same.
While we're at it, avoid writing to std::vector::end()...
Bug found with random testing and a lot of coffee.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220051
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Rafael Espindola [Fri, 17 Oct 2014 16:07:43 +0000 (16:07 +0000)]
Don't crash if find_executable return None.
This was crashing when trying to run the tests on Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220048
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Bill Schmidt [Fri, 17 Oct 2014 15:13:38 +0000 (15:13 +0000)]
[PowerPC] Enable use of lxvw4x/stxvw4x in VSX code generation
Currently the VSX support enables use of lxvd2x and stxvd2x for 2x64
types, but does not yet use lxvw4x and stxvw4x for 4x32 types. This
patch adds that support.
As with lxvd2x/stxvd2x, this involves straightforward overriding of
the patterns normally recognized for lvx/stvx, with preference given
to the VSX patterns when VSX is enabled.
In addition, the logic for permitting misaligned memory accesses is
modified so that v4r32 and v4i32 are treated the same as v2f64 and
v2i64 when VSX is enabled. Finally, the DAG generation for unaligned
loads is changed to just use a normal LOAD (which will become lxvw4x)
on P8 and later hardware, where unaligned loads are preferred over
lvsl/lvx/lvx/vperm.
A number of tests now generate the VSX loads/stores instead of
lvx/stvx, so this patch adds VSX variants to those tests. I've also
added <4 x float> tests to the vsx.ll test case, and created a
vsx-p8.ll test case to be used for testing code generation for the
P8Vector feature. For now, that simply tests the unaligned load/store
behavior.
This has been tested along with a temporary patch to enable the VSX
and P8Vector features, with no new regressions encountered with or
without the temporary patch applied.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220047
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Jan Vesely [Fri, 17 Oct 2014 14:45:28 +0000 (14:45 +0000)]
Mips: Only set divrem i64 to custom on 64bit
Reviewed-by: Daniel Sanders <daniel.sanders@imgtec.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220046
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Jan Vesely [Fri, 17 Oct 2014 14:45:27 +0000 (14:45 +0000)]
R600: Add EG to FMA test
Reviewed-by: Tom Stellard <tom@stellard.net>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220045
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Jan Vesely [Fri, 17 Oct 2014 14:45:25 +0000 (14:45 +0000)]
SelectionDAG: Add sext_inreg optimizations
v2: use dyn_cast
fixup comments
v3: use cast
Reviewed-by: Matt Arsenault <arsenm2@gmail.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220044
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Vasileios Kalintiris [Fri, 17 Oct 2014 14:08:28 +0000 (14:08 +0000)]
[mips] Add support for COP1's Branch-On-Cond-Likely instructions
Summary: Depends on D5782
Reviewers: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5802
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220042
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Vasileios Kalintiris [Fri, 17 Oct 2014 12:38:35 +0000 (12:38 +0000)]
[mips] Add support for COP0's Branch-On-Cond-Likely instructions
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5782
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220036
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Hal Finkel [Fri, 17 Oct 2014 11:56:00 +0000 (11:56 +0000)]
[DSE] Remove no-data-layout-only type-based overlap checking
DSE's overlap checking contained special logic, used only when no DataLayout
was available, which inferred a complete overwrite when the pointee types were
equal. This logic seems fine for regular loads/stores, but does not work for
memcpy and friends. Instead of fixing this, I'm just removing it.
Philosophically, transformations should not contain enhanced behavior used only
when data layout is lacking (data layout should be strictly additive), and
maintaining these rarely-tested code paths seems not worthwhile at this stage.
Credit to Aliaksei Zasenka for the bug report and the diagnosis. The test case
(slightly reduced from that provided by Aliaksei) replaces the original
contents of test/Transforms/DeadStoreElimination/no-targetdata.ll -- a few
other tests have been updated to have a data layout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220035
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Peter Collingbourne [Fri, 17 Oct 2014 02:20:40 +0000 (02:20 +0000)]
Fix bashism in build.sh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220027
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Rafael Espindola [Fri, 17 Oct 2014 01:48:58 +0000 (01:48 +0000)]
Add back commits r219835 and a fixed version of r219829.
The only difference from r219829 is using
getOrCreateSectionSymbol(*ELFSec)
instead of
GetOrCreateSymbol(ELFSec->getSectionName())
in ELFObjectWriter which causes us to use the correct section symbol even if
we have multiple sections with the same name.
Original messages:
r219829:
Correctly handle references to section symbols.
When processing assembly like
.long .text
we were creating a new undefined symbol .text. GAS on the other hand would
handle that as a reference to the .text section.
This patch implements that by creating the section symbols earlier so that
they are visible during asm parsing.
The patch also updates llvm-readobj to print the symbol number in the relocation
dump so that the test can differentiate between two sections with the same name.
r219835:
Allow forward references to section symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220021
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Bill Schmidt [Fri, 17 Oct 2014 01:41:22 +0000 (01:41 +0000)]
[PPC] Adjust some PowerPC tests to account for presence/absence of VSX
Patch by Bill Seurer; committed on his behalf.
These test cases generate slightly different code sequences when VSX
is activated and thus fail. The update turns off VSX explicitly for
the existing checks and then adds a second set of checks for most of
them that test the VSX instruction output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220019
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Rafael Espindola [Fri, 17 Oct 2014 01:34:23 +0000 (01:34 +0000)]
Add a test that would have found the bug in r219829.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220016
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Akira Hatanaka [Fri, 17 Oct 2014 01:31:47 +0000 (01:31 +0000)]
ARM: Fix a bug which was causing convergence failure in constant-island pass.
The bug is in ARMConstantIslands::createNewWater where the upper bound of the
new water split point is computed:
// This could point off the end of the block if we've already got constant
// pool entries following this block; only the last one is in the water list.
// Back past any possible branches (allow for a conditional and a maximally
// long unconditional).
if (BaseInsertOffset + 8 >= UserBBI.postOffset()) {
BaseInsertOffset = UserBBI.postOffset() - UPad - 8;
DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset));
}
The split point is supposed to be somewhere between the machine instruction that
loads from the constant pool entry and the end of the basic block, before branch
instructions. The code above is fine if the basic block is large enough and
there are a sufficient number of instructions following the machine instruction.
However, if the machine instruction is near the end of the basic block,
BaseInsertOffset can point to the machine instruction or another instruction
that precedes it, and this can lead to convergence failure.
This commit fixes this bug by ensuring BaseInsertOffset is larger than the
offset of the instruction following the constant-loading instruction.
rdar://problem/
18581150
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220015
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Rafael Espindola [Fri, 17 Oct 2014 01:06:02 +0000 (01:06 +0000)]
Revert commit r219835 and r219829.
Revert "Correctly handle references to section symbols."
Revert "Allow forward references to section symbols."
Rui found a regression I am debugging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220010
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Peter Zotov [Fri, 17 Oct 2014 01:02:40 +0000 (01:02 +0000)]
[OCaml] Add Llvm.instr_clone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220008
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Peter Zotov [Fri, 17 Oct 2014 01:02:34 +0000 (01:02 +0000)]
[LLVM-C] Add LLVMInstructionClone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220007
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Alexander Potapenko [Fri, 17 Oct 2014 00:50:19 +0000 (00:50 +0000)]
[llvm-symbolizer] Introduce the -dsym-hint option.
llvm-symbolizer will consult one of the .dSYM paths passed via -dsym-hint
if it fails to find the .dSYM bundle at the default location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220004
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Matt Arsenault [Fri, 17 Oct 2014 00:36:20 +0000 (00:36 +0000)]
R600/SI: Simplify debug printing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219999
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Peter Collingbourne [Thu, 16 Oct 2014 23:43:20 +0000 (23:43 +0000)]
Add our own copy of the find_executable function to cope with installations
that do not have the distutils.spawn package. Should hopefully fix the
aarch64 buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219991
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Matt Arsenault [Thu, 16 Oct 2014 23:33:37 +0000 (23:33 +0000)]
R600/SI: Remove another VALU pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219988
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Peter Collingbourne [Thu, 16 Oct 2014 22:48:02 +0000 (22:48 +0000)]
Initial version of Go bindings.
This code is based on the existing LLVM Go bindings project hosted at:
https://github.com/go-llvm/llvm
Note that all contributors to the gollvm project have agreed to relicense
their changes under the LLVM license and submit them to the LLVM project.
Differential Revision: http://reviews.llvm.org/D5684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219976
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Peter Collingbourne [Thu, 16 Oct 2014 22:47:52 +0000 (22:47 +0000)]
Introduce LLVMParseCommandLineOptions C API function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219975
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Juergen Ributzka [Thu, 16 Oct 2014 21:26:35 +0000 (21:26 +0000)]
Reduce code duplication between patchpoint and non-patchpoint lowering. NFC.
This is in preparation for another patch that makes patchpoints invokable.
Reviewers: atrick, ributzka
Reviewed By: ributzka
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5657
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219967
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Chandler Carruth [Thu, 16 Oct 2014 21:11:55 +0000 (21:11 +0000)]
[SROA] Switch the common variable name for the 'AllocaSlices' class to
'AS'.
Using 'S' as this was a terrible idea. Arguably, 'AS' is not much
better, but it at least follows the idea of using initialisms and
removes active confusion about the AllocaSlices variable and a Slice
variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219963
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Chandler Carruth [Thu, 16 Oct 2014 21:05:14 +0000 (21:05 +0000)]
[SROA] More range-based cleanups to SROA, these brought to you by
clang-modernize.
I did have to clean up the variable types and whitespace a bit because
the use of auto made the code much less readable here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219962
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Chandler Carruth [Thu, 16 Oct 2014 20:42:08 +0000 (20:42 +0000)]
[SROA] Switch a couple of overly complex iterator accessors to just be
ArrayRef accessors.
I think this even came up in review that this was over-engineered, and
indeed it was. Time to un-build it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219958
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Robin Morisset [Thu, 16 Oct 2014 20:34:57 +0000 (20:34 +0000)]
Erase fence insertion from SelectionDAGBuilder.cpp (NFC)
Summary:
Backends can use setInsertFencesForAtomic to signal to the middle-end that
montonic is the only memory ordering they can accept for
stores/loads/rmws/cmpxchg. The code lowering those accesses with a stronger
ordering to fences + monotonic accesses is currently living in
SelectionDAGBuilder.cpp. In this patch I propose moving this logic out of it
for several reasons:
- There is lots of redundancy to avoid: extremely similar logic already
exists in AtomicExpand.
- The current code in SelectionDAGBuilder does not use any target-hooks, it
does the same transformation for every backend that requires it
- As a result it is plain *unsound*, as it was apparently designed for ARM.
It happens to mostly work for the other targets because they are extremely
conservative, but Power for example had to switch to AtomicExpand to be
able to use lwsync safely (see r218331).
- Because it produces IR-level fences, it cannot be made sound ! This is noted
in the C++11 standard (section 29.3, page 1140):
```
Fences cannot, in general, be used to restore sequential consistency for atomic
operations with weaker ordering semantics.
```
It can also be seen by the following example (called IRIW in the litterature):
```
atomic<int> x = y = 0;
int r1, r2, r3, r4;
Thread 0:
x.store(1);
Thread 1:
y.store(1);
Thread 2:
r1 = x.load();
r2 = y.load();
Thread 3:
r3 = y.load();
r4 = x.load();
```
r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all seq_cst.
But if they are lowered to monotonic accesses, no amount of fences can prevent it..
This patch does three things (I could cut it into parts, but then some of them
would not be tested/testable, please tell me if you would prefer that):
- it provides a default implementation for emitLeadingFence/emitTrailingFence in
terms of IR-level fences, that mimic the original logic of SelectionDAGBuilder.
As we saw above, this is unsound, but the best that can be done without knowing
the targets well (and there is a comment warning about this risk).
- it then switches Mips/Sparc/XCore to use AtomicExpand, relying on this default
implementation (that exactly replicates the logic of SelectionDAGBuilder, so no
functional change)
- it finally erase this logic from SelectionDAGBuilder as it is dead-code.
Ideally, each target would define its own override for emitLeading/TrailingFence
using target-specific fences, but I do not know the Sparc/Mips/XCore memory model
well enough to do this, and they appear to be dealing fine with the ARM-inspired
default expansion for now (probably because they are overly conservative, as
Power was). If anyone wants to compile fences more agressively on these
platforms, the long comment should make it clear why he should first override
emitLeading/TrailingFence.
Test Plan: make check-all, no functional change
Reviewers: jfb, t.p.northover
Subscribers: aemerson, llvm-commits
Differential Revision: http://reviews.llvm.org/D5474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219957
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Matt Arsenault [Thu, 16 Oct 2014 20:31:50 +0000 (20:31 +0000)]
R600/SI: Remove unnecessary VALU patterns
These haven't been necessary since allowing
selecting SALU instructions in non-entry blocks
was enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219956
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Chandler Carruth [Thu, 16 Oct 2014 20:24:07 +0000 (20:24 +0000)]
[SROA] Start more deeply moving SROA to use ranges rather than just
iterators.
There are a ton of places where it essentially wants ranges
rather than just iterators. This is just the first step that adds the
core slice range typedefs and uses them in a couple of places. I still
have to explicitly construct them because they've not been punched
throughout the entire set of code. More range-based cleanups incoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219955
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Matt Arsenault [Thu, 16 Oct 2014 20:07:40 +0000 (20:07 +0000)]
R600: Fix nonsensical implementation of computeKnownBits for BFE
This was resulting in invalid simplifications of sdiv
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219953
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Rafael Espindola [Thu, 16 Oct 2014 20:00:02 +0000 (20:00 +0000)]
Delete -std-compile-opts.
These days -std-compile-opts was just a silly alias for -O3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219951
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Bjorn Steinbrink [Thu, 16 Oct 2014 19:43:08 +0000 (19:43 +0000)]
Allow call-slop optzn for destinations with a suitable dereferenceable attribute
Summary:
Currently, call slot optimization requires that if the destination is an
argument, the argument has the sret attribute. This is to ensure that
the memory access won't trap. In addition to sret, we can also allow the
optimization to happen for arguments that have the new dereferenceable
attribute, which gives the same guarantee.
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5832
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219950
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Jonathan Roelofs [Thu, 16 Oct 2014 19:28:10 +0000 (19:28 +0000)]
Fix lang-ref doc bug: s/icmp lt/icmp slt/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219947
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Nick Kledzik [Thu, 16 Oct 2014 18:58:20 +0000 (18:58 +0000)]
[llvm-objdump] Fix -private-headers for mach-o to print all LC_*_DYLIB variants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219945
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Sanjay Patel [Thu, 16 Oct 2014 18:48:17 +0000 (18:48 +0000)]
fold: sqrt(x * x * y) -> fabs(x) * sqrt(y)
If a square root call has an FP multiplication argument that can be reassociated,
then we can hoist a repeated factor out of the square root call and into a fabs().
In the simplest case, this:
y = sqrt(x * x);
becomes this:
y = fabs(x);
This patch relies on an earlier optimization in instcombine or reassociate to put the
multiplication tree into a canonical form, so we don't have to search over
every permutation of the multiplication tree.
Because there are no IR-level FastMathFlags for intrinsics (PR21290), we have to
use function-level attributes to do this optimization. This needs to be fixed
for both the intrinsics and in the backend.
Differential Revision: http://reviews.llvm.org/D5787
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219944
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Juergen Ributzka [Thu, 16 Oct 2014 16:41:15 +0000 (16:41 +0000)]
[AArch64] Fix miscompile of sdiv-by-power-of-2.
When the constant divisor was larger than 32bits, then the optimized code
generated for the AArch64 backend would emit the wrong code, because the shift
was defined as a shift of a 32bit constant '(1<<Lg2(divisor))' and we would
loose the upper 32bits.
This fixes rdar://problem/
18678801.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219934
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Vasileios Kalintiris [Thu, 16 Oct 2014 15:41:51 +0000 (15:41 +0000)]
[mips] Account for endianess when expanding BuildPairF64/ExtractElementF64 nodes.
Summary:
In order to support big endian targets for the BuildPairF64 nodes we
just need to swap the low/high pair registers. Additionally, for the
ExtractElementF64 nodes we have to calculate the correct stack offset
with respect to the node's register/operand that we want to extract.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5753
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219931
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Vasileios Kalintiris [Thu, 16 Oct 2014 15:23:52 +0000 (15:23 +0000)]
[mips] Marked the DI/EI instruction aliases as MIPS32r2
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5751
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219927
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Vasileios Kalintiris [Thu, 16 Oct 2014 14:37:00 +0000 (14:37 +0000)]
Test commit access: remove extra new line at the end of file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219925
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Benjamin Kramer [Thu, 16 Oct 2014 10:10:07 +0000 (10:10 +0000)]
Add missing header guard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219922
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Akira Hatanaka [Thu, 16 Oct 2014 06:00:46 +0000 (06:00 +0000)]
Reapply r219832 - InstCombine: Narrow switch instructions using known bits.
The code committed in r219832 asserted when it attempted to shrink a switch
statement whose type was larger than 64-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219902
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Saleem Abdulrasool [Thu, 16 Oct 2014 03:27:30 +0000 (03:27 +0000)]
TRE: make TRE a bit more aggressive
Make tail recursion elimination a bit more aggressive. This allows us to get
tail recursion on functions that are just branches to a different function. The
fact that the function takes a byval argument does not restrict it from being
optimised into just a tail call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219899
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Akira Hatanaka [Thu, 16 Oct 2014 01:17:02 +0000 (01:17 +0000)]
Revert r219832.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219884
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Hal Finkel [Thu, 16 Oct 2014 00:40:05 +0000 (00:40 +0000)]
[LVI] Add some additional comments about caching and context instructions
Philip Reames and I had a long conversation about this, mostly because it is
not obvious why the current logic is correct. Hopefully, these comments will
prevent such confusion in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219882
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NAKAMURA Takumi [Thu, 16 Oct 2014 00:14:57 +0000 (00:14 +0000)]
llvm/Support/Options.h: Use \tparam. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219881
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Matt Arsenault [Thu, 16 Oct 2014 00:08:09 +0000 (00:08 +0000)]
R600: Remove dead function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219879
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Sanjoy Das [Wed, 15 Oct 2014 23:46:04 +0000 (23:46 +0000)]
Revert "r219834 - Teach ScalarEvolution to sharpen range information"
This change breaks the asan buildbots:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux/builds/13468
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219878
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Hal Finkel [Wed, 15 Oct 2014 23:44:41 +0000 (23:44 +0000)]
Preserve non-byval pointer alignment attributes using @llvm.assume when inlining
For pointer-typed function arguments, enhanced alignment can be asserted using
the 'align' attribute. When inlining, if this enhanced alignment information is
not otherwise available, preserve it using @llvm.assume-based alignment
assumptions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219876
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Hal Finkel [Wed, 15 Oct 2014 23:44:22 +0000 (23:44 +0000)]
Add CreateAlignmentAssumption to IRBuilder
Clang CodeGen had a utility function for creating pointer alignment assumptions
using the @llvm.assume intrinsic. This functionality will also be needed by the
inliner (to preserve function-argument alignment attributes when inlining), so
this moves the utility function into IRBuilder where it can be used both by
Clang CodeGen and also other LLVM-level code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219875
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Adam Nemet [Wed, 15 Oct 2014 23:42:17 +0000 (23:42 +0000)]
[AVX512] Add DQ subvector inserts
In AVX512f we support 64x2 and 32x8 inserts via matching them to 32x4 and 64x4
respectively. These are matched by "Alt" Pat<>'s (Alt stands for alternative
VTs).
Since DQ has native support for these intructions, I peeled off the non-"Alt"
part of the baseclass into vinsert_for_size_no_alt. The DQ instructions are
derived from this multiclass. The "Alt" Pat<>'s are disabled with DQ.
Fixes <rdar://problem/
18426089>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219874
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Adam Nemet [Wed, 15 Oct 2014 23:42:14 +0000 (23:42 +0000)]
[AVX512] Add SKX testing to avx512-insert-extract.ll
This is in preparation to adding DQ subvector inserts to this testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219873
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Adam Nemet [Wed, 15 Oct 2014 23:42:11 +0000 (23:42 +0000)]
[AVX512] Fix test to produce a defined value
We're inserting into a 8 wide vector, so the index should be < 8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219872
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Adam Nemet [Wed, 15 Oct 2014 23:42:09 +0000 (23:42 +0000)]
[AVX512] Two new attributes in X86VectorVTInfo for subvector insert
The new attributes are NumElts and the CD8TupleForm. This prepares the code
to enable x8 and x2 inserts.
NFC, no change in X86.td.expanded except for the new attributes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219871
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Adam Nemet [Wed, 15 Oct 2014 23:42:04 +0000 (23:42 +0000)]
[AVX512] Rename arg from Opcode32/64 to Opcode128/256 in vinsert_for_size
It's the W bit that selects between 32 or 64 elt type and not the opcode. The
opcode selects between the width of the insert (128 or 256).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219870
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Matt Arsenault [Wed, 15 Oct 2014 23:37:49 +0000 (23:37 +0000)]
R600: Remove unnecessary part of computeKnownBitsForTargetNode
Zero-width BFEs are combined away already, so there's no point in
handling them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219868
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Matt Arsenault [Wed, 15 Oct 2014 23:37:42 +0000 (23:37 +0000)]
Move variable down to use
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219867
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Alexander Potapenko [Wed, 15 Oct 2014 23:35:45 +0000 (23:35 +0000)]
Add MachOObjectFile::getUuid()
This CL introduces MachOObjectFile::getUuid(). This function returns an ArrayRef to the object file's UUID, or an empty ArrayRef if the object file doesn't contain an LC_UUID load command.
The new function is gonna be used by llvm-symbolizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219866
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Chris Bieneman [Wed, 15 Oct 2014 23:11:40 +0000 (23:11 +0000)]
Updating documentation based on my change to remove the template disambiguation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219862
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Chris Bieneman [Wed, 15 Oct 2014 23:11:35 +0000 (23:11 +0000)]
Fixing the build failure due to compiler warnings and unnecessary disambiguation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219861
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Chris Bieneman [Wed, 15 Oct 2014 21:54:35 +0000 (21:54 +0000)]
Defining a new API for debug options that doesn't rely on static global cl::opts.
Summary:
This is based on the discussions from the LLVMDev thread:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-August/075886.html
Reviewers: chandlerc
Reviewed By: chandlerc
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219854
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Tom Stellard [Wed, 15 Oct 2014 21:08:59 +0000 (21:08 +0000)]
R600/SI: Fix bug where immediates were being used in DS addr operands
The SelectDS1Addr1Offset complex pattern always tries to store constant
lds pointers in the offset operand and store a zero value in the addr operand.
Since the addr operand does not accept immediates, the zero value
needs to first be copied to a register.
This newly created zero value will not go through normal instruction
selection, so we need to manually insert a V_MOV_B32_e32 in the complex
pattern.
This bug was hidden by the fact that if there was another zero value
in the DAG that had not been selected yet, then the CSE done by the DAG
would use the unselected node for the addr operand rather than the one
that was just created. This would lead to the zero value being selected
and the DAG automatically inserting a V_MOV_B32_e32 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219848
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Eric Christopher [Wed, 15 Oct 2014 21:06:25 +0000 (21:06 +0000)]
Avoid caching the MachineFunction, we don't use it outside of
runOnMachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219847
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Sid Manning [Wed, 15 Oct 2014 20:41:17 +0000 (20:41 +0000)]
Wrong attribute. LLVM_ATTRIBUTE_UNUSED not LLVM_ATTRIBUTE_USED
This original fix for the build break was correct. LLVM_ATTRIBUTE_USED
removes the warning message because it keeps the function in the object
file. LLVM_ATTRIBUTE_UNUSED indicates that it may or may not be used
depending on build settings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219846
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Duncan P. N. Exon Smith [Wed, 15 Oct 2014 20:39:05 +0000 (20:39 +0000)]
IR: Move NumOperands from User to Value, NFC
Store `User::NumOperands` (and `MDNode::NumOperands`) in `Value`.
On 64-bit host architectures, this reduces `sizeof(User)` and all
subclasses by 8, and has no effect on `sizeof(Value)` (or, incidentally,
on `sizeof(MDNode)`).
On 32-bit host architectures, this increases `sizeof(Value)` by 4.
However, it has no effect on `sizeof(User)` and `sizeof(MDNode)`, so the
only concrete subclasses of `Value` that actually see the increase are
`BasicBlock`, `Argument`, `InlineAsm`, and `MDString`. Moreover, I'll
be shocked and confused if this causes a tangible memory regression.
This has no functionality change (other than memory footprint).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219845
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Duncan P. N. Exon Smith [Wed, 15 Oct 2014 20:28:31 +0000 (20:28 +0000)]
IR: Cleanup comments for Value, User, and MDNode
A follow-up commit will modify the memory-layout of `Value`, `User`, and
`MDNode`. First fix the comments to be doxygen-friendly (and to follow
the coding standards).
- Use "\brief" instead of "repeatedName -".
- Add a brief intro where it was missing.
- Remove duplicated comments from source files (and a couple of
noisy/trivial comments altogether).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219844
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Sid Manning [Wed, 15 Oct 2014 19:32:52 +0000 (19:32 +0000)]
Wrong attribute. LLVM_ATTRIBUTE_USED not LLVM_ATTRIBUTE_UNUSED
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219837
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Rafael Espindola [Wed, 15 Oct 2014 19:30:18 +0000 (19:30 +0000)]
Allow forward references to section symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219835
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Sanjoy Das [Wed, 15 Oct 2014 19:25:28 +0000 (19:25 +0000)]
Teach ScalarEvolution to sharpen range information.
If x is known to have the range [a, b) in a loop predicated by (icmp
ne x, a), its range can be sharpened to [a + 1, b). Get
ScalarEvolution and hence IndVars to exploit this fact.
This change triggers an optimization to widen-loop-comp.ll, so it had
to be edited to get it to pass.
phabricator: http://reviews.llvm.org/D5639
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219834
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Sid Manning [Wed, 15 Oct 2014 19:24:14 +0000 (19:24 +0000)]
Add LLVM_ATTRIBUTE_UNUSED to function currently just used in an assert
Fixes break when -Wunused-function is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219833
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Akira Hatanaka [Wed, 15 Oct 2014 19:05:50 +0000 (19:05 +0000)]
InstCombine: Narrow switch instructions using known bits.
Truncate the operands of a switch instruction to a narrower type if the upper
bits are known to be all ones or zeros.
rdar://problem/
17720004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219832
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Juergen Ributzka [Wed, 15 Oct 2014 18:58:07 +0000 (18:58 +0000)]
Reapply "[FastISel][AArch64] Add custom lowering for GEPs."
This is mostly a copy of the existing FastISel GEP code, but we have to
duplicate it for AArch64, because otherwise we would bail out even for simple
cases. This is because the standard fastEmit functions don't cover MUL at all
and ADD is lowered very inefficientily.
The original commit had a bug in the add emit logic, which has been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219831
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Juergen Ributzka [Wed, 15 Oct 2014 18:58:02 +0000 (18:58 +0000)]
[FastISel][AArch64] Factor out add with immediate emission into a helper function. NFC.
Simplify add with immediate emission by factoring it out into a helper function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219830
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Rafael Espindola [Wed, 15 Oct 2014 18:55:30 +0000 (18:55 +0000)]
Correctly handle references to section symbols.
When processing assembly like
.long .text
we were creating a new undefined symbol .text. GAS on the other hand would
handle that as a reference to the .text section.
This patch implements that by creating the section symbols earlier so that
they are visible during asm parsing.
The patch also updates llvm-readobj to print the symbol number in the relocation
dump so that the test can differentiate between two sections with the same name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219829
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Sid Manning [Wed, 15 Oct 2014 18:27:40 +0000 (18:27 +0000)]
Enable the instruction printer in HexagonMCTargetDesc
This adds the MCInstPrinter to the LLVMHexagonDesc library and removes
the dependency LLVMHexagonAsmPrinter had on LLVMHexagonDesc. This is
a prerequisite needed by the disassembler.
Phabricator Revision: http://reviews.llvm.org/D5734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219826
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Matt Arsenault [Wed, 15 Oct 2014 18:06:43 +0000 (18:06 +0000)]
R600/SI: Also try to use 0 base for misaligned 8-byte DS loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219823
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Matt Arsenault [Wed, 15 Oct 2014 17:58:34 +0000 (17:58 +0000)]
R600: Fix miscompiles when BFE has multiple uses
SimplifyDemandedBits would break the other uses of the operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219819
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Sanjay Patel [Wed, 15 Oct 2014 17:45:13 +0000 (17:45 +0000)]
correct const-ness with auto and dyn_cast
1. Use const with autos.
2. Don't bother with explicit const in cast ops because they do it automagically.
Thanks, David B. / Aaron B. / Reid K.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219817
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Hal Finkel [Wed, 15 Oct 2014 17:35:01 +0000 (17:35 +0000)]
[SLPVectorize] Basic ephemeral-value awareness
The SLP vectorizer should not vectorize ephemeral values. These are used to
express information to the optimizer, and vectorizing them does not lead to
faster code (because the ephemeral values are dropped prior to code generation,
vectorized or not), and obscures the information the instructions are
attempting to communicate (the logic that interprets the arguments to
@llvm.assume generically does not understand vectorized conditions).
Also, uses by ephemeral values are free (because they, and the necessary
extractelement instructions, will be dropped prior to code generation).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219816
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Hal Finkel [Wed, 15 Oct 2014 17:34:48 +0000 (17:34 +0000)]
Treat the WorkSet used to find ephemeral values as double-ended
We need to make sure that we visit all operands of an instruction before moving
deeper in the operand graph. We had been pushing operands onto the back of the work
set, and popping them off the back as well, meaning that we might visit an
instruction before visiting all of its uses that sit in between it and the call
to @llvm.assume.
To provide an explicit example, given the following:
%q0 = extractelement <4 x float> %rd, i32 0
%q1 = extractelement <4 x float> %rd, i32 1
%q2 = extractelement <4 x float> %rd, i32 2
%q3 = extractelement <4 x float> %rd, i32 3
%q4 = fadd float %q0, %q1
%q5 = fadd float %q2, %q3
%q6 = fadd float %q4, %q5
%qi = fcmp olt float %q6, %q5
call void @llvm.assume(i1 %qi)
%q5 is used by both %qi and %q6. When we visit %qi, it will be marked as
ephemeral, and we'll queue %q6 and %q5. %q6 will be marked as ephemeral and
we'll queue %q4 and %q5. Under the old system, we'd then visit %q4, which
would become ephemeral, %q1 and then %q0, which would become ephemeral as
well, and now we have a problem. We'd visit %rd, but it would not be marked as
ephemeral because we've not yet visited %q2 and %q3 (because we've not yet
visited %q5).
This will be covered by a test case in a follow-up commit that enables
ephemeral-value awareness in the SLP vectorizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219815
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Derek Schuff [Wed, 15 Oct 2014 17:10:04 +0000 (17:10 +0000)]
[MC] Make bundle alignment mode setting idempotent and support nested bundles
Summary:
Currently an error is thrown if bundle alignment mode is set more than once
per module (either via the API or the .bundle_align_mode directive). This
change allows setting it multiple times as long as the alignment doesn't
change.
Also nested bundle_lock groups are currently not allowed. This change allows
them, with the effect that the group stays open until all nests are exited,
and if any of the bundle_lock directives has the align_to_end flag, the
group becomes align_to_end.
These changes make the bundle aligment simpler to use in the compiler, and
also better match the corresponding support in GNU as.
Reviewers: jvoung, eliben
Differential Revision: http://reviews.llvm.org/D5801
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219811
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Duncan P. N. Exon Smith [Wed, 15 Oct 2014 17:01:28 +0000 (17:01 +0000)]
DI: Make comments "brief"-er, NFC
Follow-up to r219801. Post-commit review pointed out that all comments
require a `\brief` description [1], so I converted many and recrafted a
few to be briefer or to include a brief intro. (If I'm going to clean
them up, I should do it right!)
[1]: http://llvm.org/docs/CodingStandards.html#doxygen-use-in-documentation-comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219808
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Sanjay Patel [Wed, 15 Oct 2014 16:21:37 +0000 (16:21 +0000)]
Use 'auto' for easier reading; no functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219804
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Sanjay Patel [Wed, 15 Oct 2014 16:20:45 +0000 (16:20 +0000)]
remove function names from comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219803
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Duncan P. N. Exon Smith [Wed, 15 Oct 2014 16:15:15 +0000 (16:15 +0000)]
DI: Cleanup comments, NFC
A number of comment cleanups:
- Remove duplicated function and class names from comments.
- Remove duplicated comments from source file (some of which were
out-of-sync).
- Move any unduplicated comments from source file to header.
- Remove some noisy comments entirely (e.g., a comment for
`DIDescriptor::print()` saying "print descriptor" just gets in the
way of reading the code).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219801
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Rafael Espindola [Wed, 15 Oct 2014 16:12:52 +0000 (16:12 +0000)]
Simplify handling of --noexecstack by using getNonexecutableStackSection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219799
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Duncan P. N. Exon Smith [Wed, 15 Oct 2014 16:11:41 +0000 (16:11 +0000)]
DI: Use a `DenseMap` instead of named metadata, NFC
Remove a strange round-trip through named metadata to assign preserved
local variables to their subprograms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219798
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Rafael Espindola [Wed, 15 Oct 2014 15:44:16 +0000 (15:44 +0000)]
Move getNonexecutableStackSection up to the base ELF class.
The .note.GNU-stack section is not SystemZ/X86 specific.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219796
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Matt Arsenault [Wed, 15 Oct 2014 05:07:00 +0000 (05:07 +0000)]
R600: Use existing variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219778
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Matt Arsenault [Wed, 15 Oct 2014 05:06:57 +0000 (05:06 +0000)]
R600: Remove outdated comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219777
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Juergen Ributzka [Wed, 15 Oct 2014 04:55:48 +0000 (04:55 +0000)]
Revert "[FastISel][AArch64] Add custom lowering for GEPs."
This breaks our internal build bots. Reverting it to get the bots green again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219776
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Jingyue Wu [Wed, 15 Oct 2014 03:27:43 +0000 (03:27 +0000)]
[MachineSink] Use the real post dominator tree
Summary:
Fixes a FIXME in MachineSinking. Instead of using the simple heuristics in
isPostDominatedBy, use the real MachinePostDominatorTree and MachineLoopInfo.
The old heuristics caused instructions to sink unnecessarily, and might create
register pressure.
This is the second try of the fix. The first one (D4814) caused a performance
regression due to failing to sink instructions out of loops (PR21115). This
patch fixes PR21115 by sinking an instruction from a deeper loop to a shallower
one regardless of whether the target block post-dominates the source.
Thanks Alexey Volkov for reporting PR21115!
Test Plan:
Added a NVPTX codegen test to verify that our change prevents the backend from
over-sinking. It also shows the unnecessary register pressure caused by
over-sinking.
Added an X86 test to verify we can sink instructions out of loops regardless of
the dominance relationship. This test is reduced from Alexey's test in PR21115.
Updated an affected test in X86.
Also ran SPEC CINT2006 and llvm-test-suite for compilation time and runtime
performance. Results are attached separately in the review thread.
Reviewers: Jiangning, resistor, hfinkel
Reviewed By: hfinkel
Subscribers: hfinkel, bruno, volkalexey, llvm-commits, meheff, eliben, jholewinski
Differential Revision: http://reviews.llvm.org/D5633
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219773
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Tim Northover [Wed, 15 Oct 2014 01:05:01 +0000 (01:05 +0000)]
ARM: drop check for triple that's no longer used.
Early attempts to support AAPCS bare metal MachO targets based the decision on
the CPU being compiled for. This was not a particularly great idea and we've
got a better option now, but this check remained.
No functional change for any target we care about.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219767
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Eric Christopher [Wed, 15 Oct 2014 00:09:07 +0000 (00:09 +0000)]
Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219750
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Eric Christopher [Tue, 14 Oct 2014 23:58:51 +0000 (23:58 +0000)]
No need to cache this unused variable.
Patch by Ehsan Akhgari.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219749
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Gerolf Hoflehner [Tue, 14 Oct 2014 23:55:00 +0000 (23:55 +0000)]
[AArch64] Wrong CC access in CSINC-conditional branch sequence
This is a follow up to commit r219742. It removes the CCInMI variable
and accesses the CC in CSCINC directly. In the case of a conditional
branch accessing the CC with CCInMI was wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219748
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Nick Kledzik [Tue, 14 Oct 2014 23:29:38 +0000 (23:29 +0000)]
[llvm-objdump] Update error message and add test case for mach-o file with bad library ordinals
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219746
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Gerolf Hoflehner [Tue, 14 Oct 2014 23:07:53 +0000 (23:07 +0000)]
[AAarch64] Optimize CSINC-branch sequence
Peephole optimization that generates a single conditional branch
for csinc-branch sequences like in the examples below. This is
possible when the csinc sets or clears a register based on a condition
code and the branch checks that register. Also the condition
code may not be modified between the csinc and the original branch.
Examples:
1. Convert csinc w9, wzr, wzr, <CC>;tbnz w9, #0, 0x44
to b.<invCC>
2. Convert csinc w9, wzr, wzr, <CC>; tbz w9, #0, 0x44
to b.<CC>
rdar://problem/
18506500
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219742
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