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Simon Pilgrim [Thu, 12 Jul 2018 13:29:41 +0000 (13:29 +0000)]
[X86][SSE] Utilize ZeroableElements for canWidenShuffleElements
canWidenShuffleElements can do a better job if given a mask with ZeroableElements info. Apparently, ZeroableElements was being only used to identify AllZero candidates, but possibly we could plug it into more shuffle matchers.
Original Patch by Zvi Rackover @zvi
Differential Revision: https://reviews.llvm.org/D42044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336903
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Chen Zheng [Thu, 12 Jul 2018 13:28:20 +0000 (13:28 +0000)]
[InstCombine]add testcases for folding more SPFofSPF pattern
Differential Revision: https://reviews.llvm.org/D49222
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336902
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Simon Pilgrim [Thu, 12 Jul 2018 13:03:58 +0000 (13:03 +0000)]
[X86][AVX] Use Zeroable mask to improve shuffle mask widening
Noticed while updating D42044, lowerV2X128VectorShuffle can improve the shuffle mask with the zeroable data to create a target shuffle mask to recognise more 'zero upper 128' patterns.
NOTE: lowerV4X128VectorShuffle could benefit as well but the code needs refactoring first to discriminate between SM_SentinelUndef and SM_SentinelZero for negative shuffle indices.
Differential Revision: https://reviews.llvm.org/D49092
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336900
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David Green [Thu, 12 Jul 2018 10:44:47 +0000 (10:44 +0000)]
[UnJ] Use SmallPtrSets for block collections. NFC
We no longer care about the order of blocks in these collections,
so can change to SmallPtrSets, making contains checks quicker.
Differential revision: https://reviews.llvm.org/D49060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336897
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Simon Pilgrim [Thu, 12 Jul 2018 09:10:55 +0000 (09:10 +0000)]
Fix -Wdocumentation warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336895
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Simon Pilgrim [Thu, 12 Jul 2018 09:04:28 +0000 (09:04 +0000)]
[X86] Add UDIV by uniform/non-uniform constant tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336894
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Simon Atanasyan [Thu, 12 Jul 2018 08:50:11 +0000 (08:50 +0000)]
[mips] Mark standard encoded instructions as not being in MIPS16e
Mark standard encoded instructions and pseudo "standard encoded"
as not being in MIPS16e by default.
Patch by Simon Dardis.
Differential revision: https://reviews.llvm.org/D48379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336893
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Craig Topper [Thu, 12 Jul 2018 07:30:01 +0000 (07:30 +0000)]
[X86] Remove i128 type from FR128 regclass.
i128 isn't a legal type in our x86 implementation today. So remove this and the few patterns that used it until it becomes necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336889
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Sam McCall [Thu, 12 Jul 2018 07:11:28 +0000 (07:11 +0000)]
[Support] Require llvm::Error passed to formatv() to be wrapped in fmt_consume()
Summary:
Someone must be responsible for handling an Error. When formatv takes
ownership of an Error, the formatv_object destructor must take care of this.
Passing an error by value to formatv() is not considered explicit enough to mark
the error as handled (see D49013), so we require callers to use a format adapter
to confirm this intent.
Reviewers: zturner
Subscribers: llvm-commits, lhames
Differential Revision: https://reviews.llvm.org/D49170
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336888
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Stefan Granitz [Thu, 12 Jul 2018 06:41:41 +0000 (06:41 +0000)]
Fix few typos in comments (write access test commit)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336887
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Chijun Sima [Thu, 12 Jul 2018 04:08:14 +0000 (04:08 +0000)]
[Dominators] Add isUpdateLazy() method to the DomTreeUpdater
Summary:
Previously, when people need to deal with DTU with different UpdateStrategy using different actions, they need to
```
if (DTU.getUpdateStrategy() == DomTreeUpdater::UpdateStrategy::Lazy) {
...
}
if (DTU.getUpdateStrategy() == DomTreeUpdater::UpdateStrategy::Eager) {
...
}
```
After the patch, they can avoid code patterns above
```
if (DTU.isUpdateLazy()){
...
}
if (!DTU.isUpdateLazy()){
...
}
```
Reviewers: kuhar, brzycki, dmgreen
Reviewed By: kuhar
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336886
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Craig Topper [Thu, 12 Jul 2018 03:42:41 +0000 (03:42 +0000)]
[X86] Remove patterns and ISD nodes for the old scalar FMA intrinsic lowering.
We now use llvm.fma.f32/f64 or llvm.x86.fmadd.f32/f64 intrinsics that use scalar types rather than vector types. So we don't these special ISD nodes that operate on the lowest element of a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336883
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Chen Zheng [Thu, 12 Jul 2018 03:06:04 +0000 (03:06 +0000)]
[InstSimplify] simplify add instruction if two operands are negative
Differential Revision: https://reviews.llvm.org/D49216
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336881
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Fangrui Song [Thu, 12 Jul 2018 02:03:53 +0000 (02:03 +0000)]
[AsmParser] Fix inconsistent declaration parameter name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336879
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Eric Christopher [Thu, 12 Jul 2018 01:53:21 +0000 (01:53 +0000)]
Temporarily revert "Recommit r328307: [IPSCCP] Use constant range information for comparisons of parameters." as it's causing miscompiles.
A testcase was provided in the original review thread.
This reverts commit r336098.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336877
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Chandler Carruth [Thu, 12 Jul 2018 01:43:21 +0000 (01:43 +0000)]
[x86] Fix another trivial bug in x86 flags copy lowering that has been
there for a long time.
The boolean tracking whether we saw a kill of the flags was supposed to
be per-block we are scanning and instead was outside that loop and never
cleared. It requires a quite contrived test case to hit this as you have
to have multiple levels of successors and interleave them with kills.
I've included such a test case here.
This is another bug found testing SLH and extracted to its own focused
patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336876
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Craig Topper [Thu, 12 Jul 2018 00:54:40 +0000 (00:54 +0000)]
[X86] Add patterns to use VMOVSS/SD zero masking for scalar f32/f64 select with zero.
These showed up in some of the upgraded FMA code. We really need to improve these test cases more, but this helps for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336875
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Chandler Carruth [Thu, 12 Jul 2018 00:52:50 +0000 (00:52 +0000)]
[x86] Fix EFLAGS copy lowering to correctly handle walking past uses in
multiple successors where some of the uses end up killing the EFLAGS
register.
There was a bug where rather than skipping to the next basic block
queued up with uses once we saw a kill, we stopped processing the blocks
entirely. =/
Test case produces completely nonsensical code w/o this tiny fix.
This was found testing Speculative Load Hardening and split out of that
work.
Differential Revision: https://reviews.llvm.org/D49211
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336874
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Craig Topper [Thu, 12 Jul 2018 00:29:56 +0000 (00:29 +0000)]
[X86] Remove and autoupgrade the scalar fma intrinsics with masking.
This converts them to what clang is now using for codegen. Unfortunately, there seem to be a few kinks to work out still. I'll try to address with follow up patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336871
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Eric Christopher [Thu, 12 Jul 2018 00:01:51 +0000 (00:01 +0000)]
Add -allow-deprecated-dag-overlap to one of the experimental webassembly target tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336870
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Duncan P. N. Exon Smith [Wed, 11 Jul 2018 23:30:25 +0000 (23:30 +0000)]
IR: Skip -print-*-all after -print-*
This changes `-print-*` from transformation passes to analysis passes so
that `-print-after-all` and `-print-before-all` don't trigger. This
avoids some redundant output.
Patch by Son Tuan Vu!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336869
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Eli Friedman [Wed, 11 Jul 2018 23:26:35 +0000 (23:26 +0000)]
[CodeGen] Emit more precise AssertZext/AssertSext nodes.
This is marginally helpful for removing redundant extensions, and the
code is easier to read, so it seems like an all-around win. In the new
test i8-phi-ext.ll, we used to emit an AssertSext i8; now we emit an
AssertZext i2, which allows the extension of the return value to be
eliminated.
Differential Revision: https://reviews.llvm.org/D49004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336868
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Craig Topper [Wed, 11 Jul 2018 22:35:28 +0000 (22:35 +0000)]
[LoopIdiomRecognize] Don't convert a do while loop to ctlz.
This commit suppresses turning loops like this into "(bitwidth - ctlz(input))".
unsigned foo(unsigned input) {
unsigned num = 0;
do {
++num;
input >>= 1;
} while (input != 0);
return num;
}
The loop version returns a value of 1 for both an input of 0 and an input of 1. Converting to a naive ctlz does not preserve that.
Theoretically we could do better if we checked isKnownNonZero or we could insert a select to handle the divergence. But until we have motivating cases for that, this is the easiest solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336864
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Craig Topper [Wed, 11 Jul 2018 22:17:26 +0000 (22:17 +0000)]
[LoopIdiomRecognize] Add a test case showing a loop we turn into ctlz that we shouldn't.
This loop executes one iteration without checking the input value. This produces a count of 1 for an input of 0 and 1. We are turning this into 32 - ctlz(n), but that returns 0 if n is 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336862
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Tom Stellard [Wed, 11 Jul 2018 22:15:15 +0000 (22:15 +0000)]
AMDGPU/SI: Initialize InstrInfo before TargetLoweringInfo in GCNSubtarget
SITargetLowering queries SIInstrInfo in its constructor, so SIInstrInfo
must be initialized first. This fixes msan buildbot failures and was
introduced by r336851.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336861
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Alina Sbirlea [Wed, 11 Jul 2018 22:11:46 +0000 (22:11 +0000)]
[MemorySSA] Add APIs to move memory accesses between blocks, following CFG changes.
Summary:
The move APIs added in this patch will be used to update MemorySSA when CFG changes merge or split blocks, by moving memory accesses accordingly in MemorySSA's internal data structures.
[Split from D45299 for easier review]
Reviewers: george.burgess.iv
Subscribers: sanjoy, jlebar, Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D48897
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336860
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Bill Wendling [Wed, 11 Jul 2018 21:47:55 +0000 (21:47 +0000)]
Temporarily reverting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336858
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Roman Lebedev [Wed, 11 Jul 2018 21:28:42 +0000 (21:28 +0000)]
[NFC][InstCombine] Tests for x & (-1 >> y) != x -> x u> (-1 >> y) fold
https://bugs.llvm.org/show_bug.cgi?id=38123
https://rise4fun.com/Alive/Rny
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336857
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Tom Stellard [Wed, 11 Jul 2018 21:12:03 +0000 (21:12 +0000)]
AMDGPU: Remove duplicate call to initializeSubtargetDependencies()
This was added in r336851.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336853
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Tom Stellard [Wed, 11 Jul 2018 20:59:01 +0000 (20:59 +0000)]
AMDGPU: Refactor Subtarget classes
Summary:
This is a follow-up to r335942.
- Merge SISubtarget into AMDGPUSubtarget and rename to GCNSubtarget
- Rename AMDGPUCommonSubtarget to AMDGPUSubtarget
- Merge R600Subtarget::Generation and GCNSubtarget::Generation into
AMDGPUSubtarget::Generation.
Reviewers: arsenm, jvesely
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D49037
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336851
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Joel E. Denny [Wed, 11 Jul 2018 20:31:51 +0000 (20:31 +0000)]
finish: [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
Differential Revision: https://reviews.llvm.org/D47171
This contains the portions of that patch that could not be committed
using the git monorepo because of dos line ending problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336848
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Joel E. Denny [Wed, 11 Jul 2018 20:27:27 +0000 (20:27 +0000)]
[FileCheck] Don't permit overlapping CHECK-DAG
That is, make CHECK-DAG skip matches that overlap the matches of any
preceding consecutive CHECK-DAG directives. This change makes
CHECK-DAG more consistent with other directives, and there is evidence
it makes CHECK-DAG more intuitive and less error-prone. See the RFC
discussion starting at:
http://lists.llvm.org/pipermail/llvm-dev/2018-May/123010.html
Moreover, this behavior enables CHECK-DAG groups for unordered,
non-unique strings or patterns. For example, it is useful for
verifying output or logs from a parallel program, such as the OpenMP
runtime.
This patch also implements the command-line option
-allow-deprecated-dag-overlap, which reverts CHECK-DAG to the old
overlapping behavior. This option should not be used in new tests.
It is meant only for the existing tests that are broken by this change
and that need time to update.
See the following bugzilla issue for tracking of such tests:
https://bugs.llvm.org/show_bug.cgi?id=37532
Patches to add -allow-deprecated-dag-overlap to those tests will
follow immediately.
Reviewed By: probinson
Differential Revision: https://reviews.llvm.org/D47106
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336847
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Joel E. Denny [Wed, 11 Jul 2018 20:25:49 +0000 (20:25 +0000)]
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
See https://reviews.llvm.org/D47106 for details.
Reviewed By: probinson
Differential Revision: https://reviews.llvm.org/D47171
This commit drops that patch's changes to:
llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
llvm/test/CodeGen/NVPTX/param-load-store.ll
For some reason, the dos line endings there prevent me from commiting
via the monorepo. A follow-up commit (not via the monorepo) will
finish the patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336843
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Teresa Johnson [Wed, 11 Jul 2018 20:08:32 +0000 (20:08 +0000)]
Revert "[docs] As of binutils 2.21.51.0.2, ld.bfd supports plugins too, represent this in docs"
This reverts commit r306102.
This change was made without any review, and has a couple of issues.
First, AFAIK we do not test the combination of the LLVM gold plugin with
ld.bfd. Second, the change removed documentation for how to build gold
and replaced it with instructions for building ld.bfd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336841
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Bill Wendling [Wed, 11 Jul 2018 19:13:26 +0000 (19:13 +0000)]
gold: Add ability to toggle function/data sections
Some programs (e.g. Linux) aren't able to handle function/data sections when
LTO is used. Thus they need a way to disable it. That can be done with these
plugin options:
-plugin-opt=-function-sections=0
-plugin-opt=-data-sections=0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336838
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Fangrui Song [Wed, 11 Jul 2018 19:09:37 +0000 (19:09 +0000)]
[DebugInfo] Fix getPreviousSibling after r336823
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336837
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Roman Lebedev [Wed, 11 Jul 2018 19:05:04 +0000 (19:05 +0000)]
[InstCombine] Fold x & (-1 >> y) == x to x u<= (-1 >> y)
Summary:
https://bugs.llvm.org/show_bug.cgi?id=38123
This pattern will be produced by Implicit Integer Truncation sanitizer,
https://reviews.llvm.org/D48958
https://bugs.llvm.org/show_bug.cgi?id=21530
in unsigned case, therefore it is probably a good idea to improve it.
https://rise4fun.com/Alive/Rny
^ there are more opportunities for folds, i will follow up with them afterwards.
Caveat: this somehow exposes a missing opportunities
in `test/Transforms/InstCombine/icmp-logical.ll`
It seems, the problem is in `foldLogOpOfMaskedICmps()` in `InstCombineAndOrXor.cpp`.
But i'm not quite sure what is wrong, because it calls `getMaskedTypeForICmpPair()`,
which calls `decomposeBitTestICmp()` which should already work for these cases...
As @spatel notes in https://reviews.llvm.org/D49179#
1158760,
that code is a rather complex mess, so we'll let it slide.
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: yamauchi, majnemer, t.p.northover, llvm-commits
Differential Revision: https://reviews.llvm.org/D49179
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336834
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Joel E. Denny [Wed, 11 Jul 2018 19:03:00 +0000 (19:03 +0000)]
Revert r336830: [FileCheck] Don't permit overlapping CHECK-DAG
Companion patches are failing to commit, and this patch alone breaks
many tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336833
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Paul Robinson [Wed, 11 Jul 2018 18:51:15 +0000 (18:51 +0000)]
Quick fix for some Windows bots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336832
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Joel E. Denny [Wed, 11 Jul 2018 18:42:58 +0000 (18:42 +0000)]
[FileCheck] Don't permit overlapping CHECK-DAG
That is, make CHECK-DAG skip matches that overlap the matches of any
preceding consecutive CHECK-DAG directives. This change makes
CHECK-DAG more consistent with other directives, and there is evidence
it makes CHECK-DAG more intuitive and less error-prone. See the RFC
discussion starting at:
http://lists.llvm.org/pipermail/llvm-dev/2018-May/123010.html
Moreover, this behavior enables CHECK-DAG groups for unordered,
non-unique strings or patterns. For example, it is useful for
verifying output or logs from a parallel program, such as the OpenMP
runtime.
This patch also implements the command-line option
-allow-deprecated-dag-overlap, which reverts CHECK-DAG to the old
overlapping behavior. This option should not be used in new tests.
It is meant only for the existing tests that are broken by this change
and that need time to update.
See the following bugzilla issue for tracking of such tests:
https://bugs.llvm.org/show_bug.cgi?id=37532
Patches to add -allow-deprecated-dag-overlap to those tests will
follow immediately.
Reviewed By: probinson
Differential Revision: https://reviews.llvm.org/D47106
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336830
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Paul Semel [Wed, 11 Jul 2018 18:09:52 +0000 (18:09 +0000)]
Revert "[llvm-objdump] Add -demangle (-C) option"
This reverts commit
3a44ccd156e0edd2e89226f8ed63928e227900bb.
This reverts commit
d5cfc836bb5552e20507d3612d13ff66ff9e36a0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336829
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Craig Topper [Wed, 11 Jul 2018 18:09:04 +0000 (18:09 +0000)]
[X86] Remove patterns for inserting a load into a zero vector.
We can instead block the load folding isProfitableToFold. Then isel will emit a register->register move for the zeroing part and a separate load. The PostProcessISelDAG should be able to remove the register->register move.
This saves us patterns and fixes the fact that we only had unaligned load patterns. The test changes show places where we should have been using an aligned load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336828
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Simon Pilgrim [Wed, 11 Jul 2018 17:51:27 +0000 (17:51 +0000)]
[TargetTransformInfo] Add pow2 analysis for scalar constants
Add ConstantInt analysis to getOperandInfo so we get more realistic div/rem expansion costs comparable to the vector costs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336827
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Konstantin Zhuravlyov [Wed, 11 Jul 2018 17:27:17 +0000 (17:27 +0000)]
AMDGPU/NFC: Use already available explicit kernarg
size instead of calculating it again when filling
out the metadata.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336825
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Jonas Devlieghere [Wed, 11 Jul 2018 17:11:11 +0000 (17:11 +0000)]
[DebugInfo] Make children iterator bidirectional
Make the DIE iterator bidirectional so we can move to the previous
sibling of a DIE.
Differential revision: https://reviews.llvm.org/D49173
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336823
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Sanjay Patel [Wed, 11 Jul 2018 16:52:18 +0000 (16:52 +0000)]
[InstSimplify] add/move tests for add folds; NFC
isKnownNegation() is currently proposed as part of D48754,
but it could be used to make InstSimplify stronger independently
of any abs() improvements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336822
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Paul Semel [Wed, 11 Jul 2018 16:31:33 +0000 (16:31 +0000)]
Fix llvm-objdump demangle test (added triple option)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336821
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Andrea Di Biagio [Wed, 11 Jul 2018 15:27:50 +0000 (15:27 +0000)]
[X86] Fix MayLoad/HasSideEffect flag for (V)MOVLPSrm instructions.
Before revision 336728, the "mayLoad" flag for instruction (V)MOVLPSrm was
inferred directly from the "default" pattern associated with the instruction
definition.
r336728 removed special node X86Movlps, and all the patterns associated to it.
Now instruction (V)MOVLPSrm doesn't have a pattern associated to it, and the
'mayLoad/hasSideEffects' flags are left unset.
When the instruction info is emitted by tablegen, method
CodeGenDAGPatterns::InferInstructionFlags() sees that (V)MOVLPSrm doesn't have a
pattern, and flags are undefined. So, it conservatively sets the
"hasSideEffects" flag for it.
As a consequence, we were losing the 'mayLoad' flag, and we were gaining a
'hasSideEffect' flag in its place.
This patch fixes the issue (originally reported by Michael Holmen).
The mca tests show the differences in the instruction info flags. Instructions
that were affected by this problem were: MOVLPSrm/VMOVLPSrm/VMOVLPSZ128rm.
Differential Revision: https://reviews.llvm.org/D49182
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336818
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Paul Semel [Wed, 11 Jul 2018 15:25:39 +0000 (15:25 +0000)]
[llvm-objdump] Add -demangle (-C) option
Differential Revision: https://reviews.llvm.org/D49043
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336816
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Simon Pilgrim [Wed, 11 Jul 2018 15:05:10 +0000 (15:05 +0000)]
[SLPVectorizer] Add initial alternate opcode support for cast instructions. (REAPPLIED)
We currently only support binary instructions in the alternate opcode shuffles.
This patch is an initial attempt at adding cast instructions as well, this raises several issues that we probably want to address as we continue to generalize the alternate mechanism:
1 - Duplication of cost determination - we should probably add scalar/vector costs helper functions and get BoUpSLP::getEntryCost to use them instead of determining costs directly.
2 - Support alternate instructions with the same opcode (e.g. casts with different src types) - alternate vectorization of calls with different IntrinsicIDs will require this.
3 - Allow alternates to be a different instruction type - mixing binary/cast/call etc.
4 - Allow passthrough of unsupported alternate instructions - related to PR30787/D28907 'copyable' elements.
Reapplied with fix to only accept 2 different casts if they come from the same source type.
Differential Revision: https://reviews.llvm.org/D49135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336812
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Simon Pilgrim [Wed, 11 Jul 2018 14:34:43 +0000 (14:34 +0000)]
[SLPVectorizer] Ensure alternate/passthrough doesn't vectorize sdiv with undef elts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336809
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Simon Pilgrim [Wed, 11 Jul 2018 14:29:13 +0000 (14:29 +0000)]
[SLPVectorizer] Add some additional alternate cast tests
Initial attempt at D49135 failed as we weren't correctly handling casts with different source types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336808
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Simon Pilgrim [Wed, 11 Jul 2018 14:08:16 +0000 (14:08 +0000)]
Revert rL336804: [SLPVectorizer] Add initial alternate opcode support for cast instructions.
Reverting due to buildbot failures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336806
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Florian Hahn [Wed, 11 Jul 2018 13:39:59 +0000 (13:39 +0000)]
Recommit r334887: [SmallSet] Add SmallSetIterator.
This version now uses the subset of is_trivially_XXX provided by
GCC 4.8 and llvm/Support/type_traits.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336805
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Simon Pilgrim [Wed, 11 Jul 2018 13:34:09 +0000 (13:34 +0000)]
[SLPVectorizer] Add initial alternate opcode support for cast instructions.
We currently only support binary instructions in the alternate opcode shuffles.
This patch is an initial attempt at adding cast instructions as well, this raises several issues that we probably want to address as we continue to generalize the alternate mechanism:
1 - Duplication of cost determination - we should probably add scalar/vector costs helper functions and get BoUpSLP::getEntryCost to use them instead of determining costs directly.
2 - Support alternate instructions with the same opcode (e.g. casts with different src types) - alternate vectorization of calls with different IntrinsicIDs will require this.
3 - Allow alternates to be a different instruction type - mixing binary/cast/call etc.
4 - Allow passthrough of unsupported alternate instructions - related to PR30787/D28907 'copyable' elements.
Differential Revision: https://reviews.llvm.org/D49135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336804
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Krzysztof Parzyszek [Wed, 11 Jul 2018 13:30:27 +0000 (13:30 +0000)]
[CodeGen] Ignore debug uses in MachineCopyPropagation
Debug uses should not count as real uses, since the presence of debug
information could affect the generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336803
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Simon Atanasyan [Wed, 11 Jul 2018 13:21:10 +0000 (13:21 +0000)]
[mips] Update the P5600 scheduler model not to use instruction itineraries.
This mostly brings the P5600 scheduler model to a mostly complete
status. There are a number of instructions which trigger the
`error:'MipsP5600Model' lacks information for` error. These are certain
codegen only instructions relating to MIPS64 which can be addressed by
using the correct predicates for them. That will be done in a full-up
patch.
Patch by Simon Dardis.
Differential revision: https://reviews.llvm.org/D45245
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336802
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Diogo N. Sampaio [Wed, 11 Jul 2018 12:59:42 +0000 (12:59 +0000)]
[NFC][InstCombine] Converts isLegalNarrowLoad into isLegalNarrowLdSt
Reuse this function as to test correctness and profitability of
reducing width of either load or store operations.
Reviewsers: samparker
Differential Revision: https://reviews.llvm.org/D48624
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336800
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Andrea Di Biagio [Wed, 11 Jul 2018 12:44:44 +0000 (12:44 +0000)]
[llvm-mca] Use a different character to flag instructions with side-effects in the Instruction Info View. NFC
This makes easier to identify changes in the instruction info flags. It also
helps spotting potential regressions similar to the one recently introduced at
r336728.
Using the same character to mark MayLoad/MayStore/HasSideEffects is problematic
for llvm-lit. When pattern matching substrings, llvm-lit consumes tabs and
spaces. A change in position of the flag marker may not trigger a test failure.
This patch only changes the character used for flag `hasSideEffects`. The reason
why I didn't touch other flags is because I want to avoid spamming the mailing
because of the massive diff due to the numerous tests affected by this change.
In future, each instruction flag should be associated with a different character
in the Instruction Info View.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336797
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Roman Lebedev [Wed, 11 Jul 2018 12:37:12 +0000 (12:37 +0000)]
[NFC][InstCombine] Tests for x & (-1 >> y) == x -> x u<= (-1 >> y) fold
https://bugs.llvm.org/show_bug.cgi?id=38123
This pattern will be produced by Implicit Integer Truncation sanitizer,
https://reviews.llvm.org/D48958
https://bugs.llvm.org/show_bug.cgi?id=21530
in unsigned case, therefore it is probably a good idea to improve it.
https://rise4fun.com/Alive/Rny
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336796
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Sjoerd Meijer [Wed, 11 Jul 2018 12:36:25 +0000 (12:36 +0000)]
[ARM] ParallelDSP: multiple reduction stmts in loop
This fixes an issue that we were not properly supporting multiple reduction
stmts in a loop, and not generating SMLADs for these cases. The alias analysis
checks were done too early, making it too conservative.
Differential revision: https://reviews.llvm.org/D49125
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336795
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Jonas Devlieghere [Wed, 11 Jul 2018 12:30:35 +0000 (12:30 +0000)]
Use debug-prefix-map for AT_NAME
AT_NAME was being emitted before the directory paths were remapped. This
ensures that all paths are remapped before anything is emitted.
An additional test case has been added.
Note that this only works if the replacement string is an absolute path.
If not, then AT_decl_file believes the new path is a relative path, and
joins that path with the compilation directory. I do not know of a good
way to resolve this.
Patch by: Siddhartha Bagaria (starsid)
Differential revision: https://reviews.llvm.org/D49169
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336793
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Florian Hahn [Wed, 11 Jul 2018 11:54:30 +0000 (11:54 +0000)]
Recommit r336653: [VPlan] Add VPlanTestBase.h with helper
The original version caused a memsan failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336792
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Sander de Smalen [Wed, 11 Jul 2018 11:22:26 +0000 (11:22 +0000)]
[AArch64][SVE] Asm: Support for COMPACT instruction.
The compact instruction shuffles active elements of vector
into lowest numbered elements and sets remaining elements
to zero.
e.g.
compact z0.s, p0, z1.s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336789
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Simon Pilgrim [Wed, 11 Jul 2018 10:42:51 +0000 (10:42 +0000)]
Fix check-prefix vs check-prefixes typo in updated test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336787
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Simon Pilgrim [Wed, 11 Jul 2018 10:39:50 +0000 (10:39 +0000)]
[AArch64] Regenerate SDIV tests
Will make codegen diffs much easier to grok in a future patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336786
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Roman Lebedev [Wed, 11 Jul 2018 10:31:12 +0000 (10:31 +0000)]
[NFC][InstCombine] icmp-logical.ll: add a few more tests.
The @masked_and_notA_slightly_optimized and @masked_or_A
will break when PR38123 will be fixed:
https://rise4fun.com/Alive/Rny
Clearly, they aren't optimized currently.
https://rise4fun.com/Alive/ERo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336784
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Sander de Smalen [Wed, 11 Jul 2018 10:08:00 +0000 (10:08 +0000)]
[AArch64][SVE] Asm: Support for LAST(A|B) and CLAST(A|B) instructions.
The LASTB and LASTA instructions extract the last active element,
or element after the last active, from the source vector.
The added variants are:
Scalar:
last(a|b) w0, p0, z0.b
last(a|b) w0, p0, z0.h
last(a|b) w0, p0, z0.s
last(a|b) x0, p0, z0.d
SIMD & FP Scalar:
last(a|b) b0, p0, z0.b
last(a|b) h0, p0, z0.h
last(a|b) s0, p0, z0.s
last(a|b) d0, p0, z0.d
The CLASTB and CLASTA conditionally extract the last or element after
the last active element from the source vector.
The added variants are:
Scalar:
clast(a|b) w0, p0, w0, z0.b
clast(a|b) w0, p0, w0, z0.h
clast(a|b) w0, p0, w0, z0.s
clast(a|b) x0, p0, x0, z0.d
SIMD & FP Scalar:
clast(a|b) b0, p0, b0, z0.b
clast(a|b) h0, p0, h0, z0.h
clast(a|b) s0, p0, s0, z0.s
clast(a|b) d0, p0, d0, z0.d
Vector:
clast(a|b) z0.b, p0, z0.b, z1.b
clast(a|b) z0.h, p0, z0.h, z1.h
clast(a|b) z0.s, p0, z0.s, z1.s
clast(a|b) z0.d, p0, z0.d, z1.d
Please refer to the architecture specification for more details on
the semantics of the added instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336783
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Paul Semel [Wed, 11 Jul 2018 10:00:29 +0000 (10:00 +0000)]
[llvm-readobj] Add -hex-dump (-x) option
Differential Revision: https://reviews.llvm.org/D48281
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336782
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Roman Lebedev [Wed, 11 Jul 2018 09:57:53 +0000 (09:57 +0000)]
[NFC][InstCombine] Fix extra space padding in icmp-mul-zext.ll test
update_test_checks will drop it anyway, creating noise..
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336781
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Roman Lebedev [Wed, 11 Jul 2018 09:57:46 +0000 (09:57 +0000)]
[NFC][InstCombine] Add variable names and regenerate icmp-logical.ll test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336780
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Simon Pilgrim [Wed, 11 Jul 2018 09:56:41 +0000 (09:56 +0000)]
[SelectionDAG] Add constant buildvector support to isKnownNeverZero
This allows us to use SelectionDAG::isKnownNeverZero in DAGCombiner::visitREM (visitSDIVLike/visitUDIVLike handle the checking for constants).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336779
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Andrea Di Biagio [Wed, 11 Jul 2018 09:50:00 +0000 (09:50 +0000)]
[llvm-mca] Add tests for partial register writes.
llvm-mca doesn't know that on modern AMD processors, portions of a general
purpose register are not treated independently. So, a partial register write has
a false dependency on the super-register.
The issue with partial register writes will be addressed by a follow-up patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336778
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Simon Atanasyan [Wed, 11 Jul 2018 09:41:28 +0000 (09:41 +0000)]
[mips] Remove dead code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336777
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Simon Pilgrim [Wed, 11 Jul 2018 09:22:42 +0000 (09:22 +0000)]
[DAGCombiner] Support non-uniform X%C -> X-(X/C)*C folds
First stage in PR38057 - support non-uniform constant vectors in the combine to reuse the division-by-constant logic.
We can definitely do better for srem pow2 remainders (and avoid that extra multiply....) but this at least helps keep everything on the vector unit.
Differential Revision: https://reviews.llvm.org/D48975
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336774
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Simon Pilgrim [Wed, 11 Jul 2018 09:14:37 +0000 (09:14 +0000)]
[DAGCombiner] Add (urem X, -1) -> select(X == -1, 0, x) fold
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336773
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Simon Tatham [Wed, 11 Jul 2018 08:57:56 +0000 (08:57 +0000)]
[TableGen] Add missing std::moves to fix build failure.
gcc 4.7 seems to disagree with gcc 5.3 about whether you need to say
'return std::move(thing)' instead of just 'return thing'. All the
json::Arrays and json::Objects that I was implicitly turning into
json::Values by returning them from functions now have explicit
std::move wrappers, so hopefully 4.7 will be happy now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336772
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Simon Tatham [Wed, 11 Jul 2018 08:40:19 +0000 (08:40 +0000)]
[TableGen] Add a general-purpose JSON backend.
The aim of this backend is to output everything TableGen knows about
the record set, similarly to the default -print-records backend. But
where -print-records produces output in TableGen's input syntax
(convenient for humans to read), this backend produces it as
structured JSON data, which is convenient for loading into standard
scripting languages such as Python, in order to extract information
from the data set in an automated way.
The output data contains a JSON representation of the variable
definitions in output 'def' records, and a few pieces of metadata such
as which of those definitions are tagged with the 'field' prefix and
which defs are derived from which classes. It doesn't dump out
absolutely every piece of knowledge it _could_ produce, such as type
information and complicated arithmetic operator nodes in abstract
superclasses; the main aim is to allow consumers of this JSON dump to
essentially act as new backends, and backends don't generally need to
depend on that kind of data.
The new backend is implemented as an EmitJSON() function similar to
all of llvm-tblgen's other EmitFoo functions, except that it lives in
lib/TableGen instead of utils/TableGen on the basis that I'm expecting
to add it to clang-tblgen too in a future patch.
To test it, I've written a Python script that loads the JSON output
and tests properties of it based on comments in the .td source - more
or less like FileCheck, except that the CHECK: lines have Python
expressions after them instead of textual pattern matches.
Reviewers: nhaehnle
Reviewed By: nhaehnle
Subscribers: arichardson, labath, mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D46054
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336771
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Eric Liu [Wed, 11 Jul 2018 08:16:47 +0000 (08:16 +0000)]
[WebAssembly] Only call llvm::value::dump() in debug build.
This fixes compile error in r336759. llvm::value::dump is not available
in released build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336770
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Craig Topper [Wed, 11 Jul 2018 06:57:42 +0000 (06:57 +0000)]
[X86] The TEST instruction is eliminated when BSF/TZCNT is used
Summary:
These changes cover the PR#31399.
Now the ffs(x) function is lowered to (x != 0) ? llvm.cttz(x) + 1 : 0
and it corresponds to the following llvm code:
%cnt = tail call i32 @llvm.cttz.i32(i32 %v, i1 true)
%tobool = icmp eq i32 %v, 0
%.op = add nuw nsw i32 %cnt, 1
%add = select i1 %tobool, i32 0, i32 %.op
and x86 asm code:
bsfl %edi, %ecx
addl $1, %ecx
testl %edi, %edi
movl $0, %eax
cmovnel %ecx, %eax
In this case the 'test' instruction can't be eliminated because
the 'add' instruction modifies the EFLAGS, namely, ZF flag
that is set by the 'bsf' instruction when 'x' is zero.
We now produce the following code:
bsfl %edi, %ecx
movl $-1, %eax
cmovnel %ecx, %eax
addl $1, %eax
Patch by Ivan Kulagin
Reviewers: davide, craig.topper, spatel, RKSimon
Reviewed By: craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48765
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336768
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Lang Hames [Wed, 11 Jul 2018 06:46:17 +0000 (06:46 +0000)]
Revert r336760: "[ORC] Add unit tests for the reexports utility that were..."
This patch broke a few buildbots. I will investigate and re-apply when I have
a fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336767
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Craig Topper [Wed, 11 Jul 2018 04:51:40 +0000 (04:51 +0000)]
[X86] Remove some composite MOVSS/MOVSD isel patterns.
These patterns looked for a MOVSS/SD followed by a scalar_to_vector. Or a scalar_to_vector followed by a load.
In both cases we emitted a MOVSS/SD for the MOVSS/SD part, a REG_CLASS for the scalar_to_vector, and a MOVSS/SD for the load.
But we have patterns that do each of those 3 things individually so there's no reason to build large patterns.
Most of the test changes are just reorderings. The one test that had a meaningful change is pr30430.ll and it appears to be a regression. But its doing -O0 so I think it missed a lot of opportunities and was just getting lucky before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336762
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Lang Hames [Wed, 11 Jul 2018 04:39:12 +0000 (04:39 +0000)]
[ORC] Remove a shadowing definition.
There is already a VSO member V in the CoreAPIsStandardTest test fixture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336761
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Lang Hames [Wed, 11 Jul 2018 04:39:11 +0000 (04:39 +0000)]
[ORC] Add unit tests for the reexports utility that were left out of r336741,
and fix a bug that these exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336760
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Sam Clegg [Wed, 11 Jul 2018 04:29:36 +0000 (04:29 +0000)]
[WebAssembly] Add pass to infer prototypes for prototype-less functions
See https://bugs.llvm.org/show_bug.cgi?id=35385
Differential Revision: https://reviews.llvm.org/D48471
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336759
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Lang Hames [Wed, 11 Jul 2018 03:58:47 +0000 (03:58 +0000)]
[ORC] Drop constexpr in unit test to appease a bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336758
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Lang Hames [Wed, 11 Jul 2018 03:09:36 +0000 (03:09 +0000)]
[ORC] Use a gtest fixture to remove a bunch of boilerplate in CoreAPIsTest.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336757
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Stefan Pintilie [Wed, 11 Jul 2018 01:42:22 +0000 (01:42 +0000)]
[Power9] Add remaining __flaot128 builtin support for FMA round to odd
Implement this as it is done on GCC:
__float128 a, b, c, d;
a = __builtin_fmaf128_round_to_odd (b, c, d); // generates xsmaddqpo
a = __builtin_fmaf128_round_to_odd (b, c, -d); // generates xsmsubqpo
a = - __builtin_fmaf128_round_to_odd (b, c, d); // generates xsnmaddqpo
a = - __builtin_fmaf128_round_to_odd (b, c, -d); // generates xsnmsubpqp
Differential Revision: https://reviews.llvm.org/D48218
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336754
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Chen Zheng [Wed, 11 Jul 2018 01:07:21 +0000 (01:07 +0000)]
[test cases] add test cases for find more abs pattern
Differential Revision: https://reviews.llvm.org/D49123
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336752
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Craig Topper [Wed, 11 Jul 2018 01:01:55 +0000 (01:01 +0000)]
[TableGen] Fix some bad formatting. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336751
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Eli Friedman [Wed, 11 Jul 2018 00:02:01 +0000 (00:02 +0000)]
[LangRef] Clarify alloca of zero bytes.
Let's be conservative here; it matches what we actually implemented, and
it should be rare in practice anyway.
Differential Revision: https://reviews.llvm.org/D49042
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336744
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Eli Friedman [Tue, 10 Jul 2018 23:44:37 +0000 (23:44 +0000)]
[ARM] Treat cmn immediates as legal in isLegalICmpImmediate.
The original code attempted to do this, but the std::abs() call didn't
actually do anything due to implicit type conversions. Fix the type
conversions, and perform the correct check for negative immediates.
This probably has very little practical impact, but it's worth fixing
just to avoid confusion in the future, I think.
Differential Revision: https://reviews.llvm.org/D48907
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336742
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Lang Hames [Tue, 10 Jul 2018 23:34:56 +0000 (23:34 +0000)]
[ORC] Generalize alias materialization to support re-exports (i.e. aliasing of
symbols in another VSO).
Also fixes a bug where chained aliases within a single VSO would deadlock on
materialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336741
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George Burgess IV [Tue, 10 Jul 2018 22:48:13 +0000 (22:48 +0000)]
Sort includes + include a missing `extern "C"` header
If we don't include Initialization.h,
`LLVMInitializeAggressiveInstCombiner` won't see its `extern "C"` decl.
This causes sadness, name mangling, and linker errors.
Reported on the mailing lists by Vladimir Vissoultchev. Thanks!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336736
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Craig Topper [Tue, 10 Jul 2018 22:23:54 +0000 (22:23 +0000)]
[X86] Remove AddedComplexity from all patterns that use X86vzmovl as their root.
Some added 20 and some added 15. Its unclear when to use which value and whether they are required at all.
This patch removes them all. If we start finding real world issues we may need to add them back with proper tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336735
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Richard Trieu [Tue, 10 Jul 2018 22:09:33 +0000 (22:09 +0000)]
Fix -Wmismatched-tags warning
class -> struct in forward declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336733
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Craig Topper [Tue, 10 Jul 2018 22:02:23 +0000 (22:02 +0000)]
[X86] Teach X86InstrInfo::commuteInstructionImpl to use MOVSD/MOVSS for BLEND under optsize when the immediate allows it.
Isel currently emits movss/movsd a lot of the time and an accidental double commute turns it into a blend.
Ideally we'd select blend directly in isel under optspeed and not rely on the double commute to create blend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336731
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JF Bastien [Tue, 10 Jul 2018 21:52:39 +0000 (21:52 +0000)]
[NFC] typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336730
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Craig Topper [Tue, 10 Jul 2018 21:00:22 +0000 (21:00 +0000)]
[X86] Remove X86ISD::MOVLPS and X86ISD::MOVLPD. NFCI
These ISD nodes try to select the MOVLPS and MOVLPD instructions which are special load only instructions. They load data and merge it into the lower 64-bits of an XMM register. They are logically equivalent to our MOVSD node plus a load.
There was only one place in X86ISelLowering that used MOVLPD and no places that selected MOVLPS. The one place that selected MOVLPD had to choose between it and MOVSD based on whether there was a load. But lowering is too early to tell if the load can really be folded. So in isel we have patterns that use MOVSD for MOVLPD if we can't find a load.
We also had patterns that select the MOVLPD instruction for a MOVSD if we can find a load, but didn't choose the MOVLPD ISD opcode for some reason.
So it seems better to just standardize on MOVSD ISD opcode and manage MOVSD vs MOVLPD instruction with isel patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336728
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Scott Linder [Tue, 10 Jul 2018 20:07:22 +0000 (20:07 +0000)]
[AMDGPU] Fix layering issue with AMDGPUHSAMetadataStreamer (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336722
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