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Craig Topper [Mon, 19 Mar 2018 16:38:33 +0000 (16:38 +0000)]
[X86] Make the multiply and divide itineraries more consistent.
Sometimes we used the same itinerary for MEM and REG forms, but that seems inconsistent with our usual usage.
We also used the MUL8 itinerary for MULX32/64 which was also weird.
The test changes are because we were using IIC_IMUL32_RR and IIC_IMUL64_RR instead of IIC_IMUL32_REG/IIC_IMUL64_REG for the 32 and 64 bit multiplies that produce double width result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327866
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Zaara Syeda [Mon, 19 Mar 2018 16:19:44 +0000 (16:19 +0000)]
Revert [MachineLICM] This reverts commit rL327856
Failing build bots. Revert the commit now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327864
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Matt Davis [Mon, 19 Mar 2018 16:06:40 +0000 (16:06 +0000)]
[CodeGen] Avoid handling DBG_VALUE in the LivePhysRegs (addUses,removeDefs,stepForward)
Summary:
This patch prevents DBG_VALUE instructions from influencing
LivePhysRegs::stepBackwards and stepForwards. In at least one case,
specifically branch folding, the stepBackwards logic was having an
influence on code generation. The result was that certain code
compiled with '-g -O2' would differ from that compiled with '-O2'
alone. It seems that the original logic, accounting for DBG_VALUE,
was influencing the placement of an IMPLICIT_DEF which had a later
impact on how blocks were processed in branch folding.
Reviewers: kparzysz, MatzeB
Reviewed By: kparzysz
Subscribers: bjope, llvm-commits
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D43850
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327862
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Erik Pilkington [Mon, 19 Mar 2018 15:18:23 +0000 (15:18 +0000)]
[demangler] Recopy the demangler from libcxxabi.
Some significant work has gone into libcxxabi's copy of this file:
- Uses an AST to represent mangled names.
- Support/bugfixes for many C++ features.
- Uses LLVM coding style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327859
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Sanjay Patel [Mon, 19 Mar 2018 15:14:30 +0000 (15:14 +0000)]
[InstCombine] canonicalize fcmp+select to fabs
This is complicated by -0.0 and nan. This is based on the DAG patterns
as shown in D44091. I'm hoping that we can just remove those DAG folds
and always rely on IR canonicalization to handle the matching to fabs.
We would still need to delete the broken code from DAGCombiner to fix
PR36600:
https://bugs.llvm.org/show_bug.cgi?id=36600
Differential Revision: https://reviews.llvm.org/D44550
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327858
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Zaara Syeda [Mon, 19 Mar 2018 14:52:25 +0000 (14:52 +0000)]
[MachineLICM] Add functions to MachineLICM to hoist invariant stores
This patch adds functions to allow MachineLICM to hoist invariant stores.
Currently, MachineLICM does not hoist any store instructions, however
when storing the same value to a constant spot on the stack, the store
instruction should be considered invariant and be hoisted. The function
isInvariantStore iterates each operand of the store instruction and checks
that each register operand satisfies isCallerPreservedPhysReg. The store
may be fed by a copy, which is hoisted by isCopyFeedingInvariantStore.
This patch also adds the PowerPC changes needed to consider the stack
register as caller preserved.
Differential Revision: https://reviews.llvm.org/D40196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327856
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Simon Pilgrim [Mon, 19 Mar 2018 14:46:07 +0000 (14:46 +0000)]
[X86] Generalize schedule classes to support multiple stages
Currently the WriteResPair style multi-classes take a single pipeline stage and latency, this patch generalizes this to make it easier to create complex schedules with ResourceCycles and NumMicroOps be overriden from their defaults.
This has already been done for the Jaguar scheduler to remove a number of custom schedule classes and adding it to the other x86 targets will make it much tidier as we add additional classes in the future to try and replace so many custom cases.
I've converted some instructions but a lot of the models need a bit of cleanup after the patch has been committed - memory latencies not being consistent, the class not actually being used when we could remove some/all customs, etc. I'd prefer to keep this as NFC as possible so later patches can be smaller and target specific.
Differential Revision: https://reviews.llvm.org/D44612
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327855
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Sanjay Patel [Mon, 19 Mar 2018 14:26:50 +0000 (14:26 +0000)]
[x86] put nops into the WriteNop class and customize for Jaguar
1. Given that we already have a classification bucket with 'nop' in the name,
that's where 'nop' belongs. Right now, it's only used for prefix bytes and 'pause'.
2. Make the latency of this class '1' for Jaguar to tell the scheduler (and presumably
llvm-mca) how to model the resource requirements better even though a nop has no
dependencies.
Differential Revision: https://reviews.llvm.org/D44608
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327853
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Ilya Biryukov [Mon, 19 Mar 2018 14:19:58 +0000 (14:19 +0000)]
Changed createTemporaryFile without FD to actually create a file.
Summary:
This commit changes semantics of createUniqueFile and
createTemporaryFile variants that do not return file descriptors.
Previously they only checked if files exist, therefore being subject
to race conditions. Now they will create an empty file to avoid them.
Functions that do not create a file are now called
getPotentiallyUniqueTempFileName and getPotentiallyUniqueFileName.
Reviewers: klimek, bkramer, krasimir, JDevlieghere, espindola
Reviewed By: klimek
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36827
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327851
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Nicolai Haehnle [Mon, 19 Mar 2018 14:14:28 +0000 (14:14 +0000)]
TableGen: Explicitly forbid self-references to field members
Summary:
Otherwise, patterns like in the test case produce cryptic error
messages about fields being resolved incompletely.
Change-Id: I713c0191f00fe140ad698675803ab1f8823dc5bd
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44476
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327850
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Nicolai Haehnle [Mon, 19 Mar 2018 14:14:20 +0000 (14:14 +0000)]
TableGen: Check the dynamic type of !cast<Rec>(string)
Summary:
The docs already claim that this happens, but so far it hasn't. As a
consequence, existing TableGen files get this wrong a lot, but luckily
the fixes are all reasonably straightforward.
To make this work with all the existing forms of self-references (since
the true type of a record is only built up over time), the lookup of
self-references in !cast is delayed until the final resolving step.
Change-Id: If5923a72a252ba2fbc81a889d59775df0ef31164
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D44475
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327849
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Nicolai Haehnle [Mon, 19 Mar 2018 14:14:10 +0000 (14:14 +0000)]
TableGen: Explicitly test some cases of self-references and !cast errors
Summary:
These are cases of self-references that exist today in practice. Let's
add tests for them to avoid regressions.
The self-references in PPCInstrInfo.td can be expressed in a simpler
way. Allowing this type of self-reference while at the same time
consistently doing late-resolve even for self-references is problematic
because there are references to fields that aren't in any class. Since
there's no need for this type of self-reference anyway, let's just
remove it.
Change-Id: I914e0b3e1ae7adae33855fac409b536879bc3f62
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: nemanjai, wdng, kbarton, llvm-commits
Differential Revision: https://reviews.llvm.org/D44474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327848
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Nicolai Haehnle [Mon, 19 Mar 2018 14:14:04 +0000 (14:14 +0000)]
TableGen: Only fold when some operand made resolve progress
Summary:
Make sure that we always fold immediately, so there's no point in
attempting to re-fold when nothing changes.
Change-Id: I069e1989455b6f2ca8606152f6adc1a5e817f1c8
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44198
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327847
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Nicolai Haehnle [Mon, 19 Mar 2018 14:13:59 +0000 (14:13 +0000)]
TableGen: Remove OpInit::Fold
Summary:
Virtual dispatch is not actually used anywhere.
Change-Id: I9829c5c59920ea27fb9bc17f1442156a3bb09a65
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44197
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327846
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Nicolai Haehnle [Mon, 19 Mar 2018 14:13:54 +0000 (14:13 +0000)]
TableGen: Move GenStrConcat to a helper function in BinOpInit
Summary:
Make it accessible for more users.
Change-Id: Ib05f09ba14e7942ced5d2f24b205efa285e40cd5
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327845
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Nicolai Haehnle [Mon, 19 Mar 2018 14:13:37 +0000 (14:13 +0000)]
TableGen: Remove the cast-from-string-to-variable-reference feature
Summary:
Cast-from-string for records isn't going away, but cast-from-string for
variables is a pretty dodgy feature to have, especially when referencing
template arguments. It's doubtful that this ever worked in a reliable
way, and nobody seems to be using it, so let's get rid of it and get
some related cleanups.
Change-Id: I395ac8a43fef4cf98e611f2f552300d21e99b66a
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44195
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327844
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Matt Arsenault [Mon, 19 Mar 2018 14:07:23 +0000 (14:07 +0000)]
AMDGPU/GlobalISel: RegBankSelect for basic int ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327843
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Matt Arsenault [Mon, 19 Mar 2018 14:07:15 +0000 (14:07 +0000)]
AMDGPU: Don't leave dead illegal VGPR->SGPR copies
Normally DCE kills these, but at -O0 these get left behind
leaving suspicious looking illegal copies.
Replace with IMPLICIT_DEF to avoid iterator issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327842
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Karl-Johan Karlsson [Mon, 19 Mar 2018 13:48:40 +0000 (13:48 +0000)]
[NFC] Fix minor typos in comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327841
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Clement Courbet [Mon, 19 Mar 2018 13:37:04 +0000 (13:37 +0000)]
[MergeICmps] Re-land 324317 "Enable the MergeICmps Pass by default."
Now that PR36557 is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327840
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Sjoerd Meijer [Mon, 19 Mar 2018 13:35:25 +0000 (13:35 +0000)]
[ARM] Support for v4f16 and v8f16 vectors
This is the groundwork for adding the Armv8.2-A FP16 vector intrinsics, which
uses v4f16 and v8f16 vector operands and return values. All the moving parts
are tested with two intrinsics, a 1-operand v8f16 and a 2-operand v4f16
intrinsic. In a follow-up patch the rest of the intrinsics and tests will be
added.
Differential Revision: https://reviews.llvm.org/D44538
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327839
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Xin Tong [Mon, 19 Mar 2018 13:35:23 +0000 (13:35 +0000)]
Stylish change. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327838
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Andrea Di Biagio [Mon, 19 Mar 2018 13:23:07 +0000 (13:23 +0000)]
[llvm-mca] Add pipeline stall events.
This patch introduces a new class named HWStallEvent (see HWEventListener.h),
and updates the event listener interface. A HWStallEvent represents a pipeline
stall caused by the lack of hardware resources. Similarly to HWInstructionEvent,
the event type is an unsigned, and the exact meaning depends on the subtarget.
At the moment, HWStallEvent supports a few generic dispatch events.
The main goals of this patch is to remove the logic that counts dispatch stalls
from the DispatchUnit to the BackendStatistics view.
Previously, DispatchUnit was responsible for counting and classifying dispatch
stall events. With this patch, we delegate the task of counting and classifying
stall events to the listeners (i.e. in our case, it is view
"BackendStatistics"). So, the DispatchUnit doesn't have to do extra
(unnecessary) bookkeeping.
This patch also helps futher simplifying the Backend interface. Now class
BackendStatistics no longer has to query the Backend interface to obtain the
number of dispatch stalls. As a consequence, we can get rid of all the
'getNumXXX()' methods from class Backend.
The long term goal is to remove all the remaining dependencies between the
Backend and the BackendStatistics interface.
Differential Revision: https://reviews.llvm.org/D44621
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327837
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Hans Wennborg [Mon, 19 Mar 2018 13:05:37 +0000 (13:05 +0000)]
build_llvm_package.bat: Drop LLDB from the package.
I don't think anyone ever got this to work, what with getting exactly
the right Python dependency and so on. Removing it simplifies the
script, removes a number of hairy dependencies, and cuts ~30 MB off the
installer size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327835
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Jonas Paulsson [Mon, 19 Mar 2018 13:05:22 +0000 (13:05 +0000)]
[SystemZ] Bugfix of CC liveness in emitMemMemWrapper (CLC).
If DoneMBB becomes empty it must have CC added to its live-in list, since it
will fall-through into EndMBB. This happens when the CLC loop does the
complete range.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327834
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Hans Wennborg [Mon, 19 Mar 2018 12:55:58 +0000 (12:55 +0000)]
HexagonISelLowering.cpp: fix 'enum in bool context' warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327832
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Alex Bradbury [Mon, 19 Mar 2018 11:54:28 +0000 (11:54 +0000)]
[RISCV] Peephole optimisation for load/store of global values or constant addresses
(load (add base, off), 0) -> (load base, off)
(store val, (add base, off)) -> (store val, base, off)
This is similar to an equivalent peephole optimisation in PPCISelDAGToDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327831
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Alexander Potapenko [Mon, 19 Mar 2018 10:08:04 +0000 (10:08 +0000)]
[MSan] fix the types of RegSaveAreaPtrPtr and OverflowArgAreaPtrPtr
Despite their names, RegSaveAreaPtrPtr and OverflowArgAreaPtrPtr
used to be i8* instead of i8**.
This is important, because these pointers are dereferenced twice
(first in CreateLoad(), then in getShadowOriginPtr()), but for some
reason MSan allowed this - most certainly because it was possible
to optimize getShadowOriginPtr() away at compile time.
Differential revision: https://reviews.llvm.org/D44520
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327830
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Alexander Potapenko [Mon, 19 Mar 2018 10:03:47 +0000 (10:03 +0000)]
[MSan] Don't create zero offsets in getShadowPtrForArgument(). NFC
For MSan instrumentation with MS.ParamTLS and MS.ParamOriginTLS being
TLS variables, the CreateAdd() with ArgOffset==0 is a no-op, because
the compiler is able to fold the addition of 0.
But for KMSAN, which receives ParamTLS and ParamOriginTLS from a call
to the runtime library, this introduces a stray instruction which
complicates reading/testing the IR.
Differential revision: https://reviews.llvm.org/D44514
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327829
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Alexander Potapenko [Mon, 19 Mar 2018 09:59:44 +0000 (09:59 +0000)]
[MSan] Introduce insertWarningFn(). NFC
This is a step towards the upcoming KMSAN implementation patch.
KMSAN is going to use a different warning function,
__msan_warning_32(uptr origin), so we'd better create the warning
calls in one place.
Differential Revision: https://reviews.llvm.org/D44513
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327828
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Mikhail Maltsev [Mon, 19 Mar 2018 09:48:58 +0000 (09:48 +0000)]
[ARM] Fix warnings about missing parentheses in ARMAsmParser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327827
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Serguei Katkov [Mon, 19 Mar 2018 08:32:09 +0000 (08:32 +0000)]
[SCEV] Factor out isKnownViaInduction. NFC.
This just extracts the isKnownViaInduction from isKnownPredicate.
Reviewers: sanjoy, mkazantsev, reames
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44554
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327824
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Serguei Katkov [Mon, 19 Mar 2018 06:35:30 +0000 (06:35 +0000)]
[SCEV] Re-land: Fix isKnownPredicate
This is re-land of https://reviews.llvm.org/rL327362 with a fix
and regression test.
The crash was due to it is possible that for found MDL loop,
LHS or RHS may contain an invariant unknown SCEV which
does not dominate the MDL. Please see regression
test for an example.
Reviewers: sanjoy, mkazantsev, reames
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44553
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327822
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Craig Topper [Mon, 19 Mar 2018 04:21:42 +0000 (04:21 +0000)]
[X86] Merge XADD8rr regular expression with XADD16rr/XADD32rr/XADD64rr in a couple scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327821
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Craig Topper [Mon, 19 Mar 2018 04:21:40 +0000 (04:21 +0000)]
[X86] Add ADD16i16/ADD32i32/ADD64i32 and similar to the scheduler models to match ADD8i8.
Also move ADC8i8 and SBB8i8 in the Sandy Bridge model to the same class as ADC8ri and SBB8ri. That seems more accurate since its the 8i8 is just the register forced to AL instead of coming from modrm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327820
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Craig Topper [Mon, 19 Mar 2018 02:07:32 +0000 (02:07 +0000)]
[X6] Remove two unused InstrItinClass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327819
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Craig Topper [Mon, 19 Mar 2018 00:56:12 +0000 (00:56 +0000)]
[X86] Use IIC_CMOV64_RR/RM on 64-bit cmov instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327817
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Craig Topper [Mon, 19 Mar 2018 00:56:11 +0000 (00:56 +0000)]
[X86] Merge 32 and 64-bit RORX/SHLX/SARX/SHRX into single regular expressions in scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327816
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Craig Topper [Mon, 19 Mar 2018 00:56:09 +0000 (00:56 +0000)]
[X86] Merge 8-bit instructions into instregex with 16/32/64 instructions in the scheduler models as much as possible. NFCI
This reduces the total number of generated scheduler classes from 5404 to 5316.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327815
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Dylan McKay [Mon, 19 Mar 2018 00:55:50 +0000 (00:55 +0000)]
[AVR] Lower i128 divisions to runtime library calls
This patch adds i128 division support by instruction LLVM to lower
128-bit divisions to the __udivmodti4 and __divmodti4 rtlib functions.
This also adds test for 64-bit division and 128-bit division.
Patch by Peter Nimmervoll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327814
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Craig Topper [Sun, 18 Mar 2018 22:16:54 +0000 (22:16 +0000)]
[Mips] Remove duplicate lines from MipsScheduleP5600.td and enable FullInstRWOverlapCheck.
This fixes the errors found by the new check added in r327808.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327813
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Craig Topper [Sun, 18 Mar 2018 22:16:53 +0000 (22:16 +0000)]
[AArch64] Fix a few InstRWs in the A53 scheduler model and enable FullInstRWOverlapCheck.
This fixes the errors found by the new check added in r327808.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327812
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Craig Topper [Sun, 18 Mar 2018 21:28:11 +0000 (21:28 +0000)]
[SelectionDAG] Don't default the SelectionDAG* parameter to SDValue::dump to nullptr. Use two different signatures instead.
This matches what we do in SDNode.
This should allow SDValue::dump to be used in the debugger without getting an error if you don't pass an argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327811
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Craig Topper [Sun, 18 Mar 2018 19:56:15 +0000 (19:56 +0000)]
[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
This is similar to the check later when we remap some of the instructions from one class to a new one. But if we reuse the class we don't get to do that check.
So many CPUs have violations of this check that I had to add a flag to the SchedMachineModel to allow it to be disabled. Hopefully we can get those cleaned up quickly and remove this flag.
A lot of the violations are due to overlapping regular expressions, but that's not the only kind of issue it found.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327808
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Simon Pilgrim [Sun, 18 Mar 2018 19:54:42 +0000 (19:54 +0000)]
[X86][Btver2] Fix crc32 schedule costs
The default is currently FAdd for some reason
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327807
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Simon Pilgrim [Sun, 18 Mar 2018 18:55:34 +0000 (18:55 +0000)]
[X86][Btver2] Add crc32 resource tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327805
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Simon Pilgrim [Sun, 18 Mar 2018 18:45:57 +0000 (18:45 +0000)]
[X86][Btver2] FADD/FHADD ymm instructions are double pumped on the JFPA functional pipe
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327804
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Simon Pilgrim [Sun, 18 Mar 2018 17:10:12 +0000 (17:10 +0000)]
[X86][Btver2] Float bitwise ymm instructions are double pumped on the JFPX (JFPA/JFPM) functional pipes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327803
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Simon Pilgrim [Sun, 18 Mar 2018 15:59:51 +0000 (15:59 +0000)]
[X86][Btver2] F16C instructions are performed on the JSTC functional pipe
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327801
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Anastasis Grammenos [Sun, 18 Mar 2018 15:59:19 +0000 (15:59 +0000)]
[LICM] Salvage DI from dying Instructions
LICM deletes trivially dead instructions which it won't attempt to sink.
Attempt to salvage debug values which reference these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327800
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Roman Lebedev [Sun, 18 Mar 2018 15:53:02 +0000 (15:53 +0000)]
[InstCombine] peek through unsigned FP casts for zero-equality compares (PR36682)
Summary:
This pattern came up in PR36682 / D44390
https://bugs.llvm.org/show_bug.cgi?id=36682
https://reviews.llvm.org/D44390
https://godbolt.org/g/oKvT5H
See also D44416
Reviewers: spatel, majnemer, efriedma, arsenm
Reviewed By: spatel
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44424
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327799
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Andrea Di Biagio [Sun, 18 Mar 2018 15:33:27 +0000 (15:33 +0000)]
[llvm-mca] Allow the definition of multiple register files.
This is a refactoring in preparation for other two changes that will allow
scheduling models to define multiple register files. This is the first step
towards fixing PR36662.
class RegisterFile (in Dispatch.h) now can emulate multiple register files.
Internally, it tracks the number of available physical registers in each
register file (described by class RegisterFileInfo).
Each register file is associated to a list of MCRegisterClass indices. Knowing
the register class indices allows to map physical registers to register files.
The long term goal is to allow processor models to optionally specify how many
register files are implemented via tablegen.
Differential Revision: https://reviews.llvm.org/D44488
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327798
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Sanjay Patel [Sun, 18 Mar 2018 14:32:54 +0000 (14:32 +0000)]
[InstCombine] add nnan requirement for sqrt(x) * sqrt(y) -> sqrt(x*y)
This is similar to D43765.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327797
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Sanjay Patel [Sun, 18 Mar 2018 14:12:25 +0000 (14:12 +0000)]
[InstSimplify] loosen FMF for sqrt(X) * sqrt(X) --> X
As shown in the code comment, we don't need all of 'fast',
but we do need reassoc + nsz + nnan.
Differential Revision: https://reviews.llvm.org/D43765
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327796
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Simon Pilgrim [Sun, 18 Mar 2018 13:16:11 +0000 (13:16 +0000)]
[X86][Btver2] Strip default latency/resource values. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327795
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Simon Pilgrim [Sun, 18 Mar 2018 13:05:09 +0000 (13:05 +0000)]
[X86][Btver2] SSE4A EXTRQ/INSERTQ instructions are performed on the JVALU0/JVALU1 functional pipes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327794
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Simon Pilgrim [Sun, 18 Mar 2018 12:37:35 +0000 (12:37 +0000)]
[X86][Btver2] Modelled float bitwise instructions as being performed on the float cluster (FPA/FPM) not the integer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327793
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Jonas Devlieghere [Sun, 18 Mar 2018 12:27:05 +0000 (12:27 +0000)]
[dsymutil] Fix add_llvm_tool_symlink
Update the arguments to add_llvm_tool_symlink to symlink llvm-dsymutil
to dsymutil.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327792
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Simon Pilgrim [Sun, 18 Mar 2018 12:09:17 +0000 (12:09 +0000)]
[X86][Btver2] Correctly distinguish between scheduling pipe and functional unit for JWriteResFpuPair defs
Jaguar's FPU has 2 scheduler pipes (JFPU0/JFPU1) which forward to multiple functional sub-units each. We need to model that an micro-op will both consume the scheduler pipe and a functional unit.
This patch just handles the ops defined through JWriteResFpuPair, I'll go through the custom cases later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327791
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Jonas Devlieghere [Sun, 18 Mar 2018 11:38:41 +0000 (11:38 +0000)]
[dsymutil] Rename llvm-dsymutil -> dsymutil
Now that almost all functionality of Apple's dsymutil has been
upstreamed, the open source variant can be used as a drop in
replacement. Hence we feel it's no longer necessary to have the llvm
prefix.
Differential revision: https://reviews.llvm.org/D44527
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327790
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Simon Pilgrim [Sun, 18 Mar 2018 10:22:35 +0000 (10:22 +0000)]
[X86][Btver2] Merge equivalent VBLENDVY + VPERMILY schedule groups
Thanks to Craig Topper for noticing this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327789
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Simon Pilgrim [Sun, 18 Mar 2018 09:32:38 +0000 (09:32 +0000)]
[X86][Btver2] Add llvm-mca tests to show pipe resource usage of most vector instructions
Hopefully these tests can be easily reused should any other subtarget get in depth llvm-mca coverage (we can either copy the tests or move them into a common dir and run it with multiple prefixes).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327788
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Craig Topper [Sun, 18 Mar 2018 08:38:06 +0000 (08:38 +0000)]
[X86] Fix a bunch of overlapping regular expressions in the scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327787
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Craig Topper [Sun, 18 Mar 2018 08:38:04 +0000 (08:38 +0000)]
[X86] Fix a couple typos in the Zen scheduler model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327786
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Craig Topper [Sun, 18 Mar 2018 08:38:03 +0000 (08:38 +0000)]
[TableGen] Remove unnecessary uses of make_range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327785
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Craig Topper [Sun, 18 Mar 2018 08:38:02 +0000 (08:38 +0000)]
[TableGen] Move some variables into for loop declaration. NFC
They aren't needed after the loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327784
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Craig Topper [Sun, 18 Mar 2018 03:24:42 +0000 (03:24 +0000)]
[X86] Remove MMX_MASKMOVQ64 and VMASKMOVDQU from scheduler models.
The information was so wildly inaccurate and incomplete its better to just remove it.
MMX_MASKMOVQ64 showed up twice in several scheduler models. In Haswell and Broadwell they were on adjacent lines. On Skylake the copies had different information.
MMX_MASKMOVQ and MASKMOVDQU were completely missing.
MMX_MASKMOVQ64 was listed on Haswell/Broadwell as 1 cycle on port 1 despite it being a store instruction.
Filed PR36780 to track fixing this right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327783
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Martin Storsjo [Sat, 17 Mar 2018 20:08:48 +0000 (20:08 +0000)]
[AArch64] Skip an unnecessary getCopyToReg in DYNAMIC_STACKALLOC
Differential Revision: https://reviews.llvm.org/D44586
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327779
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Nirav Dave [Sat, 17 Mar 2018 19:24:54 +0000 (19:24 +0000)]
Revert "[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172""
as it times out building test-suite on PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327778
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Nirav Dave [Sat, 17 Mar 2018 17:42:10 +0000 (17:42 +0000)]
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
Reland ISel cycle checking improvements after simplifying and reducing
node id invariant traversal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327777
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Sylvestre Ledru [Sat, 17 Mar 2018 17:30:08 +0000 (17:30 +0000)]
Fix some user facing typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327776
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Matt Arsenault [Sat, 17 Mar 2018 15:17:48 +0000 (15:17 +0000)]
AMDGPU/GlobalISel: Cleanup constant legality
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327774
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Matt Arsenault [Sat, 17 Mar 2018 15:17:45 +0000 (15:17 +0000)]
AMDGPU/GlobalISel: Basic G_GEP legality
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327773
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Matt Arsenault [Sat, 17 Mar 2018 15:17:41 +0000 (15:17 +0000)]
AMDGPU/GlobalISel: Basic legality for load/store
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327772
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Chandler Carruth [Sat, 17 Mar 2018 15:12:52 +0000 (15:12 +0000)]
[bindings/go] Add a missing `,` in the test code to fix a go compile
failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327771
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Oren Ben Simhon [Sat, 17 Mar 2018 13:29:46 +0000 (13:29 +0000)]
[X86] Added support for nocf_check attribute for indirect Branch Tracking
X86 Supports Indirect Branch Tracking (IBT) as part of Control-Flow Enforcement Technology (CET).
IBT instruments ENDBR instructions used to specify valid targets of indirect call / jmp.
TheĀ `nocf_check` attribute has two roles in the context of X86 IBT technology:
1. Appertains to a function - do not add ENDBR instruction at the beginning of the function.
2. Appertains to a function pointer - do not track the target function of this pointer by adding nocf_check prefix to the indirect-call instruction.
This patch implementsĀ `nocf_check` context for Indirect Branch Tracking.
It also auto generatesĀ `nocf_check` prefixes before indirect branchs to jump tables that are guarded by range checks.
Differential Revision: https://reviews.llvm.org/D41879
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327767
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Jonas Paulsson [Sat, 17 Mar 2018 09:15:13 +0000 (09:15 +0000)]
[SystemZ] Add 'REQUIRES: asserts' to test case using debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327766
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Jonas Paulsson [Sat, 17 Mar 2018 08:32:12 +0000 (08:32 +0000)]
[SystemZ] computeKnownBitsForTargetNode() / ComputeNumSignBitsForTargetNode()
Improve/implement these methods to improve DAG combining. This mainly
concerns intrinsics.
Some constant operands to SystemZISD nodes have been marked Opaque to avoid
transforming back and forth between generic and target nodes infinitely.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327765
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Jonas Paulsson [Sat, 17 Mar 2018 08:04:00 +0000 (08:04 +0000)]
[SelectionDAG] Handle big endian target BITCAST in computeKnownBits()
The BITCAST handling in computeKnownBits() previously only worked for little
endian.
This patch reverses the iteration over elements for a big endian target which
allows this to work in this case also.
SystemZ test case.
Review: Eli Friedman
https://reviews.llvm.org/D44249
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327764
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Chandler Carruth [Fri, 16 Mar 2018 23:51:33 +0000 (23:51 +0000)]
[GlobalsAA] Fix a pretty terrible bug that has been in GlobalsAA for
a long time.
The key thing is that we need to create value handles for every function
that we create a `FunctionInfo` object around. Without this, when that
function is deleted we can end up creating a new function that collides
with its address and look up a stale AA result. With that AA result we
can in turn miscompile code in ways that break.
This is seriously one of the most absurd miscompiles I've seen. It only
reproduced for us recently and only when building a very large server
with both ThinLTO and PGO.
A *HUGE* shout out to Wei Mi who tracked all of this down and came up
with this patch. I'm just landing it because I happened to still by at
a computer.
He or I can work on crafting a test case to hit this (now that we know
what to target) but it'll take a while, and we've been chasing this for
a long time and need it fix Right Now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327761
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Jessica Paquette [Fri, 16 Mar 2018 22:53:34 +0000 (22:53 +0000)]
[MachineOutliner] Make KILLs invisible
At the point the outliner runs, KILLs don't impact anything, but they're still
considered unique instructions. This commit makes them invisible like
DebugValues so that they can still be outlined without impacting outlining
decisions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327760
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Andrea Di Biagio [Fri, 16 Mar 2018 22:21:52 +0000 (22:21 +0000)]
[llvm-mca] Remove method getSchedModel() from the Backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327756
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Andrea Di Biagio [Fri, 16 Mar 2018 22:02:47 +0000 (22:02 +0000)]
[llvm-mca] Remove unused methods from Backend. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327749
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David L Kreitzer [Fri, 16 Mar 2018 21:21:23 +0000 (21:21 +0000)]
Quiet unused variable warnings. NFC.
Differential revision: https://reviews.llvm.org/D44583
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327745
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Craig Topper [Fri, 16 Mar 2018 21:10:07 +0000 (21:10 +0000)]
[X86] Pass SelectionDAG into X86ISelAddressMode::dump and on to SDNode::dump.
This prevents a crash in SelectionDAGDumper with -debug when trying to print mem operands if one of the registers in the addressing mode comes from a load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327744
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Sanjay Patel [Fri, 16 Mar 2018 20:55:55 +0000 (20:55 +0000)]
[InstSimplify] add NaN constant diversity; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327743
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Krzysztof Parzyszek [Fri, 16 Mar 2018 20:55:49 +0000 (20:55 +0000)]
[Hexagon] Avoid bank conflicts in post-RA scheduler
Avoid scheduling two loads in such a way that they would end up in the
same packet. If there is a load in a packet, try to schedule a non-load
next.
Patch by Brendon Cahoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327742
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Krzysztof Parzyszek [Fri, 16 Mar 2018 20:21:43 +0000 (20:21 +0000)]
[Hexagon] Add lit testcases for atomic intrinsics
Patch by Ben Craig.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327737
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Reid Kleckner [Fri, 16 Mar 2018 20:13:32 +0000 (20:13 +0000)]
[IR] Avoid the need to prefix MS C++ symbols with '\01'
Now the Windows mangling modes ('w' and 'x') do not do any mangling for
symbols starting with '?'. This means that clang can stop adding the
hideous '\01' leading escape. This means LLVM debug logs are less likely
to contain ASCII escape characters and it will be easier to copy and
paste MS symbol names from IR.
Finally.
For non-Windows platforms, names starting with '?' still get IR
mangling, so once clang stops escaping MS C++ names, we will get extra
'_' prefixing on MachO. That's fine, since it is currently impossible to
construct a triple that uses the MS C++ ABI in clang and emits macho
object files.
Differential Revision: https://reviews.llvm.org/D7775
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327734
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Reid Kleckner [Fri, 16 Mar 2018 20:11:55 +0000 (20:11 +0000)]
Revert r327721 "This patch fixes the invalid usage of OptSize in Machine Combiner."
It causes asserts when compiling Chromium on Win32 with optimizations.
We compile many things with -Os.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327733
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Craig Topper [Fri, 16 Mar 2018 18:25:59 +0000 (18:25 +0000)]
[X86] Merge ADDSUB/SUBADD detection into single methods that can detect either and indicate what they found.
Previously, we called the same functions twice with a bool flag determining whether we should look for ADDSUB or SUBADD. It would be more efficient to run the code once and detect either pattern with a flag to tell which type it found.
Differential Revision: https://reviews.llvm.org/D44540
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327730
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Craig Topper [Fri, 16 Mar 2018 18:18:47 +0000 (18:18 +0000)]
[CorrelatedValuePropagation] Use SelectInst::getCondition/getTrueValue/getFalseValue instead of getOperand for readability. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327728
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Farhana Aleen [Fri, 16 Mar 2018 18:12:00 +0000 (18:12 +0000)]
[AMDGPU] Supported ds_write_b128 generation.
Summary: This is a follow-on patch of https://reviews.llvm.org/D44210
Author: FarhanaAleen
Reviewed By: msearles
Subscribers: llvm-commits, AMDGPU
Differential Revision: https://reviews.llvm.org/D44319
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327726
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Craig Topper [Fri, 16 Mar 2018 17:13:42 +0000 (17:13 +0000)]
[X86] Post process the DAG after isel to remove vector moves that were added to zero upper bits.
We previously avoided inserting these moves during isel in a few cases which is implemented using a whitelist of opcodes. But it's too difficult to generate a perfect list of opcodes to whitelist. Especially with AVX512F without AVX512VL using 512 bit vectors to implement some 128/256 bit operations. Since isel is done bottoms up, we'd have to check the VT and opcode and subtarget in order to determine whether an EXTRACT_SUBREG would be generated for some operations.
So instead of doing that, this patch adds a post processing step that detects when the moves are unnecesssary after isel. At that point any EXTRACT_SUBREGs would have already been created and appear in the DAG. So then we just need to ensure the input to the move isn't one.
Differential Revision: https://reviews.llvm.org/D44289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327724
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Dmitry Preobrazhensky [Fri, 16 Mar 2018 16:38:04 +0000 (16:38 +0000)]
[AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP opcodes
See bug 36751: https://bugs.llvm.org/show_bug.cgi?id=36751
Differential Revision: https://reviews.llvm.org/D44529
Reviewers: artem.tamazov, arsenm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327723
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Philip Reames [Fri, 16 Mar 2018 16:33:49 +0000 (16:33 +0000)]
[LICM/mustexec] Extend first iteration must execute logic to fcmps
This builds on the work from https://reviews.llvm.org/D44287. It turned out supporting fcmp was much easier than I realized, so let's do that now.
As an aside, our -O3 handling of a floating point IVs leaves a lot to be desired. We do convert the float IV to an integer IV, but do so late enough that many other optimizations are missed (e.g. we don't vectorize).
Differential Revision: https://reviews.llvm.org/D44542
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327722
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Andrew V. Tischenko [Fri, 16 Mar 2018 16:06:24 +0000 (16:06 +0000)]
This patch fixes the invalid usage of OptSize in Machine Combiner.
Differential Revision: https://reviews.llvm.org/D43813
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327721
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Dmitry Preobrazhensky [Fri, 16 Mar 2018 15:40:27 +0000 (15:40 +0000)]
[AMDGPU][MC] Corrected default values for unused SDWA operands
See bug 36355: https://bugs.llvm.org/show_bug.cgi?id=36355
Differential Revision: https://reviews.llvm.org/D44481
Reviewers: artem.tamazov, arsenm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327720
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Sanjay Patel [Fri, 16 Mar 2018 15:27:39 +0000 (15:27 +0000)]
[InstCombine] add nnan requirement to potential fabs folds tests; NFC
As noted in D44550, we can't guarantee preserving the sign-bit of NaN
if we convert these to fabs().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327718
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Jonas Paulsson [Fri, 16 Mar 2018 15:21:26 +0000 (15:21 +0000)]
[SystemZ] Make AnyRegBitRegClass unallocatable.
AnyReg is just for the assembler and it is better to have it as not
allocatable in order to simplify (make more intuitive) the RegPressureSets.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327715
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