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Daniel Neilson [Tue, 18 Jul 2017 01:06:52 +0000 (01:06 +0000)]
Add element-atomic mem intrinsic canary tests for Dataflow Sanitizer.
Summary:
Add canary tests to verify that DFSAN currently does nothing with the element atomic memory intrinsics for memcpy, memmove, and memset.
Placeholder tests that will fail once @llvm.mem[cpy|move|set] instrinsics have been added to the MemIntrinsic class hierarchy. These will act as a reminder to verify that DFSAN handles these intrinsics properly once they have been added to that class hierarchy.
Note that there could be some trickiness with these element-atomic intrinsics for the dataflow sanitizer in racy multithreaded programs. The data flow sanitizer inserts additional lib calls to mirror the memory intrinsic's action, so it is possible (very likely, even) that the dfsan buffers will not be in sync with the original buffers. Furthermore, implementation of the dfsan buffer updates for the element atomic intrinsics will have to also use unordered atomic instructions. If we can assume that dfsan is never run on racy multithreaded programs, then the element atomic memory intrinsics can pretty much be treated the same as the regular memory intrinsics.
Reviewers: reames
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D35507
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308249
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Daniel Neilson [Tue, 18 Jul 2017 01:06:52 +0000 (01:06 +0000)]
Add element-atomic mem intrinsic canary tests for Address Sanitizer.
Summary:
Add canary tests to verify that ASAN currently does nothing with the element atomic memory intrinsics for memcpy, memmove, and memset.
Placeholder tests that will fail once element atomic @llvm.mem[cpy|move|set] instrinsics have been added to the MemIntrinsic class hierarchy. These will act as a reminder to verify that ASAN handles these intrinsics properly once they have been added to that class hierarchy.
Reviewers: reames
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D35505
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308248
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Daniel Neilson [Tue, 18 Jul 2017 01:06:47 +0000 (01:06 +0000)]
Add element-atomic mem intrinsic canary tests for InstCombine.
Summary:
Add canary tests to verify that InstCombine currently does nothing with the element atomic memory intrinsics for memmove and memset.
Placeholder tests that will fail once element atomic @llvm.mem[move|set] instrinsics have been added to the MemIntrinsic class hierarchy. These will act as a reminder to verify that inst combine handles these intrinsics properly once they have been added to that class hierarchy.
Reviewers: reames
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D35502
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308247
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Kostya Serebryany [Tue, 18 Jul 2017 01:00:28 +0000 (01:00 +0000)]
[libFuzzer] disable fuzzer-flags.test on windows to fix the bots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308246
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Spyridoula Gravani [Tue, 18 Jul 2017 01:00:26 +0000 (01:00 +0000)]
[DWARF] Modification of code for the verification of .debug_info section.
Summary:
This patch modifies the handleDebugInfo() function so that we verify the contents of each unit
in the .debug_info section only if its header has been successfully verified.
This change will allow for more/different verification checks depending on the type of the unit since from
dwarf5, the .debug_info section may consist of different types of units.
Subscribers: aprantl
Differential Revision: https://reviews.llvm.org/D35521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308245
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Reid Kleckner [Tue, 18 Jul 2017 00:44:10 +0000 (00:44 +0000)]
Fix pdbdump-headers.test after TPI hash changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308244
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Reid Kleckner [Tue, 18 Jul 2017 00:33:45 +0000 (00:33 +0000)]
[PDB] Finish and simplify TPI hashing
Summary:
This removes the CVTypeVisitor updater and verifier classes. They were
made dead by the minimal type dumping refactoring. Replace them with a
single function that takes a type record and produces a hash. Call this
from the minimal type dumper and compare the hash.
I also noticed that the microsoft-pdb reference repository uses a basic
CRC32 for records that aren't special. We already have an implementation
of that CRC ready to use, because it's used in COFF for ICF.
I'll make LLD call this hashing utility in a follow-up change. We might
also consider using this same hash in type stream merging, so that we
don't have to hash our records twice.
Reviewers: inglorion, ruiu
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D35515
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308240
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Reid Kleckner [Tue, 18 Jul 2017 00:21:25 +0000 (00:21 +0000)]
[PDB] Merge in types and items from type servers (/Zi)
Summary:
Object files compiled with /Zi emit type information into a type server
PDB. The .debug$S section will contain a single TypeServer2Record with
the absolute path and GUID of the type server. LLD needs to load the
type server PDB and merge all types and items it finds in it into the
destination PDB.
Depends on D35495
Reviewers: ruiu, inglorion
Subscribers: zturner, llvm-commits
Differential Revision: https://reviews.llvm.org/D35504
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308235
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Reid Kleckner [Mon, 17 Jul 2017 23:59:44 +0000 (23:59 +0000)]
[codeview] Fix YAML for LF_TYPESERVER2 by hoisting PDB_UniqueId
Summary:
We were treating the GUIDs in TypeServer2Record as strings, and the
non-ASCII bytes in the GUID would not round-trip through YAML.
We already had the PDB_UniqueId type portably represent a Windows GUID,
but we need to hoist that up to the DebugInfo/CodeView library so that
we can use it in the TypeServer2Record as well as in PDB parsing code.
Reviewers: inglorion, amccarth
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D35495
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308234
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Eric Beckmann [Mon, 17 Jul 2017 23:36:13 +0000 (23:36 +0000)]
Adding yet more debug info to fix fedora issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308232
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Eric Beckmann [Mon, 17 Jul 2017 22:46:10 +0000 (22:46 +0000)]
Adding temporary debugging info to llvm-mt to solve fedora failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308227
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Matt Arsenault [Mon, 17 Jul 2017 22:35:50 +0000 (22:35 +0000)]
AMDGPU: Annotate features from x work item/group IDs.
This wasn't necessary before since they are always enabled
for kernels, but this is necessary if they need to be
forwarded to a callable function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308226
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Eric Beckmann [Mon, 17 Jul 2017 21:35:12 +0000 (21:35 +0000)]
Create empty shell of llvm-mt.
Summary:
This is the first patch towards creating the llvm-mt tool for merging
Windows manifests. This is a reimplementation of mt.exe.
Reviewers: zturner, ruiu, rnk
Subscribers: llvm-commits, mgorny
Differential Revision: https://reviews.llvm.org/D35333
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308224
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Mandeep Singh Grang [Mon, 17 Jul 2017 21:25:19 +0000 (21:25 +0000)]
[COFF, ARM64] Correct the data layout string for COFF ARM64 target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308223
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Reid Kleckner [Mon, 17 Jul 2017 20:31:38 +0000 (20:31 +0000)]
[codeview] Don't use the type visitor to merge types
Summary:
This didn't do much to speed things up, but it implements a FIXME, and I
think it's a nice simplification. We don't need the record kind switch.
We're doing that ourselves.
Reviewers: ruiu, inglorion
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D35496
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308213
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Reid Kleckner [Mon, 17 Jul 2017 20:28:06 +0000 (20:28 +0000)]
[codeview] Remove TypeServerHandler and PDBTypeServerHandler
Summary:
Instead of wiring these through the CVTypeVisitor interface, clients
should inspect the CVTypeArray before visiting it and potentially load
up the type server's TPI stream if they need it.
No tests relied on this functionality because LLD was the only client.
Reviewers: ruiu
Subscribers: mgorny, hiraditya, zturner, llvm-commits
Differential Revision: https://reviews.llvm.org/D35394
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308212
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Geoff Berry [Mon, 17 Jul 2017 20:19:05 +0000 (20:19 +0000)]
[AArch64][Falkor] Address some stylistic review comments. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308211
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Martin Storsjo [Mon, 17 Jul 2017 20:05:19 +0000 (20:05 +0000)]
[AArch64] Extend CallingConv::X86_64_Win64 to AArch64 as well
Rename the enum value from X86_64_Win64 to plain Win64.
The symbol exposed in the textual IR is changed from 'x86_64_win64cc'
to 'win64cc', but the numeric value is kept, keeping support for
old bitcode.
Differential Revision: https://reviews.llvm.org/D34474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308208
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Teresa Johnson [Mon, 17 Jul 2017 19:25:38 +0000 (19:25 +0000)]
Revert "Restore with fix "[ThinLTO] Ensure we always select the same function copy to import""
This reverts commit r308114 (and follow on fixes to test).
There is a linking failure in a ThinLTO bot:
http://green.lab.llvm.org/green/job/clang-stage2-configure-Rthinlto_build/3663/
(and undefined reference). It seems like it must be a second order
effect of the heuristic change I made, and may take some time to try
to reproduce locally and track down. Therefore, reverting for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308206
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Lang Hames [Mon, 17 Jul 2017 18:36:35 +0000 (18:36 +0000)]
[ORC] Remove extraneous else.
As suggested by Dave Blaikie in review on r307952. Thanks Dave!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308203
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George Karpenkov [Mon, 17 Jul 2017 18:18:03 +0000 (18:18 +0000)]
Revert "[libFuzzer] Add a dependency on symbolizer from libFuzzer tests"
This reverts commit
546e006a023cccd0fd32afd442ab992d3515d4b8.
Reverting until I can figure out llvm-symbolizer breakages on mac os.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308202
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Adam Nemet [Mon, 17 Jul 2017 18:00:41 +0000 (18:00 +0000)]
[opt-viewer] Accept directories that are searched for opt.yaml files
This allows to pass the build directory where all the opt.yaml files are
rather than find | xargs which may invoke opt-viewer multiple times producing
incomplete html output.
The patch generalizes the same functionality from opt-diff.
Differential Revision: https://reviews.llvm.org/D35491
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308200
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Ulrich Weigand [Mon, 17 Jul 2017 17:44:20 +0000 (17:44 +0000)]
[SystemZ] Add support for IBM z14 processor (3/3)
This adds support for the new 128-bit vector float instructions of z14.
Note that these instructions actually only operate on the f128 type,
since only each 128-bit vector register can hold only one 128-bit
float value. However, this is still preferable to the legacy 128-bit
float instructions, since those operate on pairs of floating-point
registers (so we can hold at most 8 values in registers), while the
new instructions use single vector registers (so we hold up to 32
value in registers).
Adding support includes:
- Enabling the instructions for the assembler/disassembler.
- CodeGen for the instructions. This includes allocating the f128
type now to the VR128BitRegClass instead of FP128BitRegClass.
- Scheduler description support for the instructions.
Note that for a small number of operations, we have no new vector
instructions (like integer <-> 128-bit float conversions), and so
we use the legacy instruction and then reformat the operand
(i.e. copy between a pair of floating-point registers and a
vector register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308196
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Ulrich Weigand [Mon, 17 Jul 2017 17:42:48 +0000 (17:42 +0000)]
[SystemZ] Add support for IBM z14 processor (2/3)
This adds support for the new 32-bit vector float instructions of z14.
This includes:
- Enabling the instructions for the assembler/disassembler.
- CodeGen for the instructions, including new LLVM intrinsics.
- Scheduler description support for the instructions.
- Update to the vector cost function calculations.
In general, CodeGen support for the new v4f32 instructions closely
matches support for the existing v2f64 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308195
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Ulrich Weigand [Mon, 17 Jul 2017 17:41:11 +0000 (17:41 +0000)]
[SystemZ] Add support for IBM z14 processor (1/3)
This patch series adds support for the IBM z14 processor. This part includes:
- Basic support for the new processor and its features.
- Support for new instructions (except vector 32-bit float and 128-bit float).
- CodeGen for new instructions, including new LLVM intrinsics.
- Scheduler description for the new processor.
- Detection of z14 as host processor.
Support for the new 32-bit vector float and 128-bit vector float
instructions is provided by separate patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308194
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Mandeep Singh Grang [Mon, 17 Jul 2017 17:32:45 +0000 (17:32 +0000)]
[llvm] Remove redundant check-prefix=CHECK from tests. NFC.
Reviewers: t.p.northover, oren_ben_simhon, niravd, mcrosier
Reviewed By: oren_ben_simhon, mcrosier
Subscribers: nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D35466
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308193
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Krzysztof Parzyszek [Mon, 17 Jul 2017 15:45:45 +0000 (15:45 +0000)]
[Hexagon] Remove custom lowering of loads of v4i16
The target-independent lowering works fine, except concatenating 32-bit
words. Add a pattern to generate A2_combinew instead of 64-bit asl/or.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308186
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Nirav Dave [Mon, 17 Jul 2017 15:09:47 +0000 (15:09 +0000)]
Avoid store merge to f128 in context of noimpiccitfloat NFCI.
Prevent store merge from merging stores into an invalid 128-bit store
(realized as a f128 value in the context of the noimplicitfloat
attribute). Previously, such stores are immediately split back into
valid stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308184
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Simon Pilgrim [Mon, 17 Jul 2017 14:37:17 +0000 (14:37 +0000)]
[X86] Add LEA scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308180
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Sam Kolton [Mon, 17 Jul 2017 14:23:38 +0000 (14:23 +0000)]
[AMDGPU] CodeGen: check dst operand type to determine if omod is supported for VOP3 instructions
Summary:
Previously, CodeGen checked first src operand type to determine if omod is supported by instruction. This isn't correct for some instructions: e.g. V_CMP_EQ_F32 has floating-point src operands but desn't support omod.
Changed .td files to check if dst operand instead of src operand.
Reviewers: arsenm, vpykhtin
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye
Differential Revision: https://reviews.llvm.org/D35350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308179
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Simon Pilgrim [Mon, 17 Jul 2017 14:11:30 +0000 (14:11 +0000)]
[X86][AVX512] Add lowering of vXi32/vXi64 ISD::ROTL/ISD::ROTR
Add support for lowering to ISD::ROTL/ISD::ROTR, including rotate by immediate
Differential Revision: https://reviews.llvm.org/D35463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308177
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Simon Pilgrim [Mon, 17 Jul 2017 13:58:20 +0000 (13:58 +0000)]
Fixed line endings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308175
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Javed Absar [Mon, 17 Jul 2017 13:15:26 +0000 (13:15 +0000)]
[CodeGen] Add begin-end iterators to MachineInstr
Convert iteration over operands to range-loop.
Reviewed by: @rovka, @echristo
Differential Revision: https://reviews.llvm.org/D35419
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308173
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Alex Bradbury [Mon, 17 Jul 2017 11:41:30 +0000 (11:41 +0000)]
[YAMLTraits] Add filename support to yaml::Input
Summary:
The current yaml::Input constructor takes a StringRef of data as its
first parameter, discarding any filename information that may have been
present when a YAML file was opened. Add an alterate yaml::Input
constructor that takes a MemoryBufferRef, which can have a filename
associated with it. This leads to clearer diagnostic messages.
Sponsored By: DARPA, AFRL
Reviewed By: arphaman
Differential Revision: https://reviews.llvm.org/D35398
Patch by: Jonathan Anderson (trombonehero)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308172
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Simon Pilgrim [Mon, 17 Jul 2017 10:35:51 +0000 (10:35 +0000)]
[X86][AVX] Fix typo in vector rotate tests
Was preventing rotate matching
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308171
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Simon Pilgrim [Mon, 17 Jul 2017 10:09:48 +0000 (10:09 +0000)]
[X86][AVX512] Add constant splat vector rotate tests for D35463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308169
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Simon Pilgrim [Mon, 17 Jul 2017 09:53:45 +0000 (09:53 +0000)]
[X86][AVX512] Regenerate shift tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308168
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Simon Pilgrim [Mon, 17 Jul 2017 09:35:03 +0000 (09:35 +0000)]
Remove unnecessary cast. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308166
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Craig Topper [Mon, 17 Jul 2017 05:16:16 +0000 (05:16 +0000)]
[X86] Use MSVC's __cpuidex intrinsic instead of inline assembly in getHostCPUName/getHostCPUFeatures for 32-bit builds too.
We're already using it in 64-bit builds because 64-bit MSVC doesn't support inline assembly.
As far as I know we were using inline assembly because at the time the code was added we had to support MSVC 2008 pre-SP1 while the intrinsic was added to MSVC in SP1. Now that we don't have to support that we should be able to just use the intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308163
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NAKAMURA Takumi [Mon, 17 Jul 2017 04:31:26 +0000 (04:31 +0000)]
Analysis/MemorySSA.cpp: Prune unused "llvm/Transforms/Scalar.h".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308162
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NAKAMURA Takumi [Mon, 17 Jul 2017 04:31:23 +0000 (04:31 +0000)]
IR/Core.cpp: Prune unused "llvm/Bitcode/BitcodeReader.h".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308161
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NAKAMURA Takumi [Mon, 17 Jul 2017 04:31:20 +0000 (04:31 +0000)]
Support/Path.cpp: Prune unused "llvm/BinaryFormat".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308160
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Mandeep Singh Grang [Mon, 17 Jul 2017 00:05:32 +0000 (00:05 +0000)]
[COFF, ARM64] Add initial relocation types
Reviewers: compnerd, ruiu, rnk
Reviewed By: compnerd
Subscribers: mstorsjo, aemerson, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D34857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308154
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Dylan McKay [Sun, 16 Jul 2017 23:33:50 +0000 (23:33 +0000)]
[AVR] Add/remove XFAILs to get the backend passing Generic CodeGen tests
A few tests have since been fixed, and a few since now fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308151
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Andrew Zhogin [Sun, 16 Jul 2017 23:11:45 +0000 (23:11 +0000)]
[DAGCombiner] Recognise vector rotations with non-splat constants
Fixes PR33691.
Differential revision: https://reviews.llvm.org/D35381
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308150
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Dylan McKay [Sun, 16 Jul 2017 22:31:07 +0000 (22:31 +0000)]
[AVR] Fix a typo in the tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308148
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Konstantin Zhuravlyov [Sun, 16 Jul 2017 19:38:47 +0000 (19:38 +0000)]
AMDGPU: Fix amdgpu-flat-work-group-size/amdgpu-waves-per-eu check
Differential Revision: https://reviews.llvm.org/D35433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308147
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Simon Pilgrim [Sun, 16 Jul 2017 19:26:49 +0000 (19:26 +0000)]
[X86][AVX512] Add 512-bit vector rotate tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308146
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Konstantin Zhuravlyov [Sun, 16 Jul 2017 19:24:08 +0000 (19:24 +0000)]
AMDGPU: Remove duplicate print outs from .AMDGPU.csdata
Differential Revision: https://reviews.llvm.org/D35428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308145
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Davide Italiano [Sun, 16 Jul 2017 18:56:30 +0000 (18:56 +0000)]
[InstCombine] Don't violate dominance when replacing instructions.
Differential Revision: https://reviews.llvm.org/D35376
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308144
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 16 Jul 2017 18:37:23 +0000 (18:37 +0000)]
Strip trailing whitespace. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308143
91177308-0d34-0410-b5e6-
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Amjad Aboud [Sun, 16 Jul 2017 17:39:56 +0000 (17:39 +0000)]
[X86] X86::CMOV to Branch heuristic based optimization.
LLVM compiler recognizes opportunities to transform a branch into IR select instruction(s) - later it will be lowered into X86::CMOV instruction, assuming no other optimization eliminated the SelectInst.
However, it is not always profitable to emit X86::CMOV instruction. For example, branch is preferable over an X86::CMOV instruction when:
1. Branch is well predicted
2. Condition operand is expensive, compared to True-value and the False-value operands
In CodeGenPrepare pass there is a shallow optimization that tries to convert SelectInst into branch, but it is not enough.
This commit, implements machine optimization pass that converts X86::CMOV instruction(s) into branch, based on a conservative heuristic.
Differential Revision: https://reviews.llvm.org/D34769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308142
91177308-0d34-0410-b5e6-
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Jakub Kuderski [Sun, 16 Jul 2017 17:29:19 +0000 (17:29 +0000)]
Apply explicit instantiation workaround to DominanceFrontier
This is a workaround for the same explicit instantiation bug
as in DominatorTreeBase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308141
91177308-0d34-0410-b5e6-
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Jakub Kuderski [Sun, 16 Jul 2017 17:01:40 +0000 (17:01 +0000)]
[Dominators] Workaround explicit instantiation bug.
Some platforms have problems with emmiting constructors when class
templates get explicitly instantiated.
This patch fixes the bug reported in D35315 by replacing `= default`
with an empty constructor body.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308140
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 16 Jul 2017 14:34:18 +0000 (14:34 +0000)]
[X86] Add F16C scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308138
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 16 Jul 2017 14:22:39 +0000 (14:22 +0000)]
[X86] Add POPCNT scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308137
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 16 Jul 2017 14:09:15 +0000 (14:09 +0000)]
[X86] Add BMI2 scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308136
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 16 Jul 2017 13:59:44 +0000 (13:59 +0000)]
[X86] Add BMI1 scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308135
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 16 Jul 2017 13:40:44 +0000 (13:40 +0000)]
[X86] Add LZCNT scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308133
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 16 Jul 2017 12:06:06 +0000 (12:06 +0000)]
[X86][SSE4A] Add EXTRQ/INSERTQ values to BTVER2 scheduling model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308132
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 16 Jul 2017 11:43:16 +0000 (11:43 +0000)]
[X86][AVX] Regenerate tests with constant broadcast comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308131
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 16 Jul 2017 11:40:23 +0000 (11:40 +0000)]
[X86][AVX] Regenerate vector tzcnt tests with constant broadcast comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308130
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 16 Jul 2017 11:38:14 +0000 (11:38 +0000)]
[X86][AVX] Regenerate vector idiv tests with constant broadcast comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308129
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 16 Jul 2017 11:36:11 +0000 (11:36 +0000)]
[X86][AVX] Regenerate combine tests with constant broadcast comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308128
91177308-0d34-0410-b5e6-
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Hiroshi Inoue [Sun, 16 Jul 2017 08:11:56 +0000 (08:11 +0000)]
fix typos in comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308127
91177308-0d34-0410-b5e6-
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Hiroshi Inoue [Sun, 16 Jul 2017 07:48:48 +0000 (07:48 +0000)]
fix typos in comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308126
91177308-0d34-0410-b5e6-
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Craig Topper [Sun, 16 Jul 2017 06:57:41 +0000 (06:57 +0000)]
[InstSimplify] Use commutable matchers to simplify some code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308125
91177308-0d34-0410-b5e6-
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Craig Topper [Sun, 16 Jul 2017 05:37:58 +0000 (05:37 +0000)]
[InstCombine] Move (0 - x) & 1 --> x & 1 to SimplifyDemandedUseBits.
This removes a dedicated matcher and allows us to support more than just an AND masking the lower bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308124
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Teresa Johnson [Sun, 16 Jul 2017 00:28:22 +0000 (00:28 +0000)]
Fix bot failures from r308114
Finally figured out that some bots were failing from r308114
with the message:
llvm-lto2: LTO::run failed: No available targets are compatible with this triple.
after adding in some other checking that finally caused this to show up
in the FileCheck output.
Added "REQUIRES: x86-registered-target" which should fix it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308119
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Teresa Johnson [Sun, 16 Jul 2017 00:01:16 +0000 (00:01 +0000)]
Attempt 2 to debug bot failures
Modify checks from r308114 even more, to see if I can narrow down
why some bots are still failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308116
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Teresa Johnson [Sat, 15 Jul 2017 23:31:32 +0000 (23:31 +0000)]
Attempt to debug bot failures
Simplifying checks from r308114, to see if I can narrow down why some
bots are still failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308115
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Teresa Johnson [Sat, 15 Jul 2017 22:58:06 +0000 (22:58 +0000)]
Restore with fix "[ThinLTO] Ensure we always select the same function copy to import"
This restores r308078/r308079 with a fix for bot non-determinisim (make
sure we run llvm-lto in single threaded mode so the debug output doesn't get
interleaved).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308114
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Craig Topper [Sat, 15 Jul 2017 22:06:19 +0000 (22:06 +0000)]
[IR] Implement Constant::isNegativeZeroValue/isZeroValue/isAllOnesValue/isOneValue/isMinSignedValue for ConstantDataVector without going through getElementAsConstant
Summary:
Currently these methods call ConstantDataVector::getSplatValue which uses getElementsAsConstant to create a Constant object representing the element value. This method incurs a map lookup to see if we already have created such a Constant before and if not allocates a new Constant object.
This patch changes these methods to use getElementAsAPFloat and getElementAsInteger so we can just examine the data values directly.
Reviewers: spatel, pcc, dexonsmith, bogner, craig.topper
Reviewed By: craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D35040
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308112
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Craig Topper [Sat, 15 Jul 2017 21:49:49 +0000 (21:49 +0000)]
[InstCombine] Improve the expansion in SimplifyUsingDistributiveLaws to handle cases where one side doesn't simplify, but the other side resolves to an identity value
Summary:
If one side simplifies to the identity value for inner opcode, we can replace the value with just the operation that can't be simplified.
I've removed a couple now unneeded special cases in visitAnd and visitOr. There are probably other cases I missed.
Reviewers: spatel, majnemer, hfinkel, dberlin
Reviewed By: spatel
Subscribers: grandinj, llvm-commits, spatel
Differential Revision: https://reviews.llvm.org/D35451
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308111
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Simon Pilgrim [Sat, 15 Jul 2017 21:17:35 +0000 (21:17 +0000)]
[X86][AVX] Regenerate tests with constant broadcast comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308110
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sat, 15 Jul 2017 20:28:09 +0000 (20:28 +0000)]
[X86][AVX] Regenerate tests with constant broadcast comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308109
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sat, 15 Jul 2017 19:29:19 +0000 (19:29 +0000)]
Strip trailing whitespace. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308108
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Reid Kleckner [Sat, 15 Jul 2017 18:10:39 +0000 (18:10 +0000)]
[CodeView] Dump BuildInfoSym and ProcSym type indices
I need to print the type index in hex so that I can match it in
FileCheck for a test I'm writing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308107
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Reid Kleckner [Sat, 15 Jul 2017 18:10:15 +0000 (18:10 +0000)]
Fix mis-use of std::lower_bound
Binary search in C++ is such a PITA. =/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308106
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Sanjay Patel [Sat, 15 Jul 2017 17:26:01 +0000 (17:26 +0000)]
[InstCombine] improve (1 << x) & 1 --> zext(x == 0) folding
1. Add a one-use check to prevent increasing instruction count.
2. Generalize the pattern matching to include vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308105
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Craig Topper [Sat, 15 Jul 2017 17:09:23 +0000 (17:09 +0000)]
[InstCombine] Add test cases for (X & (Y | ~X)) -> (X & Y) where the not is an inverted compare. NFC
Do the same for (X | (Y & ~X)) -> (X | Y)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308104
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Craig Topper [Sat, 15 Jul 2017 17:09:22 +0000 (17:09 +0000)]
[InstCombine] Move 4 test cases from a test that didn't use FileCheck and merge them into a existing test file. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308103
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Sanjay Patel [Sat, 15 Jul 2017 15:55:07 +0000 (15:55 +0000)]
[InstCombine] add tests for (1 << x) & 1 --> zext(x == 0) ; NFC
This fold hit the trifecta:
1. It was untested.
2. It oversteps (multiuse is not checked, so increases instruction count).
3. It is incomplete (doesn't work for vectors).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308102
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Chandler Carruth [Sat, 15 Jul 2017 15:44:36 +0000 (15:44 +0000)]
[wasm] Update two tests for r308025 which causes scheduling changes due
to the newly improved AA information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308100
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Sanjay Patel [Sat, 15 Jul 2017 15:29:47 +0000 (15:29 +0000)]
[InstCombine] allow (0 - x) & 1 --> x & 1 for vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308098
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Sanjay Patel [Sat, 15 Jul 2017 15:01:33 +0000 (15:01 +0000)]
[InstCombine] remove dead code/tests; NFCI
These patterns and tests were added to InstSimplify with:
https://reviews.llvm.org/rL303004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308096
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Chandler Carruth [Sat, 15 Jul 2017 13:50:26 +0000 (13:50 +0000)]
Revert r308078 (and subsequent tweak in r308079) which introduces a test
that appears to exhibit non-determinism and is flaking on the bots
pretty consistently.
r308078: [ThinLTO] Ensure we always select the same function copy to import
r308079: Require asserts in new test that uses debug flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308095
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Florian Hahn [Sat, 15 Jul 2017 13:13:19 +0000 (13:13 +0000)]
[LoopInterchange] Add some optimization remarks.
Reviewers: anemet, karthikthecool, blitz.opensource
Reviewed By: anemet
Subscribers: mzolotukhin, llvm-commits
Differential Revision: https://reviews.llvm.org/D35122
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308094
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Nuno Lopes [Sat, 15 Jul 2017 09:09:24 +0000 (09:09 +0000)]
[docs] AliasAnalysis: clarify that PartialAlias doesn't enforce
objects to start at the same address
As discussed on the ML, there's consensus that this is what the implementations
do and it seems sensible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308090
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Chandler Carruth [Sat, 15 Jul 2017 08:08:19 +0000 (08:08 +0000)]
[PM/LCG] Teach the LazyCallGraph to maintain reference edges from every
function to every defined function known to LLVM as a library function.
LLVM can introduce calls to these functions either by replacing other
library calls or by recognizing patterns (such as memset_pattern or
vector math patterns) and replacing those with calls. When these library
functions are actually defined in the module, we need to have reference
edges to them initially so that we visit them during the CGSCC walk in
the right order and can effectively rebuild the call graph afterward.
This was discovered when building code with Fortify enabled as that is
a common case of both inline definitions of library calls and
simplifications of code into calling them.
This can in extreme cases of LTO-ing with libc introduce *many* more
reference edges. I discussed a bunch of different options with folks but
all of them are unsatisfying. They either make the graph operations
substantially more complex even when there are *no* defined libfuncs, or
they introduce some other complexity into the callgraph. So this patch
goes with the simplest possible solution of actual synthetic reference
edges. If this proves to be a memory problem, I'm happy to implement one
of the clever techniques to save memory here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308088
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Simon Atanasyan [Sat, 15 Jul 2017 07:14:25 +0000 (07:14 +0000)]
[mips] Handle the `long-calls` feature flags in the MIPS backend
If the `long-calls` feature flags is enabled, disable use of the `jal`
instruction. Instead of that call a function by by first loading its
address into a register, and then using the contents of that register.
Differential revision: https://reviews.llvm.org/D35168
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308087
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NAKAMURA Takumi [Sat, 15 Jul 2017 06:32:12 +0000 (06:32 +0000)]
SystemZCodeGen: Update libdeps. r308024 introduced LoopDataPrefetchPass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308086
91177308-0d34-0410-b5e6-
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Yonghong Song [Sat, 15 Jul 2017 06:08:08 +0000 (06:08 +0000)]
bpf: fix a compilation bug due to unused variable for release build
Signed-off-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308083
91177308-0d34-0410-b5e6-
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Matt Arsenault [Sat, 15 Jul 2017 05:52:59 +0000 (05:52 +0000)]
AMDGPU: Return correct type during argument lowering
The type needs to be casted back to the original argument type.
Fixes an assert that for some reason is only run when
using -debug.
Includes an additional combine to avoid test regressions
from having conversions mixed with multiple Assert[SZ]ext
nodes. On subtargets where i16 is legal, this was producing an i32
register with an i16 AssertZExt, truncated to i16 with another i8
AssertZExt.
t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0
t3: i16 = truncate t2
t5: i16 = AssertZext t3, ValueType:ch:i8
t6: i8 = truncate t5
t7: i32 = zero_extend t6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308082
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Dinar Temirbulatov [Sat, 15 Jul 2017 05:43:54 +0000 (05:43 +0000)]
[SLPVectorizer] Add an extra parameter to tryScheduleBundle function, NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308081
91177308-0d34-0410-b5e6-
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Yonghong Song [Sat, 15 Jul 2017 05:41:42 +0000 (05:41 +0000)]
bpf: generate better lowering code for certain select/setcc instructions
Currently, for code like below,
===
inner_map = bpf_map_lookup_elem(outer_map, &port_key);
if (!inner_map) {
inner_map = &fallback_map;
}
===
the compiler generates (pseudo) code like the below:
===
I1: r1 = bpf_map_lookup_elem(outer_map, &port_key);
I2: r2 = 0
I3: if (r1 == r2)
I4: r6 = &fallback_map
I5: ...
===
During kernel verification process, After I1, r1 holds a state
map_ptr_or_null. If I3 condition is not taken
(path [I1, I2, I3, I5]), supposedly r1 should become map_ptr.
Unfortunately, kernel does not recognize this pattern
and r1 remains map_ptr_or_null at insn I5. This will cause
verificaiton failure later on.
Kernel, however, is able to recognize pattern "if (r1 == 0)"
properly and give a map_ptr state to r1 in the above case.
LLVM here generates suboptimal code which causes kernel verification
failure. This patch fixes the issue by changing BPF insn pattern
matching and lowering to generate proper codes if the righthand
parameter of the above condition is a constant. A test case
is also added.
Signed-off-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308080
91177308-0d34-0410-b5e6-
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Teresa Johnson [Sat, 15 Jul 2017 05:27:57 +0000 (05:27 +0000)]
Require asserts in new test that uses debug flag
This should fix bot failures from r308078.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308079
91177308-0d34-0410-b5e6-
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Teresa Johnson [Sat, 15 Jul 2017 04:53:05 +0000 (04:53 +0000)]
[ThinLTO] Ensure we always select the same function copy to import
Summary:
Check if the first eligible callee is under the instruction threshold.
Checking this on the first eligible callee ensures that we don't end
up selecting different callees to import when we invoke this routine
with different thresholds due to reaching the callee via paths that
are shallower or hotter (when there are multiple copies, i.e. with
weak or linkonce linkage). We don't want to leave the decision of which
copy to import up to the backend.
Reviewers: mehdi_amini
Subscribers: inglorion, fhahn, llvm-commits
Differential Revision: https://reviews.llvm.org/D35436
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308078
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Haicheng Wu [Sat, 15 Jul 2017 02:12:16 +0000 (02:12 +0000)]
[TTI] Refine the cost of EXT in getUserCost()
Now, getUserCost() only checks the src and dst types of EXT to decide it is free
or not. This change first checks the types, then calls isExtFreeImpl(), and
check if EXT can form ExtLoad at last. Currently, only AArch64 has customized
implementation of isExtFreeImpl() to check if EXT can be folded into its use.
Differential Revision: https://reviews.llvm.org/D34458
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308076
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Kostya Serebryany [Sat, 15 Jul 2017 01:31:40 +0000 (01:31 +0000)]
[libFuzzer] remove stale code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308075
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