OSDN Git Service
Diana Picus [Fri, 6 Oct 2017 14:52:43 +0000 (14:52 +0000)]
[ARM] GlobalISel: Map shift operands to GPRs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315067
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Francis Ricci [Fri, 6 Oct 2017 14:49:20 +0000 (14:49 +0000)]
[llvm-dsymutil] Add support for __swift_ast MachO DWARF section
Summary:
Xcode's dsymutil emits a __swift_ast DWARF section, which is required for debugging,
and which contains a byte-for-byte dump of the swiftmodule file.
Add this feature to llvm-dsymutil.
Tested with `gobjdump --dwarf=info -s`, by verifying that the contents of
`__DWARF.__swift_ast` match between Xcode's dsymutil and llvm-dsymutil
(Xcode's dwarfdump and llvm-dwarfdump don't currently recognize the
__swift_ast section).
Reviewers: aprantl, friss
Subscribers: llvm-commits, JDevlieghere
Differential Revision: https://reviews.llvm.org/D38504
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315066
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Diana Picus [Fri, 6 Oct 2017 14:30:05 +0000 (14:30 +0000)]
[ARM] GlobalISel: Mark shifts as legal for s32
The new legalize combiner introduces shifts all over the place, so we
should support them sooner rather than later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315064
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Jonas Paulsson [Fri, 6 Oct 2017 13:59:28 +0000 (13:59 +0000)]
[SystemZ] Enable machine scheduler.
The machine scheduler (before register allocation) is enabled by default for
SystemZ.
The SelectionDAG scheduling preference now becomes source order scheduling
(was regpressure).
Review: Ulrich Weigand
https://reviews.llvm.org/D37977
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315063
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Clement Courbet [Fri, 6 Oct 2017 13:45:16 +0000 (13:45 +0000)]
[MergeICmp][NFC] Make test tuple-four-int8.ll more readable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315062
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Simon Pilgrim [Fri, 6 Oct 2017 13:40:29 +0000 (13:40 +0000)]
[X86][SSE] Add SKX cpu tests to SSE/AVX scheduling tests (D38443)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315061
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Clement Courbet [Fri, 6 Oct 2017 13:02:24 +0000 (13:02 +0000)]
Revert "[MergeICmps] Disable mergeicmps if the target does not want to handle memcmp expansion."
Still a few stability issues on windows.
This reverts commit
67e3db9bc121ba244e20337aabc7cf341a62b545.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315058
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Clement Courbet [Fri, 6 Oct 2017 12:12:35 +0000 (12:12 +0000)]
Re-land "[MergeICmps] Disable mergeicmps if the target does not want to handle memcmp expansion."
(fixed unit tests by making comparisons stable)
This reverts commit
1b2d359ce256fd6737da4e93833346a0bd6d7583.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315056
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Javed Absar [Fri, 6 Oct 2017 09:32:45 +0000 (09:32 +0000)]
[TableGen] : CodeGenInsrtuction modify to range loop. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315050
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Xinliang David Li [Fri, 6 Oct 2017 05:15:25 +0000 (05:15 +0000)]
Roll forward r314928
Fixed ThinLTO bootstrap failure : track new
bitcast per incomingVal. Added new tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315044
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Davide Italiano [Fri, 6 Oct 2017 04:39:40 +0000 (04:39 +0000)]
[PM] Retire disable unit-at-a-time switch.
This is a vestige from the GCC-3 days, which disables IPO passes
when set. I don't think anybody actually uses it as there are
several IPO passes which still run with this flag set and
nobody complained/noticed. This reduces the delta between
current and new pass manager and allows us to easily review
the difference when we decide to flip the switch (or audit
which passes should run, FWIW).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315043
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Jakub Kuderski [Fri, 6 Oct 2017 03:37:06 +0000 (03:37 +0000)]
[CodeExtractor] Fix multiple bugs under certain shape of extracted region
Summary:
If the extracted region has multiple exported data flows toward the same BB which is not included in the region, correct resotre instructions and PHI nodes won't be generated inside the exitStub. The solution is simply put the restore instructions right after the definition of output values instead of putting in exitStub.
Unittest for this bug is included.
Author: myhsu
Reviewers: chandlerc, davide, lattner, silvas, davidxl, wmi, kuhar
Subscribers: dberlin, kuhar, mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D37902
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315041
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Daniel Berlin [Fri, 6 Oct 2017 01:33:06 +0000 (01:33 +0000)]
NewGVN: Factor out duplicate parts of OpIsSafeForPHIOfOps
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315040
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Francis Ricci [Thu, 5 Oct 2017 23:09:17 +0000 (23:09 +0000)]
Revert "[llvm-dsymutil] Add support for __swift_ast MachO DWARF section"
Breaks aarch64 builders
This reverts commit r315014.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315034
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Xin Tong [Thu, 5 Oct 2017 23:00:04 +0000 (23:00 +0000)]
[MBP] Remove an invalid assert.
The patch that this assert comes with is fixing a bug in MBP. The assert is
invalid however.
Thanks to @sergey.k.okunev for finding this
Currently this fails SPECCPU2006 LTO. I will add a test case when I do more
investigation and have one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315032
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Peter Collingbourne [Thu, 5 Oct 2017 21:54:53 +0000 (21:54 +0000)]
ModuleUtils: Stop using comdat members to generate unique module ids.
It is possible for two modules to define the same set of external
symbols without causing a duplicate symbol error at link time,
as long as each of the symbols is a comdat member. So we cannot
use them as part of a unique id for the module.
Differential Revision: https://reviews.llvm.org/D38602
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315026
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Reid Kleckner [Thu, 5 Oct 2017 21:37:39 +0000 (21:37 +0000)]
[X86] Extract CATCHRET handling from emitEpilogue, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315023
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Derek Schuff [Thu, 5 Oct 2017 21:18:42 +0000 (21:18 +0000)]
[WebAssembly] Add the rest of the atomic loads
Add extending loads and constant offset patterns
A bit more refactoring of the tablegen to make the patterns fairly nice and
uniform between the regular and atomic loads.
Differential Revision: https://reviews.llvm.org/D38523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315022
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Sanjay Patel [Thu, 5 Oct 2017 21:11:49 +0000 (21:11 +0000)]
[InstCombine] improve folds for icmp gt/lt (shr X, C1), C2
We can always eliminate the shift in: icmp gt/lt (shr X, C1), C2 --> icmp gt/lt X, C'
This patch was supposed to just be an efficiency improvement because we were doing this 3-step process to fold:
IC: Visiting: %c = icmp ugt i4 %s, 1
IC: ADD: %s = lshr i4 %x, 1
IC: ADD: %1 = udiv i4 %x, 2
IC: Old = %c = icmp ugt i4 %1, 1
New = <badref> = icmp uge i4 %x, 4
IC: ADD: %c = icmp uge i4 %x, 4
IC: ERASE %2 = icmp ugt i4 %1, 1
IC: Visiting: %c = icmp uge i4 %x, 4
IC: Old = %c = icmp uge i4 %x, 4
New = <badref> = icmp ugt i4 %x, 3
IC: ADD: %c = icmp ugt i4 %x, 3
IC: ERASE %2 = icmp uge i4 %x, 4
IC: Visiting: %c = icmp ugt i4 %x, 3
IC: DCE: %1 = udiv i4 %x, 2
IC: ERASE %1 = udiv i4 %x, 2
IC: DCE: %s = lshr i4 %x, 1
IC: ERASE %s = lshr i4 %x, 1
IC: Visiting: ret i1 %c
When we could go directly to canonical icmp form:
IC: Visiting: %c = icmp ugt i4 %s, 1
IC: Old = %c = icmp ugt i4 %s, 1
New = <badref> = icmp ugt i4 %x, 3
IC: ADD: %c = icmp ugt i4 %x, 3
IC: ERASE %1 = icmp ugt i4 %s, 1
IC: ADD: %s = lshr i4 %x, 1
IC: DCE: %s = lshr i4 %x, 1
IC: ERASE %s = lshr i4 %x, 1
IC: Visiting: %c = icmp ugt i4 %x, 3
...but then I noticed that the folds were incomplete too:
https://godbolt.org/g/aB2hLE
Here are attempts to prove the logic with Alive:
https://rise4fun.com/Alive/92o
Name: lshr_ult
Pre: ((C2 << C1) u>> C1) == C2
%sh = lshr i8 %x, C1
%r = icmp ult i8 %sh, C2
=>
%r = icmp ult i8 %x, (C2 << C1)
Name: ashr_slt
Pre: ((C2 << C1) >> C1) == C2
%sh = ashr i8 %x, C1
%r = icmp slt i8 %sh, C2
=>
%r = icmp slt i8 %x, (C2 << C1)
Name: lshr_ugt
Pre: (((C2+1) << C1) u>> C1) == (C2+1)
%sh = lshr i8 %x, C1
%r = icmp ugt i8 %sh, C2
=>
%r = icmp ugt i8 %x, ((C2+1) << C1) - 1
Name: ashr_sgt
Pre: (C2 != 127) && ((C2+1) << C1 != -128) && (((C2+1) << C1) >> C1) == (C2+1)
%sh = ashr i8 %x, C1
%r = icmp sgt i8 %sh, C2
=>
%r = icmp sgt i8 %x, ((C2+1) << C1) - 1
Name: ashr_exact_sgt
Pre: ((C2 << C1) >> C1) == C2
%sh = ashr exact i8 %x, C1
%r = icmp sgt i8 %sh, C2
=>
%r = icmp sgt i8 %x, (C2 << C1)
Name: ashr_exact_slt
Pre: ((C2 << C1) >> C1) == C2
%sh = ashr exact i8 %x, C1
%r = icmp slt i8 %sh, C2
=>
%r = icmp slt i8 %x, (C2 << C1)
Name: lshr_exact_ugt
Pre: ((C2 << C1) u>> C1) == C2
%sh = lshr exact i8 %x, C1
%r = icmp ugt i8 %sh, C2
=>
%r = icmp ugt i8 %x, (C2 << C1)
Name: lshr_exact_ult
Pre: ((C2 << C1) u>> C1) == C2
%sh = lshr exact i8 %x, C1
%r = icmp ult i8 %sh, C2
=>
%r = icmp ult i8 %x, (C2 << C1)
We did something similar for 'shl' in D28406.
Differential Revision: https://reviews.llvm.org/D38514
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315021
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Krzysztof Parzyszek [Thu, 5 Oct 2017 20:20:06 +0000 (20:20 +0000)]
[Hexagon] Make PS_fi and PS_fia extendable (they both expand to A2_addi)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315019
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Francis Ricci [Thu, 5 Oct 2017 20:16:16 +0000 (20:16 +0000)]
[dsymutil] Fix typo in swift-ast.test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315017
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Dehao Chen [Thu, 5 Oct 2017 20:15:29 +0000 (20:15 +0000)]
Annotate VP prof on indirect call if it is ICPed in the profiled binary.
Summary: In SamplePGO, when an indirect call is promoted in the profiled binary, before profile annotation, it will be promoted and inlined. For the original indirect call, the current implementation will not mark VP profile on it. This is an issue when profile becomes stale. This patch annotates VP prof on indirect calls during annotation.
Reviewers: tejohnson
Reviewed By: tejohnson
Subscribers: sanjoy, llvm-commits
Differential Revision: https://reviews.llvm.org/D38477
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315016
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Francis Ricci [Thu, 5 Oct 2017 20:03:01 +0000 (20:03 +0000)]
[llvm-dsymutil] Add support for __swift_ast MachO DWARF section
Summary:
Xcode's dsymutil emits a __swift_ast DWARF section, which is required for debugging,
and which contains a byte-for-byte dump of the swiftmodule file.
Add this feature to llvm-dsymutil.
Tested with `gobjdump --dwarf=info -s`, by verifying that the contents of
`__DWARF.__swift_ast` match between Xcode's dsymutil and llvm-dsymutil
(Xcode's dwarfdump and llvm-dwarfdump don't currently recognize the
__swift_ast section).
Reviewers: aprantl, friss
Subscribers: llvm-commits, JDevlieghere
Differential Revision: https://reviews.llvm.org/D38504
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315014
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Krzysztof Parzyszek [Thu, 5 Oct 2017 20:01:38 +0000 (20:01 +0000)]
[Hexagon] Give uniform names to functions changing addressing modes, NFC
The new format is changeAddrMode_xx_yy, where xx is the current mode,
and yy is the new one.
Old name: New name:
getBaseWithImmOffset changeAddrMode_abs_io
getAbsoluteForm changeAddrMode_io_abs
getBaseWithRegOffset changeAddrMode_io_rr
xformRegToImmOffset changeAddrMode_rr_io
getBaseWithLongOffset changeAddrMode_rr_ur
getRegShlForm changeAddrMode_ur_rr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315013
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Rafael Espindola [Thu, 5 Oct 2017 20:01:32 +0000 (20:01 +0000)]
Added phdr upper bound checks to ElfObject.
Ensure the program_headers call will fail correctly if the program
headers are larger than the underlying buffer.
Patch by Parker Thompson!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315012
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Francis Ricci [Thu, 5 Oct 2017 19:47:13 +0000 (19:47 +0000)]
Revert "[llvm-dsymutil] Add support for __swift_ast MachO DWARF section"
This reverts commit r315004, because of a failing test on non-apple platforms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315009
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Francis Ricci [Thu, 5 Oct 2017 19:35:55 +0000 (19:35 +0000)]
[dsymutil] Fix unused variable warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315006
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Francis Ricci [Thu, 5 Oct 2017 19:17:28 +0000 (19:17 +0000)]
[llvm-dsymutil] Add support for __swift_ast MachO DWARF section
Summary:
Xcode's dsymutil emits a __swift_ast DWARF section, which is required for debugging,
and which contains a byte-for-byte dump of the swiftmodule file.
Add this feature to llvm-dsymutil.
Tested with `gobjdump --dwarf=info -s`, by verifying that the contents of
`__DWARF.__swift_ast` match between Xcode's dsymutil and llvm-dsymutil
(Xcode's dwarfdump and llvm-dwarfdump don't currently recognize the
__swift_ast section).
Reviewers: aprantl, friss
Subscribers: llvm-commits, JDevlieghere
Differential Revision: https://reviews.llvm.org/D38504
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315004
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Davide Italiano [Thu, 5 Oct 2017 18:36:01 +0000 (18:36 +0000)]
[NewPassManager] Run global dead code elimination after the inliner.
This is the same exact change we did for the current pass manager
in rL314997, but the new pass manager pipeline already happened
to run GlobalOpt after the inliner, so we just insert a run of
GDCE here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315003
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Balaram Makam [Thu, 5 Oct 2017 18:33:34 +0000 (18:33 +0000)]
[ARM/AARCH64] Make test MachineBranchProb.ll more robust and re-enable for ARM/AArch64
Summary: Make test robust enough to not fail due to CFG changes and re-enable for ARM/AArch64.
Reviewers: rovka, fhahn
Reviewed By: fhahn
Subscribers: fhahn, aemerson, rengolin, mcrosier, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D38590
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315002
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Reid Kleckner [Thu, 5 Oct 2017 18:27:08 +0000 (18:27 +0000)]
[X86] Simplify X86 epilogue frame size calculation, NFC
Sink the insertion of "pop ebp" out of the frame size calculation
branches. They all check for HasFP.
Our handling of CLEANUPRET and CATCHRET was equivalent, both are
funclets and use the same frame size. We can eliminate the CLEANUPRET
case.
Hoist the hasFP(MF) query into a local bool.
Rename TargetMBB to CatchRetTarget to be more descriptive.
Eliminate the Optional<unsigned> RetOpcode local, now that it has one
use.
It's only a net savings of 10 lines, but hopefully it's *slightly* more
readable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315000
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Davide Italiano [Thu, 5 Oct 2017 18:23:25 +0000 (18:23 +0000)]
[PassManager] Improve the interaction between -O2 and ThinLTO.
Run GDCE slightly later so that we don't have to repeat it
twice when preparing for Thin. Thanks to Mehdi for the suggestion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314999
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Davide Italiano [Thu, 5 Oct 2017 18:06:37 +0000 (18:06 +0000)]
[PassManager] Run global optimizations after the inliner.
The inliner performs some kind of dead code elimination as it goes,
but there are cases that are not really caught by it. We might
at some point consider teaching the inliner about them, but it
is OK for now to run GlobalOpt + GlobalDCE in tandem as their
benefits generally outweight the cost, making the whole pipeline
faster.
This fixes PR34652.
Differential Revision: https://reviews.llvm.org/D38154
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314997
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Matthew Simpson [Thu, 5 Oct 2017 18:03:30 +0000 (18:03 +0000)]
[SparsePropagation] Move member definitions to header (NFC)
AbstractLatticeFunction and SparseSolver are class templates parameterized by a
lattice value, so we need to move these member functions over to the header.
Differential Revision: https://reviews.llvm.org/D38561
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314996
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Petar Jovanovic [Thu, 5 Oct 2017 17:40:32 +0000 (17:40 +0000)]
[mips] implement .set dspr2 directive
Implement .set dspr2 directive with appropriate feature bits. This
directive is a counterpart of -mattr=dspr2 command line option with the
exception that it does not influence elf header flags.
Patch by Milos Stojanovic.
Differential Revision: https://reviews.llvm.org/D38537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314994
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Matt Arsenault [Thu, 5 Oct 2017 17:38:30 +0000 (17:38 +0000)]
AMDGPU: Set v2i32 any_extend to expand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314993
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Krzysztof Parzyszek [Thu, 5 Oct 2017 17:12:49 +0000 (17:12 +0000)]
[RDF] Simplify construction of maximal registers
The old algoritm was not correct, although it worked most of the time.
Avoid the complex reachability analysis and simply calculate the maximal
registers out of the set of all referenced registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314991
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Rong Xu [Thu, 5 Oct 2017 17:05:20 +0000 (17:05 +0000)]
[ProfileData] Fix data racing in merging indexed profiles
There is data racing to the static variable RecordIndex in index profile reader
when merging in multiple threads. Make it a member variable in
IndexedInstrProfReader to fix this.
Differential Revision: https://reviews.llvm.org/D38431
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314990
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Artur Pilipenko [Thu, 5 Oct 2017 16:28:21 +0000 (16:28 +0000)]
[X86] Fix chains update when lowering BUILD_VECTOR to a vector load
The code which lowers BUILD_VECTOR of consecutive loads into a single vector
load doesn't update chains properly. As a result the vector load can be
reordered with the store to the same location.
The current code in EltsFromConsecutiveLoads only updates the chain following
the first load. The fix is to update the chains following all the loads
comprising the vector.
This is a fix for PR10114.
Reviewed By: niravd
Differential Revision: https://reviews.llvm.org/D38547
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314988
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Konstantin Zhuravlyov [Thu, 5 Oct 2017 16:19:18 +0000 (16:19 +0000)]
AMDGPU: Add and set AMDGPU-specific e_flags
Differential Revision: https://reviews.llvm.org/D38556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314987
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Ayal Zaks [Thu, 5 Oct 2017 15:45:14 +0000 (15:45 +0000)]
[LV] Fix PR34743 - handle casts that sink after interleaved loads
When ignoring a load that participates in an interleaved group, make sure to
move a cast that needs to sink after it.
Testcase derived from reproducer of PR34743.
Differential Revision: https://reviews.llvm.org/D38338
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314986
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Clement Courbet [Thu, 5 Oct 2017 14:42:06 +0000 (14:42 +0000)]
Revert "Re-land "[MergeICmps] Disable mergeicmps if the target does not want to handle memcmp expansion."""
broken test on windows
This reverts commit
c91479518344fd1fc071c5bd5848f6eb83e53dca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314985
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Sanjay Patel [Thu, 5 Oct 2017 14:26:15 +0000 (14:26 +0000)]
revert r314698 - [InstCombine] remove one-use restriction for icmp (shr exact X, C1), C2 --> icmp X, (C2<<C1)
There is a bot failure that appears to be related to this change:
http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15-selfhost-neon/builds/2117
...so reverting to confirm that and attempting to keep the bot green while investigating.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314984
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Javed Absar [Thu, 5 Oct 2017 13:27:43 +0000 (13:27 +0000)]
[TablgeGen] : Tidy up CodeGenSchedule. NFC.
Reviewed by: @MatzeB
Differential Revision: https://reviews.llvm.org/D38534
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314982
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Ayal Zaks [Thu, 5 Oct 2017 12:41:49 +0000 (12:41 +0000)]
[LV] Fix PR34711 - widen instruction ranges when sinking casts
Instead of trying to keep LastWidenRecipe updated after creating each recipe,
have tryToWiden() retrieve the last recipe of the current VPBasicBlock and check
if it's a VPWidenRecipe when attempting to extend its range. This ensures that
such extensions, optimized to maintain the original instruction order, do so
only when the instructions are to maintain their relative order. The latter does
not always hold, e.g., when a cast needs to sink to unravel first order
recurrence (r306884).
Testcase derived from reproducer of PR34711.
Differential Revision: https://reviews.llvm.org/D38339
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314981
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Clement Courbet [Thu, 5 Oct 2017 12:39:57 +0000 (12:39 +0000)]
Re-land "[MergeICmps] Disable mergeicmps if the target does not want to handle memcmp expansion.""
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314980
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Simon Dardis [Thu, 5 Oct 2017 10:27:37 +0000 (10:27 +0000)]
[mips] Place certain 64 bit FPU instructions in their own decoder namespace
Previously, instructions that were defined to use the FGR64 register class
were associated with the Mips64 table which was incorrect.
Reviewers: nitesh.jain, atanasyan
Differential Revision: https://reviews.llvm.org/D38454
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314976
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Karl-Johan Karlsson [Thu, 5 Oct 2017 08:37:31 +0000 (08:37 +0000)]
[DebugInfo] Insert DEBUG_VALUEs after each register redefinition
Summary:
When reinserting debug values after register allocation, make sure to
insert debug values after each redefinition of debug value register in
the slot index range. The reason for this is that DwarfDebug will end
the range of a debug variable when the physical reg is defined. For
instructions with e.g. tied operands this result in prematurely ended
debug range.
This resolves pr34545
Patch by Karl-Johan Karlsson and Bjorn Pettersson
Reviewers: rnk, aprantl
Reviewed By: rnk
Subscribers: bjope, llvm-commits
Differential Revision: https://reviews.llvm.org/D38229
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314974
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George Rimar [Thu, 5 Oct 2017 08:15:55 +0000 (08:15 +0000)]
[MC] - llvm-mc hangs on non-english characters.
Currently llvm-mc just hangs inside infinite loop
while trying to parse file which has ".section .с" inside,
where section name is non-english character.
Patch fixes the issue.
In this patch I also moved content of non-english-characters.s
to test/MC/AsmParser/Inputs folder so that non-english-characters.s
becomes a single testcase for all invalid inputs containing non-english
symbols. That is convinent because llvm-mc otherwise tries
to parse and tokenize the whole testcase file with tools invocations and
it is harder to isolate the issue.
Differential revision: https://reviews.llvm.org/D38545
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314973
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Clement Courbet [Thu, 5 Oct 2017 08:03:39 +0000 (08:03 +0000)]
Revert "[MergeICmps] Disable mergeicmps if the target does not want to handle memcmp expansion."
Breaks
clang-stage1-cmake-RA-incremental/llvm/test/Transforms/MergeICmps/X86/tuple-four-int8.ll
This reverts commit
3038c459d67f8898ffa295d54a013b280690abfa.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314972
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Craig Topper [Thu, 5 Oct 2017 07:59:11 +0000 (07:59 +0000)]
[InstCombine] Fix a vector splat handling bug in transformZExtICmp.
We were using an i1 type and then zero extending to a vector. Instead just create the 0/1 directly as a ConstantInt with the correct type. No need to ask ConstantExpr to zero extend for us.
This bug is a bit tricky to hit because it requires us to visit a zext of an icmp that would normally be simplified to true/false, but that icmp hasnt' been visited yet. In the test case this zext and icmp were created by visiting a udiv and due to worklist ordering we got to the zext first.
Fixes PR34841.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314971
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Clement Courbet [Thu, 5 Oct 2017 07:49:09 +0000 (07:49 +0000)]
[MergeICmps] Disable mergeicmps if the target does not want to handle memcmp expansion.
Summary: This is to avoid e.g. merging two cheap icmps if the target is not going to expand to something nice later.
Reviewers: dberlin, spatel
Subscribers: davide, nemanjai
Differential Revision: https://reviews.llvm.org/D38232
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314970
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Mikael Holmen [Thu, 5 Oct 2017 07:07:09 +0000 (07:07 +0000)]
Minor refactoring regarding Cast::isNoopCast(), NFC
Summary:
FastISel::hasTrivialKill() was the only user of the "IntPtrTy" version of
Cast::isNoopCast(). According to review comments in D37894 we could instead
use the "DataLayout" version of the method, and thus get rid of the
"IntPtrTy" versions of isNoopCast() completely.
With the above done, the remaining isNoopCast() could then be simplified
a bit more.
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D38497
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314969
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Dean Michael Berris [Thu, 5 Oct 2017 05:18:17 +0000 (05:18 +0000)]
[XRay][tools] Support arg1 logging entries in the basic logging mode
Summary:
The arg1 logging handler changed in compiler-rt to start writing a
different type for entries encountered when logging the first argument
of XRay-instrumented functions. This change allows the trace loader to
support reading these record types as well as prepare for when the
basic (naive) mode implementation starts writing down the argument
payloads.
Without this change, binaries with arg1 logging support enabled start
writing unreadable logs for any of the XRay tracing tools.
Reviewers: pelikan
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38550
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314967
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Sean Fertile [Thu, 5 Oct 2017 01:48:42 +0000 (01:48 +0000)]
Enabling new pass manager in LTO (and thinLTO) link step.
Adds the option 'new-pass-manager' to the gold pluggin to enable using the
new pass manager during the lto/thinlto link step.
Patch by Graham Yiu.
Differential Revision: https://reviews.llvm.org/D38517
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314963
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Xinliang David Li [Thu, 5 Oct 2017 01:40:13 +0000 (01:40 +0000)]
Revert r314928 to investigate thinLTO bootstrap failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314961
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Eugene Zelenko [Thu, 5 Oct 2017 00:33:50 +0000 (00:33 +0000)]
[X86] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314953
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Matt Arsenault [Thu, 5 Oct 2017 00:13:20 +0000 (00:13 +0000)]
AMDGPU: Add comment about clamps
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314952
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Matt Arsenault [Thu, 5 Oct 2017 00:13:17 +0000 (00:13 +0000)]
AMDGPU: Do not fold clamp instructions when sources are different
Patch by hakzsam (Samuel Pitoiset)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314951
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Craig Topper [Wed, 4 Oct 2017 23:06:13 +0000 (23:06 +0000)]
[InstCombine] Improve support for ashr in foldICmpAndShift
We can support ashr similar to lshr, if we know that none of the shifted in bits are used. In that case SimplifyDemandedBits would normally convert it to lshr. But that conversion doesn't happen if the shift has additional users.
Differential Revision: https://reviews.llvm.org/D38521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314945
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Matt Arsenault [Wed, 4 Oct 2017 22:59:12 +0000 (22:59 +0000)]
AMDGPU: Fix not accounting for instruction size in bundles
These were counted as 0. Fixes branch limit exceeded errors
in some large programs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314944
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Konstantin Zhuravlyov [Wed, 4 Oct 2017 22:44:13 +0000 (22:44 +0000)]
AMDGPU: Correctly set EI_OSABI based on the os
Differential Revision: https://reviews.llvm.org/D38555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314943
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Adrian Prantl [Wed, 4 Oct 2017 22:26:19 +0000 (22:26 +0000)]
clang-format file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314942
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Adrian Prantl [Wed, 4 Oct 2017 22:26:19 +0000 (22:26 +0000)]
delete commented out code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314941
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Sanjoy Das [Wed, 4 Oct 2017 22:02:27 +0000 (22:02 +0000)]
Do not call Loop::getName on possibly dead loops
This fixes PR34832.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314938
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Xin Tong [Wed, 4 Oct 2017 21:39:25 +0000 (21:39 +0000)]
[MachineBlockPlacement] Make sure PreferredLoopExit is cleared everytime new loop is processed
Summary: Rotate on exit that actually exits the current loop.
Reviewers: davidxl, danielcdh, iteratee, chandlerc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38563
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314937
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Hans Wennborg [Wed, 4 Oct 2017 21:14:07 +0000 (21:14 +0000)]
Fix a -Wparentheses warning. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314936
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Justin Lebar [Wed, 4 Oct 2017 20:47:33 +0000 (20:47 +0000)]
Convert an APInt to int64_t properly in TTI::getGEPCost().
Summary:
If the pointer width is 32 bits and the calculated GEP offset is
negative, we call APInt::getLimitedValue(), which does a
*zero*-extension of the offset. That's wrong -- we should do an sext.
Fixes a bug introduced in rL314362 and found by Evgeny Astigeevich.
Reviewers: efriedma
Subscribers: sanjoy, javed.absar, llvm-commits, eastig
Differential Revision: https://reviews.llvm.org/D38557
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314935
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Marcello Maggioni [Wed, 4 Oct 2017 20:42:46 +0000 (20:42 +0000)]
[LoopDeletion] Move deleteDeadLoop to to LoopUtils. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314934
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Rafael Espindola [Wed, 4 Oct 2017 20:27:01 +0000 (20:27 +0000)]
Bring r314809 back.
But now include a check for CPU_COUNT so we still build on 10 year old
versions of glibc.
Original message:
Use sched_getaffinity instead of std::thread::hardware_concurrency.
The issue with std::thread::hardware_concurrency is that it forwards
to libc and some implementations (like glibc) don't take thread
affinity into consideration.
With this change a llvm program that can execute in only 2 cores will
use 2 threads, even if the machine has 32 cores.
This makes benchmarking a lot easier, but should also help if someone
doesn't want to use all cores for compilation for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314931
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Sanjay Patel [Wed, 4 Oct 2017 20:26:25 +0000 (20:26 +0000)]
[SimplifyCFG] put the optional assumption cache pointer in the options struct; NFCI
This is a follow-up to https://reviews.llvm.org/D38138.
I fixed the capitalization of some functions because we're changing those
lines anyway and that helped verify that we weren't accidentally dropping
any options by using default param values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314930
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Xinliang David Li [Wed, 4 Oct 2017 20:17:55 +0000 (20:17 +0000)]
Recommit r314561 after fixing msan build failure
(trial 2) Incoming val defined by terminator instruction which
also requires bitcasts can not be handled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314928
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Guozhi Wei [Wed, 4 Oct 2017 20:14:08 +0000 (20:14 +0000)]
[TargetTransformInfo] Check if function pointer is valid before calling isLoweredToCall
Function isLoweredToCall can only accept non-null function pointer, but a function pointer can be null for indirect function call. So check it before calling isLoweredToCall from getInstructionLatency.
Differential Revision: https://reviews.llvm.org/D38204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314927
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Jun Bum Lim [Wed, 4 Oct 2017 18:33:52 +0000 (18:33 +0000)]
Recommit : Use the basic cost if a GEP is not used as addressing mode
Recommitting r314517 with the fix for handling ConstantExpr.
Original commit message:
Currently, getGEPCost() returns TCC_FREE whenever a GEP is a legal addressing
mode in the target. However, since it doesn't check its actual users, it will
return FREE even in cases where the GEP cannot be folded away as a part of
actual addressing mode. For example, if an user of the GEP is a call
instruction taking the GEP as a parameter, then the GEP may not be folded in
isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314923
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Daniel Neilson [Wed, 4 Oct 2017 18:19:03 +0000 (18:19 +0000)]
Revert D38481 due to missing cmake check for CPU_COUNT
Summary:
This reverts D38481. The change breaks systems with older versions of glibc. It
injects a use of CPU_COUNT() from sched.h without checking to ensure that the
function exists first.
Reviewers:
Subscribers:
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314922
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Simon Pilgrim [Wed, 4 Oct 2017 18:00:42 +0000 (18:00 +0000)]
[X86][AVX] Improve (i8 bitcast (v8i1 x)) handling for v8i64/v8f64 512-bit vector compare results.
AVX1/AVX2 targets were missing a chance to use vmovmskps for v8f32/v8i32 results for bool vector bitcasts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314921
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Krzysztof Parzyszek [Wed, 4 Oct 2017 18:00:15 +0000 (18:00 +0000)]
[Hexagon] Add a member Subtarget to HexagonInstrInfo, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314920
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Hans Wennborg [Wed, 4 Oct 2017 17:54:06 +0000 (17:54 +0000)]
Revert r314886 "[X86] Improvement in CodeGen instruction selection for LEAs (re-applying post required revision changes.)"
It broke the Chromium / SQLite build; see PR34830.
> Summary:
> 1/ Operand folding during complex pattern matching for LEAs has been
> extended, such that it promotes Scale to accommodate similar operand
> appearing in the DAG.
> e.g.
> T1 = A + B
> T2 = T1 + 10
> T3 = T2 + A
> For above DAG rooted at T3, X86AddressMode will no look like
> Base = B , Index = A , Scale = 2 , Disp = 10
>
> 2/ During OptimizeLEAPass down the pipeline factorization is now performed over LEAs
> so that if there is an opportunity then complex LEAs (having 3 operands)
> could be factored out.
> e.g.
> leal 1(%rax,%rcx,1), %rdx
> leal 1(%rax,%rcx,2), %rcx
> will be factored as following
> leal 1(%rax,%rcx,1), %rdx
> leal (%rdx,%rcx) , %edx
>
> 3/ Aggressive operand folding for AM based selection for LEAs is sensitive to loops,
> thus avoiding creation of any complex LEAs within a loop.
>
> Reviewers: lsaba, RKSimon, craig.topper, qcolombet, jmolloy
>
> Reviewed By: lsaba
>
> Subscribers: jmolloy, spatel, igorb, llvm-commits
>
> Differential Revision: https://reviews.llvm.org/D35014
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314919
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Jake Ehrlich [Wed, 4 Oct 2017 17:44:42 +0000 (17:44 +0000)]
[llvm-objcopy] Fix major layout bugs in llvm-objcopy
Somehow a few massive errors slipped though the cracks of testing.
1. The code in Segment::finalize was left over from the old layout
algorithm. In certain situations this would cause very strange issues
with segment layout. For instance in the shift-segments.test case it
would cause the second segment to have the same offset as the first.
2. In debugging this I discovered another issue. Namely section alignment
was not being computed based on Section->Align but instead
Section->Offset which is bizarre and makes no sense. I have no clue how
it worked in the first place. This issue is also fixed
3. Fixing #2 exposed a bug where things were not being written past the end
of the file that technically should have been. This was because in
certain cases (like overlapping-segments) the end of the file wouldn't
always be bumped if the offset could be chosen relative to an existing
segment that already had it's offset chosen. For fully nested segments
this is fine but for overlapping segments this leaves the end of the
file short. So I changed how the offset is bumped when looping though
segments.
Differential Revision: https://reviews.llvm.org/D38436
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314918
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Jakub Kuderski [Wed, 4 Oct 2017 17:32:55 +0000 (17:32 +0000)]
[Dominators] Take fast path when applying <=1 updates
Summary:
This patch teaches `DT.applyUpdates` to take the fast when applying zero or just one update and makes it not run the internal batch updater machinery.
With this patch, it should no longer make sense to have a special check in user's code that checks the update sequence size before applying them, e.g.
```
if (!MyUpdates.empty())
DT.applyUpdates(MyUpdates);
```
or
```
if (MyUpdates.size() == 1)
if (...)
DT.insertEdge(...)
else
DT.deleteEdge(...)
```
Reviewers: dberlin, brzycki, davide, grosser, sanjoy
Reviewed By: dberlin, davide
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38541
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314917
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Simon Pilgrim [Wed, 4 Oct 2017 17:31:28 +0000 (17:31 +0000)]
[X86][SSE] Add support for lowering v8i16 binary shuffles to PACKSS/PACKUS
Missed in D38472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314916
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Francis Ricci [Wed, 4 Oct 2017 17:30:28 +0000 (17:30 +0000)]
[test] Fix append_path in the empty case
Summary:
normpath() was being called on an empty string and appended to
the environment variable in the case where the environment variable
was unset. This led to ":." being appended to the path, since
normpath() of an empty string is '.', presumably to represent cwd.
Reviewers: zturner, sqlbyme, modocache
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38542
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314915
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Craig Topper [Wed, 4 Oct 2017 17:20:12 +0000 (17:20 +0000)]
[X86] Redefine MOVSS/MOVSD instructions to take VR128 regclass as input instead of FR32/FR64
This patch redefines the MOVSS/MOVSD instructions to take VR128 as its second input. This allows the MOVSS/SD->BLEND commute to work without requiring a COPY to be inserted.
This should fix PR33079
Overall this looks to be an improvement in the generated code. I haven't checked the EXPENSIVE_CHECKS build but I'll do that and update with results.
Differential Revision: https://reviews.llvm.org/D38449
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314914
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Balaram Makam [Wed, 4 Oct 2017 16:45:24 +0000 (16:45 +0000)]
"[ARM] Mark flaky test MachineBranchProb.ll unsupported again for ARM/AArch64"
r314857 changed the CFG that resulted in the flaky test MachineBranchProb.ll to
fail the bots again. Marking it as unsupported for ARM/AArch64 again until we
find the cause.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314912
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Yonghong Song [Wed, 4 Oct 2017 16:11:52 +0000 (16:11 +0000)]
bpf: fix an insn encoding issue for neg insn
Signed-off-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314911
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Adam Nemet [Wed, 4 Oct 2017 15:18:11 +0000 (15:18 +0000)]
[OptRemark] Move YAML writing to IR
Before the patch this was in Analysis. Moving it to IR and making it implicit
part of LLVMContext::diagnose allows the full opt-remark facility to be used
outside passes e.g. the pass manager. Jessica is planning to use this to
report function size after each pass. The same could be used for time
reports.
Tested with BUILD_SHARED_LIBS=On.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314909
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Adam Nemet [Wed, 4 Oct 2017 15:18:07 +0000 (15:18 +0000)]
Also update MachineORE after r314874.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314908
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Sanjay Patel [Wed, 4 Oct 2017 15:17:25 +0000 (15:17 +0000)]
[InstCombine] add 'exact' variants of all tests; NFC
We can likely remove most of these as redundant in the near future,
but I'm trying to make sure I don't introduce any regressions with D38514.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314907
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Clement Courbet [Wed, 4 Oct 2017 15:13:52 +0000 (15:13 +0000)]
[NFC] clang-format lib/Transforms/Scalar/MergeICmps.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314906
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Simon Pilgrim [Wed, 4 Oct 2017 13:41:26 +0000 (13:41 +0000)]
[X86][SSE] Early out from ComputeNumSignBitsForTargetNode. NFCI.
Early out from vector shift by immediates that will exceed eltsize - don't bother making an unnecessary ComputeNumSignBits recursive call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314903
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Simon Pilgrim [Wed, 4 Oct 2017 13:12:08 +0000 (13:12 +0000)]
[X86][SSE] Add support for lowering unary shuffles to PACKSS/PACKUS
Extension to D38472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314901
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George Rimar [Wed, 4 Oct 2017 11:00:30 +0000 (11:00 +0000)]
[gold-plugin] - Fix compilation after LLVM update (r314883). NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314899
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Dylan McKay [Wed, 4 Oct 2017 10:37:22 +0000 (10:37 +0000)]
[AVR] Implement LPMWRdZ pseudo-instruction's expansion.
FIXME: implementation is mostly copy-pasted from LDWRdPtr, so we should
refactor a bit and unify the two
Patch by Gerdo Erdi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314898
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Dylan McKay [Wed, 4 Oct 2017 10:36:07 +0000 (10:36 +0000)]
[AVR] Factor out mayLoad in tablegen patterns
Patch by Gergo Erdi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314897
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Dylan McKay [Wed, 4 Oct 2017 10:33:36 +0000 (10:33 +0000)]
[AVR] Elaborate LDWRdPtr into `ld r, X++; ld r+1, X`
Patch by Gergo Erdi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314896
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Dylan McKay [Wed, 4 Oct 2017 09:51:28 +0000 (09:51 +0000)]
[AVR] Insert JMP for long branches
Previously, on long branches (relative jumps of >4 kB), an assertion
failure was hit, as AVRInstrInfo::insertIndirectBranch was not
implemented. Despite its name, it is called by the branch relaxator
for *all* unconditional jumps.
Patch by Thomas Backman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314891
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Dylan McKay [Wed, 4 Oct 2017 09:51:21 +0000 (09:51 +0000)]
[AVR] Fix displacement overflow for LDDW/STDW
In some cases, the code generator attempts to generate instructions such as:
lddw r24, Y+63
which expands to:
ldd r24, Y+63
ldd r25, Y+64 # Oops! This is actually ld r25, Y in the binary
This commit limits the first offset to 62, and thus the second to 63.
It also updates some asserts in AVRExpandPseudoInsts.cpp, including for
INW and OUTW, which appear to be unused.
Patch by Thomas Backman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314890
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Oliver Stannard [Wed, 4 Oct 2017 09:24:54 +0000 (09:24 +0000)]
[ARM] Add diag string for movw/movt immediates in assembly
This adds diagnostics for invalid immediate operands to the MOVW and MOVT
instructions (ARM and Thumb).
Differential revision: https://reviews.llvm.org/D31879
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314888
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Oliver Stannard [Wed, 4 Oct 2017 09:18:07 +0000 (09:18 +0000)]
[ARM, Asm] Change grammar of immediate operand diagnostics
Currently, our diagnostics for assembly operands are not consistent.
Some start with (for example) "immediate operand must be ...",
and some with "operand must be an immediate ...". I think the latter
form is preferable for a few reasons:
* It's unambiguous that it is referring to the expected type of operand, not
the type the user provided. For example, the user could provide an register
operand, and get a message taking about an operand is if it is already an
immediate, just not in the accepted range.
* It allows us to have a consistent style once we add diagnostics for operands
that could take two forms, for example a label or pc-relative memory operand.
Differential revision: https://reviews.llvm.org/D36689
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314887
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Jatin Bhateja [Wed, 4 Oct 2017 09:02:10 +0000 (09:02 +0000)]
[X86] Improvement in CodeGen instruction selection for LEAs (re-applying post required revision changes.)
Summary:
1/ Operand folding during complex pattern matching for LEAs has been
extended, such that it promotes Scale to accommodate similar operand
appearing in the DAG.
e.g.
T1 = A + B
T2 = T1 + 10
T3 = T2 + A
For above DAG rooted at T3, X86AddressMode will no look like
Base = B , Index = A , Scale = 2 , Disp = 10
2/ During OptimizeLEAPass down the pipeline factorization is now performed over LEAs
so that if there is an opportunity then complex LEAs (having 3 operands)
could be factored out.
e.g.
leal 1(%rax,%rcx,1), %rdx
leal 1(%rax,%rcx,2), %rcx
will be factored as following
leal 1(%rax,%rcx,1), %rdx
leal (%rdx,%rcx) , %edx
3/ Aggressive operand folding for AM based selection for LEAs is sensitive to loops,
thus avoiding creation of any complex LEAs within a loop.
Reviewers: lsaba, RKSimon, craig.topper, qcolombet, jmolloy
Reviewed By: lsaba
Subscribers: jmolloy, spatel, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D35014
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314886
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