OSDN Git Service
Francisco Jerez [Fri, 1 Nov 2013 18:29:13 +0000 (11:29 -0700)]
i965/gen7: Add instruction latency estimates for untyped atomics and reads.
The latency information has been obtained empirically from
measurements taken on Haswell and Ivy Bridge.
Acked-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 25 Sep 2013 23:31:35 +0000 (16:31 -0700)]
i965/gen7: Handle atomic instructions from the VEC4 back-end.
This can deal with all the 15 32-bit untyped atomic operations the
hardware supports, but only INC and PREDEC are going to be exposed
through the API for now.
v2: Represent atomics as GLSL intrinsics. Add support for variably
indexed atomic counter arrays.
v3: Add comment on why we don't need to assign uniform storage for
atomic counters.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Francisco Jerez [Wed, 25 Sep 2013 23:30:20 +0000 (16:30 -0700)]
i965/gen7: Handle atomic instructions from the FS back-end.
This can deal with all the 15 32-bit untyped atomic operations the
hardware supports, but only INC and PREDEC are going to be exposed
through the API for now.
v2: Represent atomics as GLSL intrinsics. Add support for variably
indexed atomic counter arrays. Fix interaction with fragment
discard.
v3: Add comment on why we don't need to assign uniform storage for
atomic counters.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Francisco Jerez [Sun, 20 Oct 2013 21:02:08 +0000 (14:02 -0700)]
i965: Add a 'has_side_effects' back-end instruction predicate.
This patch fixes the three dead code elimination passes and the
VEC4/FS instruction scheduling passes so they leave instructions with
side effects alone.
At some point it might be interesting to have the instruction
scheduler calculate the exact memory dependencies between atomic ops,
but they're rare enough that it seems unlikely that it will make any
practical difference.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Francisco Jerez [Mon, 4 Nov 2013 19:26:13 +0000 (11:26 -0800)]
clover: Calculate optimal work group size when it's not specified by the user.
Inspired by a patch sent to the mailing list by Tom Stellard, but
using a different algorithm to calculate the optimal block size that
has been found to be considerably more effective.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Francisco Jerez [Mon, 4 Nov 2013 19:24:10 +0000 (11:24 -0800)]
clover: Constify some command_queue arguments.
Francisco Jerez [Wed, 30 Oct 2013 18:11:06 +0000 (11:11 -0700)]
clover: Workaround compiler bug present in GCC 4.7.0-4.7.2.
Variadic template aliases make these versions of GCC very confused,
write down the full type spec instead.
Emil Velikov [Fri, 1 Nov 2013 16:44:10 +0000 (16:44 +0000)]
st/xorg: handle updates to DamageUnregister API
xserver 1.14.99.2 simplified the DamageUnregister API, by
dropping the drawable argument.
Follow xf86-video-intel and xf86-video-vmware approach and
handle the new API by checking XORG_VERSION_CURRENT.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71110
Reported-by: Michał Górny <mgorny@gentoo.org>
Reported-by: Vinson Lee <vlee@freedesktop.org>
Tested-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Brian Paul [Mon, 4 Nov 2013 14:33:41 +0000 (07:33 -0700)]
mesa: remove Watcom C support
Reviewed-by: Eric Anholt <eric@anholt.net>
Brian Paul [Mon, 4 Nov 2013 14:26:54 +0000 (07:26 -0700)]
mesa: remove Centerline C support from gl.h
Reviewed-by: Eric Anholt <eric@anholt.net>
Brian Paul [Mon, 4 Nov 2013 14:29:57 +0000 (07:29 -0700)]
mesa: remove BUILD_FOR_SNAP bits
Reviewed-by: Eric Anholt <eric@anholt.net>
Brian Paul [Mon, 4 Nov 2013 14:25:22 +0000 (07:25 -0700)]
mesa: remove SciTech stuff from gl.h
Reviewed-by: Eric Anholt <eric@anholt.net>
Marek Olšák [Sun, 3 Nov 2013 19:27:28 +0000 (20:27 +0100)]
r600g: properly unbind a DSA state being deleted in r600_delete_dsa_state
Tested-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Thu, 31 Oct 2013 14:49:36 +0000 (15:49 +0100)]
docs/GL3: document radeonsi support, minor cleanup
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Marek Olšák [Thu, 31 Oct 2013 14:20:06 +0000 (15:20 +0100)]
radeonsi: implement ARB_vertex_type_2_10_10_10_rev
Marek Olšák [Thu, 31 Oct 2013 14:32:30 +0000 (15:32 +0100)]
r600g,radeonsi: properly expose texture buffer formats
This exposes GL_ARB_texture_buffer_object_rgb32.
Marek Olšák [Thu, 31 Oct 2013 14:08:49 +0000 (15:08 +0100)]
radeonsi: implement texture buffer objects
GLSL 1.40 is done.
Marek Olšák [Wed, 30 Oct 2013 20:44:07 +0000 (21:44 +0100)]
radeonsi: report our border color behavior
Marek Olšák [Wed, 30 Oct 2013 19:44:23 +0000 (20:44 +0100)]
radeonsi: bind a dummy constant buffer in place of NULL buffers
Marek Olšák [Fri, 25 Oct 2013 09:45:47 +0000 (11:45 +0200)]
radeonsi: implement uniform buffer objects
Marek Olšák [Wed, 30 Oct 2013 13:24:27 +0000 (14:24 +0100)]
tgsi/scan: set maximum index for each constant buffer
Marek Olšák [Tue, 29 Oct 2013 23:36:58 +0000 (00:36 +0100)]
radeonsi: try to fix IA_MULTI_VGT_PARAM programming
This doesn't make any difference on Bonaire, but it might help on Hawaii.
Marek Olšák [Tue, 29 Oct 2013 23:22:01 +0000 (00:22 +0100)]
winsys/radeon: use type-3 NOPs for CS padding on CIK
The type-2 NOPs are said to be unstable. It doesn't make a difference here.
Aaron Watry [Fri, 1 Nov 2013 15:25:43 +0000 (10:25 -0500)]
clover: fix build with LLVM 3.4
dso_list was added as an argument for createInternalizePass in 3.4, and then
it was removed again in the same llvm version.
Tested-by: Mike Lothian <mike@fireburn.co.uk>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Brian Paul [Fri, 1 Nov 2013 23:07:55 +0000 (17:07 -0600)]
draw: move type construction out of loop
We can create clip_ptr_type once instead of n times inside the loop.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Chad Versace [Sun, 3 Nov 2013 21:14:50 +0000 (13:14 -0800)]
i965: Add driconf option clamp_max_samples
The new option clamps GL_MAX_SAMPLES to a hardware-supported MSAA mode.
If negative, then no clamping occurs.
v2: (for Paul)
- Add option to i965 only, not to all DRI drivers.
- Do not realy on int->uint cast to convert negative
values to large positive values. Explicitly check for
clamp_max_samples < 0.
v3: (for Ken)
- Don't allow clamp_max_samples to alter context version.
- Use clearer for-loop and correct comment.
- Rename variables.
v4: (for Ken)
- Merge identical if-branches.
Reviewed-and-tested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Vinson Lee [Sun, 3 Nov 2013 22:43:53 +0000 (14:43 -0800)]
i965: Fix logic_op check.
Fixes "Macro compares unsigned to 0" defect reported by Coverity.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Vinson Lee [Sun, 3 Nov 2013 22:42:18 +0000 (14:42 -0800)]
i915: Fix logic_op check.
Fixes "Macro compares unsigned to 0" defect reported by Coverity.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Vinson Lee [Sat, 26 Oct 2013 07:10:25 +0000 (00:10 -0700)]
i965: Initialize vec4_visitor member variables.
Fixes "Uninitialized pointer field" defect reported by Coverity.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Marek Olšák [Sat, 2 Nov 2013 11:20:29 +0000 (12:20 +0100)]
gallium/targets: remove vdpau-softpipe
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Sat, 2 Nov 2013 11:18:44 +0000 (12:18 +0100)]
gallium/targets: remove xvmc-softpipe
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Sat, 2 Nov 2013 11:07:42 +0000 (12:07 +0100)]
gallium/targets: remove r300/vdpau
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Sat, 2 Nov 2013 11:03:42 +0000 (12:03 +0100)]
gallium/targets: remove r300/xvmc
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Fri, 1 Nov 2013 18:42:47 +0000 (19:42 +0100)]
gallium/targets: remove radeonsi/xorg
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Fri, 1 Nov 2013 18:36:12 +0000 (19:36 +0100)]
gallium/targets: remove r600/xorg
Reviewed-by: Christian König <christian.koenig@amd.com>
Rob Clark [Fri, 1 Nov 2013 23:46:55 +0000 (19:46 -0400)]
freedreno/a3xx/texture: min/max lod
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 1 Nov 2013 23:45:02 +0000 (19:45 -0400)]
freedreno/a3xx: update envytools headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 1 Nov 2013 14:11:27 +0000 (10:11 -0400)]
freedreno/a3xx: fix VS out / FS in linking
Actually link VS out / FS in based on semantic info, keeping in mind
that position/pointsize can also be an input to the FS. This fixes a
few fragment shaders which were using gl_Position.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 1 Nov 2013 14:09:39 +0000 (10:09 -0400)]
freedreno/a3xx: allow num_samplers != num_textures
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 31 Oct 2013 13:59:49 +0000 (09:59 -0400)]
freedreno/a3xx/compiler: highp frag shader
Fixes use of full-precision in fragment shader (ie. don't clobber r0.x
since that can be used by future bary instructions for varying fetch).
And makes use of full-precision the default in fragment shader (but can
be overriden via FD_MESA_DEBUG=fraghalf).
Seems like half precision is often not enough for texture coordinates.
The blob compiler is clever enough to keep texture coords in full
precision registers while using half precision for everything else. But
we aren't quite that clever yet, so better to default to full precision.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sun, 27 Oct 2013 14:19:58 +0000 (10:19 -0400)]
freedreno/a3xx/compiler: relative addressing fixes.
Handle some relative addressing constraints: cannot handle const or
relative in cat5 and src2 of cat3.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 25 Oct 2013 15:48:24 +0000 (11:48 -0400)]
freedreno: we do actually support sqrt
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Anuj Phogat [Fri, 30 Aug 2013 20:13:15 +0000 (13:13 -0700)]
i965: Enable ARB_sample_shading on intel hardware >= gen6
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Ken Graunke <kenneth@whitecape.org>
Anuj Phogat [Mon, 7 Oct 2013 19:45:44 +0000 (12:45 -0700)]
i965/gen7: Enable the features required for GL_ARB_sample_shading
- Enable GEN7_WM_MSDISPMODE_PERSAMPLE, GEN7_WM_POSOFFSET_SAMPLE,
GEN7_WM_OMASK_TO_RENDER_TARGET as per extension's specification.
- Only enable one of GEN7_WM_8_DISPATCH_ENABLE or GEN7_WM_16_DISPATCH_ENABLE
when GEN7_WM_MSDISPMODE_PERSAMPLE is enabled. Refer IVB PRM Vol. 2, Part 1,
Page 288 for details.
V2:
- Use shared function _mesa_get_min_invocations_per_fragment().
- Use brw_wm_prog_data variables: uses_pos_offset, uses_omask.
V3:
- Enable simd16 dispatch with per sample shading.
- Make changes to give preference to 'simd16 only' mode over
'simd8 only' mode in case of non 1x per sample shading.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Anuj Phogat [Mon, 7 Oct 2013 19:05:56 +0000 (12:05 -0700)]
i965/gen6: Enable the features required for GL_ARB_sample_shading
- Enable GEN6_WM_MSDISPMODE_PERSAMPLE, GEN6_WM_POSOFFSET_SAMPLE,
GEN6_WM_OMASK_TO_RENDER_TARGET as per extension's specification.
- Only enable one of GEN6_WM_8_DISPATCH_ENABLE or GEN6_WM_16_DISPATCH_ENABLE
when GEN6_WM_MSDISPMODE_PERSAMPLE is enabled.
Refer SNB PRM Vol. 2, Part 1, Page 279 for details.
V2:
- Use shared function _mesa_get_min_invocations_per_fragment().
- Use brw_wm_prog_data variables: uses_pos_offset, uses_omask.
V3:
- Enable simd16 dispatch with per sample shading.
- Make changes to give preference to 'simd16 only' mode over
'simd8 only' mode in case of non 1x per sample shading.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Anuj Phogat [Thu, 24 Oct 2013 23:21:13 +0000 (16:21 -0700)]
i965: Add FS backend for builtin gl_SampleMask[]
V2:
- Update comments
- Add a special backend instructions to compute sample_mask.
- Add a new variable uses_omask in brw_wm_prog_data.
V3:
- Make changes to support simd16 mode.
- Delete redundant AND instruction and handle the register
stride in FS backend instruction.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Anuj Phogat [Thu, 24 Oct 2013 23:17:08 +0000 (16:17 -0700)]
i965: Add FS backend for builtin gl_SampleID
V2:
- Update comments
- Add compute_sample_id variables in brw_wm_prog_key
- Add a special backend instruction to compute sample_id.
V3:
- Make changes to support simd16 mode.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Anuj Phogat [Thu, 24 Oct 2013 22:53:05 +0000 (15:53 -0700)]
i965: Add FS backend for builtin gl_SamplePosition
V2:
- Update comments.
- Add compute_pos_offset variable in brw_wm_prog_key.
- Add variable uses_pos_offset in brw_wm_prog_data.
V3:
- Make changes to support simd16 mode.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Anuj Phogat [Tue, 22 Oct 2013 19:00:11 +0000 (12:00 -0700)]
i965: Don't do vector splitting for ir_var_system_value
This is required while adding builtin system value vec{2, 3, 4}
variables. For example:
(declare (sys) vec2 gl_SamplePosition)
Without this patch above glsl ir splits in to:
(declare (temporary) float gl_SamplePosition_x)
(declare (temporary) float gl_SamplePosition_y)
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Anuj Phogat [Thu, 17 Oct 2013 00:22:18 +0000 (17:22 -0700)]
mesa: Add a helper function _mesa_get_min_invocations_per_fragment()
This function is used to test if we need to do per sample shading or
per fragment shading.
V2: Use MAX2() to make sure the function returns a number >= 1.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Anuj Phogat [Fri, 30 Aug 2013 20:10:54 +0000 (13:10 -0700)]
glsl: Add new builtins required by GL_ARB_sample_shading
New builtins added by GL_ARB_sample_shading:
in vec2 gl_SamplePosition
in int gl_SampleID
in int gl_NumSamples
out int gl_SampleMask[]
V2: - Use SWIZZLE_XXXX for STATE_NUM_SAMPLES.
- Use "result.samplemask" in arb_output_attrib_string.
- Add comment to explain the size of gl_SampleMask[] array.
- Make gl_SampleID and gl_SamplePosition system values.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Anuj Phogat [Thu, 3 Oct 2013 01:02:20 +0000 (18:02 -0700)]
mesa: Pass number of samples as a program state variable
Number of samples will be required in fragment shader program by new
GLSL builtin uniform "gl_NumSamples".
V2: Use "state.numsamples" in place of "state.num.samples"
Use _NEW_BUFFERS flag in place of _NEW_MULTISAMPLE
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ian Romanick <idr@freedesktop.org>
Reviewed-by: Ken Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Anuj Phogat [Fri, 30 Aug 2013 19:52:38 +0000 (12:52 -0700)]
mesa: Add new functions and enums required by GL_ARB_sample_shading
New functions added by GL_ARB_sample_shading:
glMinSampleShadingARB()
New enums:
GL_SAMPLE_SHADING_ARB
GL_MIN_SAMPLE_SHADING_VALUE_ARB
V2: Update comments.
Create new GL4x.xml.
Remove redundant code in get.c.
Update the API_XML list in Makefile.am.
Add extra_gl40_ARB_sample_shading predicate to get.c.
V3:
Fix make check failure.
Add checks for desktop GL.
Use GLfloat in place of GLclampf in glMinSampleShading().
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ken Graunke <kenneth@whitecape.org>
Anuj Phogat [Fri, 30 Aug 2013 19:34:36 +0000 (12:34 -0700)]
mesa: Add infrastructure for GL_ARB_sample_shading
This patch implements the common support code required for the
GL_ARB_sample_shading extension.
V2: Move GL_ARB_sample_shading to ARB extension list.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ian Romanick <idr@freedesktop.org>
Reviewed-by: Ken Graunke <kenneth@whitecape.org>
Matt Turner [Mon, 28 Oct 2013 04:26:36 +0000 (21:26 -0700)]
i965/fs: Optimize saturating SEL.G(E) with imm val <= 0.0f.
Only one program's instruction count is changed, but a shader in Tropics
is also affected.
instructions in affected programs: 326 -> 320 (-1.84%)
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Matt Turner [Mon, 28 Oct 2013 03:03:48 +0000 (20:03 -0700)]
i965/fs: Optimize saturating SEL.L(E) with imm val >= 1.0.
total instructions in shared programs:
1409124 ->
1406971 (-0.15%)
instructions in affected programs: 158376 -> 156223 (-1.36%)
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Matt Turner [Mon, 28 Oct 2013 02:34:48 +0000 (19:34 -0700)]
i965/fs: Optimize OR with identical sources into a MOV.
Helps a lot of Steam games.
total instructions in shared programs:
1409360 ->
1409124 (-0.02%)
instructions in affected programs: 20842 -> 20606 (-1.13%)
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Thu, 17 Oct 2013 17:28:40 +0000 (10:28 -0700)]
glsl: Add a CSE pass.
This only operates on constant/uniform values for now, because otherwise I'd
have to deal with killing my available CSE entries when assignments happen,
and getting even this working in the tree ir was painful enough.
As is, it has the following effect in shader-db:
total instructions in shared programs:
1524077 ->
1521964 (-0.14%)
instructions in affected programs: 50629 -> 48516 (-4.17%)
GAINED: 0
LOST: 0
And, for tropics, that accounts for most of the effect, the FPS
improvement is 11.67% +/- 0.72% (n=3).
v2: Use read_only field of the variable, manually check the lod_info union
members, use get_num_operands(), rename cse_operands_visitor to
is_cse_candidate_visitor, move all is-a-candidate logic to that
function, and call it before checking for CSE on a given rvalue, more
comments, use private keyword.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Thu, 31 Oct 2013 00:09:53 +0000 (17:09 -0700)]
i965/vec4: Don't overwrite op[1] when doing a UBO load.
Prior to the GLSL CSE pass, all of our testing happened to have a freshly
computed temporary in op[1], from the multiply by 16 to get a byte offset.
As of CSE you'll get var_refs of a reused value when you've got multiple
loads from the same offset.
Make a proper temporary for computing our temporary value, to avoid
shifting the value farther and farther down. Avoids a regression in
gs-float-array-variable-index
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Brian Paul [Fri, 1 Nov 2013 14:43:22 +0000 (08:43 -0600)]
st/mesa: fix _mesa_init_transform_feedback_object() argument
Need to pass a pointer of the base type, not the st type.
Fixes a compiler warning.
Kenneth Graunke [Wed, 30 Oct 2013 23:06:06 +0000 (16:06 -0700)]
i965: Fix brw_store_register_mem64 to stay within a single batch.
Previously, the write of each 32-bit half might land in separate batch
buffers, which is insane.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Thu, 31 Oct 2013 18:10:20 +0000 (11:10 -0700)]
docs: List transfom_feedback{2,3,instanced} for i965 in release notes.
Kenneth Graunke [Sat, 26 Oct 2013 20:27:18 +0000 (13:27 -0700)]
i965: Enable the ARB_transform_feedback_instanced extension on Gen7+.
This depends on ARB_transform_feedback2, so I've predicated it on the
ability to do register writes.
It also depends on ARB_transform_feedback3, which is the only reason we
couldn't expose it previously.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Sat, 26 Oct 2013 20:20:02 +0000 (13:20 -0700)]
i965: Enable the ARB_transform_feedback3 extension on Gen7+.
This extension is written a bit strangely. Although it introduces the
concept of multiple transform feedback streams, it doesn't actually
provide more than a single stream.
The ARB_gpu_shader5 extension is what introduces the ability to write to
streams other than stream #0 and increases the required number of streams.
Since we don't yet support ARB_gpu_shader5, we can safely enable
ARB_transform_feedback3 even though we only support a single stream.
This does provide some useful functionality: applications can now use
more than one interleaved transform feedback buffer.
v2: Only expose the extension if ARB_transform_feedback2 is also
available, to avoid confusing applications (suggested by Ian).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Sat, 26 Oct 2013 18:34:11 +0000 (11:34 -0700)]
i965: Add support for gl_SkipComponents[1234].
ARB_transform_feedback3 allows applications to insert blank space
between interleaved varyings by adding fake 1, 2, 3, or 4-component
varyings named gl_SkipComponents[1234].
Mesa's core data structures don't explicitly track these, instead simply
tracking the buffer offset for each real varying. If there is padding
due to gl_SkipComponents, these will not be contiguous.
Our hardware takes the specification quite literally. Instead of
specifying offsets for each varying, it assumes they're all contiguous
and requires you to program fake varyings for each "hole".
This patch adds support for emitting SO_DECL structures for these holes.
Although we've lost the information about exactly how the application
specified their padding (i.e. gl_SkipComponents2, gl_SkipComponents2
vs. a single gl_SkipComponents4), it shouldn't matter. We just need to
emit the right amount of space. This patch emits the minimal number of
hole SO_DECL structures.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Sat, 26 Oct 2013 18:14:55 +0000 (11:14 -0700)]
i965: Explicitly maintain a count of SO_DECL structures emitted.
Currently, we emit one SO_DECL structure per output, so we use the index
in the Outputs[] array as the index into the so_decl[] array as well.
In order to support the fake "gl_SkipComponents[1234]" varyings from
ARB_transform_feedback3, we'll need to emit SO_DECLs to fill in the
holes between successive outputs. This means we'll likely emit more
SO_DECLs than there are outputs, so we need to count it explicitly.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Sat, 26 Oct 2013 18:12:48 +0000 (11:12 -0700)]
i965: Create a temporary for transform feedback output components.
This is a bit shorter.
v2: Mark the temporary const (requested by Ian).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Tue, 28 May 2013 03:09:56 +0000 (20:09 -0700)]
i965: Enable ARB_transform_feedback2 on Gen7+ if register writes work.
With Linux 3.12, register writes work on Ivybridge and Baytrail, but not
Haswell. That will be fixed in a future kernel revision, at which point
this extension will automatically be enabled.
v2: Use I915_GEM_DOMAIN_INSTRUCTION for the register read, and also
correctly set the writeable flag when mapping (caught by Eric).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Sat, 26 Oct 2013 05:44:19 +0000 (22:44 -0700)]
i965: Initialize batchbuffer and state modules before extensions.
We only want to enable ARB_transform_feedback2 if we can write to
registers from batchbuffers. In order to test that, we need to be able
to submit batches. And for batches to work, we need to program the
initial pipeline state (like PIPELINE_SELECT), which is done from
brw_state_init().
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Fri, 6 Sep 2013 23:59:31 +0000 (16:59 -0700)]
i965: Implement glDrawTransformFeedback().
Implementing the GetTransformFeedbackVertexCount() driver hook allows
the VBO module to call us with the right number of vertices.
The hardware doesn't directly count the number of vertices written by
SOL, so we instead use the SO_NUM_PRIMS_WRITTEN(n) counters and multiply
by the number of vertices per primitive.
Unfortunately, counting the number of primitives generated is tricky:
a program might pause a transform feedback operation, start a second one
with a different object, then switch back and resume. Both transform
feedback operations share the SO_NUM_PRIMS_WRITTEN counters.
To work around this, we save the counter values at Begin, Pause, Resume,
and End. This "bookends" each section where transform feedback is
active for the current object. Adding up differences of pairs gives
us the number of primitives generated. (This is similar to what we
do for occlusion queries on platforms without hardware contexts.)
v2: Fix missing parenthesis in assertion (caught by Eric Anholt).
v3: Reuse prim_count_bo rather than freeing it and immediately
allocating a new one (suggested by Topi Pohjolainen).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Mon, 27 May 2013 18:41:21 +0000 (11:41 -0700)]
i965: Mark brw_draw_prims tfb_vertcount parameter as unused.
Renaming it makes it obvious that it isn't used, and the assertion
verifies that the VBO module never passes us such an object.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Mon, 27 May 2013 18:27:18 +0000 (11:27 -0700)]
mesa: Add a new GetTransformFeedbackVertexCount() driver hook.
DrawTransformFeedback() needs to obtain the number of vertices written
to a particular stream during the last Begin/EndTransformFeedback block.
The new driver hook returns exactly that information.
Gallium drivers already implement this by passing the transform feedback
object to the drawing function, counting the number of vertices written
on the GPU, and using draw indirect. This is efficient, but doesn't
always work:
If vertex data comes from user arrays, then the VBO module needs to
know how many vertices to upload, so we need to synchronously count.
Gallium drivers are currently broken in this case.
It also doesn't work if primitive restart is done in software. For
normal drawing, vbo_draw_arrays() performs software primitive restart,
splitting the draw call in two. vbo_draw_transform_feedback() currently
doesn't because it has no idea how many vertices need to be drawn.
The new driver hook gives it that information, allowing us to reuse
the existing vbo_draw_arrays() code to do everything right.
On Intel hardware (at least Ivybridge), using the draw indirect approach
is difficult since the hardware counts primitives, rather than vertices,
which requires doing some simple math. So we always use this hook.
Gallium drivers will likely want to use this hook in some cases, but
want to use the existing draw indirect approach where possible. Hence,
I've added a flag to allow drivers to opt-in to this call.
v2: Make it possible to implement this hook but only use this path
when necessary (suggested by Marek).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Kenneth Graunke [Mon, 27 May 2013 00:53:14 +0000 (17:53 -0700)]
i965: Implement Pause/ResumeTransformfeedback driver hooks on Gen7+.
The ARB_transform_feedback2 extension introduces the ability to pause
and resume transform feedback sessions. Although only one can be active
at a time, it's possible to switch between multiple transform feedback
objects while paused.
In order to facilitate this, we need to save/restore the SO_WRITE_OFFSET
registers so that after resuming, the GPU continues writing where it
left off.
This functionality also exists in ES 3.0, but somehow we completely
forgot to implement it.
v2: Reduce alignment from 4096 to 64 (it seemed excessive).
v3: Use I915_GEM_DOMAIN_INSTRUCTION instead of RENDER, for consistency
with other writes. It shouldn't matter on IVB+.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Fri, 24 May 2013 08:29:14 +0000 (01:29 -0700)]
i965: Create a new brw_transform_feedback_object subclass.
This adds the basic driver hooks to allocate/free the brw variant.
It doesn't contain any additional information yet, but it will soon.
v2: Use the new _mesa_init_transform_feedback_object helper function
(requested by Eric and Ian).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Fri, 25 Oct 2013 22:58:46 +0000 (15:58 -0700)]
st/mesa: Use the new _mesa_init_transform_feedback_object() helper.
This picks up a missing obj->EverBound = GL_FALSE line, and will catch
any new fields that get added in the future.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Fri, 25 Oct 2013 22:54:10 +0000 (15:54 -0700)]
mesa: Separate transform feedback object initialization from allocation.
Both Gallium and i965 subclass gl_transform_feedback_object, which
requires implementing a custom NewTransformFeedback hook. Creating a
helper function to initialize the fields avoids code duplication and
divergence.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Brian Paul [Tue, 29 Oct 2013 20:11:28 +0000 (14:11 -0600)]
vbo: fix MSVC double->float conversion warnings
Brian Paul [Tue, 29 Oct 2013 20:11:18 +0000 (14:11 -0600)]
swrast: fix MSVC double->float conversion warnings
Brian Paul [Tue, 29 Oct 2013 20:11:01 +0000 (14:11 -0600)]
mesa: fix some MSVC signed/unsigned compiler warnings
Brian Paul [Tue, 29 Oct 2013 20:10:11 +0000 (14:10 -0600)]
meta: fix assorted MSVC int/float conversion warnings
Brian Paul [Tue, 29 Oct 2013 20:09:46 +0000 (14:09 -0600)]
glsl: fix MSVC int->bool conversion warning
Brian Paul [Tue, 29 Oct 2013 15:48:32 +0000 (09:48 -0600)]
st/draw: silence Mingw warning in pointer_to_offset()
Fixes "warning: cast from pointer to integer of different size" for
64-bit builds.
Matt Turner [Sun, 20 Oct 2013 18:38:17 +0000 (11:38 -0700)]
i965/fs: Perform CSE on CMP(N) instructions.
Optimizes
cmp.ge.f0(8) null g45<8,8,1>F 0F
(+f0) sel(8) g50<1>F g40<8,8,1>F g10<8,8,1>F
cmp.ge.f0(8) null g45<8,8,1>F 0F
(+f0) sel(8) g51<1>F g41<8,8,1>F g11<8,8,1>F
cmp.ge.f0(8) null g45<8,8,1>F 0F
(+f0) sel(8) g52<1>F g42<8,8,1>F g12<8,8,1>F
cmp.ge.f0(8) null g45<8,8,1>F 0F
(+f0) sel(8) g53<1>F g43<8,8,1>F g13<8,8,1>F
into
cmp.ge.f0(8) null g45<8,8,1>F 0F
(+f0) sel(8) g50<1>F g40<8,8,1>F g10<8,8,1>F
(+f0) sel(8) g51<1>F g41<8,8,1>F g11<8,8,1>F
(+f0) sel(8) g52<1>F g42<8,8,1>F g12<8,8,1>F
(+f0) sel(8) g53<1>F g43<8,8,1>F g13<8,8,1>F
total instructions in shared programs:
1644938 ->
1638181 (-0.41%)
instructions in affected programs: 574955 -> 568198 (-1.18%)
Two more 16-wide programs (in L4D2). Some large (-9%) decreases in
instruction count in some of Valve's Source Engine games. No
regressions.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Matt Turner [Tue, 22 Oct 2013 22:40:08 +0000 (15:40 -0700)]
i965/fs: Don't emit null MOVs in CSE.
We'd like to CSE some instructions, like CMP, that often have null
destinations. Instead of replacing them with MOVs to null, just don't
emit the MOV.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Matt Turner [Tue, 22 Oct 2013 23:23:27 +0000 (16:23 -0700)]
i965/fs: Use reads_flag and writes_flag methods in the scheduler.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Matt Turner [Sun, 20 Oct 2013 18:32:01 +0000 (11:32 -0700)]
i965/fs: Add reads_flag() and writes_flag() to fs_inst.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Matt Turner [Tue, 22 Oct 2013 19:32:23 +0000 (12:32 -0700)]
i965/fs: Add is_null() method to fs_reg.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Wed, 16 Oct 2013 18:51:22 +0000 (11:51 -0700)]
i965/fs: Use the gen7 scratch read opcode when possible.
This avoids a lot of message setup we had to do otherwise. Improves
GLB2.7 performance with register spilling force enabled by 1.6442% +/-
0.553218% (n=4).
v2: Use BRW_PREDICATE_NONE, improve a comment (by Paul).
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Wed, 16 Oct 2013 18:45:06 +0000 (11:45 -0700)]
i965: Merge together opcodes for SHADER_OPCODE_GEN4_SCRATCH_READ/WRITE
I'm going to be introducing gen7 variants, and the previous naming was
going to get confusing.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Wed, 16 Oct 2013 19:39:07 +0000 (12:39 -0700)]
i965/fs: Fix register unspills from a reg_offset.
We were clearing the reg_offset before trying to use it. Oops. Fixes
glsl-fs-texture2drect with the reg spilling debug enabled.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Wed, 16 Oct 2013 19:16:51 +0000 (12:16 -0700)]
i965/fs: Fix register spilling for 16-wide.
Things blew up when I enabled the debug register spill code without
disabling 16-wide, so I decided to just fix 16-wide spilling.
We still don't generate 16-wide when register spilling happens as part of
allocation (since we expect it to be slower), but now we can experiment
with allowing it in some cases in the future.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Tue, 29 Oct 2013 19:46:18 +0000 (12:46 -0700)]
i965/fs: Exit the compile if spilling would overwrite in-use MRFs.
I believe this will never happen in SIMD8 mode, but it could for SIMD16
when we fix it.
v2: Fix off-by-one in my register counting comment (caught by Paul).
Reviewed-by: Paul Berry <stereotype441@gmail.com> (v1)
Eric Anholt [Wed, 16 Oct 2013 19:02:41 +0000 (12:02 -0700)]
i965/fs: Fix broken register spilling debug code.
Now that reg spilling generates new vgrfs, we were looping forever if you
ever turned it on.
Instead, move the debug code into the register allocator right near where
we'd be doing spilling anyway, which should more accurately reflect how
register spilling occurs in the wild.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Tue, 29 Oct 2013 19:18:10 +0000 (12:18 -0700)]
i965/fs: Split "find what MRFs were used" to a helper function.
I'm going to need to reuse this for fixing register spilling on SIMD16.
Note that BRW_MAX_MRF is 16, which is the same as BRW_MAX_GRF -
GEN7_MRF_HACK_START.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Tue, 29 Oct 2013 08:06:09 +0000 (01:06 -0700)]
i965/fs: Update an ancient, wrong comment about reg_offset.
This hasn't been true since SIMD16 mode was added.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Kai Wasserbäch [Sun, 27 Oct 2013 18:36:07 +0000 (19:36 +0100)]
radeonsi: Allow longer intrinsic names
Fixes a boat load of Piglit tests for me, which crashed like fdo#70913
before.
Thanks to Michel Dänzer for the tip.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70913
Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tom Stellard [Tue, 29 Oct 2013 16:48:37 +0000 (12:48 -0400)]
clover: Don't install headers when using the icd
The ICD loader should be responsible for installing headers.
Reviewed and Tested-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Tom Stellard [Tue, 22 Oct 2013 16:26:12 +0000 (09:26 -0700)]
radeon/llvm: Specify the DataLayout when running optimizations
Without DataLayout, a lot of optimization passes aren't run and the ones
that are don't work as well.
Eric Anholt [Mon, 28 Oct 2013 22:17:07 +0000 (15:17 -0700)]
i965/fs: Prefer more-critical instructions of the same age in LIFO scheduling.
When faced with a million instructions that all became candidates at the
same time (none of which individually reduce register pressure), the ones
on the critical path are more likely to be the ones that will free up some
candidates soon.
shader-db:
total instructions in shared programs:
1681070 ->
1681070 (0.00%)
instructions in affected programs: 0 -> 0
GAINED: 40
LOST: 74
Fixes indistinguishable-from-hanging behavior in GLES3conform's
uniform_buffer_object_max_uniform_block_size test, regressed by
c3c9a8c85758796a26b48e484286e6b6f5a5299a. Given that
93bd627d5a6c485948b94488e6cd53a06b7ebdcf was unlocked by that commit, the
net effect on 16-wide program count is still quite positive, and I think
this should give us more stable scheduling (less dependency on original
instruction emit order).
v2: Comment suggestions by Paul
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70943
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Mon, 28 Oct 2013 07:11:45 +0000 (00:11 -0700)]
i965: Compute the node's delay time for scheduling.
This is a step in doing scheduling as described in Muchnick (p538). A
difference is that our latency function is only specific to one
instruction (it doesn't describe, for example, the different latency
between WAR of a send's arguments and RAW of a send's destination), but
that's changeable later. We also don't separately compute the postorder
traversal of the graph, since we can use the setting of the delay field as
the "visited" flag.
Reviewed-by: Paul Berry <stereotype441@gmail.com>