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Marek Olsak [Fri, 9 Dec 2016 19:49:48 +0000 (19:49 +0000)]
AMDGPU/SI: Don't reserve FLAT_SCR on non-HSA targets & without stack objects
Summary: This frees 2 scalar registers.
Reviewers: tstellarAMD
Subscribers: qcolombet, arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D27150
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289261
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Marek Olsak [Fri, 9 Dec 2016 19:49:40 +0000 (19:49 +0000)]
AMDGPU/SI: Allow using SGPRs 96-101 on VI
Summary:
There is no point in setting SGPRS=104, because VI allocates SGPRs
in multiples of 16, so 104 -> 112. That enables us to use all 102 SGPRs
for general purposes.
Reviewers: tstellarAMD
Subscribers: qcolombet, arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D27149
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289260
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Reid Kleckner [Fri, 9 Dec 2016 19:20:28 +0000 (19:20 +0000)]
Remove /Zc:sizedDealloc- from the MSVC build
According to the connect bug
(https://connect.microsoft.com/VisualStudio/feedback/details/
1351894),
this was only necessary with pre-release versions of MSVC 2015.
Fixes PR23513
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289257
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Paul Robinson [Fri, 9 Dec 2016 19:15:32 +0000 (19:15 +0000)]
[DWARF] Suppress .loc directives from CFI instructions
Like DBG_VALUE, these emit nothing to the .text section, and sometimes
have no source location specified. Just ignore them.
Differential Revision: http://reviews.llvm.org/D27492
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289256
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Matthias Braun [Fri, 9 Dec 2016 19:08:15 +0000 (19:08 +0000)]
Move .mir tests to appropriate directories
test/CodeGen/MIR should contain tests that intent to test the MIR
printing or parsing. Tests that test something else should be in
test/CodeGen/TargetName even when they are written in .mir.
As a rule of thumb, only tests using "llc -run-pass none" should be in
test/CodeGen/MIR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289254
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Matt Arsenault [Fri, 9 Dec 2016 17:57:43 +0000 (17:57 +0000)]
AMDGPU: Fix isTypeDesirableForOp for i16
This should do nothing for targets without i16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289235
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Simon Pilgrim [Fri, 9 Dec 2016 17:53:11 +0000 (17:53 +0000)]
[SelectionDAG] Add knownbits support for EXTRACT_VECTOR_ELT opcodes (REAPPLIED)
Reapplied with fix for PR31323 - X86 SSE2 vXi16 multiplies for illegal types were creating CONCAT_VECTORS nodes with vector inputs that might not total the number of elements in the result type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289232
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Matt Arsenault [Fri, 9 Dec 2016 17:49:14 +0000 (17:49 +0000)]
AMDGPU: Fix i128 mul
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289231
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Matt Arsenault [Fri, 9 Dec 2016 17:49:11 +0000 (17:49 +0000)]
AMDGPU: Allow TBA, TMA, TTMP* registers with SMEM instructions
Fixes assembler regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289230
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Matt Arsenault [Fri, 9 Dec 2016 17:49:08 +0000 (17:49 +0000)]
AMDGPU: Clean up instruction bits
Sort the instruction bits by type and make sure there is one
for each format.
Also cleanup namespaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289229
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Sean Fertile [Fri, 9 Dec 2016 17:21:42 +0000 (17:21 +0000)]
[PPC] Add intrinsics for vector extract word and vector insert word.
Revision: https://reviews.llvm.org/D26547
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289227
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Nirav Dave [Fri, 9 Dec 2016 17:18:24 +0000 (17:18 +0000)]
Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."
This reverts commit r289221 which appears to be triggering an assertion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289226
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Nirav Dave [Fri, 9 Dec 2016 16:15:12 +0000 (16:15 +0000)]
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Retrying after fixing overly aggressive load-store forwarding optimization.
Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search which only checks for parallel stores
through the chain subgraph. This is cleaner as the separation of
non-interfering loads/stores from the store-merging logic.
Whem merging stores, search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited. This improves the quality of the
output SelectionDAG and generally the output CodeGen (with some
exceptions).
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the the chain aggregation in the merged stores across
code paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seemed sufficient to not cause regressions in
tests.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable. Some tests relying on the order were changed to use
volatile memory operations
Noteworthy tests:
CodeGen/AArch64/argument-blocks.ll -
It's not entirely clear what the test_varargs_stackalign test is
supposed to be asserting, but the new code looks right.
CodeGen/AArch64/arm64-memset-inline.lli -
CodeGen/AArch64/arm64-stur.ll -
CodeGen/ARM/memset-inline.ll -
The backend now generates *worse* code due to store merging
succeeding, as we do do a 16-byte constant-zero store efficiently.
CodeGen/AArch64/merge-store.ll -
Improved, but there still seems to be an extraneous vector insert
from an element to itself?
CodeGen/PowerPC/ppc64-align-long-double.ll -
Worse code emitted in this case, due to the improved store->load
forwarding.
CodeGen/X86/dag-merge-fast-accesses.ll -
CodeGen/X86/MergeConsecutiveStores.ll -
CodeGen/X86/stores-merging.ll -
CodeGen/Mips/load-store-left-right.ll -
Restored correct merging of non-aligned stores
CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll -
Improved. Correctly merges buffer_store_dword calls
CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll -
Improved. Sidesteps loading a stored value and
merges two stores
CodeGen/X86/pr18023.ll -
This test has been removed, as it was asserting incorrect
behavior. Non-volatile stores *CAN* be moved past volatile loads,
and now are.
CodeGen/X86/vector-idiv.ll -
CodeGen/X86/vector-lzcnt-128.ll -
It's basically impossible to tell what these tests are actually
testing. But, looks like the code got better due to the memory
operations being recognized as non-aliasing.
CodeGen/X86/win32-eh.ll -
Both loads of the securitycookie are now merged.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
Subscribers: wdng, nhaehnle, nemanjai, arsenm, weimingz, niravd, RKSimon, aemerson, qcolombet, dsanders, resistor, tstellarAMD, t.p.northover, spatel
Differential Revision: https://reviews.llvm.org/D14834
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289221
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Simon Pilgrim [Fri, 9 Dec 2016 16:01:50 +0000 (16:01 +0000)]
Use SelectionDAG.getSplatBuildVector helper. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289220
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Tom Stellard [Fri, 9 Dec 2016 15:57:15 +0000 (15:57 +0000)]
AMDGPU/SI: Don't mark VINTRP instructions as mayLoad
Summary:
These instructions technically do read from memory, but the memory
is considered to be out of bounds for normal load/store instructions.
shader-db stats:
SGPRS:
1416075 ->
1413323 (-0.19 %)
VGPRS: 867413 -> 863935 (-0.40 %)
Spilled SGPRs: 1409 -> 1354 (-3.90 %)
Spilled VGPRs: 63 -> 63 (0.00 %)
Private memory VGPRs: 880 -> 880 (0.00 %)
Scratch size: 2648 -> 2632 (-0.60 %) dwords per thread
Code Size:
37889052 ->
37897340 (0.02 %) bytes
LDS: 2147 -> 2147 (0.00 %) blocks
Max Waves: 279243 -> 280369 (0.40 %)
Wait states: 0 -> 0 (0.00 %)
Reviewers: nhaehnle, mareko, arsenm
Subscribers: kzhuravl, wdng, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D27593
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289219
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Simon Pilgrim [Fri, 9 Dec 2016 15:23:41 +0000 (15:23 +0000)]
[SelectionDAG] Use SelectionDAG.getBuildVector helper. NFCI.
Makes interception of BUILD_VECTOR creation easier for debugging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289218
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Sanjoy Das [Fri, 9 Dec 2016 14:42:14 +0000 (14:42 +0000)]
[SCEVExpander] Remove \brief, reflow comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289216
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Sanjoy Das [Fri, 9 Dec 2016 14:42:11 +0000 (14:42 +0000)]
[SCEVExpander] Use llvm data structures; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289215
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Simon Pilgrim [Fri, 9 Dec 2016 14:27:52 +0000 (14:27 +0000)]
[SelectionDAG] Add additional checks to CONCAT_VECTORS creation
Part of the work for PR31323 - add extra asserts checking that the input vectors are of consistent type and result in the correct number of vector elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289214
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Benjamin Kramer [Fri, 9 Dec 2016 13:33:41 +0000 (13:33 +0000)]
Plug another leak in the DWARF unittests, DIEInlineStrings are never destroyed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289208
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Benjamin Kramer [Fri, 9 Dec 2016 13:12:30 +0000 (13:12 +0000)]
Fix memory leak in unit test.
The StringPool entries are destroyed with the allocator, the string pool
itself is not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289207
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NAKAMURA Takumi [Fri, 9 Dec 2016 11:44:57 +0000 (11:44 +0000)]
llvm/test/Object/archive-thin-create.test: Make sure that %t is empty to stabilize the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289202
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Dylan McKay [Fri, 9 Dec 2016 11:22:26 +0000 (11:22 +0000)]
[AVR] Remove a set of redundant tests
This fixes the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289201
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Simon Pilgrim [Fri, 9 Dec 2016 10:13:45 +0000 (10:13 +0000)]
[SelectionDAG] Add partial BITCAST support to computeKnownBits
Adds support for bitcasting a little endian 'small element' vector to 'large element' scalar/vector (e.g. v16i8 to v4i32 or v2i32 to i64), which is required for PR30845. We extract the knownbits for each 'small element' part and concatenate the results together.
We can add support for big endian and 'large element' scalar/vector to 'small element' vector bitcasting once we have test cases for them.
Differential Revision: https://reviews.llvm.org/D27129
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289200
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Malcolm Parsons [Fri, 9 Dec 2016 09:33:33 +0000 (09:33 +0000)]
Update Doxygen comment in StringSaver (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289196
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Daniel Jasper [Fri, 9 Dec 2016 09:04:51 +0000 (09:04 +0000)]
Revert "[SelectionDAG] Add knownbits support for EXTRACT_VECTOR_ELT opcodes"
This reverts commit r288916 as it is currently causing a crasher in
Halide. Reproducer on llvm.org/PR31323. While it might be that halide is
generating invalid IR, llc shouldn't crash.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289194
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Craig Topper [Fri, 9 Dec 2016 07:57:21 +0000 (07:57 +0000)]
[X86] Modify patterns from memory form of RCP/RSQRT/SQRT intrinsics to only allow (scalar_to_vector (loadf32/load64)) instead of anything that sse_load_f32/f64 can match.
sse_load_f32/f64 can also match loads that are zero extended to vectors. We shouldn't match that because we wouldn't be able to get the instruction to zero the upper bits like the intrinsic semantics would require for such a case.
There is a test case that does depend on this behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289193
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Dylan McKay [Fri, 9 Dec 2016 07:49:14 +0000 (07:49 +0000)]
[AVR] Use a more appropriate integer type for wide IN/OUT instructions
We could previously select an integer which would hit an assertion error
in pseudo expansion.
The new type will also generate the appropriate fixups if needed, which
wasn't done beforehand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289192
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Dylan McKay [Fri, 9 Dec 2016 07:49:04 +0000 (07:49 +0000)]
[AVR] Add tests for a large number of pseudo instructions
This adds MIR tests for 24 pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289191
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Craig Topper [Fri, 9 Dec 2016 06:42:28 +0000 (06:42 +0000)]
[AVX-512] Correctly preserve the passthru semantics of the FMA scalar intrinsics
Summary:
Scalar intrinsics have specific semantics about the which input's upper bits are passed through to the output. The same input is also supposed to be the input we use for the lower element when the mask bit is 0 in a masked operation. We aren't currently keeping these semantics with instruction selection.
This patch corrects this by introducing new scalar FMA ISD nodes that indicate whether operand 1(one of the multiply inputs) or operand 3(the additon/subtraction input) should pass thru its upper bits.
We use this information to select 213/132 form for the operand 1 version and the 231 form for the operand 3 version.
We also use this information to suppress combining FNEG operations on the passthru input since semantically the passthru bits aren't negated. This is stronger than the earlier check added for a user being SELECTS so we can remove that.
This fixes PR30913.
Reviewers: delena, zvi, v_klochkov
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D27144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289190
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Matt Arsenault [Fri, 9 Dec 2016 06:19:12 +0000 (06:19 +0000)]
AMDGPU: Select i16 instructions to VOP3 forms
These were selecting directly to the VOP2 form instead
of VOP3 like the i32 instructions. Fixes regressions in
future commits where an immediate isn't folded because it was
initially used for the second operand.
Because uniform 16-bit operations are promoted to i32, it's
difficult to get a simple testcase where this matters. Fold
failures in SIFoldOperands here tend to be hidden by commute
and fold in SIShrinkInstructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289189
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Peter Collingbourne [Fri, 9 Dec 2016 05:20:43 +0000 (05:20 +0000)]
Re-commit r289184, "Support: Use a 64-bit seek in raw_fd_ostream::seek()." with a configure-time check for lseek64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289187
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Craig Topper [Fri, 9 Dec 2016 05:20:11 +0000 (05:20 +0000)]
[X86] Add masked versions of VPERMT2* and VPERMI2* to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289186
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Peter Collingbourne [Fri, 9 Dec 2016 05:04:30 +0000 (05:04 +0000)]
Revert r289184, we need more configury for Darwin and *BSD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289185
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Peter Collingbourne [Fri, 9 Dec 2016 04:57:19 +0000 (04:57 +0000)]
Support: Use a 64-bit seek in raw_fd_ostream::seek().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289184
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Davide Italiano [Fri, 9 Dec 2016 03:49:20 +0000 (03:49 +0000)]
[SCCP] Make the test added in r289175 more meaningful.
Add a comment while here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289182
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Davide Italiano [Fri, 9 Dec 2016 03:08:42 +0000 (03:08 +0000)]
[SCCP] Teach the pass about `mul %x 0` even if %x is overdefined.
The motivating example is:
extern int patatino;
int goo() {
int x = 0;
for (int i = 0; i <
1000000; ++i) {
x *= patatino;
}
return x;
}
Currently SCCP will not realize that this function returns always zero,
therefore will try to unroll and vectorize the loop at -O3 producing an
awful lot of (useless) code. With this change, it will just produce:
0000000000000000 <g>:
xor %eax,%eax
retq
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289175
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Craig Topper [Fri, 9 Dec 2016 02:18:11 +0000 (02:18 +0000)]
[AVX-512] Add vpermilps/pd to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289173
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Craig Topper [Fri, 9 Dec 2016 02:18:07 +0000 (02:18 +0000)]
[AVX-512] Move some floating point stack folding test cases out of the integer test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289172
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Craig Topper [Fri, 9 Dec 2016 02:18:04 +0000 (02:18 +0000)]
[Analysis] Fix typo in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289171
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Kostya Serebryany [Fri, 9 Dec 2016 01:17:24 +0000 (01:17 +0000)]
[libFuzzer] implement crash-resistant merge (https://github.com/google/sanitizers/issues/722). This is a first experimental variant that needs some more testing, thus not yet adding a lit test (but there are unit tests).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289166
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Peter Collingbourne [Fri, 9 Dec 2016 01:10:11 +0000 (01:10 +0000)]
WholeProgramDevirt: Teach the pass to handle structs of arrays.
This will become necessary in some cases once D22296 lands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289165
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Chandler Carruth [Fri, 9 Dec 2016 00:46:44 +0000 (00:46 +0000)]
[LCG] Minor cleanup to the LCG walk over a function, NFC.
This just hoists the check for declarations up a layer which allows
various sets used in the walk to be smaller. Also moves the relevant
comments to match, and catches a few other cleanups in this code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289163
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Peter Collingbourne [Fri, 9 Dec 2016 00:33:27 +0000 (00:33 +0000)]
Make WholeProgramDevirt understand ConstStruct vtables.
Based on a patch by LemonBoy!
Differential Revision: https://reviews.llvm.org/D26581
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289162
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Chris Bieneman [Fri, 9 Dec 2016 00:26:44 +0000 (00:26 +0000)]
[ObjectYAML] Support for DWARF debug_aranges
This patch adds support for round tripping DWARF debug_aranges in and out of YAML.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289161
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Sanjay Patel [Thu, 8 Dec 2016 23:44:58 +0000 (23:44 +0000)]
[InstCombine] add tests for umin+icmp; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289157
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Sanjay Patel [Thu, 8 Dec 2016 23:36:57 +0000 (23:36 +0000)]
[InstCombine] add tests for umax+icmp; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289156
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Zia Ansari [Thu, 8 Dec 2016 23:27:40 +0000 (23:27 +0000)]
[InstSimplify] Add "X / 1.0" to SimplifyFDivInst.
Differential Revision: https://reviews.llvm.org/D27587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289153
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Sanjay Patel [Thu, 8 Dec 2016 23:16:06 +0000 (23:16 +0000)]
[InstCombine] add tests for smax+icmp; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289151
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Tim Northover [Thu, 8 Dec 2016 22:44:13 +0000 (22:44 +0000)]
GlobalISel: fall back gracefully for debug intrinsics.
Supporting them properly is a reasonably complex chunk of work, so to allow bot
testing before then we should at least be able to fall back to DAG ISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289150
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Tim Northover [Thu, 8 Dec 2016 22:44:00 +0000 (22:44 +0000)]
GlobalISel: factor overflow handling into separate function. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289149
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Davide Italiano [Thu, 8 Dec 2016 22:28:53 +0000 (22:28 +0000)]
[SCCP] Make sure SCCP and ConstantFolding agree on undef >> a.
Currently SCCP folds the value to -1, while ConstantProp folds to
0. This changes SCCP to do what ConstantFolding does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289147
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Simon Atanasyan [Thu, 8 Dec 2016 22:10:52 +0000 (22:10 +0000)]
[mips] Make the test case more specific and provide OS component of a triple. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289117
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Simon Atanasyan [Thu, 8 Dec 2016 22:10:48 +0000 (22:10 +0000)]
[mips] Change instruction s/daddiu/addiu/ since O32 prohibits the use of 64-bit GPRs. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289115
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Simon Atanasyan [Thu, 8 Dec 2016 22:10:44 +0000 (22:10 +0000)]
[mips] Change gnueabi to gnu in the triple because EABI has been removed recently. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289114
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Simon Atanasyan [Thu, 8 Dec 2016 22:10:38 +0000 (22:10 +0000)]
[mips] Remove N32 Android test because Android does not support N32 ABI. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289113
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Reid Kleckner [Thu, 8 Dec 2016 20:38:46 +0000 (20:38 +0000)]
Don't emit .seh_handler directives for any cleanup funclets
We were falsely claiming that we had an LSDA for the relevant EH
personality before this change, which could lead to the EH machinery
interpreting random adjacent data as an LSDA.
Fixes PR31317
This change is safe because cleanups can't contain exception handlers
today. We do these things to maintain that invariant:
- C++ destructors are naturally out-of-line
- __finally blocks are outlined in clang
- LLVM's inliner will not inline EH constructs into cleanups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289101
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Krzysztof Parzyszek [Thu, 8 Dec 2016 20:33:45 +0000 (20:33 +0000)]
[RDF] Fix incorrect lane mask calculation
This was exposed by some code that used more than one level of sub-
registers. There is no testcase, because there is no such code in the
Hexagon backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289099
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Sanjay Patel [Thu, 8 Dec 2016 20:23:56 +0000 (20:23 +0000)]
[InstSimplify] add fdiv x/1.0 test and update checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289098
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Matt Arsenault [Thu, 8 Dec 2016 20:14:46 +0000 (20:14 +0000)]
AMDGPU: Make f16 ConstantFP legal
Not having this legal led to combine failures, resulting
in dumb things like bitcasts of constants not being folded
away.
The only reason I'm leaving the v_mov_b32 hack that f32
already uses is to avoid madak formation test regressions.
PeepholeOptimizer has an ordering issue where the immediate
fold attempt is into the sgpr->vgpr copy instead of the actual
use. Running it twice avoids that problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289096
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Stanislav Mekhanoshin [Thu, 8 Dec 2016 20:07:23 +0000 (20:07 +0000)]
[AMDGPU] Fix number of reserved SGPRs on CI to reflect flat scratch use
Differential Revision: https://reviews.llvm.org/D27225
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289095
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Matt Arsenault [Thu, 8 Dec 2016 19:52:38 +0000 (19:52 +0000)]
AMDGPU: Fix commuting v_sub_u16
The correct commutable opcode was set to itself, so this
was simply swapping the operands to commute instead of also
changing the opcode to v_subrev_u16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289093
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Stanislav Mekhanoshin [Thu, 8 Dec 2016 19:46:04 +0000 (19:46 +0000)]
[AMDGPU] Add amdgpu-unify-metadata pass
Multiple metadata values for records such as opencl.ocl.version, llvm.ident
and similar are created after linking several modules. For some of them, notably
opencl.ocl.version, this creates semantic problem because we cannot tell which
version of OpenCL the composite module conforms.
Moreover, such repetitions of identical values often create a huge list of
unneeded metadata, which grows bitcode size both in memory and stored on disk.
It can go up to several Mb when linked against our OpenCL library. Lastly, such
long lists obscure reading of dumped IR.
The pass unifies metadata after linking.
Differential Revision: https://reviews.llvm.org/D25381
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289092
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Peter Collingbourne [Thu, 8 Dec 2016 19:01:00 +0000 (19:01 +0000)]
IR, X86: Understand !absolute_symbol metadata on global variables.
Summary:
Attaching !absolute_symbol to a global variable does two things:
1) Marks it as an absolute symbol reference.
2) Specifies the value range of that symbol's address.
Teach the X86 backend to allow absolute symbols to appear in place of
immediates by extending the relocImm and mov64imm32 matchers. Start using
relocImm in more places where it is legal.
As previously proposed on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2016-October/105800.html
Differential Revision: https://reviews.llvm.org/D25878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289087
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Chris Bieneman [Thu, 8 Dec 2016 17:46:57 +0000 (17:46 +0000)]
[ObjectYAML] Remove DWARF from class names
Since all the DWARF classes are in a DWARFYAML namespace having every class start with DWARF seems like a bit of overkill.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289080
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Alexander Timofeev [Thu, 8 Dec 2016 17:28:47 +0000 (17:28 +0000)]
[AMDGPU] Scalarization of global uniform loads.
Summary:
LC can currently select scalar load for uniform memory access
basing on readonly memory address space only. This restriction
originated from the fact that in HW prior to VI vector and scalar caches
are not coherent. With MemoryDependenceAnalysis we can check that the
memory location corresponding to the memory operand of the LOAD is not
clobbered along the all paths from the function entry.
Reviewers: rampitec, tstellarAMD, arsenm
Subscribers: wdng, arsenm, nhaehnle
Differential Revision: https://reviews.llvm.org/D26917
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289076
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Keno Fischer [Thu, 8 Dec 2016 17:22:35 +0000 (17:22 +0000)]
ConstantFolding: Don't crash when encountering vector GEP
ConstantFolding tried to cast one of the scalar indices to a vector
type. Instead, use the vector type only for the first index (which
is the only one allowed to be a vector) and use its scalar type
otherwise.
Fixes PR31250.
Reviewers: majnemer
Differential Revision: https://reviews.llvm.org/D27389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289073
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Greg Clayton [Thu, 8 Dec 2016 16:57:04 +0000 (16:57 +0000)]
Fix ASAN buildbots by fixing a double free crash.
The dwarfgen::Generator::StringPool was in a unique_ptr but it was owned by the Allocator member variable so it was being free twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289070
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NAKAMURA Takumi [Thu, 8 Dec 2016 15:28:02 +0000 (15:28 +0000)]
Prune unused libdeps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289060
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NAKAMURA Takumi [Thu, 8 Dec 2016 15:00:12 +0000 (15:00 +0000)]
Prune unused \param(s) in r289050. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289057
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NAKAMURA Takumi [Thu, 8 Dec 2016 15:00:07 +0000 (15:00 +0000)]
DIE::addAttribute(): Prune a redundant \param. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289056
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NAKAMURA Takumi [Thu, 8 Dec 2016 14:26:30 +0000 (14:26 +0000)]
LanaiInstPrinter: Prune unused libdeps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289054
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NAKAMURA Takumi [Thu, 8 Dec 2016 14:26:23 +0000 (14:26 +0000)]
DebugInfoDWARFTests: Prune unused libdeps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289053
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NAKAMURA Takumi [Thu, 8 Dec 2016 14:11:02 +0000 (14:11 +0000)]
DebugInfoDWARFTests: Add missing deps, AsmPrinter and Object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289052
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NAKAMURA Takumi [Thu, 8 Dec 2016 14:10:57 +0000 (14:10 +0000)]
DebugInfoDWARFTests: Reorder LLVM_LINK_COMPONENTS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289051
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Nicolai Haehnle [Thu, 8 Dec 2016 14:08:14 +0000 (14:08 +0000)]
[SelectionDAG] Add expansion and promotion of [US]MUL_LOHI
Summary:
Most targets set the action for these nodes to Expand even though there
isn't actually any code for them in ExpandNode. Instead, targets simply
relied on the fact that no code generates these nodes as long as the
nodes aren't legal or custom.
However, generating these nodes can be useful e.g. for divide-by-constant
in wider integer types.
Expand of [US]MUL_LOHI will use MULH[US] when legal or custom, and
a sequence of half-width multiplications otherwise. Promote uses a wider
multiply.
This patch intends to not change the generated code, but indirect effects
are possible since expansions/promotions that were previously done in
DAGCombine may now be done in LegalizeDAG.
See D24822 for a change that actually uses the new expansion.
Reviewers: spatel, bkramer, venkatra, efriedma, hfinkel, ast, nadav, tstellarAMD
Subscribers: arsenm, jyknight, nemanjai, wdng, nhaehnle, llvm-commits
Differential Revision: https://reviews.llvm.org/D24956
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289050
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Nicolai Haehnle [Thu, 8 Dec 2016 14:08:08 +0000 (14:08 +0000)]
X86: Add checks for fma_patterns[_wide].ll with -enable-no-infs-fp-math
This re-adds checks for the patterns that were disabled with r288506.
Reviewers: spatel, delena, craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D27346
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289049
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Nicolai Haehnle [Thu, 8 Dec 2016 14:08:02 +0000 (14:08 +0000)]
AMDGPU: Properly implement SIRegisterInfo::isFrameOffsetLegal and needsFrameBaseReg
Summary:
Without the fix to isFrameOffsetLegal to consider the instruction's
immediate offset, the new test case hits the corresponding assertion in
resolveFrameIndex, because the LocalStackSlotAllocation pass re-uses a
different base register.
With only the fix to isFrameOffsetLegal, code quality reduces in a bunch of
places because frame base registers are added where they're not needed.
This is addressed by properly implementing needsFrameBaseReg, which also
helps to avoid unnecessary zero frame indices in a bunch of other places.
Fixes piglit glsl-1.50/execution/variable-indexing/gs-output-array-vec4-index-wr.shader_test
Reviewers: arsenm, tstellarAMD
Subscribers: qcolombet, kzhuravl, wdng, yaxunl, tony-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D27344
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289048
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Daniel Jasper [Thu, 8 Dec 2016 12:45:29 +0000 (12:45 +0000)]
Move DwarfGenerator.cpp to unittests
So far it creates a test helper and so it should be moved there. It also
create a layering cycle between CodeGen and CodeGen/AsmPrinter, which
should be avoided.
Review: https://reviews.llvm.org/D27570
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289044
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Alexey Bataev [Thu, 8 Dec 2016 11:57:51 +0000 (11:57 +0000)]
[SLP] Fix for PR6246: vectorization for scalar ops on vector elements.
When trying to vectorize trees that start at insertelement instructions
function tryToVectorizeList() uses vectorization factor calculated as
MinVecRegSize/ScalarTypeSize. But sometimes it does not work as tree
cost for this fixed vectorization factor is too high.
Patch tries to improve the situation. It tries different vectorization
factors from max(PowerOf2Floor(NumberOfVectorizedValues),
MinVecRegSize/ScalarTypeSize) to MinVecRegSize/ScalarTypeSize and tries
to choose the best one.
Differential Revision: https://reviews.llvm.org/D27215
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289043
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Pavel Labath [Thu, 8 Dec 2016 11:45:38 +0000 (11:45 +0000)]
Fix MSCV compilation broken by r289040
I wanted to use the "not" keyword to make sure it does not get lost in between
other checks. MSVC does not like that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289041
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Pavel Labath [Thu, 8 Dec 2016 11:31:19 +0000 (11:31 +0000)]
Improve format member detection in llvm::formatv
Summary:
The existing detection of a format member function has a couple of deficiencies:
- the member function does not get detected if one calls formatv with an lvalue,
because the template parameter gets deduced as T&, which fails the is_class
check.
- it also did not work if the function was called with a const variable because
the template parameter would get deduced as const T&, again failing the
is_class check.
This fixes the problem by stripping the references in the uses_format_member
template, to make sure the type is correctly detected as class. It also provides
specializations of the has_FormatMember template for const and non-const members
of the types in order to enable declaring the format member as a "const"
function. I have added tests that verify that formatv can be now called in these
scenarios. As some scenarios could not be verified at runtime (e.g. making sure
that calling a non-const format member on a const object does *not* compile), I
have also added some static_asserts which test the behaviour of the template
classes used internally by formatv().
Reviewers: zturner
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D27525
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289040
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Dylan McKay [Thu, 8 Dec 2016 10:52:13 +0000 (10:52 +0000)]
[AVR] Add MIR tests for pseudo instruction expansions
This adds tests for 13 pseudo instruction expansions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289039
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Simon Pilgrim [Thu, 8 Dec 2016 10:41:41 +0000 (10:41 +0000)]
Wdocumentation fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289038
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Simon Pilgrim [Thu, 8 Dec 2016 10:31:32 +0000 (10:31 +0000)]
Wdocumentation fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289037
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Oliver Stannard [Thu, 8 Dec 2016 10:31:21 +0000 (10:31 +0000)]
Add a comment consumer mechanism to MCAsmLexer
This allows clients to register an AsmCommentConsumer with the MCAsmLexer,
which receives a callback each time a comment is parsed.
Differential Revision: https://reviews.llvm.org/D27511
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289036
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Simon Pilgrim [Thu, 8 Dec 2016 10:17:25 +0000 (10:17 +0000)]
[X86][SSE] Add vector test for (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2) detailed in D19325
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289035
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Dylan McKay [Thu, 8 Dec 2016 08:54:41 +0000 (08:54 +0000)]
[AVR] Add MIR tests for a few pseudo instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289031
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Dylan McKay [Thu, 8 Dec 2016 08:34:13 +0000 (08:34 +0000)]
[AVR] Add an assertion to ensure we don't emit LPM when it's unsupported
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289030
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Peter Collingbourne [Thu, 8 Dec 2016 05:28:30 +0000 (05:28 +0000)]
LTO: Hash the parts of the LTO configuration that affect code generation.
Most importantly, we need to hash the relocation model, otherwise we can
end up trying to link non-PIC object files into PIEs or DSOs.
Differential Revision: https://reviews.llvm.org/D27556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289024
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Greg Clayton [Thu, 8 Dec 2016 02:11:03 +0000 (02:11 +0000)]
Unbreak buildbots where the debug info test was crashing due to unchecked error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289017
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Keno Fischer [Thu, 8 Dec 2016 01:56:23 +0000 (01:56 +0000)]
Revert "[CodeGen] Fix invalid DWARF info on Win64"
Appears to break on build bots. Reverting pending investigation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289014
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Keno Fischer [Thu, 8 Dec 2016 01:40:21 +0000 (01:40 +0000)]
[CodeGen] Fix invalid DWARF info on Win64
The relocations for `DIEEntry::EmitValue` were wrong for Win64
(emitting FK_Data_4 instead of FK_SecRel_4). This corrects that
oversight so that the DWARF data is correct in Win64 COFF files.
Fixes PR15393.
Patch by Jameson Nash <jameson@juliacomputing.com> based on a patch
by David Majnemer.
Differential Revision: https://reviews.llvm.org/D21731
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289013
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Greg Clayton [Thu, 8 Dec 2016 01:03:48 +0000 (01:03 +0000)]
Make a DWARF generator so we can unit test DWARF APIs with gtest.
The only tests we have for the DWARF parser are the tests that use llvm-dwarfdump and expect output from textual dumps.
More DWARF parser modification are coming in the next few weeks and I wanted to add tests that can verify that we can encode and decode all form types, as well as test some other basic DWARF APIs where we ask DIE objects for their children and siblings.
DwarfGenerator.cpp was added in the lib/CodeGen directory. This file contains the code necessary to easily create DWARF for tests:
dwarfgen::Generator DG;
Triple Triple("x86_64--");
bool success = DG.init(Triple, Version);
if (!success)
return;
dwarfgen::CompileUnit &CU = DG.addCompileUnit();
dwarfgen::DIE CUDie = CU.getUnitDIE();
CUDie.addAttribute(DW_AT_name, DW_FORM_strp, "/tmp/main.c");
CUDie.addAttribute(DW_AT_language, DW_FORM_data2, DW_LANG_C);
dwarfgen::DIE SubprogramDie = CUDie.addChild(DW_TAG_subprogram);
SubprogramDie.addAttribute(DW_AT_name, DW_FORM_strp, "main");
SubprogramDie.addAttribute(DW_AT_low_pc, DW_FORM_addr, 0x1000U);
SubprogramDie.addAttribute(DW_AT_high_pc, DW_FORM_addr, 0x2000U);
dwarfgen::DIE IntDie = CUDie.addChild(DW_TAG_base_type);
IntDie.addAttribute(DW_AT_name, DW_FORM_strp, "int");
IntDie.addAttribute(DW_AT_encoding, DW_FORM_data1, DW_ATE_signed);
IntDie.addAttribute(DW_AT_byte_size, DW_FORM_data1, 4);
dwarfgen::DIE ArgcDie = SubprogramDie.addChild(DW_TAG_formal_parameter);
ArgcDie.addAttribute(DW_AT_name, DW_FORM_strp, "argc");
// ArgcDie.addAttribute(DW_AT_type, DW_FORM_ref4, IntDie);
ArgcDie.addAttribute(DW_AT_type, DW_FORM_ref_addr, IntDie);
StringRef FileBytes = DG.generate();
MemoryBufferRef FileBuffer(FileBytes, "dwarf");
auto Obj = object::ObjectFile::createObjectFile(FileBuffer);
EXPECT_TRUE((bool)Obj);
DWARFContextInMemory DwarfContext(*Obj.get());
This code is backed by the AsmPrinter code that emits DWARF for the actual compiler.
While adding unit tests it was discovered that DIEValue that used DIEEntry as their values had bugs where DW_FORM_ref1, DW_FORM_ref2, DW_FORM_ref8, and DW_FORM_ref_udata forms were not supported. These are all now supported. Added support for DW_FORM_string so we can emit inlined C strings.
Centralized the code to unique abbreviations into a new DIEAbbrevSet class and made both the dwarfgen::Generator and the llvm::DwarfFile classes use the new class.
Fixed comments in the llvm::DIE class so that the Offset is known to be the compile/type unit offset.
DIEInteger now supports more DW_FORM values.
There are also unit tests that cover:
Encoding and decoding all form types and values
Encoding and decoding all reference types (DW_FORM_ref1, DW_FORM_ref2, DW_FORM_ref4, DW_FORM_ref8, DW_FORM_ref_udata, DW_FORM_ref_addr) including cross compile unit references with that go forward one compile unit and backward on compile unit.
Differential Revision: https://reviews.llvm.org/D27326
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289010
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Evgeniy Stepanov [Thu, 8 Dec 2016 00:32:26 +0000 (00:32 +0000)]
CFI-icall on Thumb
Replace @progbits in the section directive with %progbits, because "@" starts a comment on arm/thumb.
Use b.w branch instruction.
Use .thumb_function and .thumb_set for proper arm/thumb interwork. This way jumptable entry addresses on thumb have bit 0 set (correctly). This does not affect CFI check math, because the address of the jumptable start also has that bit set.
This does not work on thumbv5, because it does not support b.w, and the linker would not insert a veneer (trampoline?) to extend the range of b.n. We may need to do full-range plt-style jumptables on thumbv54, which are 12 bytes per entry. Another option is "push lr; bl; pop pc" (4 bytes) but that needs unwinding instructions, etc.
Differential Revision: https://reviews.llvm.org/D27499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289008
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Peter Collingbourne [Thu, 8 Dec 2016 00:27:37 +0000 (00:27 +0000)]
LTO: Remove the unused Config::Features field.
We are currently initializing Features via MAttrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289007
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Matthias Braun [Thu, 8 Dec 2016 00:16:42 +0000 (00:16 +0000)]
The few days mentioned in r267095 are over
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289004
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Matthias Braun [Thu, 8 Dec 2016 00:16:08 +0000 (00:16 +0000)]
TargetPassConfig: Rename DisablePostRA -> DisablePostRASched; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289003
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Matthias Braun [Thu, 8 Dec 2016 00:15:51 +0000 (00:15 +0000)]
LivePhysReg: Use reference instead of pointer in init(); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289002
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Quentin Colombet [Thu, 8 Dec 2016 00:06:51 +0000 (00:06 +0000)]
[InlineSpiller] Don't call TargetInstrInfo::foldMemoryOperand with an empty list.
Since r287792 if we try to do that we will hit an assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289001
91177308-0d34-0410-b5e6-
96231b3b80d8