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Craig Topper [Sun, 22 Apr 2018 00:52:02 +0000 (00:52 +0000)]
[X86] Remove DATA32_PREFIX. Hack the printing for DATA16_PREFIX to print 'data32' in 16-bit mode. Hack the asm parser to convert 'data32' to 'data16' in 16-bit mode.
Improve the error messages to match GNU assembler.
This also allows us to remove the hack from the disassembler table building.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330531
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Brian Gesiak [Sat, 21 Apr 2018 23:52:04 +0000 (23:52 +0000)]
[bcanalyzer] Recognize more stream types
Summary:
`llvm-bcanalyzer` prints out the stream type of the file it is
analyzing. If the file begins with the LLVM IR magic number, it reports
a stream type of "LLVM IR". However, any other bitstream format is
reported as "unknown".
Add some checks for two other common bitstream formats: Clang AST
files, which begin with 'CPCH', and Clang serialized diagnostics, which
begin with 'DIAG'.
Test Plan: `check-llvm`
Reviewers: pcc, aprantl, mehdi_amini, davide, george.karpenkov, JDevlieghere
Reviewed By: JDevlieghere
Subscribers: JDevlieghere, bruno, davide, llvm-commits
Differential Revision: https://reviews.llvm.org/D41979
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330529
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Simon Pilgrim [Sat, 21 Apr 2018 21:59:36 +0000 (21:59 +0000)]
[X86] Strip unnecessary prefetch + vector move/load instrw overrides from scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330527
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Jonas Devlieghere [Sat, 21 Apr 2018 21:36:11 +0000 (21:36 +0000)]
[Support] Add optional prefix to convenience helpers in WithColor.
Several tools prefix the error/warning/note output with the name of the
tool. One such tool is LLD for example. This commit adds as an optional
'Prefix' argument to the convenience helpers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330526
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Simon Pilgrim [Sat, 21 Apr 2018 21:16:44 +0000 (21:16 +0000)]
[X86] Strip unnecessary WriteCvtF2I instrw overrides from scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330525
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Jonas Devlieghere [Sat, 21 Apr 2018 21:11:59 +0000 (21:11 +0000)]
[tools] Use WithColor for printing errors.
Use convenience helpers in WithColor to print errors, warnings and notes
in a few more tools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330524
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Simon Pilgrim [Sat, 21 Apr 2018 20:45:12 +0000 (20:45 +0000)]
[X86] Strip unnecessary broadcast/shuffle256 instrw overrides from scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330523
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Simon Pilgrim [Sat, 21 Apr 2018 20:04:24 +0000 (20:04 +0000)]
[X86][AVX] VPERM2F128/VINSERTF128 should be a shuffle256 schedule like VPERM2I128/VINSERTI128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330522
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Simon Pilgrim [Sat, 21 Apr 2018 19:11:55 +0000 (19:11 +0000)]
[X86] Strip unnecessary vector integer math, shift-imm, extend, shuffle, pack/unpack instruction instrw overrides from scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330521
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Craig Topper [Sat, 21 Apr 2018 18:39:21 +0000 (18:39 +0000)]
[X86] Add DAG combine to turn (trunc (srl (mul ext, ext), 16) into PMULHW/PMULHUW.
Ultimately I want to use this to remove the intrinsics for these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330520
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Craig Topper [Sat, 21 Apr 2018 18:39:20 +0000 (18:39 +0000)]
[X86] Add test cases that show the current codegen for (trunc (srl (mul ext, ext), 16)). NFC
A future patch will turn this into MULHU/MULHS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330519
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Craig Topper [Sat, 21 Apr 2018 18:07:36 +0000 (18:07 +0000)]
[X86] Add SchedWrites for LDMXCSR/STMXCSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330517
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Sanjay Patel [Sat, 21 Apr 2018 16:58:00 +0000 (16:58 +0000)]
[InstSimplify] move tests for shifts; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330516
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Sanjay Patel [Sat, 21 Apr 2018 16:23:47 +0000 (16:23 +0000)]
[InstSimplify] move/add/regenerate checks for tests; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330515
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Simon Pilgrim [Sat, 21 Apr 2018 16:20:28 +0000 (16:20 +0000)]
[X86][Haswell] Strip unnecessary WriteFAdd/WriteFHAdd instruction instrw overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330514
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Simon Pilgrim [Sat, 21 Apr 2018 16:17:47 +0000 (16:17 +0000)]
[X86][Broadwell] Remove unnecessary VORPD/VORPS instrw override - missed in D45629
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330513
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Simon Pilgrim [Sat, 21 Apr 2018 16:12:42 +0000 (16:12 +0000)]
[llvm-mca][X86] Add AVX2 resource tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330512
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Simon Pilgrim [Sat, 21 Apr 2018 15:16:59 +0000 (15:16 +0000)]
[X86] Strip unnecessary WriteFRcp/WriteFRsqrt instruction instrw overrides from scheduler models.
The required the default skylake schedules to be updated - these were being completely overriden by the InstRW and the existing values not used at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330510
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Simon Pilgrim [Sat, 21 Apr 2018 14:56:56 +0000 (14:56 +0000)]
[X86] Strip unnecessary WriteFShuffle instruction instrw overrides from scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330508
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Simon Pilgrim [Sat, 21 Apr 2018 14:16:57 +0000 (14:16 +0000)]
[llvm-mca][X86] Add SSE resource tests to all models
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330506
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Simon Pilgrim [Sat, 21 Apr 2018 14:03:40 +0000 (14:03 +0000)]
[X86][SandyBridge] Strip unnecessary MOVQ/CVT instruction instrw overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330505
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Simon Pilgrim [Sat, 21 Apr 2018 12:15:42 +0000 (12:15 +0000)]
[X86] Strip unnecessary MMX instruction instrw overrides from scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330503
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Simon Pilgrim [Sat, 21 Apr 2018 11:28:59 +0000 (11:28 +0000)]
[llvm-mca][X86] Add MMX resource tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330502
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Simon Pilgrim [Sat, 21 Apr 2018 11:25:02 +0000 (11:25 +0000)]
[X86] Strip unnecessary x87 instruction instrw overrides from scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330501
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Simon Pilgrim [Sat, 21 Apr 2018 10:36:19 +0000 (10:36 +0000)]
[llvm-mca][X86] Add X87 resource tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330499
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Simon Pilgrim [Sat, 21 Apr 2018 10:35:04 +0000 (10:35 +0000)]
[X86][X87] Add missing fldlg2 schedule test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330498
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Hiroshi Inoue [Sat, 21 Apr 2018 09:32:17 +0000 (09:32 +0000)]
[PowerPC] fix incorrect vectorization of abs() on POWER9
Vectorized loops with abs() returns incorrect results on POWER9. This patch fixes it.
For example the following code returns negative result if input values are negative though it sums up the absolute value of the inputs.
int vpx_satd_c(const int16_t *coeff, int length) {
int satd = 0;
for (int i = 0; i < length; ++i) satd += abs(coeff[i]);
return satd;
}
This problem causes test failures for libvpx.
For vector absolute and vector absolute difference on POWER9, LLVM generates VABSDUW (Vector Absolute Difference Unsigned Word) instruction or variants.
Since these instructions are for unsigned integers, we need adjustment for signed integers.
For abs(sub(a, b)), we generate VABSDUW(a+0x80000000, b+0x80000000). Otherwise, abs(sub(-1, 0)) returns 0xFFFFFFFF(=-1) instead of 1. For abs(a), we generate VABSDUW(a+0x80000000, 0x80000000).
Differential Revision: https://reviews.llvm.org/D45522
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330497
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Eli Friedman [Sat, 21 Apr 2018 00:07:46 +0000 (00:07 +0000)]
[AArch64] Don't crash trying to resolve __stack_chk_guard.
In certain cases, the compiler might try to merge __stack_chk_guard with
another global variable. (Or someone could theoretically define
__stack_chk_guard as an alias.) In that case, make sure we don't crash.
Differential Revision: https://reviews.llvm.org/D45746
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330495
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Jessica Paquette [Fri, 20 Apr 2018 23:37:48 +0000 (23:37 +0000)]
Fix typo in test (verify-machine-instrs -> verify-machineinstrs)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330494
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Jessica Paquette [Fri, 20 Apr 2018 23:35:54 +0000 (23:35 +0000)]
[MachineOutliner] XFAIL machine-outliner-noredzone.ll
The verifier began complaining about an undefined physical register in this
test. XFAILing for the purposes of getting a bot up while I look into it.
Failure:
http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-expensive/11385/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330493
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Shoaib Meenai [Fri, 20 Apr 2018 22:14:45 +0000 (22:14 +0000)]
[ObjCARC] Take BlockColors by const reference. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330489
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Shoaib Meenai [Fri, 20 Apr 2018 22:11:03 +0000 (22:11 +0000)]
[ObjCARC] Account for funclet token in storeStrong transform
When creating a call to storeStrong in ObjCARCContract, ensure the call
gets the correct funclet token, otherwise WinEHPrepare will turn the
call (and all subsequent instructions) into unreachable.
We already have logic to do this for the ARC autorelease elision marker;
factor that out into a common function that's used for both. These are
the only two places in this transform that create call instructions.
Differential Revision: https://reviews.llvm.org/D45857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330487
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Simon Pilgrim [Fri, 20 Apr 2018 22:04:11 +0000 (22:04 +0000)]
[llvm-mca][X86] Add MMX/SSE/AES/CLMUL resource SandyBridge tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330486
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Simon Pilgrim [Fri, 20 Apr 2018 21:16:05 +0000 (21:16 +0000)]
[X86] Add WriteFSign/WriteFLogic scheduler classes
Split the fp and integer vector logical instruction scheduler classes - older CPUs especially often handled these on different pipes.
This unearthed a couple of things that are also handled in this patch:
(1) We were tagging avx512 fp logic ops as WriteFAdd, probably because of the lack of WriteFLogic
(2) SandyBridge had integer logic ops only using Port5, when afaict they can use Ports015.
(3) Cleaned up x86 FCHS/FABS scheduling as they are typically treated as fp logic ops.
Differential Revision: https://reviews.llvm.org/D45629
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330480
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Alexander Shaposhnikov [Fri, 20 Apr 2018 20:46:04 +0000 (20:46 +0000)]
[llvm-objcopy] Fix sh_link
This diff fixes sh_link for various types of sections
(i.e. for SHT_ARM_EXIDX, SHT_HASH). In particular, this change enables us
to use llvm-objcopy with clang -gsplit-dwarf for the target android-arm.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D45851
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330478
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Alex Shlyapnikov [Fri, 20 Apr 2018 20:04:04 +0000 (20:04 +0000)]
[HWASan] Introduce non-zero based and dynamic shadow memory (LLVM).
Summary:
Support the dynamic shadow memory offset (the default case for user
space now) and static non-zero shadow memory offset
(-hwasan-mapping-offset option). Keeping the the latter case around
for functionality and performance comparison tests (and mostly for
-hwasan-mapping-offset=0 case).
The implementation is stripped down ASan one, picking only the relevant
parts in the following assumptions: shadow scale is fixed, the shadow
memory is dynamic, it is accessed via ifunc global, shadow memory address
rematerialization is suppressed.
Keep zero-based shadow memory for kernel (-hwasan-kernel option) and
calls instreumented case (-hwasan-instrument-with-calls option), which
essentially means that the generated code is not changed in these cases.
Reviewers: eugenis
Subscribers: srhines, llvm-commits
Differential Revision: https://reviews.llvm.org/D45840
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330475
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Sean Fertile [Fri, 20 Apr 2018 19:56:26 +0000 (19:56 +0000)]
[PartialInlining] Fix Crash from holding a reference to a destructed ORE.
The callback used to create an ORE for the legacy PI pass caches the allocated
object in a unique_ptr in the runOnModule function, and returns a reference to
that object. Under certian circumstances we can end up holding onto that
reference after the OREs destruction. Rather then allowing the new and legacy
passes to create ORE object in diffrent ways, create the ORE at the point of
use.
Differential Revision: https://reviews.llvm.org/D43219
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330473
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Krzysztof Parzyszek [Fri, 20 Apr 2018 19:45:49 +0000 (19:45 +0000)]
[Hexagon] hexagon-autohvx was left on again
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330472
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Krzysztof Parzyszek [Fri, 20 Apr 2018 19:38:37 +0000 (19:38 +0000)]
[Hexagon] Improve HVX instruction selection (bitcast, vsplat)
There was some unfortunate interaction between VSPLAT and BITCAST
related to the selection of constant vectors (coming from selecting
shuffles). Introduce VSPLATW that always splats a 32-bit word, and
can have arbitrary result type (to avoid BITCASTs of VSPLAT).
Clean up the previous selection of BITCAST/VSPLAT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330471
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Eric Christopher [Fri, 20 Apr 2018 19:07:57 +0000 (19:07 +0000)]
Remove unused argument from emitModuleMetadata.
NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330470
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Krzysztof Parzyszek [Fri, 20 Apr 2018 19:06:46 +0000 (19:06 +0000)]
[Hexagon] Skip fixed-stack indexes in HexagonConstExtenders
Fixed slots have negative values, and TRI::stackSlot2Index and
TRI::index2StackSlot do not handle negative numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330468
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Craig Topper [Fri, 20 Apr 2018 18:55:40 +0000 (18:55 +0000)]
[X86][SandyBridge] Remove duplciate InstRWs from Sandy Brige scheduler model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330465
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Gabor Buella [Fri, 20 Apr 2018 18:42:47 +0000 (18:42 +0000)]
[X86] WaitPKG instructions
Three new instructions:
umonitor - Sets up a linear address range to be
monitored by hardware and activates the monitor.
The address range should be a writeback memory
caching type.
umwait - A hint that allows the processor to
stop instruction execution and enter an
implementation-dependent optimized state
until occurrence of a class of events.
tpause - Directs the processor to enter an
implementation-dependent optimized state
until the TSC reaches the value in EDX:EAX.
Also modifying the description of the mfence
instruction, as the rep prefix (0xF3) was allowed
before, which would conflict with umonitor during
disassembly.
Before:
$ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble
.text
mfence
After:
$ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble
.text
umonitor %rax
Reviewers: craig.topper, zvi
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D45253
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330462
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Jessica Paquette [Fri, 20 Apr 2018 18:03:21 +0000 (18:03 +0000)]
[MachineOutliner] Change B instruction for tail calls to TCRETURNdi
First off, this is more correct than having the B. Second off, this was making
a bot upset. This fixes that.
Update the test to include -verify-machineinstrs as well to prevent stuff like
this slipping by non debug/assert builds in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330459
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Zachary Turner [Fri, 20 Apr 2018 18:00:46 +0000 (18:00 +0000)]
[LLD/PDB] Emit first section contribution for DBI Module Descriptor.
Part of the DBI stream is a list of variable length structures
describing each module that contributes to the final executable.
One member of this structure is a section contribution entry that
describes the first section contribution in the output file for
the given module.
We have been leaving this structure unpopulated until now, so with
this patch it is now filled out correctly.
Differential Revision: https://reviews.llvm.org/D45832
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330457
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Nico Weber [Fri, 20 Apr 2018 17:21:10 +0000 (17:21 +0000)]
Remove llvm-build's --configure-target-def-file.
It was added 6.5 years ago in r144345, but was never hooked up and has been
unused since. If _you_ do use this, feel free to revert, but add a comment
on where it's used.
https://reviews.llvm.org/D45262
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330455
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Sanjay Patel [Fri, 20 Apr 2018 17:16:23 +0000 (17:16 +0000)]
[utils] improve AArch64 asm parser
If we don't mark the cfi line as optional, the script won't
work with 'nounwind' code. Without that attr, there may be
extra noise in the asm body that we don't want to see.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330453
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Nicholas Wilson [Fri, 20 Apr 2018 17:07:24 +0000 (17:07 +0000)]
[WebAssembly] Distinguish debug/symbol names in the Wasm structs. NFC
Differential Revision: https://reviews.llvm.org/D45021
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330448
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Michael Zolotukhin [Fri, 20 Apr 2018 16:57:10 +0000 (16:57 +0000)]
Revert r330431.
There are still stage3/stage4 miscompares :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330446
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Sanjay Patel [Fri, 20 Apr 2018 16:46:58 +0000 (16:46 +0000)]
[x86] auto-generate checks; NFC
There's a proposal to change/add to this file in D45653,
so we should know exactly what those differences would be.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330445
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Florian Hahn [Fri, 20 Apr 2018 16:37:13 +0000 (16:37 +0000)]
[NewGVN] Split OpPHI detection and creation.
It also adds a check making sure PHIs for operands are all in the same
block.
Patch by Daniel Berlin <dberlin@dberlin.org>
Reviewers: dberlin, davide
Differential Revision: https://reviews.llvm.org/D43865
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330444
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Andrew Ng [Fri, 20 Apr 2018 15:29:47 +0000 (15:29 +0000)]
[DebugInfo] Use WithColor for more debug line warnings
Updated two more debug line related warnings to use WithColor. This was
necessary to ensure consistent output order of the warnings on Windows
for debug line tests.
Differential Revision: https://reviews.llvm.org/D45871
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330440
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Simon Pilgrim [Fri, 20 Apr 2018 15:26:59 +0000 (15:26 +0000)]
[CostModel][X86] Add vector element insert/extract cost tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330439
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Douglas Yung [Fri, 20 Apr 2018 15:23:57 +0000 (15:23 +0000)]
Fix test by allowing it to accept an upper or lower case letter as the first character.
Windows for some reason uses a lower case letter, while linux uses upper case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330438
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Sanjay Patel [Fri, 20 Apr 2018 15:07:55 +0000 (15:07 +0000)]
[DAGCombine] (float)((int) f) --> ftrunc (PR36617)
This was originally committed at rL328921 and reverted at rL329920 to
investigate failures in Chrome. This time I've added to the ReleaseNotes
to warn users of the potential of exposing UB and let me repeat that
here for more exposure:
Optimization of floating-point casts is improved. This may cause surprising
results for code that is relying on undefined behavior. Code sanitizers can
be used to detect affected patterns such as this:
int main() {
float x =
4294967296.0f;
x = (float)((int)x);
printf("junk in the ftrunc: %f\n", x);
return 0;
}
$ clang -O1 ftrunc.c -fsanitize=undefined ; ./a.out
ftrunc.c:5:15: runtime error: 4.29497e+09 is outside the range of
representable values of type 'int'
junk in the ftrunc: 0.000000
Original commit message:
fptosi / fptoui round towards zero, and that's the same behavior as ISD::FTRUNC,
so replace a pair of casts with the equivalent node. We don't have to account for
special cases (NaN, INF) because out-of-range casts are undefined.
Differential Revision: https://reviews.llvm.org/D44909
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330437
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 20 Apr 2018 15:01:03 +0000 (15:01 +0000)]
[CostModel][X86] Add srem/urem constant cost tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330436
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 20 Apr 2018 14:50:34 +0000 (14:50 +0000)]
[CostModel][X86] Add SLM/GLM/BtVer2 compare + division/remainder cost tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330435
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Fri, 20 Apr 2018 13:51:36 +0000 (13:51 +0000)]
Fix typo in a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330434
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 20 Apr 2018 13:50:33 +0000 (13:50 +0000)]
[CostModel][X86] Split off BtVer2 cost checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330433
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 20 Apr 2018 13:42:53 +0000 (13:42 +0000)]
[CostModel][X86] Add GoldmontPlus cost tests
Just reuses goldmont costs atm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330432
91177308-0d34-0410-b5e6-
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Michael Zolotukhin [Fri, 20 Apr 2018 13:34:32 +0000 (13:34 +0000)]
Revert "Revert r330403 and r330413."
Reapply the patches with a fix. Thanks Ilya and Hans for the reproducer!
This reverts commit r330416.
The issue was that removing predecessors invalidated uses that we stored
for rewrite. The fix is to finish manipulating with CFG before we select
uses for rewrite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330431
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 20 Apr 2018 13:12:04 +0000 (13:12 +0000)]
[X86][BtVer2] Cleanup some old FIXMEs from the model. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330428
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 20 Apr 2018 12:54:53 +0000 (12:54 +0000)]
[X86] Tag CLDEMOTE instruction with WriteLoad scheduling class
Same as other cacheline instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330424
91177308-0d34-0410-b5e6-
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Sander de Smalen [Fri, 20 Apr 2018 12:52:01 +0000 (12:52 +0000)]
[AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load instructions.
This is patch [4/4] in a series to add assembler/disassembler support for
SVE's contiguous LD1 (scalar+scalar) instructions:
- Patch [1/4]: https://reviews.llvm.org/D45687
- Patch [2/4]: https://reviews.llvm.org/D45688
- Patch [3/4]: https://reviews.llvm.org/D45689
- Patch [4/4]: https://reviews.llvm.org/D45690
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D45690
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330423
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Fri, 20 Apr 2018 12:33:49 +0000 (12:33 +0000)]
[ObjectYAML] Add ability for DWARFYAML to calculate DIE lengths
This patch adds the ability for the ObjectYAML DWARFEmitter to calculate
the lengths of DIEs. This is accomplished by creating a DIEFixupVisitor
class which traverses the DWARF DIEs to calculate and fix up the lengths
in the Compile Unit header.
The DIEFixupVisitor can be extended in the future to enable more complex
fix ups which will enable simplified YAML string representations.
This is also very useful when using the YAML format in unit tests
because you no longer need to know the length of the compile unit when
writing the YAML string.
Differential commandeered from Chris Bieneman (beanz)
Differential revision: https://reviews.llvm.org/D30666
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330421
91177308-0d34-0410-b5e6-
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Greg Bedwell [Fri, 20 Apr 2018 11:38:11 +0000 (11:38 +0000)]
[UpdateTestChecks] Fix update_mca_test_checks.py slowness issue
The script was using Python's difflib module to calculate the number of
lines changed so that it could report it in its status output. It turns
out this can be very very slow on large sets of lines (Python bug 6931).
It's not worth the cost, so just remove the usage of difflib entirely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330419
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Fri, 20 Apr 2018 11:21:13 +0000 (11:21 +0000)]
Require asserts for stats-file-option tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330417
91177308-0d34-0410-b5e6-
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Ilya Biryukov [Fri, 20 Apr 2018 10:52:54 +0000 (10:52 +0000)]
Revert r330403 and r330413.
Revert r330413: "[SSAUpdaterBulk] Use SmallVector instead of DenseMap for storing rewrites."
Revert r330403 "Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." one more time."
r330403 commit seems to crash clang during our integrate while doing PGO build with the following stacktrace:
#2 llvm::SSAUpdaterBulk::RewriteAllUses(llvm::DominatorTree*, llvm::SmallVectorImpl<llvm::PHINode*>*)
#3 llvm::JumpThreadingPass::ThreadEdge(llvm::BasicBlock*, llvm::SmallVectorImpl<llvm::BasicBlock*> const&, llvm::BasicBlock*)
#4 llvm::JumpThreadingPass::ProcessThreadableEdges(llvm::Value*, llvm::BasicBlock*, llvm::jumpthreading::ConstantPreference, llvm::Instruction*)
#5 llvm::JumpThreadingPass::ProcessBlock(llvm::BasicBlock*)
The crash happens while compiling 'lib/Analysis/CallGraph.cpp'.
r3340413 is reverted due to conflicting changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330416
91177308-0d34-0410-b5e6-
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Roman Lebedev [Fri, 20 Apr 2018 10:49:19 +0000 (10:49 +0000)]
[NFC][InstCombine] Regenerate two tests that are affected by folding masked merge
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330415
91177308-0d34-0410-b5e6-
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Andrew Ng [Fri, 20 Apr 2018 10:44:42 +0000 (10:44 +0000)]
[DebugInfo] Fix for split dwarf test on Windows (NFC)
On Windows, %llc_dwarf automatically adds -mtriple causing this test to
error. Changed %llc_dwarf to llc.
Differential Revision: https://reviews.llvm.org/D45869
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330414
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Fri, 20 Apr 2018 10:31:06 +0000 (10:31 +0000)]
[SSAUpdaterBulk] Use SmallVector instead of DenseMap for storing rewrites.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330413
91177308-0d34-0410-b5e6-
96231b3b80d8
Ilya Biryukov [Fri, 20 Apr 2018 10:19:38 +0000 (10:19 +0000)]
[Dockerfiles] Split checkout and build scripts into separate files.
Summary:
This is a small refactoring to extract the svn checkout code from the
build script used inside the docker image.
This would give more flexibility if more than a single invocation of
cmake is needed inside the docker image.
User-facing interface (build_docker_image.sh) hasn't changed, only the
internal scripts running inside the build container are affected.
Reviewers: ioeric
Reviewed By: ioeric
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D45868
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330412
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Fri, 20 Apr 2018 10:18:36 +0000 (10:18 +0000)]
[LTO] Add stats-file option to LTO/Config.h.
This patch adds a StatsFile option to LTO/Config.h and updates both
LLVMGold and llvm-lto2 to set it.
Reviewers: MatzeB, tejohnson, espindola
Reviewed By: tejohnson
Differential Revision: https://reviews.llvm.org/D45531
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330411
91177308-0d34-0410-b5e6-
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Andrea Di Biagio [Fri, 20 Apr 2018 10:16:31 +0000 (10:16 +0000)]
CODE_OWNERS: Take code ownership of llvm-mca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330410
91177308-0d34-0410-b5e6-
96231b3b80d8
Dan Liew [Fri, 20 Apr 2018 10:11:41 +0000 (10:11 +0000)]
[lit] Fix a bug where UNRESOLVED tests were not handled in the XUnit
XML printer.
A test has been added that tries to comprehensively test emitting
XUnit XML output for shell tests.
Differential Revision: https://reviews.llvm.org/D45567
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330409
91177308-0d34-0410-b5e6-
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Sander de Smalen [Fri, 20 Apr 2018 09:45:50 +0000 (09:45 +0000)]
[AArch64][SVE] Fix diagnostic for SVE LD4 instructions:
Diagnostic:
'index must be multiple of 3 in range [-32, 28]'
Must be:
'index must be multiple of 4 in range [-32, 28]'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330407
91177308-0d34-0410-b5e6-
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Sander de Smalen [Fri, 20 Apr 2018 08:54:49 +0000 (08:54 +0000)]
[AArch64][SVE] Added GPR64shifted and GPR64NoXZRshifted register classes.
Summary:
This is patch [3/4] in a series to add assembler/disassembler support for
SVE's contiguous LD1 (scalar+scalar) instructions:
- Patch [1/4]: https://reviews.llvm.org/D45687
- Patch [2/4]: https://reviews.llvm.org/D45688
- Patch [3/4]: https://reviews.llvm.org/D45689
- Patch [4/4]: https://reviews.llvm.org/D45690
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: SjoerdMeijer
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45689
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330406
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Fri, 20 Apr 2018 08:01:08 +0000 (08:01 +0000)]
Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." one more time.
Hopefully, changing set to vector removes nondeterminism detected by
some bots, or the new assert will catch something.
This reverts commit r330180.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330403
91177308-0d34-0410-b5e6-
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Michael Zolotukhin [Fri, 20 Apr 2018 07:59:57 +0000 (07:59 +0000)]
[SSAUpdaterBulk] Add an assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330402
91177308-0d34-0410-b5e6-
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Daniel Cederman [Fri, 20 Apr 2018 07:59:13 +0000 (07:59 +0000)]
Add SPARC support to update_llc_test_checks.py
Reviewers: spatel, jyknight
Reviewed By: spatel
Subscribers: fedor.sergeev, llvm-commits
Differential Revision: https://reviews.llvm.org/D45809
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330401
91177308-0d34-0410-b5e6-
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Michael Zolotukhin [Fri, 20 Apr 2018 07:58:54 +0000 (07:58 +0000)]
[SSAUpdaterBulk] Add * and & to auto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330400
91177308-0d34-0410-b5e6-
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Michael Zolotukhin [Fri, 20 Apr 2018 07:57:24 +0000 (07:57 +0000)]
[SSAUpdaterBulk] Use PredCache in ComputeLiveInBlocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330399
91177308-0d34-0410-b5e6-
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Michael Zolotukhin [Fri, 20 Apr 2018 07:56:00 +0000 (07:56 +0000)]
[SSAUpdaterBulk] Use SmallVector instead of SmallPtrSet for uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330398
91177308-0d34-0410-b5e6-
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Daniel Cederman [Fri, 20 Apr 2018 07:53:27 +0000 (07:53 +0000)]
Revert "This pass, fixing an erratum in some LEON 2 processors..."
Summary:
Reading Atmel's AT697E errata document this does not seem like a valid
workaround. While the text only mentions SDIV, it says that the ICC flags
can be wrong, and those are only generated by SDIVcc. Verification on
hardware shows that simply replacing SDIV with SDIVcc does not avoid
the bug with negative operands.
This reverts r283727.
Reviewers: lero_chris, jyknight
Reviewed By: jyknight
Subscribers: fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D45813
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330397
91177308-0d34-0410-b5e6-
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Daniel Cederman [Fri, 20 Apr 2018 07:47:12 +0000 (07:47 +0000)]
[Sparc] Use synthetic instruction clr to zero register instead of sethi
Using `clr reg`/`mov %g0, reg`/`or %g0, %g0, reg` to zero a register
looks much better than `sethi 0, reg`.
Reviewers: jyknight, venkatra
Reviewed By: jyknight
Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D45810
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330396
91177308-0d34-0410-b5e6-
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Sander de Smalen [Fri, 20 Apr 2018 07:24:20 +0000 (07:24 +0000)]
[AArch64][AsmParser] Extend RegOp with integrated 'shift/extend'.
Summary:
In some cases the shift/extend needs to be explicitly parsed together
with the register, rather than as a separate operand. This is needed
for addressing modes where the instruction as a whole dictates the
scaling/extend, rather than specific bits in the instruction.
By parsing them as a single operand, we avoid the need to pass an
extra operand in all CodeGen patterns (because all operands need to
have an associated value), and we avoid the need to update TableGen to
accept operands that have no associated bits in the instruction.
An added benefit of parsing them together is that the assembler
can give a sensible diagnostic if the scaling is not correct.
This is patch [2/4] in a series to add assembler/disassembler support for
SVE's contiguous LD1 (scalar+scalar) instructions:
- Patch [1/4]: https://reviews.llvm.org/D45687
- Patch [2/4]: https://reviews.llvm.org/D45688
- Patch [3/4]: https://reviews.llvm.org/D45689
- Patch [4/4]: https://reviews.llvm.org/D45690
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: fhahn, SjoerdMeijer
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45688
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330394
91177308-0d34-0410-b5e6-
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Nicolai Haehnle [Fri, 20 Apr 2018 07:14:25 +0000 (07:14 +0000)]
AMDGPU: Legalize the operand of SI_INIT_M0
Summary:
This fixes a case where the argument to a sendmsg intrinsic
ends up in a VGPR, for whatever reason.
The underlying performance issue is that a multiplication that
can be an s_mul_i32 is instead needlessly generated as
v_mul_u32_u24, but this is not addressed by this patch.
Change-Id: I61fd4034314d5acdf6074632c30b65364dfa7328
Reviewers: arsenm, rampitec
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45826
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330393
91177308-0d34-0410-b5e6-
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Daniel Cederman [Fri, 20 Apr 2018 06:57:49 +0000 (06:57 +0000)]
[Sparc] Fix addressing mode when using 64-bit values in inline assembly
Summary:
If a 64-bit register is used as an operand in inline assembly together
with a memory reference, the memory addressing will be wrong. The
addressing will be a single reg, instead of reg+reg or reg+imm. This
will generate a bad offset value or an exception in printMemOperand().
For example:
```
long long int val = 5;
long long int mem;
__asm__ volatile ("std %1, %0":"=m"(mem):"r"(val));
```
becomes:
```
std %i0, [%i2+589833]
```
The problem is that SelectInlineAsmMemoryOperand() is never called for
the memory references if one of the operands is a 64-bit register.
By calling SelectInlineAsmMemoryOperands() in tryInlineAsm() the Sparc
version of SelectInlineAsmMemoryOperand() gets called for each memory
reference.
Reviewers: jyknight, venkatra
Reviewed By: jyknight
Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D45761
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330392
91177308-0d34-0410-b5e6-
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Vlad Tsyrklevich [Fri, 20 Apr 2018 02:26:12 +0000 (02:26 +0000)]
Fix build failures for r330387 on buildbots that don't build the X86 target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330388
91177308-0d34-0410-b5e6-
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Vlad Tsyrklevich [Fri, 20 Apr 2018 01:36:48 +0000 (01:36 +0000)]
LowerTypeTests: Propagate symver directives
Summary:
This change fixes https://crbug.com/834474, a build failure caused by
LowerTypeTests not preserving .symver symbol versioning directives for
exported functions. Emit symver information to ThinLTO summary data and
then propagate symver directives for exported functions to the merged
module.
Emitting symver information to the summaries increases the size of
intermediate build artifacts for a Chromium build by less than 0.2%.
Reviewers: pcc
Reviewed By: pcc
Subscribers: tejohnson, mehdi_amini, eraman, llvm-commits, eugenis, kcc
Differential Revision: https://reviews.llvm.org/D45798
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330387
91177308-0d34-0410-b5e6-
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Amara Emerson [Fri, 20 Apr 2018 00:42:46 +0000 (00:42 +0000)]
Move a dump() implementation out of line.
Fixes some link issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330384
91177308-0d34-0410-b5e6-
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Jessica Paquette [Thu, 19 Apr 2018 22:17:07 +0000 (22:17 +0000)]
[MachineOutliner] NFC: Move EnableLinkOnceODROutlining into MachineOutliner.cpp
This moves the EnableLinkOnceODROutlining flag from TargetPassConfig.cpp into
MachineOutliner.cpp. It also removes OutlineFromLinkOnceODRs from the
MachineOutliner constructor. This is now handled by the moved command-line
flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330373
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 19 Apr 2018 22:11:58 +0000 (22:11 +0000)]
[llvm-mca][X86] Add prefetch instruction resource tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330371
91177308-0d34-0410-b5e6-
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Sam Clegg [Thu, 19 Apr 2018 22:00:53 +0000 (22:00 +0000)]
[WebAssembly] Enabled -triple=wasm32-unknown-unknown-wasm path using ELF directive parser.
This is a temporary solution until a proper WASM implementation of
MCAsmParserExtension is in place, but at least for now will unblock this
path.
Added test to make sure this path works with the WASM Assembler.
Patch By Wouter van Oortmerssen!
Differential Revision: https://reviews.llvm.org/D45386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330370
91177308-0d34-0410-b5e6-
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Sanjay Patel [Thu, 19 Apr 2018 21:56:17 +0000 (21:56 +0000)]
[Reassociate] add baseline tests for binop swapping; NFC
Similar to rL330086, I don't know if we want to do these
transforms here, but we might as well have the tests
here either way to show that this pass is missing
potential functionality (intentionally or not).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330368
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 19 Apr 2018 21:32:22 +0000 (21:32 +0000)]
[llvm-mca][FMA] Add FMA resource tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330366
91177308-0d34-0410-b5e6-
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Stanislav Mekhanoshin [Thu, 19 Apr 2018 21:16:50 +0000 (21:16 +0000)]
[AMDGPU] Use packed literals with zero either lower or hi part
Differential Revision: https://reviews.llvm.org/D45790
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330365
91177308-0d34-0410-b5e6-
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Gerolf Hoflehner [Thu, 19 Apr 2018 20:48:35 +0000 (20:48 +0000)]
[llvm-objdump] Issue error message when object file cannot be created
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330364
91177308-0d34-0410-b5e6-
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Craig Topper [Thu, 19 Apr 2018 20:44:15 +0000 (20:44 +0000)]
[X86] Remove non-existant instruction name from X86DisassemblerTables.cpp.
This instruction was removed a long time so we don't need to check for it here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330363
91177308-0d34-0410-b5e6-
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Jin Lin [Thu, 19 Apr 2018 20:29:43 +0000 (20:29 +0000)]
Refine the loop rotation's API
Summary:
The following changes addresses the following two issues.
1) The existing loop rotation pass contains both loop latch simplification and loop rotation. So one flag RotationOnly is added to be passed to the loop rotation pass.
2) The threshold value is initialized with MAX_UINT since the loop rotation utility should not have threshold limit.
Reviewers: dmgreen, efriedma
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D45582
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330362
91177308-0d34-0410-b5e6-
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