OSDN Git Service
Markus Armbruster [Tue, 4 Jun 2019 18:16:17 +0000 (20:16 +0200)]
Clean up a few header guard symbols
Commit
58ea30f5145 "Clean up header guards that don't match their file
name" messed up contrib/elf2dmp/qemu_elf.h and
tests/migration/migration-test.h.
It missed target/cris/opcode-cris.h and
tests/uefi-test-tools/UefiTestToolsPkg/Include/Guid/BiosTablesTest.h
due to the scripts/clean-header-guards.pl bug fixed in the previous
commit.
Commit
a8b991b52dc "Clean up ill-advised or unusual header guards"
missed include/hw/xen/io/ring.h for the same reason.
Commit
3979fca4b69 "disas: Rename include/disas/bfd.h back to
include/disas/dis-asm.h" neglected to update the guard symbol for the
rename.
Commit
a331c6d7741 "semihosting: implement a semihosting console"
created include/hw/semihosting/console.h with an ill-advised guard
symbol.
Clean them up.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <
20190604181618.19980-4-armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Markus Armbruster [Tue, 4 Jun 2019 18:16:16 +0000 (20:16 +0200)]
scripts/clean-header-guards: Fix handling of trailing comments
clean-header-guards.pl fails to recognize a header guard #endif when
it's followed by a // comment, or multiple comments. Fix that.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <
20190604181618.19980-3-armbru@redhat.com>
Markus Armbruster [Tue, 4 Jun 2019 18:16:15 +0000 (20:16 +0200)]
Normalize position of header guard
This is the common header guard idiom:
/*
* File comment
*/
#ifndef GUARD_SYMBOL_H
#define GUARD_SYMBOL_H
... actual contents ...
#endif
A few of our headers have some #include before the guard.
target/tilegx/spr_def_64.h has #ifndef __DOXYGEN__ outside the guard.
A few more have the #define elsewhere.
Change them to match the common idiom. For spr_def_64.h, that means
dropping #ifndef __DOXYGEN__. While there, rename guard symbols to
make scripts/clean-header-guards.pl happy.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <
20190604181618.19980-2-armbru@redhat.com>
[Rebased with conflicts resolved automatically]
Markus Armbruster [Thu, 23 May 2019 14:35:08 +0000 (16:35 +0200)]
Include qemu-common.h exactly where needed
No header includes qemu-common.h after this commit, as prescribed by
qemu-common.h's file comment.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <
20190523143508.25387-5-armbru@redhat.com>
[Rebased with conflicts resolved automatically, except for
include/hw/arm/xlnx-zynqmp.h hw/arm/nrf51_soc.c hw/arm/msf2-soc.c
block/qcow2-refcount.c block/qcow2-cluster.c block/qcow2-cache.c
target/arm/cpu.h target/lm32/cpu.h target/m68k/cpu.h target/mips/cpu.h
target/moxie/cpu.h target/nios2/cpu.h target/openrisc/cpu.h
target/riscv/cpu.h target/tilegx/cpu.h target/tricore/cpu.h
target/unicore32/cpu.h target/xtensa/cpu.h; bsd-user/main.c and
net/tap-bsd.c fixed up]
Markus Armbruster [Thu, 23 May 2019 14:35:07 +0000 (16:35 +0200)]
Include qemu/module.h where needed, drop it from qemu-common.h
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <
20190523143508.25387-4-armbru@redhat.com>
[Rebased with conflicts resolved automatically, except for
hw/usb/dev-hub.c hw/misc/exynos4210_rng.c hw/misc/bcm2835_rng.c
hw/misc/aspeed_scu.c hw/display/virtio-vga.c hw/arm/stm32f205_soc.c;
ui/cocoa.m fixed up]
Markus Armbruster [Thu, 23 May 2019 14:35:06 +0000 (16:35 +0200)]
qemu-common: Move qemu_isalnum() etc. to qemu/ctype.h
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <
20190523143508.25387-3-armbru@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Markus Armbruster [Thu, 23 May 2019 14:35:05 +0000 (16:35 +0200)]
qemu-common: Move tcg_enabled() etc. to sysemu/tcg.h
Other accelerators have their own headers: sysemu/hax.h, sysemu/hvf.h,
sysemu/kvm.h, sysemu/whpx.h. Only tcg_enabled() & friends sit in
qemu-common.h. This necessitates inclusion of qemu-common.h into
headers, which is against the rules spelled out in qemu-common.h's
file comment.
Move tcg_enabled() & friends into their own header sysemu/tcg.h, and
adjust #include directives.
Cc: Richard Henderson <rth@twiddle.net>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <
20190523143508.25387-2-armbru@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[Rebased with conflicts resolved automatically, except for
accel/tcg/tcg-all.c]
Peter Maydell [Mon, 10 Jun 2019 15:09:19 +0000 (16:09 +0100)]
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-
20190610' into staging
Move softmmu tlb into CPUNegativeOffsetState
# gpg: Signature made Mon 10 Jun 2019 15:07:55 BST
# gpg: using RSA key
7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-tcg-
20190610: (39 commits)
tcg/arm: Remove mostly unreachable tlb special case
tcg/arm: Use LDRD to load tlb mask+table
tcg/aarch64: Use LDP to load tlb mask+table
cpu: Remove CPU_COMMON
cpu: Move the softmmu tlb to CPUNegativeOffsetState
cpu: Move icount_decr to CPUNegativeOffsetState
cpu: Introduce CPUNegativeOffsetState
cpu: Introduce cpu_set_cpustate_pointers
cpu: Move ENV_OFFSET to exec/gen-icount.h
target/xtensa: Use env_cpu, env_archcpu
target/unicore32: Use env_cpu, env_archcpu
target/tricore: Use env_cpu
target/tilegx: Use env_cpu
target/sparc: Use env_cpu, env_archcpu
target/sh4: Use env_cpu, env_archcpu
target/s390x: Use env_cpu, env_archcpu
target/riscv: Use env_cpu, env_archcpu
target/ppc: Use env_cpu, env_archcpu
target/openrisc: Use env_cpu, env_archcpu
target/nios2: Use env_cpu, env_archcpu
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Tue, 7 May 2019 17:33:44 +0000 (10:33 -0700)]
tcg/arm: Remove mostly unreachable tlb special case
There was nothing armv7 specific about the bic+cmp sequence, however
looking at the set of guests more closely shows that the 8-bit immediate
operand for the bic can only be satisfied with one guest in tree:
baseline m-profile -- 10-bit pages with aligned 4-byte memory ops.
Therefore it does not seem useful to keep this path.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 07:46:23 +0000 (00:46 -0700)]
tcg/arm: Use LDRD to load tlb mask+table
This changes the code generation for the tlb from e.g.
ldr ip, [r6, #-0x10]
ldr r2, [r6, #-0xc]
and ip, ip, r4, lsr #8
ldrd r0, r1, [r2, ip]!
ldr r2, [r2, #0x18]
to
ldrd r0, r1, [r6, #-0x10]
and r0, r0, r4, lsr #8
ldrd r2, r3, [r1, r0]!
ldr r1, [r1, #0x18]
for armv7 hosts. Rearranging the register allocation in
order to avoid overlap between the two ldrd pairs causes
the patch to be larger than it ordinarily would be.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 06:35:26 +0000 (23:35 -0700)]
tcg/aarch64: Use LDP to load tlb mask+table
This changes the code generation for the tlb from e.g.
ldur x0, [x19, #0xffffffffffffffe0]
ldur x1, [x19, #0xffffffffffffffe8]
and x0, x0, x20, lsr #8
add x1, x1, x0
ldr x0, [x1]
ldr x1, [x1, #0x18]
to
ldp x0, x1, [x19, #-0x20]
and x0, x0, x20, lsr #8
add x1, x1, x0
ldr x0, [x1]
ldr x1, [x1, #0x18]
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 18:35:53 +0000 (11:35 -0700)]
cpu: Remove CPU_COMMON
This macro is now always empty, so remove it. This leaves the
entire contents of CPUArchState under the control of the guest
architecture.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 05:03:39 +0000 (22:03 -0700)]
cpu: Move the softmmu tlb to CPUNegativeOffsetState
We have for some time had code within the tcg backends to
handle large positive offsets from env. This move makes
sure that need not happen. Indeed, we are able to assert
at build time that simple offsets suffice for all hosts.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 28 Mar 2019 21:54:23 +0000 (11:54 -1000)]
cpu: Move icount_decr to CPUNegativeOffsetState
Amusingly, we had already ignored the comment to keep this value
at the end of CPUState. This restores the minimum negative offset
from TCG_AREG0 for code generation.
For the couple of uses within qom/cpu.c, without NEED_CPU_H, add
a pointer from the CPUState object to the IcountDecr object within
CPUNegativeOffsetState.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 00:16:06 +0000 (17:16 -0700)]
cpu: Introduce CPUNegativeOffsetState
Nothing in there so far, but all of the plumbing done
within the target ArchCPU state.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 28 Mar 2019 21:26:22 +0000 (11:26 -1000)]
cpu: Introduce cpu_set_cpustate_pointers
Consolidate some boilerplate from foo_cpu_initfn.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 00:00:56 +0000 (17:00 -0700)]
cpu: Move ENV_OFFSET to exec/gen-icount.h
Now that we have ArchCPU, we can define this generically,
in the one place that needs it.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 02:52:17 +0000 (19:52 -0700)]
target/xtensa: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace xtensa_env_get_cpu with env_archcpu. The combination
CPU(xtensa_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Move cpu_get_tb_cpu_state below the include of "exec/cpu-all.h"
so that the definition of env_cpu is available.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 02:46:31 +0000 (19:46 -0700)]
target/unicore32: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace uc32_env_get_cpu with env_archcpu. The combination
CPU(uc32_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 02:39:59 +0000 (19:39 -0700)]
target/tricore: Use env_cpu
Cleanup in the boilerplate that each target must define.
Replace tricore_env_get_cpu with env_archcpu. The combination
CPU(tricore_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 02:38:33 +0000 (19:38 -0700)]
target/tilegx: Use env_cpu
Cleanup in the boilerplate that each target must define.
Replace tilegx_env_get_cpu with env_archcpu. The combination
CPU(tilegx_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 02:36:20 +0000 (19:36 -0700)]
target/sparc: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace sparc_env_get_cpu with env_archcpu. The combination
CPU(sparc_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 02:26:42 +0000 (19:26 -0700)]
target/sh4: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace sh_env_get_cpu with env_archcpu. The combination
CPU(sh_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 02:21:48 +0000 (19:21 -0700)]
target/s390x: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace s390_env_get_cpu with env_archcpu. The combination
CPU(s390_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 02:11:37 +0000 (19:11 -0700)]
target/riscv: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace riscv_env_get_cpu with env_archcpu. The combination
CPU(riscv_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 02:07:57 +0000 (19:07 -0700)]
target/ppc: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace ppc_env_get_cpu with env_archcpu. The combination
CPU(ppc_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 01:48:56 +0000 (18:48 -0700)]
target/openrisc: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace openrisc_env_get_cpu with env_archcpu. The combination
CPU(openrisc_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 01:44:44 +0000 (18:44 -0700)]
target/nios2: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace nios2_env_get_cpu with env_archcpu. The combination
CPU(nios2_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 01:41:52 +0000 (18:41 -0700)]
target/moxie: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace moxie_env_get_cpu with env_archcpu. The combination
CPU(moxie_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 01:38:42 +0000 (18:38 -0700)]
target/mips: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace mips_env_get_cpu with env_archcpu. The combination
CPU(mips_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 01:27:36 +0000 (18:27 -0700)]
target/microblaze: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace mb_env_get_cpu with env_archcpu. The combination
CPU(mb_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Move cpu_mmu_index below the include of "exec/cpu-all.h",
so that the definition of env_archcpu is available.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 01:23:25 +0000 (18:23 -0700)]
target/m68k: Use env_cpu
Cleanup in the boilerplate that each target must define.
The combination CPU(m68k_env_get_cpu) should have used
ENV_GET_CPU to begin; use env_cpu now.
Acked-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 01:13:44 +0000 (18:13 -0700)]
target/lm32: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace lm32_env_get_cpu with env_archcpu. The combination
CPU(lm32_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 01:08:48 +0000 (18:08 -0700)]
target/i386: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace x86_env_get_cpu with env_archcpu. The combination
CPU(x86_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 00:51:33 +0000 (17:51 -0700)]
target/hppa: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace hppa_env_get_cpu with env_archcpu. The combination
CPU(hppa_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 00:46:40 +0000 (17:46 -0700)]
target/cris: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace cris_env_get_cpu with env_archcpu. The combination
CPU(cris_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 7 May 2019 04:57:43 +0000 (21:57 -0700)]
target/cris: Reindent op_helper.c
Fix all of the coding style errors in this file at once.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 7 May 2019 03:58:57 +0000 (20:58 -0700)]
target/cris: Reindent mmu.c
Fix all of the coding style errors in this file at once.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 00:41:14 +0000 (17:41 -0700)]
target/arm: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace arm_env_get_cpu with env_archcpu. The combination
CPU(arm_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 00:26:58 +0000 (17:26 -0700)]
target/alpha: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace alpha_env_get_cpu with env_archcpu. The combination
CPU(alpha_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 23 Mar 2019 00:22:52 +0000 (17:22 -0700)]
cpu: Introduce env_archcpu
This will replace foo_env_get_cpu with a generic definition.
No changes to the target specific code so far.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 22 Mar 2019 23:07:18 +0000 (16:07 -0700)]
cpu: Replace ENV_GET_CPU with env_cpu
Now that we have both ArchCPU and CPUArchState, we can define
this generically instead of via macro in each target's cpu.h.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 22 Mar 2019 22:56:19 +0000 (15:56 -0700)]
cpu: Define ArchCPU
For all targets, do this just before including exec/cpu-all.h.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 22 Mar 2019 22:32:23 +0000 (15:32 -0700)]
cpu: Define CPUArchState with typedef
For all targets, do this just before including exec/cpu-all.h.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 22 Mar 2019 20:52:09 +0000 (13:52 -0700)]
tcg: Create struct CPUTLB
Move all softmmu tlb data into this structure. Arrange the
members so that we are able to place mask+table together and
at a smaller absolute offset from ENV.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 22 Mar 2019 18:51:19 +0000 (11:51 -0700)]
tcg: Split out target/arch/cpu-param.h
For all targets, into this new file move TARGET_LONG_BITS,
TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS,
TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES.
Include this new file from exec/cpu-defs.h.
This now removes the somewhat odd requirement that target/arch/cpu.h
defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the
bulk of the includes within target/arch/cpu.h to the top.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 22 Mar 2019 15:36:40 +0000 (08:36 -0700)]
tcg: Fold CPUTLBWindow into CPUTLBDesc
Both structures are allocated once per mmu_idx.
There is no reason for them to be separate.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Peter Maydell [Mon, 10 Jun 2019 10:53:19 +0000 (11:53 +0100)]
Merge remote-tracking branch 'remotes/kraxel/tags/usb-
20190607-pull-request' into staging
usb-mtp: refactor the flow of usb_mtp_write_data
# gpg: Signature made Fri 07 Jun 2019 17:56:31 BST
# gpg: using RSA key
4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* remotes/kraxel/tags/usb-
20190607-pull-request:
usb-mtp: refactor the flow of usb_mtp_write_data
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Mon, 10 Jun 2019 10:03:08 +0000 (11:03 +0100)]
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging
Machine Core queue, 2019-06-07
* Improve CPU hotplug error message
(Laurent Vivier)
* Remove unused AccelClass::opt_name field
(Wainer dos Santos Moschetta)
# gpg: Signature made Fri 07 Jun 2019 19:31:28 BST
# gpg: using RSA key
2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6
* remotes/ehabkost/tags/machine-next-pull-request:
accel: Remove unused AccelClass::opt_name attribute
numa: improve cpu hotplug error message with a wrong node-id
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Wainer dos Santos Moschetta [Fri, 31 May 2019 16:53:34 +0000 (12:53 -0400)]
accel: Remove unused AccelClass::opt_name attribute
The AccelType type was converted to AccelClass QOM
object on
b14a0b7469f, and the original data type had
a field to store the option name which in turn was
used to search an accelerator. The lookup method
(accel_find) changed too, making the option field
unnecessary but it became AccelClass::opt_name despite
that. Therefore, and given that none accelerator
implementation sets AccelClass::opt_name, let's
remove this attribute.
Signed-off-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Message-Id: <
20190531165334.20403-2-wainersm@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Laurent Vivier [Wed, 29 May 2019 16:07:47 +0000 (18:07 +0200)]
numa: improve cpu hotplug error message with a wrong node-id
On pseries, core-ids are strongly binded to a node-id by the command
line option. If an user tries to add a CPU to the wrong node, he has
an error but it is not really helpful:
qemu-system-ppc64 ... -smp 1,maxcpus=64,cores=1,threads=1,sockets=1 \
-numa node,nodeid=0 -numa node,nodeid=1 ...
(qemu) device_add power9_v2.0-spapr-cpu-core,core-id=30,node-id=1
Error: node-id=1 must match numa node specified with -numa option
This patch improves this error message by giving to the user the good
node-id to use with the core-id he's providing
Error: invalid node-id, must be 0
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Message-Id: <
20190529160747.778-1-lvivier@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Bandan Das [Mon, 1 Apr 2019 21:17:12 +0000 (17:17 -0400)]
usb-mtp: refactor the flow of usb_mtp_write_data
There's no functional change but the flow is (hopefully)
more consistent for both file and folder object types.
Signed-off-by: Bandan Das <bsd@redhat.com>
Message-Id: <
20190401211712.19012-4-bsd@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Peter Maydell [Fri, 7 Jun 2019 14:24:13 +0000 (15:24 +0100)]
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-
20190607-2' into staging
s390x updates:
- tcg: finalize implementation for the vector facility and
add it to the 'qemu' cpu model
- linux-user: properly generate ELF_HWCAP
# gpg: Signature made Fri 07 Jun 2019 15:14:42 BST
# gpg: using RSA key
C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF
# gpg: issuer "cohuck@redhat.com"
# gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown]
# gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full]
# gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full]
# gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown]
# gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown]
# Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF
* remotes/cohuck/tags/s390x-
20190607-2: (34 commits)
linux-user: elf: ELF_HWCAP for s390x
s390x/tcg: Use tcg_gen_gvec_bitsel for VECTOR SELECT
s390x: Bump the "qemu" CPU model up to a stripped-down z13
s390x/tcg: We support the Vector Facility
s390x/tcg: Allow linux-user to use vector instructions
s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATE
s390x/tcg: Implement VECTOR FP SUBTRACT
s390x/tcg: Implement VECTOR FP SQUARE ROOT
s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATION
s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT)
s390x/tcg: Implement VECTOR FP MULTIPLY
s390x/tcg: Implement VECTOR LOAD ROUNDED
s390x/tcg: Implement VECTOR LOAD LENGTHENED
s390x/tcg: Implement VECTOR LOAD FP INTEGER
s390x/tcg: Implement VECTOR FP DIVIDE
s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BIT
s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BIT
s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BIT
s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BIT
s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL)
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Cornelia Huck [Fri, 7 Jun 2019 14:06:09 +0000 (16:06 +0200)]
Merge tag 's390x-tcg-2019-06-07' into s390-next-staging
Finalize implementation of the "Vector Facility" for s390x TCG. Add it
to the QEMU CPU model, so it is enabled as default.
Also:
- One fix (and one workaround) for the STFLE instruction
- Fix the alignment of vector registers (and change the data type)
- Properly generate ELF_HWCAP for s390x for linux-user
- Use a gvec helper for VECTOR SELECT
# gpg: Signature made Fri 07 Jun 2019 02:58:01 PM CEST
# gpg: using RSA key
1BD9CAAD735C4C3A460DFCCA4DDE10F700FF835A
# gpg: issuer "david@redhat.com"
# gpg: Good signature from "David Hildenbrand <david@redhat.com>" [full]
# gpg: aka "David Hildenbrand <davidhildenbrand@gmail.com>" [full]
* tag 's390x-tcg-2019-06-07': (33 commits)
linux-user: elf: ELF_HWCAP for s390x
s390x/tcg: Use tcg_gen_gvec_bitsel for VECTOR SELECT
s390x: Bump the "qemu" CPU model up to a stripped-down z13
s390x/tcg: We support the Vector Facility
s390x/tcg: Allow linux-user to use vector instructions
s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATE
s390x/tcg: Implement VECTOR FP SUBTRACT
s390x/tcg: Implement VECTOR FP SQUARE ROOT
s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATION
s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT)
s390x/tcg: Implement VECTOR FP MULTIPLY
s390x/tcg: Implement VECTOR LOAD ROUNDED
s390x/tcg: Implement VECTOR LOAD LENGTHENED
s390x/tcg: Implement VECTOR LOAD FP INTEGER
s390x/tcg: Implement VECTOR FP DIVIDE
s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BIT
s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BIT
s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BIT
s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BIT
s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL)
...
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Peter Maydell [Fri, 7 Jun 2019 13:53:00 +0000 (14:53 +0100)]
Merge remote-tracking branch 'remotes/kraxel/tags/ui-
20190607-pull-request' into staging
curses: 32bit build fix.
egl: dmabuf modifier support.
# gpg: Signature made Fri 07 Jun 2019 14:18:41 BST
# gpg: using RSA key
4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* remotes/kraxel/tags/ui-
20190607-pull-request:
egl-helpers: add modifier support to egl_dmabuf_import_texture()
egl-helpers: add modifier support to egl_get_fd_for_texture().
vfio/display: set dmabuf modifier field
console: add dmabuf modifier field.
ui/curses: Fix build with -m32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
David Hildenbrand [Tue, 4 Jun 2019 09:30:07 +0000 (11:30 +0200)]
linux-user: elf: ELF_HWCAP for s390x
Let's add all HWCAPs that we can support under TCG right now, when the
respective CPU facilities are enabled.
Cc: Riku Voipio <riku.voipio@iki.fi>
Cc: Laurent Vivier <laurent@vivier.eu>
Cc: Cornelia Huck <cohuck@redhat.com>
Cc: Laurent Vivier <laurent@vivier.eu>
Cc: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Richard Henderson [Mon, 3 Jun 2019 16:57:35 +0000 (11:57 -0500)]
s390x/tcg: Use tcg_gen_gvec_bitsel for VECTOR SELECT
This replaces the target-specific implementations for VSEL.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 27 Feb 2019 08:12:09 +0000 (09:12 +0100)]
s390x: Bump the "qemu" CPU model up to a stripped-down z13
We don't care about the other two missing base features:
- S390_FEAT_DFP_PACKED_CONVERSION
- S390_FEAT_GROUP_GEN13_PTFF
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 29 May 2019 20:29:46 +0000 (22:29 +0200)]
s390x/tcg: We support the Vector Facility
Let's add it to the max model, so we can enable it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 27 Feb 2019 08:07:34 +0000 (09:07 +0100)]
s390x/tcg: Allow linux-user to use vector instructions
Once we unlock S390_FEAT_VECTOR for TCG, we want linux-user to be
able to make use of it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 29 May 2019 20:27:21 +0000 (22:27 +0200)]
s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATE
We can reuse float64_dcmask().
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 29 May 2019 20:25:34 +0000 (22:25 +0200)]
s390x/tcg: Implement VECTOR FP SUBTRACT
Similar to VECTOR FP ADD.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 29 May 2019 20:22:35 +0000 (22:22 +0200)]
s390x/tcg: Implement VECTOR FP SQUARE ROOT
Simulate XxC=0 and ERM=0 (current mode), so we can use the existing
helper function.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 29 May 2019 20:18:57 +0000 (22:18 +0200)]
s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATION
The only FP instruction we can implement without an helper.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 29 May 2019 20:17:09 +0000 (22:17 +0200)]
s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 29 May 2019 20:09:33 +0000 (22:09 +0200)]
s390x/tcg: Implement VECTOR FP MULTIPLY
Very similar to VECTOR FP DIVIDE.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 29 May 2019 20:06:42 +0000 (22:06 +0200)]
s390x/tcg: Implement VECTOR LOAD ROUNDED
We can reuse some of the infrastructure introduced for
VECTOR FP CONVERT FROM FIXED 64-BIT and friends.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 29 May 2019 20:02:09 +0000 (22:02 +0200)]
s390x/tcg: Implement VECTOR LOAD LENGTHENED
Take care of reading/indicating the 32-bit elements.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 29 May 2019 19:57:10 +0000 (21:57 +0200)]
s390x/tcg: Implement VECTOR LOAD FP INTEGER
We can reuse most of the infrastructure introduced for
VECTOR FP CONVERT FROM FIXED 64-BIT and friends.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 29 May 2019 19:54:33 +0000 (21:54 +0200)]
s390x/tcg: Implement VECTOR FP DIVIDE
We can reuse most of the infrastructure added for VECTOR FP ADD.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 29 May 2019 19:51:23 +0000 (21:51 +0200)]
s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BIT
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 29 May 2019 19:49:52 +0000 (21:49 +0200)]
s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BIT
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 29 May 2019 19:47:20 +0000 (21:47 +0200)]
s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BIT
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 29 May 2019 19:42:05 +0000 (21:42 +0200)]
s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BIT
1. We'll reuse op_vcdg() for similar instructions later, prepare for
that.
2. We'll reuse vop64_2() later for other instructions.
We have to mangle the erm (effective rounding mode) and the m4 into
the simd_data(), and properly unmangle them again.
Make sure to restore the erm before triggering an exception.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 29 May 2019 19:35:08 +0000 (21:35 +0200)]
s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL)
Provide for all three instructions all four combinations of cc bit and
s bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 29 May 2019 19:30:56 +0000 (21:30 +0200)]
s390x/tcg: Implement VECTOR FP COMPARE (AND SIGNAL) SCALAR
As far as I can see, there is only a tiny difference.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 29 May 2019 19:21:21 +0000 (21:21 +0200)]
s390x/tcg: Implement VECTOR FP ADD
1. We'll reuse op_vfa() for similar instructions later, prepare for
that.
2. We'll reuse vop64_3() for other instructions later.
3. Take care of modifying the vector register only if no trap happened.
- on traps, flags are not updated and no elements are modified
- traps don't modify the fpc flags
- without traps, all exceptions of all elements are merged
4. We'll reuse check_ieee_exc() later when we need the XxC flag.
We have to check for exceptions after processing each element.
Provide separate handlers for single/all element processing. We'll do
the same for all applicable FP instructions.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Mon, 25 Feb 2019 09:46:36 +0000 (10:46 +0100)]
s390x/tcg: Export float_comp_to_cc() and float(32|64|128)_dcmask()
Vector floating-point instructions will require these functions, so
allow to use them from other files.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Fri, 22 Feb 2019 10:19:48 +0000 (11:19 +0100)]
s390x/tcg: Introduce tcg_s390_vector_exception()
Handling is similar to data exceptions, however we can always store the
VXC into the lowore and the FPC:
z14 PoP, 6-20, "Vector-Exception Code"
When a vector-processing exception causes a pro-
gram interruption, a vector-exception code (VXC) is
stored at location 147, and zeros are stored at loca-
tions 144-146. The VXC is also placed in the DXC
field of the floating-point-control (FPC) register if bit
45 of control register 0 is one. When bit 45 of control
register 0 is zero and bit 46 of control register 0 is
one, the DXC field of the FPC register and the con-
tents of storage at location 147 are unpredictable.
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Fri, 31 May 2019 14:33:38 +0000 (16:33 +0200)]
s390x/tcg: Store only the necessary amount of doublewords for STFLE
The PoP (z14, 7-382) says:
Doublewords to the right of the doubleword in which the
highest-numbered facility bit is assigned for a model
may or may not be stored.
However, stack protection in certain binaries can't deal with that.
"gzip" example code:
f1b4: a7 08 00 03 lhi %r0,3
f1b8: b2 b0 f0 a0 stfle 160(%r15)
f1bc: e3 20 f0 b2 00 90 llgc %r2,178(%r15)
f1c2: c0 2b 00 00 00 01 nilf %r2,1
f1c8: b2 4f 00 10 ear %r1,%a0
f1cc: b9 14 00 22 lgfr %r2,%r2
f1d0: eb 11 00 20 00 0d sllg %r1,%r1,32
f1d6: b2 4f 00 11 ear %r1,%a1
f1da: d5 07 f0 b8 10 28 clc 184(8,%r15),40(%r1)
f1e0: a7 74 00 06 jne f1ec <file_read@@Base+0x1bc>
f1e4: eb ef f1 30 00 04 lmg %r14,%r15,304(%r15)
f1ea: 07 fe br %r14
f1ec: c0 e5 ff ff 9d 6e brasl %r14,2cc8 <__stack_chk_fail@plt>
In QEMU, we currently have:
max_bytes = 24
the code asks for (3 + 1) doublewords == 32 bytes.
If we write 32 bytes instead of only 24, and return "2 + 1" doublewords
("one less than the number of doulewords needed to contain all of the
facility bits"), the example code detects a stack corruption.
In my opinion, the code is wrong. However, it seems to work fine on
real machines. So let's limit storing to the minimum of the requested
and the maximum doublewords.
Cc: Stefan Liebler <stli@linux.ibm.com>
Cc: Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Fri, 31 May 2019 14:31:44 +0000 (16:31 +0200)]
s390x/tcg: Fix max_byte detection for stfle
used_stfl_bytes is 0, before initialized via prepare_stfl() on the
first invocation. We have to move the calculation of max_bytes after
prepare_stfl().
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 29 May 2019 07:15:38 +0000 (09:15 +0200)]
s390x: Use uint64_t for vector registers
CPU_DoubleU is primarily used to reinterpret between integer and floats.
We don't really need this functionality. So let's just keep it simple
and use an uint64_t.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Tue, 28 May 2019 18:46:57 +0000 (20:46 +0200)]
s390x: Align vector registers to 16 bytes
11e2bfef7990 ("tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/store")
revealed that the vregs are not aligned to 16 bytes. Align them to
16 bytes, to avoid segfault'ing on x86.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Fri, 24 May 2019 09:23:49 +0000 (11:23 +0200)]
s390x/tcg: Implement VECTOR STRING RANGE COMPARE
Unfortunately, there is no easy way to avoid looping over all elements
in v2. Provide specialized variants for !cc,!rt/!cc,rt/cc,!rt/cc,rt and
all element types. Especially for different values of rt, the compiler
might be able to optimize the code a lot.
Add s390_vec_write_element().
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Fri, 24 May 2019 09:27:56 +0000 (11:27 +0200)]
s390x/tcg: Implement VECTOR ISOLATE STRING
Logic mostly courtesy of Richard H.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Fri, 24 May 2019 09:26:45 +0000 (11:26 +0200)]
s390x/tcg: Implement VECTOR FIND ELEMENT NOT EQUAL
Similar to VECTOR FIND ELEMENT EQUAL. Core logic courtesy of Richard H.
Add s390_vec_read_element() that can deal with element sizes.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Fri, 24 May 2019 09:25:58 +0000 (11:25 +0200)]
s390x/tcg: Implement VECTOR FIND ELEMENT EQUAL
Core logic courtesy of Richard H.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Thu, 23 May 2019 13:09:49 +0000 (15:09 +0200)]
s390x/tcg: Implement VECTOR FIND ANY ELEMENT EQUAL
Complicated stuff. Provide two different helpers for CC an !CC handling.
We might want to add more helpers later.
zero_search() and match_index() are courtesy of Richard H.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Cornelia Huck [Wed, 29 May 2019 09:05:12 +0000 (11:05 +0200)]
MAINTAINERS: cover tests/migration/s390x/
The generic s390 section looks like the best resting place.
Message-Id: <
20190529091243.25562-1-cohuck@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Peter Maydell [Fri, 7 Jun 2019 10:17:28 +0000 (11:17 +0100)]
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-7-2019' into staging
MIPS Queue for June 7th, 2019
# gpg: Signature made Fri 07 Jun 2019 10:59:15 BST
# gpg: using RSA key
D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65
* remotes/amarkovic/tags/mips-queue-jun-7-2019:
tests/tcg: target/mips: Add README for MSA tests
tests/tcg: target/mips: Add tests for MSA FP max/min instructions
tests/tcg: target/mips: Add utility function reset_msa_registers()
tests/tcg: target/mips: Move four tests to a better location
tests/tcg: target/mips: Add tests for MSA shift instructions
tests/tcg: target/mips: Amend and rearrange MSA wrappers
target/mips: Unroll loops in helpers for MSA logic instructions
target/mips: Outline places for future MSA helpers
target/mips: Fix block-comment-related issues in msa_helper.c
target/mips: Fix space-related format issues in msa_helper.c
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Aleksandar Markovic [Thu, 6 Jun 2019 16:27:20 +0000 (18:27 +0200)]
tests/tcg: target/mips: Add README for MSA tests
Add README for MSA tests. This is just to explain how to run tests even
without Makefile. Makefile will be provided later on.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <
1559838440-9866-11-git-send-email-aleksandar.markovic@rt-rk.com>
Aleksandar Markovic [Thu, 6 Jun 2019 16:27:19 +0000 (18:27 +0200)]
tests/tcg: target/mips: Add tests for MSA FP max/min instructions
Add tests for MSA FP max/min instructions. This includes following
instructions:
* FMAX.W - float maximum (words)
* FMAX.D - float maximum (doublewords)
* FMAX_A.W - float maximum absolute (words)
* FMAX_A.D - float maximum absolute (doublewords)
* FMIN.W - float minimum (words)
* FMIN.D - float minimum (doublewords)
* FMIN_A.W - float minimum absolute (words)
* FMIN_A.D - float minimum absolute (doublewords)
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <
1559838440-9866-10-git-send-email-aleksandar.markovic@rt-rk.com>
Aleksandar Markovic [Thu, 6 Jun 2019 16:27:18 +0000 (18:27 +0200)]
tests/tcg: target/mips: Add utility function reset_msa_registers()
Add function reset_msa_registers() and utilize it in each MSA test.
This is needed to ensure independency of test results on the state of
MSA registers before test execution. This also allows for correction
of tests for VSHF* instructions, that are now independent on the
previous state of MSA registers.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <
1559838440-9866-9-git-send-email-aleksandar.markovic@rt-rk.com>
Aleksandar Markovic [Thu, 6 Jun 2019 16:27:17 +0000 (18:27 +0200)]
tests/tcg: target/mips: Move four tests to a better location
Move tests for <MUL|MULR>_Q.<H|B> from "integer multiply" directory
to "fixed-point multiply" directory, since they do not operate on
integers, but on fixed point numbers.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <
1559838440-9866-8-git-send-email-aleksandar.markovic@rt-rk.com>
Aleksandar Markovic [Thu, 6 Jun 2019 16:27:16 +0000 (18:27 +0200)]
tests/tcg: target/mips: Add tests for MSA shift instructions
Add tests for MSA shift instructions. This includes following
instructions:
* SLL.B - shift left logical (bytes)
* SLL.H - shift left logical (halfwords)
* SLL.W - shift left logical (words)
* SLL.D - shift left logical (doublewords)
* SRA.B - shift right arithmetic (bytes)
* SRA.H - shift right arithmetic (halfwords)
* SRA.W - shift right arithmetic (words)
* SRA.D - shift right arithmetic (doublewords)
* SRAR.B - shift right arithmetic rounded (bytes)
* SRAR.H - shift right arithmetic rounded (halfwords)
* SRAR.W - shift right arithmetic rounded (words)
* SRAR.D - shift right arithmetic rounded (doublewords)
* SRL.B - shift right logical (bytes)
* SRL.H - shift right logical (halfwords)
* SRL.W - shift right logical (words)
* SRL.D - shift right logical (doublewords)
* SRLR.B - shift right logical rounded (bytes)
* SRLR.H - shift right logical rounded (halfwords)
* SRLR.W - shift right logical rounded (words)
* SRLR.D - shift right logical rounded (doublewords)
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <
1559838440-9866-7-git-send-email-aleksandar.markovic@rt-rk.com>
Aleksandar Markovic [Thu, 6 Jun 2019 16:27:15 +0000 (18:27 +0200)]
tests/tcg: target/mips: Amend and rearrange MSA wrappers
Amend and rearrange MSA wrappers to follow the same organization as
in MSA tests.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <
1559838440-9866-6-git-send-email-aleksandar.markovic@rt-rk.com>
Aleksandar Markovic [Thu, 6 Jun 2019 16:27:14 +0000 (18:27 +0200)]
target/mips: Unroll loops in helpers for MSA logic instructions
Unroll loops in helpers for MSA logic instructions for better
performance.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <
1559838440-9866-5-git-send-email-aleksandar.markovic@rt-rk.com>
Aleksandar Markovic [Thu, 6 Jun 2019 16:27:13 +0000 (18:27 +0200)]
target/mips: Outline places for future MSA helpers
Outline places for future MSA helpers to follow the same organization
as in MSA tests.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <
1559838440-9866-4-git-send-email-aleksandar.markovic@rt-rk.com>
Gerd Hoffmann [Wed, 29 May 2019 07:21:44 +0000 (09:21 +0200)]
egl-helpers: add modifier support to egl_dmabuf_import_texture()
Check and use QemuDmaBuf->modifier in egl_dmabuf_import_texture()
for dmabuf imports.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id:
20190529072144.26737-5-kraxel@redhat.com
Gerd Hoffmann [Wed, 29 May 2019 07:21:43 +0000 (09:21 +0200)]
egl-helpers: add modifier support to egl_get_fd_for_texture().
Add modifier parameter to egl_get_fd_for_texture(), to return the used
modifier on dmabuf exports.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id:
20190529072144.26737-4-kraxel@redhat.com