OSDN Git Service
Logan Chien [Wed, 12 Dec 2012 07:14:46 +0000 (07:14 +0000)]
Add ARM NONE and PREL31 relocation types.
Add R_ARM_NONE and R_ARM_PREL31 relocation types
to MCExpr. Both of them will be used while
generating .ARM.extab and .ARM.exidx sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169965
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Rafael Espindola [Wed, 12 Dec 2012 06:18:15 +0000 (06:18 +0000)]
Remove some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169963
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NAKAMURA Takumi [Wed, 12 Dec 2012 03:34:26 +0000 (03:34 +0000)]
[CMake] Fixup R600.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169962
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Evan Cheng [Wed, 12 Dec 2012 02:34:41 +0000 (02:34 +0000)]
Sorry about the churn. One more change to getOptimalMemOpType() hook. Did I
mention the inline memcpy / memset expansion code is a mess?
This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset.
The first indicates whether it is expanding a memset or a memcpy / memmove.
The later is whether the memset is a memset of zero. It's totally possible
(likely even) that targets may want to do different things for memcpy and
memset of zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169959
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NAKAMURA Takumi [Wed, 12 Dec 2012 01:41:01 +0000 (01:41 +0000)]
llvm/test/CodeGen/X86/store_op_load_fold.ll: Fix typo, s/CHECK_NEXT/CHECK-NEXT/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169957
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NAKAMURA Takumi [Wed, 12 Dec 2012 01:40:56 +0000 (01:40 +0000)]
llvm/test/CodeGen/X86/store_op_load_fold.ll: Add explicit triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169956
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Nadav Rotem [Wed, 12 Dec 2012 01:33:47 +0000 (01:33 +0000)]
Fix the ascii drawing that was ruined when I split the H and CPP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169955
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Evan Cheng [Wed, 12 Dec 2012 01:32:07 +0000 (01:32 +0000)]
- Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.
Also added more comments to explain why it is generally ok to return true.
- Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to
be true for loaded source (memcpy) or zero constants (memset). The poor name
choice is probably some kind of legacy issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169954
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Nadav Rotem [Wed, 12 Dec 2012 01:31:10 +0000 (01:31 +0000)]
fix a typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169953
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Manman Ren [Wed, 12 Dec 2012 01:13:50 +0000 (01:13 +0000)]
DAGCombine: clamp hi bit in APInt::getBitsSet to avoid assertion
rdar://
12838504
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169951
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Nadav Rotem [Wed, 12 Dec 2012 01:11:46 +0000 (01:11 +0000)]
LoopVectorizer: When -Os is used, vectorize only loops that dont require a tail loop. There is no testcase because I dont know of a way to initialize the loop vectorizer pass without adding an additional hidden flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169950
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Evan Cheng [Wed, 12 Dec 2012 00:42:09 +0000 (00:42 +0000)]
Avoid using lossy load / stores for memcpy / memset expansion. e.g.
f64 load / store on non-SSE2 x86 targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169944
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Michael Ilseman [Wed, 12 Dec 2012 00:29:16 +0000 (00:29 +0000)]
Have SimplifyBinOp call the new FAdd/FSub/FMul helpers, with fast-math flags off
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169943
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Shuxin Yang [Wed, 12 Dec 2012 00:29:03 +0000 (00:29 +0000)]
- Fix a problematic way in creating all-the-1 APInt.
- Propagate "exact" bit of [l|a]shr instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169942
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Michael Ilseman [Wed, 12 Dec 2012 00:28:32 +0000 (00:28 +0000)]
Remove redunant optimizations from InstCombine, instead call the appropriate functions from SimplifyInstruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169941
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Michael Ilseman [Wed, 12 Dec 2012 00:27:46 +0000 (00:27 +0000)]
Added a slew of SimplifyInstruction floating-point optimizations, many of which take advantage of fast-math flags. Test cases included.
fsub X, +0 ==> X
fsub X, -0 ==> X, when we know X is not -0
fsub +/-0.0, (fsub -0.0, X) ==> X
fsub nsz +/-0.0, (fsub +/-0.0, X) ==> X
fsub nnan ninf X, X ==> 0.0
fadd nsz X, 0 ==> X
fadd [nnan ninf] X, (fsub [nnan ninf] 0, X) ==> 0
where nnan and ninf have to occur at least once somewhere in this expression
fmul X, 1.0 ==> X
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169940
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Michael Ilseman [Wed, 12 Dec 2012 00:23:43 +0000 (00:23 +0000)]
Pattern matchers for floating point values
m_ConstantFP - match and bind a float constant
m_SpecificConstantFP - match a specific floating point value or vector of floats of that value
m_FPOne - match a floating point 1.0 or vector of 1.0s
m_NegZero - match -0.0
m_AnyZero - match 0 or -0.0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169939
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Michael Ilseman [Wed, 12 Dec 2012 00:21:43 +0000 (00:21 +0000)]
Remove FIXMEs surrounding Constant[Data]Vectors, instead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169938
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Jim Grosbach [Tue, 11 Dec 2012 23:39:51 +0000 (23:39 +0000)]
Trim unneeded header #include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169933
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Dmitri Gribenko [Tue, 11 Dec 2012 23:35:23 +0000 (23:35 +0000)]
Documentation: cleanup: remove useless anchors and write :ref:s explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169932
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Jim Grosbach [Tue, 11 Dec 2012 23:31:12 +0000 (23:31 +0000)]
ARM: Remove old testing option.
Pre-regalloc frame allocation and referencing has been on by default
for ages. No need for the testing option that disables it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169931
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Jim Grosbach [Tue, 11 Dec 2012 23:31:10 +0000 (23:31 +0000)]
ARM: Remove old testing options.
Base pointer referencing has been enabled for ages.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169930
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Evan Cheng [Tue, 11 Dec 2012 23:26:14 +0000 (23:26 +0000)]
Replace TargetLowering::isIntImmLegal() with
ScalarTargetTransformInfo::getIntImmCost() instead. "Legal" is a poorly defined
term for something like integer immediate materialization. It is always possible
to materialize an integer immediate. Whether to use it for memcpy expansion is
more a "cost" conceern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169929
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Dmitri Gribenko [Tue, 11 Dec 2012 23:13:23 +0000 (23:13 +0000)]
Documentation: Lexicon.rst: add 'SLP' acronym
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169928
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Nadav Rotem [Tue, 11 Dec 2012 21:30:14 +0000 (21:30 +0000)]
PR14574. Fix a bug in the code that calculates the mask the converted PHIs in if-conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169916
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Tom Stellard [Tue, 11 Dec 2012 21:25:42 +0000 (21:25 +0000)]
Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915
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Bill Schmidt [Tue, 11 Dec 2012 20:30:11 +0000 (20:30 +0000)]
This patch implements the general dynamic TLS model for 64-bit PowerPC.
Given a thread-local symbol x with global-dynamic access, the generated
code to obtain x's address is:
Instruction Relocation Symbol
addis ra,r2,x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x
addi r3,ra,x@got@tlsgd@l R_PPC64_GOT_TLSGD16_L x
bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x
R_PPC64_REL24 __tls_get_addr
nop
<use address in r3>
The implementation borrows from the medium code model work for introducing
special forms of ADDIS and ADDI into the DAG representation. This is made
slightly more complicated by having to introduce a call to the external
function __tls_get_addr. Using the full call machinery is overkill and,
more importantly, makes it difficult to add a special relocation. So I've
introduced another opcode GET_TLS_ADDR to represent the function call, and
surrounded it with register copies to set up the parameter and return value.
Most of the code is pretty straightforward. I ran into one peculiarity
when I introduced a new PPC opcode BL8_NOP_ELF_TLSGD, which is just like
BL8_NOP_ELF except that it takes another parameter to represent the symbol
("x" above) that requires a relocation on the call. Something in the
TblGen machinery causes BL8_NOP_ELF and BL8_NOP_ELF_TLSGD to be treated
identically during the emit phase, so this second operand was never
visited to generate relocations. This is the reason for the slightly
messy workaround in PPCMCCodeEmitter.cpp:getDirectBrEncoding().
Two new tests are included to demonstrate correct external assembly and
correct generation of relocations using the integrated assembler.
Comments welcome!
Thanks,
Bill
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169910
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Eric Christopher [Tue, 11 Dec 2012 19:42:09 +0000 (19:42 +0000)]
Update some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169907
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Nadav Rotem [Tue, 11 Dec 2012 18:58:10 +0000 (18:58 +0000)]
Loop Vectorize: optimize the vectorization of trunc(induction_var). The truncation is now done on scalars.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169904
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Eli Bendersky [Tue, 11 Dec 2012 17:16:00 +0000 (17:16 +0000)]
Remove the RelaxAll overrule in MCAssembler::fixupNeedsRelaxation,
because that method is only getting called for MCInstFragment. These
fragments aren't even generated when RelaxAll is set, which is why the
flag reference here is superfluous. Removing it simplifies the code
with no harmful effects.
An assertion is added higher up to make sure this path is never
reached.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169886
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Rafael Espindola [Tue, 11 Dec 2012 16:36:02 +0000 (16:36 +0000)]
Use an ArrayRef instead of a std::vector&.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169881
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Joel Jones [Tue, 11 Dec 2012 16:10:25 +0000 (16:10 +0000)]
Add comment for load folding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169880
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Dmitri Gribenko [Tue, 11 Dec 2012 15:29:37 +0000 (15:29 +0000)]
Documentation: convert Passes.html to reST.
Since now we have an autogenerated TOC, a manually written table of all passes
was removed.
Patch by Anthony Mykhailenko with small fixes by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169867
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NAKAMURA Takumi [Tue, 11 Dec 2012 13:14:16 +0000 (13:14 +0000)]
llvm/test/TableGen: Remove XFAIL:vg_leak in dozen of tests, according to llvm-x86_64-linux-vg_leak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169862
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Evgeniy Stepanov [Tue, 11 Dec 2012 12:34:09 +0000 (12:34 +0000)]
[msan] Use explicitely aligned stores and loads with function argument shadow.
Use explicitely aligned store and load instructions to deal with argument and
retval shadow. This matters when an argument's alignment is higher than
__msan_param_tls alignment (which is the case with __m128i).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169859
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Patrik Hagglund [Tue, 11 Dec 2012 11:14:33 +0000 (11:14 +0000)]
Revert EVT->MVT changes, r169836-169851, due to buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169854
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Chandler Carruth [Tue, 11 Dec 2012 11:05:15 +0000 (11:05 +0000)]
Holding my nose and moving the accumulation routine to GEPOperator
instead of the instruction. I've left a forwarding wrapper for the
instruction so users with the instruction don't need to create
a GEPOperator themselves.
This lets us remove the copy of this code in instsimplify.
I've looked at most of the other copies of similar code, and this is the
only one I've found that is actually exactly the same. The one in
InlineCost is very close, but it requires re-mapping non-constant
indices through the cost analysis value simplification map. I could add
direct support for this to the generic routine, but it seems overly
specific.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169853
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Chandler Carruth [Tue, 11 Dec 2012 10:29:10 +0000 (10:29 +0000)]
Hoist the GEP constant address offset computation to a common home on
the GEP instruction class.
This is part of the continued refactoring and cleaning of the
infrastructure used by SROA. This particular operation is also done in
a few other places which I'll try to refactor to share this
implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169852
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Patrik Hagglund [Tue, 11 Dec 2012 10:24:48 +0000 (10:24 +0000)]
Change RegVT in BitTestBlock and RegsForValue, to contain MVTs,
instead of EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169851
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Patrik Hagglund [Tue, 11 Dec 2012 10:20:51 +0000 (10:20 +0000)]
Change TargetLowering::getTypeForExtArgOrReturn to take and return
MVTs, instead of EVTs.
Accordingly, add bitsLT (and similar) to MVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169850
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Patrik Hagglund [Tue, 11 Dec 2012 10:16:19 +0000 (10:16 +0000)]
Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT,
from EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169849
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Patrik Hagglund [Tue, 11 Dec 2012 10:09:23 +0000 (10:09 +0000)]
Change TargetLowering::RegisterTypeForVT to contain MVTs, instead of
EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169848
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Patrik Hagglund [Tue, 11 Dec 2012 10:05:04 +0000 (10:05 +0000)]
Change TargetLowering::TransformToType to contain MVTs, instead of
EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169847
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Patrik Hagglund [Tue, 11 Dec 2012 10:00:35 +0000 (10:00 +0000)]
Change TargetLowering::getRepRegClassCostFor, getIndexedLoadAction,
getIndexedStoreAction, and addRegisterClass to take an MVT, instead
of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169846
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Patrik Hagglund [Tue, 11 Dec 2012 09:57:18 +0000 (09:57 +0000)]
Change TargetLowering::findRepresentativeClass to take an MVT, instead
of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169845
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Patrik Hagglund [Tue, 11 Dec 2012 09:54:23 +0000 (09:54 +0000)]
Change TargetLowering::getTypeToPromoteTo to take and return MVTs,
instead of EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169844
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Patrik Hagglund [Tue, 11 Dec 2012 09:51:27 +0000 (09:51 +0000)]
Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169843
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Patrik Hagglund [Tue, 11 Dec 2012 09:48:14 +0000 (09:48 +0000)]
Change TargetLowering::getCondCodeAction to take an MVT, instead of
EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169842
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Patrik Hagglund [Tue, 11 Dec 2012 09:42:24 +0000 (09:42 +0000)]
Change TargetLowering::getTruncStoreAction to take MVTs, instead of EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169841
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Patrik Hagglund [Tue, 11 Dec 2012 09:39:09 +0000 (09:39 +0000)]
Change TargetLowering::getLoadExtAction to take an MVT, instead of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169840
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Patrik Hagglund [Tue, 11 Dec 2012 09:32:56 +0000 (09:32 +0000)]
Change TargetLowering::setTypeAction to take an MVT, instead fo EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169839
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Patrik Hagglund [Tue, 11 Dec 2012 09:31:43 +0000 (09:31 +0000)]
Change TargetLowering::getRepRegClassFor to take an MVT, instead of
EVT.
Accordingly, change RegDefIter to contain MVTs instead of EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169838
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Patrik Hagglund [Tue, 11 Dec 2012 09:10:33 +0000 (09:10 +0000)]
Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.
This is the first, in a series of patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169837
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Hao Liu [Tue, 11 Dec 2012 06:25:18 +0000 (06:25 +0000)]
revert the test change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169823
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Hao Liu [Tue, 11 Dec 2012 06:22:54 +0000 (06:22 +0000)]
A newbie try a test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169821
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NAKAMURA Takumi [Tue, 11 Dec 2012 05:53:54 +0000 (05:53 +0000)]
[CMake] Remove dependencies to intrinsics_gen I introduced in r169724.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169819
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NAKAMURA Takumi [Tue, 11 Dec 2012 05:53:43 +0000 (05:53 +0000)]
llvm/Target/TargetMachine.h: Remove two dependent headers.
-#include "llvm/Target/TargetTransformImpl.h"
-#include "llvm/TargetTransformInfo.h"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169818
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NAKAMURA Takumi [Tue, 11 Dec 2012 05:53:37 +0000 (05:53 +0000)]
llvm/tools: Add #include "llvm/TargetTransformInfo.h"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169817
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Jyotsna Verma [Tue, 11 Dec 2012 05:12:25 +0000 (05:12 +0000)]
Use multiclass for new-value store instructions with MEMri operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169814
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Nadav Rotem [Tue, 11 Dec 2012 04:55:10 +0000 (04:55 +0000)]
Fix PR14565. Don't if-convert loops that have switch statements in them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169813
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Rafael Espindola [Tue, 11 Dec 2012 03:10:43 +0000 (03:10 +0000)]
Change some functions to take const pointers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169812
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Evan Cheng [Tue, 11 Dec 2012 02:31:57 +0000 (02:31 +0000)]
Stylistic tweak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169811
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Chad Rosier [Tue, 11 Dec 2012 00:51:36 +0000 (00:51 +0000)]
Add a triple to this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169803
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Chandler Carruth [Tue, 11 Dec 2012 00:36:57 +0000 (00:36 +0000)]
Fix a miscompile in the DAG combiner. Previously, we would incorrectly
try to reduce the width of this load, and would end up transforming:
(truncate (lshr (sextload i48 <ptr> as i64), 32) to i32)
to
(truncate (zextload i32 <ptr+4> as i64) to i32)
We lost the sext attached to the load while building the narrower i32
load, and replaced it with a zext because lshr always zext's the
results. Instead, bail out of this combine when there is a conflict
between a sextload and a zext narrowing. The rest of the DAG combiner
still optimize the code down to the proper single instruction:
movswl 6(...),%eax
Which is exactly what we wanted. Previously we read past the end *and*
missed the sign extension:
movl 6(...), %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169802
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Paul Redmond [Tue, 11 Dec 2012 00:36:43 +0000 (00:36 +0000)]
move X86-specific test
This test case uses -mcpu=corei7 so it belongs in CodeGen/X86
Reviewed by: Nadav
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169801
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Bill Wendling [Tue, 11 Dec 2012 00:23:07 +0000 (00:23 +0000)]
Fix grammar-o.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169798
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Chad Rosier [Tue, 11 Dec 2012 00:18:02 +0000 (00:18 +0000)]
Fall back to the selection dag isel to select tail calls.
This shouldn't affect codegen for -O0 compiles as tail call markers are not
emitted in unoptimized compiles. Testing with the external/internal nightly
test suite reveals no change in compile time performance. Testing with -O1,
-O2 and -O3 with fast-isel enabled did not cause any compile-time or
execution-time failures. All tests were performed on my x86 machine.
I'll monitor our arm testers to ensure no regressions occur there.
In an upcoming clang patch I will be marking the objc_autoreleaseReturnValue
and objc_retainAutoreleaseReturnValue as tail calls unconditionally. While
it's theoretically true that this is just an optimization, it's an
optimization that we very much want to happen even at -O0, or else ARC
applications become substantially harder to debug.
Part of rdar://
12553082
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169796
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Eric Christopher [Mon, 10 Dec 2012 23:34:43 +0000 (23:34 +0000)]
Refactor out the abbreviation handling into a separate class that
controls each of the abbreviation sets (only a single one at the
moment) and computes offsets separately as well for each set
of DIEs.
No real function change, ordering of abbreviations for the skeleton
CU changed but only because we're computing in a separate order. Fix
the testcase not to care.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169793
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Evan Cheng [Mon, 10 Dec 2012 23:21:26 +0000 (23:21 +0000)]
Some enhancements for memcpy / memset inline expansion.
1. Teach it to use overlapping unaligned load / store to copy / set the trailing
bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies.
2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g.
x86 and ARM.
3. When memcpy from a constant string, do *not* replace the load with a constant
if it's not possible to materialize an integer immediate with a single
instruction (required a new target hook: TLI.isIntImmLegal()).
4. Use unaligned load / stores more aggressively if target hooks indicates they
are "fast".
5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8.
Also increase the threshold to something reasonable (8 for memset, 4 pairs
for memcpy).
This significantly improves Dhrystone, up to 50% on ARM iOS devices.
rdar://
12760078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169791
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Arnold Schwaighofer [Mon, 10 Dec 2012 23:02:41 +0000 (23:02 +0000)]
Optimistically analyse Phi cycles
Analyse Phis under the starting assumption that they are NoAlias. Recursively
look at their inputs.
If they MayAlias/MustAlias there must be an input that makes them so.
Addresses bug 14351.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169788
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Lang Hames [Mon, 10 Dec 2012 22:49:11 +0000 (22:49 +0000)]
Defer call to InitSections until after MCContext has been initialized. If
InitSections is called before the MCContext is initialized it could cause
duplicate temporary symbols to be emitted later (after context initialization
resets the temporary label counter).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169785
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Anshuman Dasgupta [Mon, 10 Dec 2012 22:45:57 +0000 (22:45 +0000)]
Fix PR14568: Avoid the DFA packetizer from making an invalid read
beyond array bounds.
No test case since I cannot reproduce an ICE with this bug. According
to Carlos -- the bug reporter -- a segfault occurs only when LLVM is
compiled with a specific version of GCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169783
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Eric Christopher [Mon, 10 Dec 2012 22:25:41 +0000 (22:25 +0000)]
Rearrange vars and make comments more obvious.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169780
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Eric Christopher [Mon, 10 Dec 2012 22:25:38 +0000 (22:25 +0000)]
Remove blank line at top of file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169779
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Eric Christopher [Mon, 10 Dec 2012 22:00:20 +0000 (22:00 +0000)]
Fix a coding style nit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169776
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Nadav Rotem [Mon, 10 Dec 2012 21:45:01 +0000 (21:45 +0000)]
Enable the loop vectorizer only on O2 and above. (Still disabled by default)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169774
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Tom Stellard [Mon, 10 Dec 2012 21:41:58 +0000 (21:41 +0000)]
LegalizeDAG: Allow type promotion of scalar loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169773
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Tom Stellard [Mon, 10 Dec 2012 21:41:54 +0000 (21:41 +0000)]
LegalizeDAG: Allow type promotion for scalar stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169772
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Nadav Rotem [Mon, 10 Dec 2012 21:39:02 +0000 (21:39 +0000)]
Split the LoopVectorizer into H and CPP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169771
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Bill Wendling [Mon, 10 Dec 2012 21:33:45 +0000 (21:33 +0000)]
Revert r169656.
The linker will call `lto_codegen_add_must_preserve_symbol' on all globals that
should be kept around. The linker will pretend that a dylib is being created.
<rdar://problem/
12528059>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169770
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Eli Bendersky [Mon, 10 Dec 2012 20:36:01 +0000 (20:36 +0000)]
Add a test for explicitly exercising the mc-relax-all flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169764
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Eli Bendersky [Mon, 10 Dec 2012 20:13:43 +0000 (20:13 +0000)]
Cleanup formatting, comments and naming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169762
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Akira Hatanaka [Mon, 10 Dec 2012 20:04:40 +0000 (20:04 +0000)]
[mips] Set HWEncoding field of registers. Use delete function
getMipsRegisterNumbering and use MCRegisterInfo::getEncodingValue instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169760
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Eric Christopher [Mon, 10 Dec 2012 19:51:21 +0000 (19:51 +0000)]
Use the somewhat semantic term "split dwarf" it more matches what's
going on and makes a lot of the terminology in comments make more sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169758
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Eric Christopher [Mon, 10 Dec 2012 19:51:18 +0000 (19:51 +0000)]
Delete the FissionCU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169757
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Eric Christopher [Mon, 10 Dec 2012 19:51:13 +0000 (19:51 +0000)]
Reorder fission variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169756
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Bill Wendling [Mon, 10 Dec 2012 19:46:49 +0000 (19:46 +0000)]
Don't use a red zone for code coverage if the user specified `-mno-red-zone'.
The `-mno-red-zone' flag wasn't being propagated to the functions that code
coverage generates. This allowed some of them to use the red zone when that
wasn't allowed.
<rdar://problem/
12843084>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169754
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Nadav Rotem [Mon, 10 Dec 2012 19:25:06 +0000 (19:25 +0000)]
Add support for reverse induction variables. For example:
while (i--)
sum+=A[i];
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169752
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Jim Grosbach [Mon, 10 Dec 2012 19:03:37 +0000 (19:03 +0000)]
CMake: Don't run 'git svn' if there is no .git/svn directory.
If the local checkout does not have 'git svn' references set up, don't try
to use 'git svn' for version information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169749
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Eli Bendersky [Mon, 10 Dec 2012 18:59:39 +0000 (18:59 +0000)]
This patch adds statistics for other non-DWARF fragments emitted by
the assembler. This is useful in order to know how the numbers add up,
since in particular the Align fragments account for a non-trivial
portion of the emitted fragments (especially on -O0 which sets
relax-all).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169747
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Hal Finkel [Mon, 10 Dec 2012 18:49:16 +0000 (18:49 +0000)]
Use GetUnderlyingObjects in misched
misched used GetUnderlyingObject in order to break false load/store
dependencies, and the -enable-aa-sched-mi feature similarly relied on
GetUnderlyingObject in order to ensure it is safe to use the aliasing analysis.
Unfortunately, GetUnderlyingObject does not recurse through phi nodes, and so
(especially due to LSR) all of these mechanisms failed for
induction-variable-dependent loads and stores inside loops.
This change replaces uses of GetUnderlyingObject with GetUnderlyingObjects
(which will recurse through phi and select instructions) in misched.
Andy reviewed, tested and simplified this patch; Thanks!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169744
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Sean Silva [Mon, 10 Dec 2012 18:37:26 +0000 (18:37 +0000)]
Fix funky copy-pasted grammatical error.
PR14343
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169742
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Chandler Carruth [Mon, 10 Dec 2012 18:23:52 +0000 (18:23 +0000)]
Revert "Make '-mtune=x86_64' assume fast unaligned memory accesses."
Accidental commit... git svn betrayed me. Sorry for the noise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169741
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Chandler Carruth [Mon, 10 Dec 2012 18:22:42 +0000 (18:22 +0000)]
Make '-mtune=x86_64' assume fast unaligned memory accesses.
Summary:
Not all chips targeted by x86_64 have this feature, but a dramatically
increasing number do. Specifying a chip-specific tuning parameter will
continue to turn the feature on or off as appropriate for that
particular chip, but the generic flag should try to achieve the best
performance on the most widely available hardware. Today, the number of
chips with fast UA access dwarfs those without in the x86-64 space.
Note that this also brings LLVM's code generation for this '-march' flag
more in line with that of modern GCCs.
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D195
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169740
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Chandler Carruth [Mon, 10 Dec 2012 18:22:40 +0000 (18:22 +0000)]
Fix a typo in my previous commit -- bloomfield is 0x1A not 0x2A.
Thanks to the PaX folks for noticing in review! We need some tests here,
any sugestions welcome...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169739
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Chandler Carruth [Mon, 10 Dec 2012 09:18:44 +0000 (09:18 +0000)]
Address a FIXME and update the fast unaligned memory feature for newer
Intel chips.
The model number rules were determined by inspecting Intel's
documentation for their newer chip model numbers. My understanding is
that all of the newer Intel chips have fast unaligned memory access, but
if anyone is concerned about a particular chip, just shout.
No tests updated; it's not clear we have dedicated tests for the chips'
various features, but if anyone would like tests (or can point me at
some existing ones), I'm happy to oblige.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169730
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Chandler Carruth [Mon, 10 Dec 2012 08:28:39 +0000 (08:28 +0000)]
Add a new visitor for walking the uses of a pointer value.
This visitor provides infrastructure for recursively traversing the
use-graph of a pointer-producing instruction like an alloca or a malloc.
It maintains a worklist of uses to visit, so it can handle very deep
recursions. It automatically looks through instructions which simply
translate one pointer to another (bitcasts and GEPs). It tracks the
offset relative to the original pointer as long as that offset remains
constant and exposes it during the visit as an APInt offset. Finally, it
performs conservative escape analysis.
However, currently it has some limitations that should be addressed
going forward:
1) It doesn't handle vectors of pointers.
2) It doesn't provide a cheaper visitor when the constant offset
tracking isn't needed.
3) It doesn't support non-instruction pointer values.
The current functionality is exactly what is required to implement the
SROA pointer-use visitors in terms of this one, rather than in terms of
their own ad-hoc base visitor, which was always very poorly specified.
SROA has been converted to use this, and the code there deleted which
this utility now provides.
Technically speaking, using this new visitor allows SROA to handle a few
more cases than it previously did. It is now more aggressive in ignoring
chains of instructions which look like they would defeat SROA, but in
fact do not because they never result in a read or write of memory.
While this is "neat", it shouldn't be interesting for real programs as
any such chains should have been removed by others passes long before we
get to SROA. As a consequence, I've not added any tests for these
features -- it shouldn't be part of SROA's contract to perform such
heroics.
The goal is to extend the functionality of this visitor going forward,
and re-use it from passes like ASan that can benefit from doing
a detailed walk of the uses of a pointer.
Thanks to Ben Kramer for the code review rounds and lots of help
reviewing and debugging this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169728
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Craig Topper [Mon, 10 Dec 2012 08:12:29 +0000 (08:12 +0000)]
Teach DAG combine to handle vector add/sub with vectors of all 0s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169727
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NAKAMURA Takumi [Mon, 10 Dec 2012 07:14:29 +0000 (07:14 +0000)]
[CMake] TARGET_TRIPLE may be internal alias of LLVM_DEFAULT_TARGET_TRIPLE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169726
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NAKAMURA Takumi [Mon, 10 Dec 2012 05:27:15 +0000 (05:27 +0000)]
[CMake] Update dependencies to intrinsics_gen corresponding to r169711.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169724
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