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Konstantin Zhuravlyov [Fri, 4 May 2018 22:53:55 +0000 (22:53 +0000)]
AMDGPU/NFC: Update D16PreservesUnusedBits description based Tony Tye's comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331564
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Philip Reames [Fri, 4 May 2018 21:35:00 +0000 (21:35 +0000)]
[LICM] Compute a must execute property for the prefix of the header as we go
Computing this property within the existing walk ensures that the cost is linear with the size of the block. If we did this from within isGuaranteedToExecute, it would be quadratic without some very fancy caching.
This allows us to reliably catch a hoistable instruction within a header which may throw at some point *after* our hoistable instruction. It doesn't do anything for non-header cases, but given how common single block loops are, this seems very worthwhile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331557
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Konstantin Zhuravlyov [Fri, 4 May 2018 20:21:31 +0000 (20:21 +0000)]
AMDGPU/NFC: Fix formatting for 900, 902 ISA Version features
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331553
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Konstantin Zhuravlyov [Fri, 4 May 2018 20:06:57 +0000 (20:06 +0000)]
AMDGPU: Add D16 instructions preserve unused bits feature
- Predicate D16 patterns on this new feature
- Added this new feature to gfx900/2/4
Differential Revision: https://reviews.llvm.org/D46366
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331551
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Geoff Berry [Fri, 4 May 2018 19:25:09 +0000 (19:25 +0000)]
[MachineLICM] Debug intrinsics shouldn't affect hoist decisions
Summary:
When checking if an instruction stores to a given frame index, check
that the instruction can write to memory before looking at the memory
operands list to avoid e.g. DBG_VALUE instructions that reference a
frame index preventing a load from that index from being hoisted.
Reviewers: dblaikie, MatzeB, qcolombet, reames, javed.absar
Subscribers: mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D46284
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331549
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Shoaib Meenai [Fri, 4 May 2018 19:03:11 +0000 (19:03 +0000)]
[ObjCARC] Account for catchswitch in bitcast insertion
A catchswitch is both a pad and a terminator, meaning it must be the
only non-phi instruction in its basic block. When we're inserting a
bitcast in the incoming basic block for a phi, if that incoming block is
a catchswitch, we should go up the dominator tree to find a valid
insertion point rather than attempting to insert before the catchswitch
(which would result in invalid IR).
Differential Revision: https://reviews.llvm.org/D46412
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331548
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Michael Berg [Fri, 4 May 2018 18:48:20 +0000 (18:48 +0000)]
Fast Math Flag mapping into SDNode
Summary: Adding support for Fast flags in the SDNode to leverage fast math sub flag usage.
Reviewers: spatel, arsenm, jbhateja, hfinkel, escha, qcolombet, echristo, wristow, javed.absar
Reviewed By: spatel
Subscribers: llvm-commits, rampitec, nhaehnle, tstellar, FarhanaAleen, nemanjai, javed.absar, jbhateja, hfinkel, wdng
Differential Revision: https://reviews.llvm.org/D45710
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331547
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Simon Pilgrim [Fri, 4 May 2018 18:16:13 +0000 (18:16 +0000)]
[X86] Add WriteEMMS scheduler class
Filled in the missing values from Btver2 SoG or Agner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331546
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Simon Pilgrim [Fri, 4 May 2018 17:47:46 +0000 (17:47 +0000)]
[X86] Finish splitting WriteVecShift and WriteVecIMul to remove InstRW overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331543
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Craig Topper [Fri, 4 May 2018 17:39:08 +0000 (17:39 +0000)]
[LoopIdiomRecognize] Don't create an IRBuilder just to call getTrue/getFalse.
We can call the methods in ConstantInt directly. We just need a context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331542
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Adhemerval Zanella [Fri, 4 May 2018 17:21:26 +0000 (17:21 +0000)]
[AArch64] Add missing testcase for r331522
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331541
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Matt Davis [Fri, 4 May 2018 17:19:40 +0000 (17:19 +0000)]
[llvm-mca] Add descriptive names for the TimelineView report characters. NFC.
Summary:
This change makes the TimelineView source simpler to read and easier to modify in the future.
This patch introduces a class of static chars used as the display values in the TimelineView report, this change just eliminates a few magic characters.
Reviewers: andreadb, courbet, RKSimon
Reviewed By: andreadb
Subscribers: tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D46409
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331540
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Peter Collingbourne [Fri, 4 May 2018 16:45:57 +0000 (16:45 +0000)]
Object: The default alignment of a section without alignment flags is 16.
Differential Revision: https://reviews.llvm.org/D46420
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331538
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Peter Collingbourne [Fri, 4 May 2018 16:28:41 +0000 (16:28 +0000)]
obj2yaml: Correctly round-trip default alignment.
Previously we were emitting the "cooked" alignment, which made it hard
to distinguish between that and the default alignment.
Differential Revision: https://reviews.llvm.org/D46418
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331537
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Adrian Prantl [Fri, 4 May 2018 16:10:43 +0000 (16:10 +0000)]
DwarfCompileUnit: Fix another assertion failure on malformed input
that is not rejected by the Verifier.
Thanks to Björn Pettersson for providing a reproducer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331535
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Clement Courbet [Fri, 4 May 2018 15:26:12 +0000 (15:26 +0000)]
[llvm-exegesis] Fix pfm counter names for BDW.
Summary: They are not consistent with other microarchitectures.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D46434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331532
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Simon Pilgrim [Fri, 4 May 2018 15:20:18 +0000 (15:20 +0000)]
[X86] Cleanup SchedWriteFMA classes and use X86SchedWriteWidths directly.
Rename scalar and XMM versions, this is to match/simplify an upcoming change to split MUL/DIV/SQRT scalar/xmm/ymm/zmm classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331531
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David Bolvansky [Fri, 4 May 2018 15:14:00 +0000 (15:14 +0000)]
[bindings/go] Add Go bindings for volatile loads/stores
Reviewers: whitequark
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331530
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Krzysztof Parzyszek [Fri, 4 May 2018 15:07:30 +0000 (15:07 +0000)]
[Hexagon] Remove leftover debugging code after r331527
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331528
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Krzysztof Parzyszek [Fri, 4 May 2018 15:04:48 +0000 (15:04 +0000)]
[Hexagon] Handle non-immediate constants in HexagonSplitDouble
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331527
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Simon Dardis [Fri, 4 May 2018 15:00:54 +0000 (15:00 +0000)]
[mips] Correct the predicates of sign extension instructions
And eliminatw the duplication of those instructions for microMIPS32r6.
Reviewers: smaksimovic, abeserminji, atanasyan
Differential Revision: https://reviews.llvm.org/D46117
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331526
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Simon Pilgrim [Fri, 4 May 2018 14:54:33 +0000 (14:54 +0000)]
[X86] Add WriteVecMOVMSKY scheduler class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331525
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Adhemerval Zanella [Fri, 4 May 2018 14:33:55 +0000 (14:33 +0000)]
[AArch64] Custom Lower MULLH{S,U} for v16i8, v8i16, and v4i32
This patch adds a custom lowering for ISD::MULH{S,U} used on divide by
constant optimization (DAGCombiner::BuildSDIV and DAGCombiner::BuildUDIV).
New patterns for smull and umull are added, so AArch64ISD::{S,U}MULL
can be correctly lowered to smull2 and umull2.
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46009
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331522
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Krzysztof Parzyszek [Fri, 4 May 2018 13:59:05 +0000 (13:59 +0000)]
[Hexagon] Skip reserved physical registers when updating liveness
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331518
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Andrea Di Biagio [Fri, 4 May 2018 13:52:12 +0000 (13:52 +0000)]
[llvm-mca] use colors for warnings and notes generated by InstrBuilder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331517
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Andrea Di Biagio [Fri, 4 May 2018 13:10:10 +0000 (13:10 +0000)]
[llvm-mca] remove unused argument from method InstrBuilder::createInstrDescImpl.
We don't need to pass the instruction index to the method that constructs new
instruction descriptors.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331516
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Simon Pilgrim [Fri, 4 May 2018 12:59:24 +0000 (12:59 +0000)]
[X86] Add SchedWriteFRnd fp rounding scheduler classes
Split off from SchedWriteFAdd for fp rounding/bit-manipulation instructions.
Fixes an issue on btver2 which only had the ymm version using the JSTC pipe instead of JFPA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331515
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Jeremy Morse [Fri, 4 May 2018 10:05:10 +0000 (10:05 +0000)]
[X86] Add test case for PR30290s failing behaviour
Following the advice in review D45022, this currently tests for the broken llc
output where an instruction is mis-scheduled. This test is committed in advance
to improve the eventual fixing patch in D45022, making the bad behaviour that
that patch fixes clearer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331514
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Jeremy Morse [Fri, 4 May 2018 08:58:06 +0000 (08:58 +0000)]
Word wrap a test-file comment to 80 columns
This is a test commit to check whether my account works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331512
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Bjorn Pettersson [Fri, 4 May 2018 08:50:48 +0000 (08:50 +0000)]
[SelectionDAG] Refactor code by adding RegsForValue::getRegsAndSizes(). NFCI
Summary:
Added a helper method in RegsForValue to get a list with
all the <RegNumber, RegSize> pairs that we want to iterate
over in SelectionDAGBuilder::EmitFuncArgumentDbgValue and
in SelectionDAGBuilder::visitIntrinsicCall.
Reviewers: vsk
Reviewed By: vsk
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46360
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331510
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Jonas Paulsson [Fri, 4 May 2018 07:50:05 +0000 (07:50 +0000)]
[RegUsageInfoCollector] Bugfix for handling of register aliases.
Don't assume the alias of a defined reg is always already in the set.
As the test case in https://bugs.llvm.org/show_bug.cgi?id=36587 discovered,
it is wrong to assume that all the aliases of the defined register in the
*current function* is already present in the UsedPhysRegsMask.
This patch changes this so that any definition in the current function of a
phys-reg always results in all its aliases inserted into the set of defined
registers.
Review: Quentin Colombet
https://reviews.llvm.org/D45157
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331509
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Max Kazantsev [Fri, 4 May 2018 07:34:35 +0000 (07:34 +0000)]
[IRCE] Fix misuse of dyn_cast which leads to UB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331508
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Dean Michael Berris [Fri, 4 May 2018 06:01:12 +0000 (06:01 +0000)]
[XRay][compiler-rt+docs] Introduce __xray_log_init_mode(...).
Summary:
This addresses http://llvm.org/PR36790.
The change Deprecates a number of functions and types in
`include/xray/xray_log_interface.h` to recommend using string-based
configuration of XRay through the __xray_log_init_mode(...) function. In
particular, this deprecates the following:
- `__xray_set_log_impl(...)` -- users should instead use the
`__xray_log_register_mode(...)` and `__xray_log_select_mode(...)` APIs.
- `__xray_log_init(...)` -- users should instead use the
`__xray_log_init_mode(...)` function, which also requires using the
`__xray_log_register_mode(...)` and `__xray_log_select_mode(...)`
functionality.
- `__xray::FDRLoggingOptions` -- in following patches, we'll be
migrating the FDR logging implementations (and tests) to use the
string-based configuration. In later stages we'll remove the
`__xray::FDRLoggingOptions` type, and ask users to migrate to using the
string-based configuration mechanism instead.
- `__xray::BasicLoggingOptions` -- same as `__xray::FDRLoggingOptions`,
we'll be removing this type later and instead rely exclusively on the
string-based configuration API.
We also update the documentation to reflect the new advice and remove
some of the deprecated notes.
Reviewers: eizan, kpw, echristo, pelikan
Reviewed By: kpw
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46173
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331503
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Michael Zolotukhin [Fri, 4 May 2018 01:40:05 +0000 (01:40 +0000)]
[MachineCSE] Rewrite a loop checking if a block is in a set of blocks without using a set. NFC.
Summary:
Using a set is unnecessary here an in some cases (see e.g. PR37277)
takes significant amount of time to just insert values into it. In this
particular case all we need is just to check if we find the block we are
looking for or not.
Reviewers: davide
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D46411
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331502
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Craig Topper [Fri, 4 May 2018 01:04:28 +0000 (01:04 +0000)]
[LoopIdiomRecognize] Replace more unchecked dyn_casts with cast.
Two of these are immediately dereferenced on the next line. The other two are passed immediately to the IRBuilder constructor which can't handle a nullptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331500
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Craig Topper [Fri, 4 May 2018 01:04:26 +0000 (01:04 +0000)]
[LoopIdiomRecognize] Use a regular array instead of a SmallVector and explicit ArrayRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331499
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Craig Topper [Fri, 4 May 2018 01:04:24 +0000 (01:04 +0000)]
[LoopIdiomRecognize] Turn two uncheck dyn_casts into regular casts.
These are casts on users of a PHINode to Instruction. I think since PHINode is an Instruction any users would also be Instructions. At least a cast will give us an assertion if its wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331498
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Craig Topper [Thu, 3 May 2018 23:50:29 +0000 (23:50 +0000)]
[LoopIdiomRecognize] Add a test case to show incorrect transformation of an infinite loop with side effets into a countable loop using ctlz.
We currently recognize this idiom where x is signed and thus the shift in an ashr.
int cnt = 0;
while (x) {
x >>= 1; // arithmetic shift right
++cnt;
}
and turn it into (bitwidth - ctlz(x)). And if there is anything else in the loop we will create a new loop that runs that many times.
If x is initially negative, the shift result will never be 0 and thus the loop is infinite. If you put something with side effects in the loop, that side effect will now only happen bitwidth times instead of an infinite number of times.
So this transform is only safe for logical shift right (which we don't currently recognize) or if we can prove that x cannot be negative before the loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331493
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Tom Stellard [Thu, 3 May 2018 22:38:06 +0000 (22:38 +0000)]
AMDGPU: Make getSubRegFromChannel a static member of AMDGPURegisterInfo
Summary:
This makes is possible to have R600RegisterInfo and SIRegisterInfo
not inherit from AMDGPURegisterInfo.
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D46280
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331490
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Simon Pilgrim [Thu, 3 May 2018 22:31:19 +0000 (22:31 +0000)]
[X86] Add WriteDPPD/WriteDPPS dot product scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331489
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Simon Pilgrim [Thu, 3 May 2018 22:12:23 +0000 (22:12 +0000)]
[X86][Znver1] Use SchedAlias to tag microcoded scheduler classes
Avoids extra entries in the class tables.
Found a typo that missed the MMX_PHSUBSW instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331488
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Justin Bogner [Thu, 3 May 2018 21:59:13 +0000 (21:59 +0000)]
Fix include of config.h that was incorrectly changed in r331184
The RWMutex implementation depends on config.h macros (specifically
HAVE_PTHREAD_H and HAVE_PTHREAD_RWLOCK_INIT), so we need to be
including it and not just llvm-config.h here or we fall back to a much
slower implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331487
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Sanjay Patel [Thu, 3 May 2018 21:58:44 +0000 (21:58 +0000)]
[InstCombine] refine select-of-constants to bitwise ops
Add logic for the special case when a cmp+select can clearly be
reduced to just a bitwise logic instruction, and remove an
over-reaching chunk of general purpose bit magic. The primary goal
is to remove cases where we are not improving the IR instruction
count when doing these select transforms, and in all cases here that
is true.
In the motivating 3-way compare tests, there are further improvements
because we can combine/propagate select values (not sure if that
belongs in instcombine, but it's there for now).
DAGCombiner has folds to turn some of these selects into bit magic,
so there should be no difference in the end result in those cases.
Not all constant combinations are handled there yet, however, so it
is possible that some targets will see more cmov/csel codegen with
this change in IR canonicalization.
Ideally, we'll go further to *not* turn selects into multiple
logic/math ops in instcombine, and we'll canonicalize to selects.
But we should make sure that this step does not result in regressions
first (and if it does, we should fix those in the backend).
The general direction for this change was discussed here:
http://lists.llvm.org/pipermail/llvm-dev/2016-September/105373.html
http://lists.llvm.org/pipermail/llvm-dev/2017-July/114885.html
Alive proofs for the new bit magic:
https://rise4fun.com/Alive/XG7
Differential Revision: https://reviews.llvm.org/D46086
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331486
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Tom Stellard [Thu, 3 May 2018 21:44:16 +0000 (21:44 +0000)]
GlobalISel: Use a callback to compute constrained reg class for unallocatble registers
Summary:
constrainOperandRegClass() currently fails if it tries to constrain the
register class of an operand that is defeined with an unallocatable register
class. This patch resolves this by adding a target callback to compute
register constriants in this case.
This is required by the AMDGPU because many of its instructions have source opreands
defined with the unallocatable register classe VS_32 which is a union of two allocatable
register classes VGPR_32 and SReg_32.
Reviewers: dsanders, aditya_nandakumar
Reviewed By: aditya_nandakumar
Subscribers: rovka, kristof.beyls, tpr, llvm-commits
Differential Revision: https://reviews.llvm.org/D45991
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331485
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Teresa Johnson [Thu, 3 May 2018 20:24:12 +0000 (20:24 +0000)]
[ThinLTO] Add support for optimization remarks to thinBackend
Summary:
Support was added to the regular LTO backend, but not thinBackend.
This patch adds that support.
Reviewers: pcc, davide
Subscribers: mehdi_amini, inglorion, llvm-commits
Differential Revision: https://reviews.llvm.org/D46376
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331481
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Sanjay Patel [Thu, 3 May 2018 18:49:35 +0000 (18:49 +0000)]
[PowerPC] add more FMF debug output; NFC
We can't see all of the problems currently unless
we look at debug output when the global 'unsafe' is
on. It's a mess. This is another attempt to make
sure that D45710 is not making changes unintentionally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331476
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Simon Pilgrim [Thu, 3 May 2018 18:22:49 +0000 (18:22 +0000)]
[X86][AVX512] VPLZCNT instructions match SchedWriteVecIMul scheduling class not SchedWriteVecALU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331473
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Simon Pilgrim [Thu, 3 May 2018 17:56:43 +0000 (17:56 +0000)]
[X86] Split WriteVecShift/WriteVarVecShift into MMX, XMM and YMM/ZMM scheduler classes
This took a bit of extra work as on Intel targets the old (V)PSLLDrr/(V)PSLLDrm style instructions act differently - I ended up creating WriteVecShiftImm classes for XMM/YMM/ZMM vector shift by immediate and retaining WriteVecShift as the default (used only by MMX) plus WriteVecShiftX/WriteVecShiftY. X86SchedWriteWidths hides most of this thank goodness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331472
91177308-0d34-0410-b5e6-
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Sanjay Patel [Thu, 3 May 2018 17:41:37 +0000 (17:41 +0000)]
[PowerPC] add tests for FMF propagation; NFC
I'm choosing PPC out of convenience because it does
all of the transforms of interest in these tests by
default. There are multiple FMF problems shown in the
current checks. D45710 is proposing to fix part of
that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331471
91177308-0d34-0410-b5e6-
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Bjorn Pettersson [Thu, 3 May 2018 17:04:21 +0000 (17:04 +0000)]
[DebugInfo] Correction for an assert in DIExpression::createFragmentExpression
Summary:
When we create a fragment expression, and there already is an
old fragment expression, we assert that the new fragment is
within the range for the old fragment.
If for example the old fragment expression says that we
describe bit 10-16 of a variable (Offset=10, Size=6),
and we now want to create a new fragment expression only
describing bit 3-6 of the original value, then the resulting
fragment expression should have Offset=13, Size=3.
The assert is supposed to catch if the resulting fragment
expression is outside the range for the old fragment. However,
it used to verify that the Offset+Size of the new fragment was
smaller or equal than Offset+Size for the old fragment. What
we really want to check is that Offset+Size of the new fragment
is smaller than the Size of the old fragment.
Reviewers: aprantl, vsk
Reviewed By: aprantl
Subscribers: davide, llvm-commits, JDevlieghere
Differential Revision: https://reviews.llvm.org/D46391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331465
91177308-0d34-0410-b5e6-
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Bjorn Pettersson [Thu, 3 May 2018 17:04:16 +0000 (17:04 +0000)]
Reapply "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)"
Summary:
This reverts SVN r331441 (reapplies r331337), together with a fix
in to handle an already existing fragment expression in the
dbg.value that must be fragmented due to a split PHI node.
This should solve the problem seen in PR37321, which was the
reason for the revert of r331337.
The situation in PR37321 is that we have a PHI node like this
%u.sroa = phi i80 [ %u.sroa.x, %if.x ],
[ %u.sroa.y, %if.y ],
[ %u.sroa.z, %if.z ]
and a dbg.value like this
call void @llvm.dbg.value(metadata i80 %u.sroa,
metadata !13,
metadata !DIExpression(DW_OP_LLVM_fragment, 0, 80))
The phi node is split into three 32-bit PHI nodes
%30:gr32 = PHI %11:gr32, %bb.4, %14:gr32, %bb.5, %27:gr32, %bb.8
%31:gr32 = PHI %12:gr32, %bb.4, %15:gr32, %bb.5, %28:gr32, %bb.8
%32:gr32 = PHI %13:gr32, %bb.4, %16:gr32, %bb.5, %29:gr32, %bb.8
but since the original value only is 80 bits we need to adjust the size
of the last fragment expression, and with this patch we get
DBG_VALUE debug-use %30:gr32, debug-use $noreg, !"u", !DIExpression(DW_OP_LLVM_fragment, 0, 32)
DBG_VALUE debug-use %31:gr32, debug-use $noreg, !"u", !DIExpression(DW_OP_LLVM_fragment, 32, 32)
DBG_VALUE debug-use %32:gr32, debug-use $noreg, !"u", !DIExpression(DW_OP_LLVM_fragment, 64, 16)
Reviewers: vsk, aprantl, mstorsjo
Reviewed By: aprantl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46384
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331464
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Nico Weber [Thu, 3 May 2018 14:25:57 +0000 (14:25 +0000)]
use LLVM's standard CMakeLists.txt layout for llvm-xray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331455
91177308-0d34-0410-b5e6-
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Roman Lebedev [Thu, 3 May 2018 13:33:07 +0000 (13:33 +0000)]
[CodeGen][X86][NFC] Copy two selectcc tests from AArch64.
These tests are for DAGCombiner::foldSelectCCToShiftAnd().
Right now, they were only tested for AArch64,
but given the upcoming X86 changes to the hasAndNot(),
the test coverage needs to be added.
These tests originated from D27489 / rL289738
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331454
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Simon Pilgrim [Thu, 3 May 2018 13:27:10 +0000 (13:27 +0000)]
[X86] Split WriteVecALU/WritePHAdd into XMM and YMM/ZMM scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331453
91177308-0d34-0410-b5e6-
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Tim Northover [Thu, 3 May 2018 12:54:25 +0000 (12:54 +0000)]
ARM: don't try to over-align large vectors as arguments.
By default LLVM thinks very large vectors get aligned to their size when
passed across functions. Unfortunately no-one told the ARM backend so it
doesn't trigger stack realignment and so accesses can cause the usual
misalignment issues (e.g. a data abort).
This changes the ABI alignment to the stack alignment, which in practice
(and as a bonus) also coincides with the alignment "natural" vectors get.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331451
91177308-0d34-0410-b5e6-
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Piotr Padlewski [Thu, 3 May 2018 11:03:53 +0000 (11:03 +0000)]
perform DSE through launder.invariant.group
Summary:
Alias Analysis knows that llvm.launder.invariant.group
returns pointer that mustalias argument, but this information
wasn't used, therefor we didn't DSE through launder.invariant.group
Reviewers: chandlerc, dberlin, bogner, hfinkel, efriedma
Reviewed By: dberlin
Subscribers: amharc, llvm-commits, nlewycky, rsmith
Differential Revision: https://reviews.llvm.org/D31581
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331449
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Piotr Padlewski [Thu, 3 May 2018 11:03:01 +0000 (11:03 +0000)]
Rename invariant.group.barrier to launder.invariant.group
Summary:
This is one of the initial commit of "RFC: Devirtualization v2" proposal:
https://docs.google.com/document/d/16GVtCpzK8sIHNc2qZz6RN8amICNBtvjWUod2SujZVEo/edit?usp=sharing
Reviewers: rsmith, amharc, kuhar, sanjoy
Subscribers: arsenm, nhaehnle, javed.absar, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D45111
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331448
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 3 May 2018 10:53:17 +0000 (10:53 +0000)]
[X86][AVX512] VPAVG instructions should be tagged as SchedWriteVecALU
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331446
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 3 May 2018 10:31:20 +0000 (10:31 +0000)]
[X86] Split WriteVecIMul/WriteVecPMULLD/WriteMPSAD/WritePSADBW into XMM and YMM/ZMM scheduler classes
Also retagged VDBPSADBW instructions as SchedWritePSADBW instead of SchedWriteVecIMul which matches the behaviour on SkylakeServer (the only thing that supports it...)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331445
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Simon Pilgrim [Thu, 3 May 2018 09:11:32 +0000 (09:11 +0000)]
[X86] Update MMX instructions to be tagged with X86SchedWriteWidths types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331443
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Thu, 3 May 2018 08:25:14 +0000 (08:25 +0000)]
[WebAssembly] MC: Don't litter test directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331442
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Martin Storsjo [Thu, 3 May 2018 07:09:33 +0000 (07:09 +0000)]
Revert "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)"
This reverts SVN r331337, see PR37321 for details on the regression
it introduced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331441
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Clement Courbet [Thu, 3 May 2018 06:08:47 +0000 (06:08 +0000)]
[TableGen][NFC] Make ResourceCycles definitions more explicit.
https://reviews.llvm.org/D46356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331439
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Craig Topper [Thu, 3 May 2018 05:48:49 +0000 (05:48 +0000)]
[LoopIdiomRecognize] When looking for 'x & (x -1)' for popcnt, make sure the left hand side of the 'and' matches the left hand side of the 'subtract'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331437
91177308-0d34-0410-b5e6-
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Craig Topper [Thu, 3 May 2018 05:48:48 +0000 (05:48 +0000)]
[LoopIdiomRecognize] Add a test case showing that we transform to ctpop without fully checking the 'x & (x-1)' part.
The code fails to check that the same value is used twice. We only make sure the left hand side of the and is part of the loop recurrence. The 'x' in the subtract can be any value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331436
91177308-0d34-0410-b5e6-
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Craig Topper [Thu, 3 May 2018 05:00:18 +0000 (05:00 +0000)]
[LoopIdiomRecognize] Remove unnecessary cast from BinaryOperator to Instruction. NFC
BinaryOperator is a sub class of Instruction. We don't need an explicit cast back to Instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331432
91177308-0d34-0410-b5e6-
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Saleem Abdulrasool [Thu, 3 May 2018 04:45:43 +0000 (04:45 +0000)]
lit: flesh out `SubsituteCaptures` further
Add overloads for `__len__` and `__getitem__` to allow use of this class
on Linux as well as Windows. With these overloads, lit can be used on
both hosts for the swift testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331431
91177308-0d34-0410-b5e6-
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Max Kazantsev [Thu, 3 May 2018 02:37:55 +0000 (02:37 +0000)]
Re-enable "[SCEV] Make computeExitLimit more simple and more powerful"
This patch was temporarily reverted because it has exposed bug 37229 on
PowerPC platform. The bug is unrelated to the patch and was just a general
bug in the optimization done for PowerPC platform only. The bug was fixed
by the patch rL331410.
This patch returns the disabled commit since the bug was fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331427
91177308-0d34-0410-b5e6-
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Petr Hosek [Thu, 3 May 2018 01:38:49 +0000 (01:38 +0000)]
[Support] Support building LLVM for Fuchsia
These are necessary changes to support building LLVM for Fuchsia.
While these are not sufficient to run on Fuchsia, they are still
useful when cross-compiling LLVM libraries and runtimes for Fuchsia.
Differential Revision: https://reviews.llvm.org/D46345
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331423
91177308-0d34-0410-b5e6-
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Shoaib Meenai [Thu, 3 May 2018 01:20:36 +0000 (01:20 +0000)]
[ObjCARC] Convert an if to an early continue. NFC
This reduces nesting and makes the logic slightly easier to follow.
Differential Revision: https://reviews.llvm.org/D46371
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331422
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Nemanja Ivanovic [Thu, 3 May 2018 01:04:13 +0000 (01:04 +0000)]
Commit r331416 breaks the big-endian PPC bot. On the big endian build, we
actually encounter constants wider than 64-bits. Add the guard to prevent
tripping the assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331420
91177308-0d34-0410-b5e6-
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Chandler Carruth [Thu, 3 May 2018 00:11:03 +0000 (00:11 +0000)]
[gcov] Switch to an explicit if clunky array to satisfy some compilers
on various build bots that are unhappy with using makeArrayRef with an
initializer list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331418
91177308-0d34-0410-b5e6-
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Michael Berg [Thu, 3 May 2018 00:07:56 +0000 (00:07 +0000)]
MachineInst support mapping SDNode fast math flags for support in Back End code generation
Summary:
Machine Instruction flags for fast math support and MIR print support
Reviewers: spatel, arsenm
Reviewed By: arsenm
Subscribers: wdng
Differential Revision: https://reviews.llvm.org/D45781
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331417
91177308-0d34-0410-b5e6-
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Nemanja Ivanovic [Wed, 2 May 2018 23:55:23 +0000 (23:55 +0000)]
[PowerPC] Implement isMaskAndCmp0FoldingBeneficial
Sinking the and closer to a compare against zero is beneficial on PPC as it
allows us to emit record-form instructions. In the future, we may expand this
to a larger set of operations that feed compares against zero since PPC has
lots of record-form instructions.
Differential revision: https://reviews.llvm.org/D46060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331416
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Sam Clegg [Wed, 2 May 2018 23:11:38 +0000 (23:11 +0000)]
[WebAssembly] MC: Create and use first class section symbols
Differential Revision: https://reviews.llvm.org/D46335
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331413
91177308-0d34-0410-b5e6-
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Sam Clegg [Wed, 2 May 2018 23:01:10 +0000 (23:01 +0000)]
[MC] Factor MCObjectStreamer::addFragmentAtoms out of MachO streamer.
This code previously existed only in MCMachOStreamer but is
useful for WebAssembly too. See: D46335
Differential Revision: https://reviews.llvm.org/D46297
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331412
91177308-0d34-0410-b5e6-
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Nemanja Ivanovic [Wed, 2 May 2018 22:56:04 +0000 (22:56 +0000)]
[PowerPC] No CTR loop if the candidate exiting block is in a different loop
The CTR loops pass will insert the decrementing branch instruction in an exiting
block for the loop being transformed. However if that block is part of another
loop as well (whether a nested loop or with irreducible CFG), it is not valid
to use that exiting block. In fact, if the loop hass irreducible CFG, we don't
bother analyzing it and we just bail on the transformation. In practice, this
doesn't lead to a noticeable reduction in the number of loops transformed by
this pass.
Fixes https://bugs.llvm.org/show_bug.cgi?id=37229
Differential Revision: https://reviews.llvm.org/D46162
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331410
91177308-0d34-0410-b5e6-
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Chandler Carruth [Wed, 2 May 2018 22:24:39 +0000 (22:24 +0000)]
[GCOV] Emit the writeout function as nested loops of global data.
Summary:
Prior to this change, LLVM would in some cases emit *massive* writeout
functions with many 10s of 1000s of function calls in straight-line
code. This is a very wasteful way to represent what are fundamentally
loops and creates a number of scalability issues. Among other things,
register allocating these calls is extremely expensive. While D46127 makes this
less severe, we'll still run into scaling issues with this eventually. If not
in the compile time, just from the code size.
Now the pass builds up global data structures modeling the inputs to
these functions, and simply loops over the data structures calling the
relevant functions with those values. This ensures that the code size is
a fixed and only data size grows with larger amounts of coverage data.
A trivial change to IRBuilder is included to make it easier to build
the constants that make up the global data.
Reviewers: wmi, echristo
Subscribers: sanjoy, mcrosier, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D46357
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331407
91177308-0d34-0410-b5e6-
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Martin Storsjo [Wed, 2 May 2018 21:15:24 +0000 (21:15 +0000)]
[llvm-rc] Default to writing the output next to the input, if no output is specified
This matches what rc.exe does if no output is specified.
Differential Revision: https://reviews.llvm.org/D46239
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331403
91177308-0d34-0410-b5e6-
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Martin Storsjo [Wed, 2 May 2018 21:15:13 +0000 (21:15 +0000)]
[llvm-cvtres] Allow parameters preceded by '-' in addition to '/'
The real cvtres.exe also allows parameters in either form.
Differential Revision: https://reviews.llvm.org/D46358
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331402
91177308-0d34-0410-b5e6-
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Paul Semel [Wed, 2 May 2018 20:19:22 +0000 (20:19 +0000)]
[llvm-objcopy] Add --discard-all (-x) option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331400
91177308-0d34-0410-b5e6-
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Roman Tereshin [Wed, 2 May 2018 20:15:11 +0000 (20:15 +0000)]
[GlobalISel][InstructionSelect] Making Coverage Info generation optional on per-match table basis
to make sure that Testgen always has access to coverage info even if
the match table used by the selector itself is stripped off that
information for performance reasons.
Reviewers: dsanders, aemerson
Reviewed By: dsanders
Subscribers: rovka, kristof.beyls, llvm-commits, dsanders
Differential Revision: https://reviews.llvm.org/D46098
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331398
91177308-0d34-0410-b5e6-
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Paul Semel [Wed, 2 May 2018 20:14:49 +0000 (20:14 +0000)]
[llvm-objcopy] Add --weaken option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331397
91177308-0d34-0410-b5e6-
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Roman Tereshin [Wed, 2 May 2018 20:08:14 +0000 (20:08 +0000)]
[GlobalISel][InstructionSelect] Refactoring buildMatchTable out, NFC
to share it between the Instruction Selector in optimized and
non-optimized modes both and the Testgen.
Reviewers: dsanders, aemerson
Reviewed By: dsanders
Subscribers: rovka, kristof.beyls, llvm-commits, dsanders
Differential Revision: https://reviews.llvm.org/D46097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331396
91177308-0d34-0410-b5e6-
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Roman Tereshin [Wed, 2 May 2018 20:07:15 +0000 (20:07 +0000)]
[GlobalISel][InstructionSelect] Refactoring out a getMatchTable virtual method + other small NFC's
The main goal is to share getMatchTable between the Instruction
Selector and the Testgen.
The commit also contains some NFC only loosely related to refactoring
out the getMatchTable, but strongly related to the initial Testgen
patch (see https://reviews.llvm.org/D43962)
Reviewers: dsanders, aemerson
Reviewed By: dsanders
Subscribers: rovka, kristof.beyls, llvm-commits, dsanders
Differential Revision: https://reviews.llvm.org/D46096
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331395
91177308-0d34-0410-b5e6-
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Martin Storsjo [Wed, 2 May 2018 19:43:44 +0000 (19:43 +0000)]
[llvm-rc] Add rudimentary support for codepages
Only support UTF-8 (since LLVM contains UTF-8 parsing support
already, and the code even does that already) and Windows-1252
(where most code points has the same value in unicode). Keep the
existing default as only allowing ASCII input.
Using the option type JoinedOrSeparate, since the real rc.exe
handles options in this form, even if llvm-rc uses Separate for
other similar existing options.
Rename the struct SearchParams to WriterParams since it's now used
for more than just include paths.
Add a missing getResourceTypeName method to the BundleResource class,
to fix error printing from within STRINGTABLE resources (used in
tests).
Differential Revision: https://reviews.llvm.org/D46238
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331391
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 2 May 2018 19:26:14 +0000 (19:26 +0000)]
[X86][SNB] Fix scheduling of MMX integer multiply instructions.
The entries were being bound to the wrong class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331388
91177308-0d34-0410-b5e6-
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Aaron Ballman [Wed, 2 May 2018 18:57:14 +0000 (18:57 +0000)]
Move the TestPlugin project into the Tests folder in CMake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331387
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 2 May 2018 18:48:23 +0000 (18:48 +0000)]
[X86] Split WriteShuffle/WriteVarShuffle + WriteBlend/WriteVarBlend into XMM and YMM/ZMM scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331386
91177308-0d34-0410-b5e6-
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Martin Storsjo [Wed, 2 May 2018 18:24:37 +0000 (18:24 +0000)]
[COFF, ARM64] Hook up a few remaining relocations
Differential Revision: https://reviews.llvm.org/D46355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331384
91177308-0d34-0410-b5e6-
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Farhana Aleen [Wed, 2 May 2018 18:16:39 +0000 (18:16 +0000)]
[AMDGPU] A trivial fix for a buildbot failure caused by "commit
224a839fcbbead221f872cd32a1dd0c308d37299".
Author: FarhanaAleen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331383
91177308-0d34-0410-b5e6-
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Daniel Sanders [Wed, 2 May 2018 17:59:16 +0000 (17:59 +0000)]
[reassociate] Fix excessive revisits when processing long chains of reassociatable instructions.
Summary:
Some of our internal testing detected a major compile time regression which I've
tracked down to:
r278938 - Revert "Reassociate: Reprocess RedoInsts after each inst".
It appears that processing long chains of reassociatable instructions causes
non-linear (potentially exponential) growth in the number of times an
instruction is revisited. For example, the included test revisits instructions
220 times in a 20-instruction test.
It appears that r278938 reversed the order instructions were visited and that
this is preventing scheduled revisits from being cancelled as a result of
visiting the instructions naturally during normal processing. However, simply
reversing the order also harmed the generated code. Upon closer inspection, it
was discovered that revisits occurred in the opposite order to the first pass
(Thanks to escha for spotting that).
This patch makes the revisit order consistent with the first pass which allows
more revisits to be cancelled. This does appear to have a small impact on the
generated code in few cases but it significantly reduces compile-time.
After this patch, our internal test that was most affected by the regression
dropped from ~2 million revisits to ~4k resulting in Reassociate having 0.46%
of the runtime it had before (99.54% improvement).
Here's the summaries reported by lnt for the LLVM test-suite with --benchmarking-only:
| metric | geomean before patch | geomean after patch | delta |
| ----- | ----- | ----- | ----- |
| compile time | 0.1956 | 0.1261 | -35.54% |
| execution time | 0.3240 | 0.3237 | - |
| code size | 7365.4459 | 7365.6079 | - |
The results have a few wins and losses on compile-time, mostly in the +/- 2.5% range. There was one outlier though:
| Performance Regressions - compile_time | Δ | Previous | Current |
| MultiSource/Benchmarks/ASC_Sequoia/CrystalMk/CrystalMk | 9.82% | 2.0473 | 2.2483 |
Reviewers: javed.absar, dberlin
Reviewed By: dberlin
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331381
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Simon Pilgrim [Wed, 2 May 2018 17:58:50 +0000 (17:58 +0000)]
[X86] Cleanup WriteFShuffle/WriteFVarShuffle (+256 variants) scheduler classes with more common default values
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331380
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Krzysztof Parzyszek [Wed, 2 May 2018 17:20:22 +0000 (17:20 +0000)]
Add assertion to padding size calculation, NFC
The size of an object cannot be less than the emitted size of all the
contained elements. This would cause an overflow in padding size
calculation. Add an assert to catch this.
Patch by Suyog Sarda.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331376
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Farhana Aleen [Wed, 2 May 2018 16:48:52 +0000 (16:48 +0000)]
Revert "[AMDGPU] performAddCombine should run after DAG is legalized."
This reverts commit
6b97d2995566b4dddd6bf0d75579ff44501d4494.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331371
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Simon Pilgrim [Wed, 2 May 2018 16:25:41 +0000 (16:25 +0000)]
[X86] Convert most remaining XOP uses of X86SchedWritePair scheduler classes to X86SchedWriteWidths.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331369
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Farhana Aleen [Wed, 2 May 2018 16:24:10 +0000 (16:24 +0000)]
[AMDGPU] performAddCombine should run after DAG is legalized.
Summary: performAddCombine should run after DAG is legalized; Otherwise generic optimization
in the DAGCombiner can optimize an addcarry+trunc into an addcarry instruction with
illegal types.
Author: FarhanaAleen
Reviewed By: rampitec
Subscribers: llvm-commits, AMDGPU
Differential Revision: https://reviews.llvm.org/D46337
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331368
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Simon Pilgrim [Wed, 2 May 2018 16:16:24 +0000 (16:16 +0000)]
Fix line-endings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331367
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Clement Courbet [Wed, 2 May 2018 14:35:48 +0000 (14:35 +0000)]
Re-land rL331357 "[X86] Fix scheduling info for VMPSADBWYrmi."
Without the rebase mess.
https://reviews.llvm.org/D46356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331362
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Simon Pilgrim [Wed, 2 May 2018 14:25:32 +0000 (14:25 +0000)]
[X86] Cleanup WriteFMul scheduler classes with more common default values
Intel models were targeting x87 instead of packed sse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331360
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