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Roman Lebedev [Mon, 1 Jul 2019 14:28:24 +0000 (14:28 +0000)]
[NFC][InstCombine] Better commutative tests for "shift amount reassociation in bittest" pattern.
As discussed in https://reviews.llvm.org/D63829
*if* *both* shifts are one-use, we'd most likely want to produce `lshr`,
and not rely on ordering.
Also, there should likely be a *separate* fold to do this reordering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364772
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Krzysztof Parzyszek [Mon, 1 Jul 2019 13:50:47 +0000 (13:50 +0000)]
[Hexagon] Rework VLCR algorithm
Add code to catch pattern for commutative instructions for VLCR.
Patch by Suyog Sarda.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364770
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Matt Arsenault [Mon, 1 Jul 2019 13:44:46 +0000 (13:44 +0000)]
AMDGPU: Convert some places to Register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364769
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Matt Arsenault [Mon, 1 Jul 2019 13:40:18 +0000 (13:40 +0000)]
AMDGPU/GlobalISel: Fix RegBankSelect for G_FCANONICALIZE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364768
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Matt Arsenault [Mon, 1 Jul 2019 13:40:17 +0000 (13:40 +0000)]
AMDGPU/GlobalISel: Fix RegBankSelect for G_BUILD_VECTOR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364767
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Matt Arsenault [Mon, 1 Jul 2019 13:37:39 +0000 (13:37 +0000)]
AMDGPU/GlobalISel: Fail on store to 32-bit address space
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364766
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Matt Arsenault [Mon, 1 Jul 2019 13:34:26 +0000 (13:34 +0000)]
AMDGPU/GlobalISel: Improve icmp selection coverage.
Select s64 eq/ne scalar icmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364765
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Roman Lebedev [Mon, 1 Jul 2019 13:31:06 +0000 (13:31 +0000)]
[NFC][InstCombine] Improve test coverage for ((~x) + y) + 1 -> y - x fold fold (PR42459)
So we indeed to have this fold, but only if +1 is not the last operation..
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364764
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Matt Arsenault [Mon, 1 Jul 2019 13:30:12 +0000 (13:30 +0000)]
AMDGPU/GlobalISel: RegBankSelect for WWM/WQM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364763
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Matt Arsenault [Mon, 1 Jul 2019 13:30:09 +0000 (13:30 +0000)]
AMDGPU/GlobalISel: Use vcc reg bank for amdgcn.wqm.vote
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364762
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Matt Arsenault [Mon, 1 Jul 2019 13:22:07 +0000 (13:22 +0000)]
AMDGPU/GlobalISel: Fix scc->vcc copy handling
This was checking the size of the register with the value of the size,
which happens to be exec. Also fix assuming VCC is 64-bit to fix
wave32.
Also remove some untested handling for physical registers which is
skipped. This doesn't insert the V_CNDMASK_B32 if SCC is the physical
copy source. I'm not sure if this should be trying to handle this
special case instead of dealing with this in copyPhysReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364761
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Matt Arsenault [Mon, 1 Jul 2019 13:22:06 +0000 (13:22 +0000)]
AMDGPU/GlobalISel: Use and instead of BFE with inline immediate
Zext from s1 is the only case where this should do anything with the
current legal extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364760
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Matt Arsenault [Mon, 1 Jul 2019 13:22:04 +0000 (13:22 +0000)]
GlobalISel: Add GINodeEquiv for min/max
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364759
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Matt Arsenault [Mon, 1 Jul 2019 13:22:00 +0000 (13:22 +0000)]
GlobalISel: Add DAG compat for G_FCANONICALIZE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364758
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Simon Atanasyan [Mon, 1 Jul 2019 13:21:05 +0000 (13:21 +0000)]
[mips] Add missing schedinfo for MSA and ASE instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364757
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Simon Atanasyan [Mon, 1 Jul 2019 13:20:56 +0000 (13:20 +0000)]
[mips] Add missing schedinfo for atomic instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364756
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Simon Atanasyan [Mon, 1 Jul 2019 13:20:48 +0000 (13:20 +0000)]
[mips] Add missing schedinfo for ADJCALLSTACKDOWN, ADJCALLSTACKUP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364755
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Florian Hahn [Mon, 1 Jul 2019 12:36:44 +0000 (12:36 +0000)]
[AMDGPU] Call isLoopExiting for blocks in the loop.
isLoopExiting should only be called for blocks in the loop. A follow
up patch makes this requirement an assertion.
I've updated the usage here, to only match for actual exit blocks. Previously,
it would also match blocks not in the loop.
Reviewers: arsenm, nhaehnle
Reviewed By: nhaehnle
Differential Revision: https://reviews.llvm.org/D63980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364750
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Roman Lebedev [Mon, 1 Jul 2019 12:22:06 +0000 (12:22 +0000)]
[NFC][InstCombine] Tests for ((~x) + y) + 1 -> y - x fold fold (PR42459)
To be noted, this pattern is not unhandled by instcombine per-se,
it is somehow does end up being folded when one runs opt -O3,
but not if it's just -instcombine. Regardless, that fold is
indirect, depends on some other folds, and is thus blind
when there are extra uses.
https://bugs.llvm.org/show_bug.cgi?id=42459
https://rise4fun.com/Alive/EPO0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364749
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Fangrui Song [Mon, 1 Jul 2019 11:41:07 +0000 (11:41 +0000)]
[RISCV] Add break; to the last switch case
As suggested by jrtc27 in the post-commit review of D60528.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364746
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Simon Pilgrim [Mon, 1 Jul 2019 11:33:45 +0000 (11:33 +0000)]
[X86] CombineShuffleWithExtract - updated description comments. NFCI.
CombineShuffleWithExtract no longer requires that both shuffle ops are extract_subvectors, from the same type or from the same size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364745
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Benjamin Kramer [Mon, 1 Jul 2019 11:00:23 +0000 (11:00 +0000)]
[SelectionDAG] Do minnum->minimum at legalization time instead of building time
The SDAGBuilder behavior stems from the days when we didn't have fast
math flags available in SDAG. We do now and doing the transformation in
the legalizer has the advantage that it also works for vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364743
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Andrew Ng [Mon, 1 Jul 2019 10:58:20 +0000 (10:58 +0000)]
[benchmark] Disable CMake get_git_version
Disabled CMake get_git_version as it is meaningless for this in-tree
build, and hardcoded a null version.
Not using get_git_version avoids a refresh of the git index that is
executed by get_git_version. Refreshing the index can take a
considerable amount of time if the index needs to be refreshed
(particularly with the mono repo). This situation can arise when
building shared source on a host in VMs.
Differential Revision: https://reviews.llvm.org/D63925
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364742
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Roman Lebedev [Mon, 1 Jul 2019 09:57:53 +0000 (09:57 +0000)]
[NFC][InstCombine] Tests for x - ~(y) -> x + y + 1 fold (PR42457)
https://bugs.llvm.org/show_bug.cgi?id=42457
https://rise4fun.com/Alive/iFhE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364739
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Roman Lebedev [Mon, 1 Jul 2019 09:41:43 +0000 (09:41 +0000)]
[InstCombine] Omit 'urem' where possible
This was added in D63390 / rL364286 to backend,
but it makes sense to also handle it in middle-end.
https://rise4fun.com/Alive/Zsln
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364738
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Roman Lebedev [Mon, 1 Jul 2019 09:41:27 +0000 (09:41 +0000)]
[NFC][InstCombine] Copy test for omit urem when possible from TargetLowering
Was added in D63390 / rL364286 to backend, but it makes sense to also handle it here.
https://rise4fun.com/Alive/Zsln
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364737
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Jeremy Morse [Mon, 1 Jul 2019 09:38:23 +0000 (09:38 +0000)]
[DebugInfo] Avoid adding too much indirection to pointer-valued variables
This patch addresses PR41675, where a stack-pointer variable is dereferenced
too many times by its location expression, presenting a value on the stack as
the pointer to the stack.
The difference between a stack *pointer* DBG_VALUE and one that refers to a
value on the stack, is currently the indirect flag. However the DWARF backend
will also try to guess whether something is a memory location or not, based
on whether there is any computation in the location expression. By simply
prepending the stack offset to existing expressions, we can accidentally
convert a register location into a memory location, which introduces a
suprise (and unintended) dereference.
The solution is to add DW_OP_stack_value whenever we add a DIExpression
computation to a stack *pointer*. It's an implicit location computed on the
expression stack, thus needs to be flagged as a stack_value.
For the edge case where the offset is zero and the location could be a register
location, DIExpression::prepend will still generate opcodes, and thus
DW_OP_stack_value must still be added.
Differential Revision: https://reviews.llvm.org/D63429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364736
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Yevgeny Rouban [Mon, 1 Jul 2019 08:43:53 +0000 (08:43 +0000)]
[SimpleLoopUnswitch] Implement handling of prof branch_weights metadata for SwitchInst
Differential Revision: https://reviews.llvm.org/D60606
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364734
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Sam Parker [Mon, 1 Jul 2019 08:21:28 +0000 (08:21 +0000)]
[ARM] WLS/LE Code Generation
Backend changes to enable WLS/LE low-overhead loops for armv8.1-m:
1) Use TTI to communicate to the HardwareLoop pass that we should try
to generate intrinsics that guard the loop entry, as well as setting
the loop trip count.
2) Lower the BRCOND that uses said intrinsic to an Arm specific node:
ARMWLS.
3) ISelDAGToDAG the node to a new pseudo instruction:
t2WhileLoopStart.
4) Add support in ArmLowOverheadLoops to handle the new pseudo
instruction.
Differential Revision: https://reviews.llvm.org/D63816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364733
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Craig Topper [Mon, 1 Jul 2019 07:59:42 +0000 (07:59 +0000)]
[X86] Add more load folding tests for vcvt(t)ps2(u)qq showing missed foldings. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364730
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Craig Topper [Mon, 1 Jul 2019 07:09:34 +0000 (07:09 +0000)]
[X86] Improve the type checking fast-isel handling of vector bitcasts.
We had a bunch of vector size legality checks for the source type
based on feature flags, but we didn't check the destination type at
all beyond ensuring that it was a "simple" type. But this allowed
the destination to be i128 which isn't legal.
This commit changes the code to use TLI's isTypeLegal logic in
place of the all the subtarget checks. Then additionally checks
that the source and dest are vectors.
Fixes 42452
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364729
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Craig Topper [Mon, 1 Jul 2019 07:09:31 +0000 (07:09 +0000)]
[X86] Add a DAG combine to replace vector loads feeding a v4i32->v2f64 CVTSI2FP/CVTUI2FP node with a vzload.
But only when the load isn't volatile.
This improves load folding during isel where we only have vzload
and scalar_to_vector+load patterns. We can't have full vector load
isel patterns for the same volatile load issue.
Also add some missing masked cvtsi2fp/cvtui2fp with vzload patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364728
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Craig Topper [Mon, 1 Jul 2019 07:09:26 +0000 (07:09 +0000)]
[X86] Add some additional load folding tests to vec_int_to_fp.ll/vec_int_to_fp-widen.ll and disable the peephole pass.
Also copy some missing test cases from vec_int_to_fp.ll to vec_int_to_fp-widen.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364727
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Craig Topper [Mon, 1 Jul 2019 07:09:23 +0000 (07:09 +0000)]
[X86] Add MOVHPDrm/MOVLPDrm patterns that use VZEXT_LOAD.
We already had patterns that used scalar_to_vector+load. But we can
also have a vzload.
Found while investigating combining scalar_to_vector+load to vzload.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364726
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Mike Spertus [Sun, 30 Jun 2019 21:54:34 +0000 (21:54 +0000)]
Clean up MSVC visualization of LLVM pointer types
Create separate natvis ptr and int views for PointerIntPair.
These are convenient in watch Windows and will be used by
Clang visualizers to be checked in shortly
Also, removed deref views as the MSVC na format has
done the same thing natively since MSVC2013.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364723
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Sanjay Patel [Sun, 30 Jun 2019 13:40:31 +0000 (13:40 +0000)]
[InstCombine] canonicalize fcmp+select to minnum/maxnum intrinsics
This is the opposite direction of D62158 (we have to choose 1 form or the other).
Now that we have FMF on the select, this becomes more palatable. And the benefits
of having a single IR instruction for this operation (less chances of missing folds
based on extra uses, etc) overcome my previous comments about the potential advantage
of larger pattern matching/analysis.
Differential Revision: https://reviews.llvm.org/D62414
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364721
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Fangrui Song [Sun, 30 Jun 2019 11:19:56 +0000 (11:19 +0000)]
Cleanup: llvm::bsearch -> llvm::partition_point after r364719
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364720
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Fangrui Song [Sun, 30 Jun 2019 09:17:59 +0000 (09:17 +0000)]
[ADT] Implement llvm::bsearch() with std::partition_point()
Summary:
Delete the begin-end form because the standard std::partition_point
can be easily used as a replacement.
The ranges-style llvm::bsearch will be renamed to llvm::partition_point
in the next clean-up patch.
The name "bsearch" doesn't meet people's expectation because in C:
> If two or more members compare equal, which member is returned is unspecified.
Reviewed By: sammccall
Differential Revision: https://reviews.llvm.org/D63718
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364719
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Craig Topper [Sun, 30 Jun 2019 06:46:37 +0000 (06:46 +0000)]
[X86] Custom lower AVX masked loads to masked load and vselect instead of selecting a maskmov+vblend during isel.
AVX masked loads only support 0 as the value for masked off elements.
So we need an extra blend to support other values. Previously we
expanded the masked load to two instructions with isel patterns.
With this patch we now insert the vselect during lowering and it
will be separately selected as a blend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364718
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Craig Topper [Sun, 30 Jun 2019 06:46:33 +0000 (06:46 +0000)]
[SelectionDAG] Use the memory VT instead of result VT for FoldingSet profiling in getMaskedLoad/getMaskedStore.
This matches what is done by the Profile function. Otherwise CSE
won't work properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364717
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Nikita Popov [Sat, 29 Jun 2019 15:12:59 +0000 (15:12 +0000)]
[LFTR] Rephrase getLoopTest into "based-on" check; NFCI
What we want to know here is whether we're already using this value
for the loop condition, so make the query about that. We can extend
this to a more general "based-on" relationship, rather than a direct
icmp use later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364715
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Sanjay Patel [Sat, 29 Jun 2019 14:28:54 +0000 (14:28 +0000)]
[InstCombine] canonicalize fmin/fmax to LLVM intrinsics minnum/maxnum
This transform came up in D62414, but we should deal with it first.
We have LLVM intrinsics that correspond exactly to libm calls (unlike
most libm calls, these libm calls never set errno).
This holds without any fast-math-flags, so we should always canonicalize
to those intrinsics directly for better optimization.
Currently, we convert to fcmp+select only when we have FMF (nnan) because
fcmp+select does not preserve the semantics of the call in the general case.
Differential Revision: https://reviews.llvm.org/D63214
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364714
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Nikita Popov [Sat, 29 Jun 2019 12:41:02 +0000 (12:41 +0000)]
[LFTR] Remove unnecessary latch check; NFCI
The whole indvars pass works on loops in simplified form, so there
is always a unique latch. Convert the condition into an assertion
in needsLFTR (though we also assert this in later LFTR functions).
Additionally update the comment on getLoopTest() now that we are
dealing with multiple exits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364713
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Roman Lebedev [Sat, 29 Jun 2019 11:51:50 +0000 (11:51 +0000)]
[InstCombine] Shift amount reassociation (PR42391)
Summary:
Given pattern:
`(x shiftopcode Q) shiftopcode K`
we should rewrite it as
`x shiftopcode (Q+K)` iff `(Q+K) u< bitwidth(x)`
This is valid for any shift, but they must be identical.
* https://rise4fun.com/Alive/9E2
* exact on both lshr => exact https://rise4fun.com/Alive/plHk
* exact on both ashr => exact https://rise4fun.com/Alive/QDAA
* nuw on both shl => nuw https://rise4fun.com/Alive/5Uk
* nsw on both shl => nsw https://rise4fun.com/Alive/0plg
Should fix [[ https://bugs.llvm.org/show_bug.cgi?id=42391 | PR42391]].
Reviewers: spatel, nikic, RKSimon
Reviewed By: nikic
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63812
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364712
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Roman Lebedev [Sat, 29 Jun 2019 11:51:37 +0000 (11:51 +0000)]
[IR][Patternmatch] Add m_SpecificInt_ULT() predicate
Summary:
Match an integer or vector with every element unsigned less than the
Threshold. For vectors, this includes constants with undefined elements.
FIXME: is it worth generalizing this to simply take ICmpInst::Predicate?
Reviewers: craig.topper, spatel, nikic
Reviewed By: spatel
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63811
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364711
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Dmitry Venikov [Sat, 29 Jun 2019 11:38:12 +0000 (11:38 +0000)]
[APInt] Fix getBitsNeeded for INT_MIN values
Summary: This patch fixes behaviour of APInt::getBitsNeeded for INT_MIN 10 bits values.
Reviewers: regehr, RKSimon
Reviewed By: RKSimon
Subscribers: grandinj, dexonsmith, kristina, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63691
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364710
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Nikita Popov [Sat, 29 Jun 2019 09:24:12 +0000 (09:24 +0000)]
[LFTR] Fix post-inc pointer IV with truncated exit count (PR41998)
Fixes https://bugs.llvm.org/show_bug.cgi?id=41998. Usually when we
have a truncated exit count we'll truncate the IV when comparing
against the limit, in which case exit count overflow in post-inc
form doesn't matter. However, for pointer IVs we don't do that, so
we have to be careful about incrementing the IV in the wide type.
I'm fixing this by removing the IVCount variable (which was
ExitCount or ExitCount+1) and replacing it with a UsePostInc flag,
and then moving the actual limit adjustment to the individual cases
(which are: pointer IV where we add to the wide type, integer IV
where we add to the narrow type, and constant integer IV where we
add to the wide type).
Differential Revision: https://reviews.llvm.org/D63686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364709
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Sam Clegg [Sat, 29 Jun 2019 01:53:26 +0000 (01:53 +0000)]
Partial revert of "[llvm-ar] Document response file support in --help"
This is partial revert of
70a8027c60fe1f95e8a8a1ff6575ebf8778d3544.
The test apparently failed on win32 bots due to the way slashes in
pathnames are handled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364705
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Matt Arsenault [Sat, 29 Jun 2019 00:55:16 +0000 (00:55 +0000)]
AMDGPU/GlobalISel: Add some more tests for icmp select
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364703
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Matt Arsenault [Sat, 29 Jun 2019 00:44:36 +0000 (00:44 +0000)]
AMDGPU/GlobalISel: RegBankSelect for update.dpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364701
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Matt Arsenault [Sat, 29 Jun 2019 00:39:20 +0000 (00:39 +0000)]
AMDGPU/GlobalISel: RegBankSelect for atomic.inc/atomic.dec
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364699
91177308-0d34-0410-b5e6-
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Matt Arsenault [Sat, 29 Jun 2019 00:33:13 +0000 (00:33 +0000)]
AMDGPU/GlobalISel: RegBankSelect for some DS intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364698
91177308-0d34-0410-b5e6-
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Matt Arsenault [Sat, 29 Jun 2019 00:29:56 +0000 (00:29 +0000)]
AMDGPU/GlobalISel: RegBankSelect for some easy intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364697
91177308-0d34-0410-b5e6-
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Matt Arsenault [Sat, 29 Jun 2019 00:28:52 +0000 (00:28 +0000)]
AMDGPU/GlobalISel: RegBankSelect for icmp/fcmp intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364696
91177308-0d34-0410-b5e6-
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Matt Arsenault [Sat, 29 Jun 2019 00:25:53 +0000 (00:25 +0000)]
AMDGPU/GlobalISel: RegBankSelect for amdgcn.div.fmas
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364695
91177308-0d34-0410-b5e6-
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Matt Arsenault [Sat, 29 Jun 2019 00:22:28 +0000 (00:22 +0000)]
AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364694
91177308-0d34-0410-b5e6-
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Philip Reames [Sat, 29 Jun 2019 00:19:31 +0000 (00:19 +0000)]
[IndVars] Remove a bit of manual constant folding [NFC]
SCEV is more than capable of folding (add x, trunc(0)) to x.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364693
91177308-0d34-0410-b5e6-
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Matt Arsenault [Fri, 28 Jun 2019 23:43:40 +0000 (23:43 +0000)]
AMDGPU: Add baseline test for packed shufflevector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364691
91177308-0d34-0410-b5e6-
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Wouter van Oortmerssen [Fri, 28 Jun 2019 22:20:33 +0000 (22:20 +0000)]
[WebAssembly] Assembler: support .int16/32/64 directives.
Reviewers: sbc100
Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63959
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364689
91177308-0d34-0410-b5e6-
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Wouter van Oortmerssen [Fri, 28 Jun 2019 21:53:11 +0000 (21:53 +0000)]
[WebAssembly] Allow @object in .type directives.
Reviewers: sbc100
Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63955
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364688
91177308-0d34-0410-b5e6-
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Sanjay Patel [Fri, 28 Jun 2019 21:45:55 +0000 (21:45 +0000)]
[x86] remove stale comment about cmov; NFC
The cmov node used to sometimes return a glue result (and that's what
'flag' meant in this context), but that was removed with D38664.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364687
91177308-0d34-0410-b5e6-
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Cameron McInally [Fri, 28 Jun 2019 21:39:08 +0000 (21:39 +0000)]
[NFC][NewGVN] Explicitly check fpmath metadata in fpmath.ll
Suggested in D63933.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364685
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Sanjay Patel [Fri, 28 Jun 2019 20:45:32 +0000 (20:45 +0000)]
[Lanai] auto-generate complete test checks; NFC
This file will fail with a common codegen transform that
I'm looking at, and I can't tell if that's an improvement
or regression based on the sparse checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364684
91177308-0d34-0410-b5e6-
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Wouter van Oortmerssen [Fri, 28 Jun 2019 20:31:13 +0000 (20:31 +0000)]
[WebAssembly] Assembler: Allow offsets and p2align in symbol load.
Reviewers: sbc100
Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63951
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364682
91177308-0d34-0410-b5e6-
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Wouter van Oortmerssen [Fri, 28 Jun 2019 20:29:16 +0000 (20:29 +0000)]
[WebAssembly] Assembler: Improve section parsing.
Reviewers: sbc100
Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364681
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Cameron McInally [Fri, 28 Jun 2019 20:09:32 +0000 (20:09 +0000)]
[NewGVN] Add unary FNeg support to NewGVN pass
Differential Revision: https://reviews.llvm.org/D63933
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364680
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Cameron McInally [Fri, 28 Jun 2019 19:57:31 +0000 (19:57 +0000)]
[GVNSink] Add unary FNeg support to GVNSink pass
Differential Revision: https://reviews.llvm.org/D63900
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364678
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Erik Pilkington [Fri, 28 Jun 2019 19:54:19 +0000 (19:54 +0000)]
[demangle] Support for C++2a char8_t
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364677
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Brad Smith [Fri, 28 Jun 2019 19:48:31 +0000 (19:48 +0000)]
Default to Secure PLT on PPC for musl libc.
This matches the default settings of clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364675
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Sam Clegg [Fri, 28 Jun 2019 18:48:05 +0000 (18:48 +0000)]
[llvm-ar] Document response file support in --help
Also a test for this.
Differential Revision: https://reviews.llvm.org/D63836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364673
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Lang Hames [Fri, 28 Jun 2019 18:36:59 +0000 (18:36 +0000)]
Re-apply r364600 with fixes.
Fix: MachO/X86_64_RELOC_GOT is a 32-bit reloc, so only compare 32 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364672
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Rainer Orth [Fri, 28 Jun 2019 18:29:18 +0000 (18:29 +0000)]
[unittests][Support] Fix LLVM-Unit :: Support/./SupportTests/FileSystemTest.permissions on Solaris
LLVM-Unit :: Support/./SupportTests/FileSystemTest.permissions currently
FAILs on Solaris:
FAIL: LLVM-Unit :: Support/./SupportTests/FileSystemTest.permissions (2940 of 51555)
******************** TEST 'LLVM-Unit :: Support/./SupportTests/FileSystemTest.permissions' FAILED ********************
Note: Google Test filter = FileSystemTest.permissions
[==========] Running 1 test from 1 test case.
[----------] Global test environment set-up.
[----------] 1 test from FileSystemTest
[ RUN ] FileSystemTest.permissions
/opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1705: Failure
Value of: CheckPermissions(fs::sticky_bit)
Actual: false
Expected: true
/opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1712: Failure
Value of: CheckPermissions(fs::set_uid_on_exe | fs::set_gid_on_exe | fs::sticky_bit)
Actual: false
Expected: true
/opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1719: Failure
Value of: CheckPermissions(fs::all_read | fs::set_uid_on_exe | fs::set_gid_on_exe | fs::sticky_bit)
Actual: false
Expected: true
/opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1722: Failure
Value of: CheckPermissions(fs::all_perms)
Actual: false
Expected: true
[ FAILED ] FileSystemTest.permissions (0 ms)
[----------] 1 test from FileSystemTest (0 ms total)
[----------] Global test environment tear-down
[==========] 1 test from 1 test case ran. (1 ms total)
[ PASSED ] 0 tests.
[ FAILED ] 1 test, listed below:
[ FAILED ] FileSystemTest.permissions
1 FAILED TEST
Checking with truss reveals that this is the same issue as on AIX and
documented in chmod(2):
If the process is not a privileged process and the file is not a direc-
tory, mode bit 01000 (S_ISVTX, the sticky bit) is cleared.
The following patch fixes this in the same way. Tested on amd64-pc-solaris2.11.
Differential Revision: https://reviews.llvm.org/D63598
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364671
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Jinsong Ji [Fri, 28 Jun 2019 18:07:19 +0000 (18:07 +0000)]
[UpdateChecks] Add support for armv7-apple-darwin
armv7-apple-darwin was not supported well, the script can't generate
checks.
https://reviews.llvm.org/D60601/new/#inline-568671
Differential Revision: https://reviews.llvm.org/D63939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364668
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Simon Pilgrim [Fri, 28 Jun 2019 17:57:32 +0000 (17:57 +0000)]
[X86] CombineShuffleWithExtract - recurse through EXTRACT_SUBVECTOR chain
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364667
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Peter Collingbourne [Fri, 28 Jun 2019 17:53:26 +0000 (17:53 +0000)]
hwasan: Remove the old frame descriptor mechanism.
Differential Revision: https://reviews.llvm.org/D63470
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364665
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Roman Lebedev [Fri, 28 Jun 2019 17:26:28 +0000 (17:26 +0000)]
[NFC][Codegen] Revisit test coverage for X % C == 0 fold once more (add tests with '1' divisor)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364661
91177308-0d34-0410-b5e6-
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Wouter van Oortmerssen [Fri, 28 Jun 2019 16:51:06 +0000 (16:51 +0000)]
[WebAssembly] Added visibility and ident directives to WasmAsmParser.
Summary:
These are output by clang -S, so can now be roundtripped thru clang.
(partially) fixes: https://bugs.llvm.org/show_bug.cgi?id=34544
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63901
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364658
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Roman Lebedev [Fri, 28 Jun 2019 16:36:53 +0000 (16:36 +0000)]
[NFC][InstCombine] Shift amount reassociation: revisit flag preservation tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364657
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Dmitry Preobrazhensky [Fri, 28 Jun 2019 16:28:46 +0000 (16:28 +0000)]
[AMDGPU][MC] Fix 2 for sanitizer failure in 364645
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364656
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Sam Tebbs [Fri, 28 Jun 2019 15:43:31 +0000 (15:43 +0000)]
[ARM] Add support for the MVE long shift instructions
MVE adds the lsll, lsrl and asrl instructions, which perform a shift on a 64 bit value separated into two 32 bit registers.
The Expand64BitShift function is modified to accept ISD::SHL, ISD::SRL and ISD::SRA and convert it into the appropriate opcode in ARMISD. An SHL is converted into an lsll, an SRL is converted into an lsrl for the immediate form and a negation and lsll for the register form, and SRA is converted into an asrl.
test/CodeGen/ARM/shift_parts.ll is added to test the logic of emitting these instructions.
Differential Revision: https://reviews.llvm.org/D63430
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364654
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Max Moroz [Fri, 28 Jun 2019 15:38:25 +0000 (15:38 +0000)]
[llvm-cov[ Fix lcov coverage report contains functions from other compilation units.
Summary: Patch by Chuan Qiu (@eagleonhill).
Reviewers: Dor1s
Reviewed By: Dor1s
Subscribers: lebedev.ri, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63571
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364653
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Roman Lebedev [Fri, 28 Jun 2019 15:32:52 +0000 (15:32 +0000)]
[NFC][InstCombine] Shift amount reassociation: add flag preservation test
As discussed in https://reviews.llvm.org/D63812#inline-569870
* exact on both lshr => exact https://rise4fun.com/Alive/plHk
* exact on both ashr => exact https://rise4fun.com/Alive/QDAA
* nuw on both shl => nuw https://rise4fun.com/Alive/5Uk
* nsw on both shl => nsw https://rise4fun.com/Alive/0plg
So basically if the same flag is set on both original shifts -> set it on new shift.
Don't think we can do anything with non-matching flags on shl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364652
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Dmitry Preobrazhensky [Fri, 28 Jun 2019 15:22:47 +0000 (15:22 +0000)]
[AMDGPU][MC] Fix for sanitizer failure in 364645
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364651
91177308-0d34-0410-b5e6-
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Cameron McInally [Fri, 28 Jun 2019 15:12:15 +0000 (15:12 +0000)]
[NFC][Float2Int] Pre-commit unary FNeg test to basic.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364649
91177308-0d34-0410-b5e6-
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Cameron McInally [Fri, 28 Jun 2019 14:39:58 +0000 (14:39 +0000)]
[NFC][NewGVN] Pre-commit unary FNeg test to fpmath.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364646
91177308-0d34-0410-b5e6-
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Dmitry Preobrazhensky [Fri, 28 Jun 2019 14:14:02 +0000 (14:14 +0000)]
[AMDGPU][MC] Enabled constant expressions as operands of sendmsg
See bug 40820: https://bugs.llvm.org/show_bug.cgi?id=40820
Reviewers: artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D62735
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364645
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Simon Pilgrim [Fri, 28 Jun 2019 12:24:49 +0000 (12:24 +0000)]
[X86] CombineShuffleWithExtract - only require 1 source to be EXTRACT_SUBVECTOR
We were requiring that both shuffle operands were EXTRACT_SUBVECTORs, but we can relax this to only require one of them to be.
Also, we shouldn't bother attempting this if both operands are from the lowest subvector (or not EXTRACT_SUBVECTOR at all).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364644
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David Green [Fri, 28 Jun 2019 11:44:03 +0000 (11:44 +0000)]
[ARM] Add MVE mul patterns
This simply adds integer and floating point VMUL patterns for MVE, same as we
have add and sub.
Differential Revision: https://reviews.llvm.org/D63866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364643
91177308-0d34-0410-b5e6-
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Roman Lebedev [Fri, 28 Jun 2019 11:36:34 +0000 (11:36 +0000)]
[NFC][Codegen] Revisit test coverage for X % C == 0 fold
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364642
91177308-0d34-0410-b5e6-
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David Green [Fri, 28 Jun 2019 11:17:38 +0000 (11:17 +0000)]
[ARM] Mark math routines as non-legal for MVE
This adds handling and tests for a number of floating point math routines,
which have no MVE instructions.
Differential Revision: https://reviews.llvm.org/D63725
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364641
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David Green [Fri, 28 Jun 2019 10:25:35 +0000 (10:25 +0000)]
[ARM] MVE patterns for VABS and VNEG
This simply adds the required patterns for fp neg and abs.
Differential Revision: https://reviews.llvm.org/D63861
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364640
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Fangrui Song [Fri, 28 Jun 2019 10:10:10 +0000 (10:10 +0000)]
[DebugInfo] Fix setStartAddress after r364637
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364638
91177308-0d34-0410-b5e6-
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Fangrui Song [Fri, 28 Jun 2019 10:06:11 +0000 (10:06 +0000)]
[DebugInfo] Simplify GSYM::AddressRange and GSYM::AddressRanges
Delete unnecessary getters of AddressRange.
Simplify AddressRange::size(): Start <= End check should be checked in an upper layer.
Delete isContiguousWith() that doesn't make sense.
Simplify AddressRanges::insert. Delete commented code. Fix it when more than 1 ranges are to be deleted.
Delete trailing newline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364637
91177308-0d34-0410-b5e6-
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David Green [Fri, 28 Jun 2019 09:47:55 +0000 (09:47 +0000)]
[ARM] Widening loads and narrowing stores
MVE has instructions to widen as it loads, and narrow as it stores. This adds
the required patterns and legalisation to make them work including specifying
that they are legal, patterns to select them and test changes.
Patch by David Sherwood.
Differential Revision: https://reviews.llvm.org/D63839
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364636
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Simon Tatham [Fri, 28 Jun 2019 09:28:39 +0000 (09:28 +0000)]
[ARM] Fix integer UB in MVE load/store immediate handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364635
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Fangrui Song [Fri, 28 Jun 2019 08:58:05 +0000 (08:58 +0000)]
[DebugInfo] GSYM cleanups after D63104/r364427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364634
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David Green [Fri, 28 Jun 2019 08:41:40 +0000 (08:41 +0000)]
[ARM] MVE loads and stores
This fills in the gaps for basic MVE loads and stores, allowing unaligned
access and adding far too many tests. These will become important as
narrowing/expanding and pre/post inc are added. Big endian might still not be
handled very well, because we have not yet added bitcasts (and I'm not sure how
we want it to work yet). I've included the alignment code anyway which maps
with our current patterns. We plan to return to that later.
Code written by Simon Tatham, with additional tests from Me and Mikhail Maltsev.
Differential Revision: https://reviews.llvm.org/D63838
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364633
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Dylan McKay [Fri, 28 Jun 2019 08:35:21 +0000 (08:35 +0000)]
[AVR] Don't look for the TargetFrameLowering in the FrameLowering implementation
c.f. r364349
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364632
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David Green [Fri, 28 Jun 2019 08:18:55 +0000 (08:18 +0000)]
[ARM] Mark div and rem as expand for MVE
We don't have vector operations for these, so they need to be expanded for both
integer and float.
Differential Revision: https://reviews.llvm.org/D63595
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364631
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David Green [Fri, 28 Jun 2019 07:41:09 +0000 (07:41 +0000)]
[ARM] Select MVE fp add and sub
The same as integer arithmetic, we can add simple floating point MVE addition and
subtraction patterns.
Initial code by David Sherwood
Differential Revision: https://reviews.llvm.org/D63257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364629
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