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Jason Ekstrand [Sat, 15 Dec 2018 00:25:38 +0000 (18:25 -0600)]
spirv: Make better use of vtn_pointer_uses_ssa_offset
The choice of whether or not we should use block_load/store isn't a
choice between external and not so much as a choice between deref
instructions and manually calculated offsets. In vtn_pointer_from_ssa,
we guard the index+offset case behind vtn_pointer_uses_ssa_offset and
then branch out from there.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Wed, 28 Nov 2018 21:20:03 +0000 (15:20 -0600)]
spirv: Add explicit pointer types
Instead of baking in uvec2 for UBO and SSBO pointers and uint for push
constant and shared memory pointers, make it configurable.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Sat, 15 Dec 2018 00:20:00 +0000 (18:20 -0600)]
spirv: Choose atomic deref type with pointer_uses_ssa_offset
Previously, we hard-coded the rule about workgroup variables and the
builder lower_workgroup_access_to_offsets flag. Instead base it on the
handy helper we have for exactly this sort of thing.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Sat, 15 Dec 2018 14:31:51 +0000 (08:31 -0600)]
spirv: Add error checking for Block and BufferBlock decorations
Variable pointers being well-defined across the block boundary requires
a couple of very specific SPIR-V validation rules. Normally, we'd trust
the validator to catch these but since CTS tests have been found in the
wild which violate them, we'll carry our own checks.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Thu, 13 Dec 2018 22:50:19 +0000 (16:50 -0600)]
nir/vulkan: Add a descriptor type to vulkan resource intrinsics
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Wed, 28 Nov 2018 03:31:42 +0000 (21:31 -0600)]
nir/lower_io: Add "explicit" IO lowering
This new pass is for lowering explicitly laid out memory coming in from
SPIR-V or a similar source. It's quite a bit more complicated than the
normal lower_io because we have to be able to handle matrices. The
way the stride information is stored for matrices is awkward and dealing
with row-major matrices is especially painful.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Fri, 14 Dec 2018 00:34:35 +0000 (18:34 -0600)]
nir/validate: Allow array derefs on vectors in more modes
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Wed, 28 Nov 2018 19:44:56 +0000 (13:44 -0600)]
nir/intrinsics: Add access flags to load/store_deref
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Wed, 28 Nov 2018 03:30:22 +0000 (21:30 -0600)]
nir/intrinsics: Allow deref sources to consume anything
This commit adds a new num_components value for intrinsic sources of -1
which means that it consumes everything and the number of components
effectively isn't validated. This is useful for deref sources which
just take the result of the deref and we leave it up to the driver to
decide what that size should be.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Thu, 13 Dec 2018 23:42:34 +0000 (17:42 -0600)]
nir/validate: Allow derefs in phi nodes
We added this assert when first moving derefs over to instructions to
ensure that deref chains could go all the way back to the variables.
Now that we're going to start using derefs for things that we can do
variable pointers on such as UBOs and SSBOs, we need to be able to run
derefs through phi nodes, selects, and basically anything else.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Wed, 28 Nov 2018 23:27:57 +0000 (17:27 -0600)]
nir/remove_dead_variables: Properly handle deref casts
We already detect any incomplete deref chains (where the deref is used
for something other than another deref or a load/store) and flag the
variable as used thanks to deref_used_for_not_store. All that's left to
do is to properly skip casts when cleaning up.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Wed, 28 Nov 2018 23:27:00 +0000 (17:27 -0600)]
nir/deref: Skip over casts in fixup_deref_modes
This pass is used when, for instance, we lazily change the mode of
variables rather than replacing the variable with a new one. Since we
only do this in cases where we know we have full deref chains, it's ok
to just skip them in fixup_deref_modes.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Thu, 13 Dec 2018 19:50:51 +0000 (13:50 -0600)]
nir/deref: Support casts and ptr_as_array in comparisons
The code which constructs deref paths already gives you the path
starting at the nearest deref_cast or deref_var. All we need to do for
casts is handle the case where the start of the path isn't a deref_var.
For ptr_as_array derefs, we just bail if we have any after the
divergence point between the two derefs. We may be able to do better in
the future but this works for now.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Thu, 13 Dec 2018 18:37:59 +0000 (12:37 -0600)]
nir/opt_deref: Properly optimize ptr_as_array derefs
When handling casts, we can't blindly propagate the parent of a cast
into a ptr_as_array deref because doing so might loose the stride
information from the cast. Instead, before we can propagate into
ptr_as_array derefs, we need to check that the cast is a cast of an
array deref and that the stride matches. For other types of derefs, we
can continue to propagate casts as normal because they don't need the
stride. We also add an optimization which can combine a ptr_as_array
deref with it parent if it is also an array deref of some form.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Fri, 4 Jan 2019 17:11:49 +0000 (11:11 -0600)]
nir/validate: Don't allow derefs in if conditions
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Wed, 28 Nov 2018 18:26:52 +0000 (12:26 -0600)]
nir: Add a ptr_as_array deref type
These correspond directly to SPIR-V's OpPtrAccessChain. As such, they
treat whatever their parent gives them as if it's the first element in
some array and dereferences that array. If the parent is, itself, an
array deref, then the two indices can just be added together to get the
final array deref. However, it can also be used in cases where what you
have is a dereference to some random vec2 value somewhere. In this
case, we require a cast before the ptr_as_array and use the ptr_stride
field in the cast to provide a stride for the ptr_as_array derefs.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Thu, 13 Dec 2018 17:08:13 +0000 (11:08 -0600)]
nir: Move propagation of cast derefs to a new nir_opt_deref pass
We're going to want to do more deref optimizations going forward and
this gives us a central place to do them. Also, cast propagation will
get a bit more complicated with the addition of ptr_as_array derefs.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Wed, 12 Dec 2018 22:07:07 +0000 (16:07 -0600)]
spirv: Propagate layout decorations to created glsl_types
Instead of just storing the decorations in the vtn_type, propagate them
all the way through to the glsl_type. For array strides, this means we
need to handle them earlier so we break array stride handling into it's
own function and explicitly call it for both pointer and array types.
Due to type deduplication in the SPIR-V, we may have explicit layout
decorations on all sorts of types that don't actually want them. In
order to prevent these leaking into unfortunate places in NIR, we
explicitly strip them off before creating NIR variables and when casting
pointers to non-external memory.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Jason Ekstrand [Wed, 12 Dec 2018 20:32:19 +0000 (14:32 -0600)]
glsl_type: Add support for explicitly laid out matrices and arrays
SPIR-V allows for matrix and array types to be decorated with explicit
byte stride decorations and matrix types to be decorated row- or
column-major. This commit adds support to glsl_type to encode this
information. Because this doesn't work nicely with std430 and std140
alignments, we add asserts to ensure that we don't use any of the std430
or std140 layout functions with explicitly laid out types.
In SPIR-V, the layout information for matrices is applied to the parent
struct member instead of to the matrix type itself. However, this is
gets rather clumsy when you're walking derefs trying to compute offsets
because, the moment you hit a matrix, you have to crawl back the deref
chain and find the struct. Instead, we take the same path here as we've
taken in spirv_to_nir and put the decorations on the matrix type itself.
This also subtly adds support for strided vector types. These don't
come up in SPIR-V directly but you can get one as the result of taking a
column from a row-major matrix or a row from a column-major matrix.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Jason Ekstrand [Wed, 12 Dec 2018 21:25:47 +0000 (15:25 -0600)]
glsl_type: Simplify glsl_channel_type
This is C++ so we can just poke at the fields of glsl_type if we wish
and calling get_instance is way easier and more reliable than handling
each instance separately. While we're at it, we re-arrange the base
type labels to match the enum order and add 8-bit type support.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Tue, 18 Dec 2018 16:30:23 +0000 (10:30 -0600)]
glsl_type: Add a C wrapper to get struct field offsets
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Wed, 12 Dec 2018 21:18:04 +0000 (15:18 -0600)]
glsl_type: Drop the glsl_get_array_instance C helper
It was added in
bce6f9987522 even though it's completely redundant with
glsl_array_type().
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Fri, 14 Dec 2018 17:21:50 +0000 (11:21 -0600)]
nir: Distinguish between normal uniforms and UBOs
Previously, NIR had a single nir_var_uniform mode used for atomic
counters, UBOs, samplers, images, and normal uniforms. This commit
splits this into nir_var_uniform and nir_var_ubo where nir_var_uniform
is still a bit of a catch-all but the nir_var_ubo is specific to UBOs.
While we're at it, we also rename shader_storage to ssbo to follow the
convention.
We need this so that we can distinguish between normal uniforms and UBO
access at the deref level without going all the way back variable and
seeing if it has an interface type.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Fri, 14 Dec 2018 17:31:08 +0000 (11:31 -0600)]
nir: Allow storing to shader_storage
I have no idea how shader_storage made it into the list of banned
variable modes for stores but it clearly should be allowed. This only
doesn't cause us a problem today because we never actually use derefs on
shader_storage variables.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Fri, 14 Dec 2018 17:16:09 +0000 (11:16 -0600)]
nir/validate: Require array indices to match the deref bit size
This doesn't currently change anything because array indices are
required to be 32 bits and all derefs are also 32 bits. However, we
will one day have 64-bit derefs for OpenCL.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Fri, 14 Dec 2018 17:06:07 +0000 (11:06 -0600)]
spirv: Handle arbitrary bit sizes for deref array indices
We already had code in link_as_ssa to handle bit sizes; we just need to
use it. While we're at it we clean up link_as_ssa a bit and add an
explicit bit_size parameter in preparation for a day when we have derefs
that aren't 32 bit.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Tue, 27 Nov 2018 22:28:32 +0000 (16:28 -0600)]
nir/builder: Add nir_i2i and nir_u2u helpers which take a bit size
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com
Jason Ekstrand [Thu, 25 Oct 2018 15:34:34 +0000 (10:34 -0500)]
spirv: Emit NIR deref instructions on-the-fly
This simplifies our deref handling by emitting the actual NIR deref
instructions on-the-fly instead of of building up a deref chain and then
emitting them at the last moment. In order for this to work with the
parts of the compiler that assume they can chase deref chains, we have
to run nir_rematerialize_derefs_in_use_blocks_impl to put the derefs
back in the right places. Otherwise, in cases such as loop continues
where the SPIR-V blocks are not in the same order as the NIR blocks, we
may end up with a deref chain with a parent that does not dominate it's
child and nir_repair_ssa_impl will insert phis in the deref chain.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Sat, 15 Dec 2018 15:57:26 +0000 (09:57 -0600)]
spirv: Sign-extend array indices
The SPIR-V spec was recently updated to clarify that array indices are
treated as signed integers.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Fri, 14 Dec 2018 00:33:46 +0000 (18:33 -0600)]
anv/apply_pipeline_layout: Set the cursor in lower_res_reindex_intrinsic
The loop through instructions doesn't set the cursor for us so unless we
set it somewhere, we may end up emitting instructions in the wrong
place. The only reason why we haven't been bitten by this in the past
is that it only happens in a few variable pointers cases and the CTS
tests for those don't use much control flow so things were getting
emitted in the correct order by accident.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Fri, 14 Dec 2018 16:54:08 +0000 (10:54 -0600)]
spirv: Handle any bit size in vector_insert/extract
This crops up both in the actual SPIR-V VectorInsert/Extract opcodes as
well as various places where we deal with vector derefs.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Wed, 12 Dec 2018 19:56:02 +0000 (13:56 -0600)]
glsl_type: Support serializing 8 and 16-bit types
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Bas Nieuwenhuizen [Sun, 6 Jan 2019 11:34:24 +0000 (12:34 +0100)]
spirv: Fix matrix parameters in function calls.
They can be handled exactly the same as arrays, we just need to handle
the base type correctly in the switches.
Fixes:
a45b6fb4524 "spirv: Pass SSA values through functions"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109204
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Wed, 2 Jan 2019 16:53:41 +0000 (17:53 +0100)]
radv: Fix rasterization precision bits.
Note that these limits are exact, not a "precision is at least x",
as texel coords also get snapped to a multiple of this step size
before filtering.
This fixes CTS tests
dEQP-VK.texture.explicit_lod.2d.sizes.31x55_nearest_linear_mipmap_nearest_repeat
dEQP-VK.texture.explicit_lod.2d.sizes.57x35_nearest_linear_mipmap_nearest_repeat
Fixes:
f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109151
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Kenneth Graunke [Thu, 3 Jan 2019 07:34:19 +0000 (23:34 -0800)]
nir: Make gl_nir_lower_samplers use gl_nir_lower_samplers_as_deref
These days, we have two sampler lowering passes. The newer one,
gl_nir_lower_samplers_as_deref, is used by radeonsi. It rewrites
variables to drop structures out of sampler deref chains, to make
life simpler. It then sets var->data.binding for non-bindless
sampler and image variables based on the GL uniform storage's
opaque index values.
The older one converts sampler deref chains (nir_tex_src_texture_deref)
to a numerical offset (nir_tex_src_texture_offset). It also stores the
constant-valued portion of that number in tex->texture_index, making
life really simple for drivers that don't support indirects. It too
pokes at GL uniform storage's opaque index values.
Logically, we can do the first pass (simplify derefs, set bindings)
then the second (turn derefs to offsets, set texture_index). This
patch does exactly that, eliminating some redundancy (only one pass
has to poke at GL uniform storage), and gaining proper var->data.binding
values for drivers using the full lowering.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Fri, 4 Jan 2019 00:12:20 +0000 (16:12 -0800)]
nir: Fix gl_nir_lower_samplers_as_deref's structure type handling.
We recurse to remove structures, and at each step, re-modify the
resulting type for our link in the deref chain. For arrays, the
result of recursion is the new underlying type - so we wrap it with
the array dimensionality again. For structs, we want to simply use
the new underlying type, skipping the struct altogether.
The correct way to do this is to do nothing at all. Previously, we
had reset type to next->type, which is the /old/ field type, not the
new field type we obtained by recursing. This undid our recursive work.
Fixes about 338 tests with nested structs, such as:
dEQP-GLES2.functional.uniform_api.value.initial.get_uniform.nested_structs_arrays.sampler2D_samplerCube_fragment
Note that currently only radeonsi uses this pass, and NIR support is
disabled there by default, so the breakage was likely not seen by most
people. The next commit uses this pass for more drivers, so this fix
prevents regressions from that change.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Bas Nieuwenhuizen [Sat, 5 Jan 2019 16:45:01 +0000 (17:45 +0100)]
amd/common: Add some parentheses to silence warning.
[1/59] Compiling C object 'src/amd/common/src@amd@common@@amd_common@sta/ac_nir_to_llvm.c.o'.
../mesa/src/amd/common/ac_nir_to_llvm.c: In function ‘get_inst_tessfactor_writemask’:
../mesa/src/amd/common/ac_nir_to_llvm.c:4089:32: warning: suggest parentheses around ‘+’ inside ‘<<’ [-Wparentheses]
writemask = ((1 << num_comps + 1) - 1) << first_component;
~~~~~~~~~~^~~
../mesa/src/amd/common/ac_nir_to_llvm.c:4091:33: warning: suggest parentheses around ‘+’ inside ‘<<’ [-Wparentheses]
writemask = (((1 << num_comps + 1) - 1) << first_component) << 4;
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Sat, 5 Jan 2019 16:43:12 +0000 (17:43 +0100)]
radv: Remove unused variable.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Sat, 5 Jan 2019 16:40:37 +0000 (17:40 +0100)]
radv: Remove device path.
unused and gcc complains about strncpy. (from what I can see because
strncpy does not leave a 0 byte on truncate. That said we don't use
it so this does not fix a real bug).
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Mon, 7 Jan 2019 19:51:13 +0000 (14:51 -0500)]
ac: remove unused variable from ac_build_ddxy
trivial
Andres Gomez [Mon, 7 Jan 2019 13:50:35 +0000 (15:50 +0200)]
glsl: correct typo in GLSL compilation error message
v2: Add the "fix" tag (Erik).
Fixes:
037f68d81e1 ("glsl: apply align layout qualifier rules to block offsets")
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Jason Ekstrand [Mon, 7 Jan 2019 15:35:50 +0000 (09:35 -0600)]
vulkan: Update the XML and headers to 1.1.97
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Andres Gomez [Mon, 17 Dec 2018 23:09:48 +0000 (01:09 +0200)]
docs: update 18.3 and add 19.x cycles for the release calendar
v2: replace incorrect "<td/>" with "<td>" (Eric).
Cc: Dylan Baker <dylan.c.baker@intel.com>
Cc: Juan A. Suarez <jasuarez@igalia.com>
Cc: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Juan A. Suarez <jasuarez@igalia.com>
Bas Nieuwenhuizen [Wed, 5 Dec 2018 10:28:12 +0000 (11:28 +0100)]
anv/android: Do not reject storage images.
We do the ImageFormatProperties check already, and rejecting an usage
flag when both ImageFormatProperties and the WSI (which is Android)
support it is not allowed.
Intel does support storage for some of the support WSI formats, such
as R8G8B8A8_UNORM, and looking at the ISL_SURF_USAGE_DISABLE_AUX_BIT,
the imported images do not have any form of compression that would
prevent this fix.
v2: Also consider STORAGE bit for Gralloc usage bits.
(From Kevin Strasser <kevin.strasser@intel.com>)
Fixes:
053d4c328fa "anv: Implement VK_ANDROID_native_buffer (v9)"
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Bas Nieuwenhuizen [Mon, 24 Dec 2018 14:41:56 +0000 (15:41 +0100)]
radv: Implement buffer stores with less than 4 components.
We started using it in the btoi paths for r32g32b32, and the LLVM IR
checker will complain about it because we end up with intrinsics with
the wrong type extension in the name.
Fixes:
593996bc02 ("radv: implement buffer to image operations for R32G32B32")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Jon Turney [Fri, 10 Nov 2017 13:42:55 +0000 (13:42 +0000)]
appveyor: Add a Cygwin build script
Jon Turney [Fri, 10 Nov 2017 13:27:06 +0000 (13:27 +0000)]
appveyor: put build steps in a script, rather than inline in appveyor.yml
Lucas Stach [Wed, 14 Nov 2018 14:29:04 +0000 (15:29 +0100)]
etnaviv: annotate variables only used in debug build
Some of the status variables in the compiler are only used in asserts
and thus may be unused in release builds. Annotate them accordingly
to avoid 'unused but set' warnings from the compiler.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Lucas Stach [Wed, 14 Nov 2018 13:56:59 +0000 (14:56 +0100)]
etnaviv: enable full overwrite in a few more cases
Take into account the render target format when checking if the color
mask affects all channels of the RT. This allows to enable full
overwrite in a few cases where a non-alpha format is used.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Timothy Arceri [Sun, 6 Jan 2019 23:33:43 +0000 (10:33 +1100)]
nir: avoid uninitialized variable warning
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109231
Timothy Arceri [Wed, 2 Jan 2019 23:03:05 +0000 (10:03 +1100)]
st/glsl: refactor st_link_nir()
The functional change here is moving the nir_lower_io_to_scalar_early()
calls inside st_nir_link_shaders() and moving the st_nir_opts() call
after the call to nir_lower_io_arrays_to_elements().
This fixes a bug with the following piglit test due to the current code
not cleaning up dead code after we lower arrays. This was causing an
assert in the new duplicate varyings link time opt introduced in
70be9afccb23.
tests/spec/glsl-1.10/execution/vsfs-unused-array-member.shader_test
Moving the nir_lower_io_to_scalar_early() calls also allows us to tidy
up the code a little and merge some loops.
Reviewed-by: Eric Anholt <eric@anholt.net>
Eric Anholt [Thu, 20 Dec 2018 17:43:43 +0000 (09:43 -0800)]
v3d: Use the core tex lowering.
Even without any clever optimization on the unpack operations, this gives
us a useful value for the channels read field, which we can use to avoid
ldtmu instructions to the no-op register.
instructions in affected programs: 890712 -> 881974 (-0.98%)
Eric Anholt [Wed, 19 Dec 2018 21:53:39 +0000 (13:53 -0800)]
nir: Add nir_lower_tex options to lower sampler return formats.
I've been doing this in the nir-to-vir and nir-to-qir backends of v3d and
vc4, but nir could potentially do some useful stuff for us (like avoiding
unpack/repacks) if we give it the information.
v2: Skip lowering for txs/query_levels
v3: Fix a crash on old-style shadow
v4: Rename to tex_packing, use nir_format_unpack_sint/uint helpers, pack
the enum.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Anholt [Wed, 2 Jan 2019 22:50:20 +0000 (14:50 -0800)]
nir: Allow nir_format_unpack_int/sint to unpack larger values.
For V3D, I want to unpack 4-16-bit packed integers for 8 and 16-bit
integer samplers.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Fri, 4 Jan 2019 17:32:40 +0000 (11:32 -0600)]
intel/blorp: Be more conservative about copying clear colors
In
92eb5bbc68d7324 we attempted to avoid copying clear colors whenever
we weren't doing a resolve. However, this broke MSAA resolves because
we need the clear color in the source. This patch makes blorp much more
conservative such that it only avoids the clear color copy if either
aux_usage == NONE or it's explicitly doing a fast-clear.
Fixes:
92eb5bbc68d7 "intel/blorp: Only copy clear color when doing..."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107728
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Eric Anholt [Thu, 3 Jan 2019 19:38:57 +0000 (11:38 -0800)]
v3d: Stop scalarizing our uniform loads.
We can pull a whole vector in a single indirect load. This saves a bunch
of round-trips to the TMU, instructions for setting up multiple loads,
references to the UBO base in the uniforms, and apparently manages to
reduce register pressure as well.
instructions in affected programs:
3086665 ->
2454967 (-20.47%)
uniforms in affected programs: 919581 -> 721039 (-21.59%)
threads in affected programs: 1710 -> 3420 (100.00%)
spills in affected programs: 596 -> 522 (-12.42%)
fills in affected programs: 680 -> 562 (-17.35%)
Improves 3dmmes performance by 2.29312% +/- 0.139825% (n=5)
Eric Anholt [Thu, 3 Jan 2019 20:13:18 +0000 (12:13 -0800)]
v3d: Do UBO loads a vector at a time.
In the process of adding support for SSBOs and CS shared vars, I ended up
needing a helper function for doing TMU general ops. This helper can be
that starting point, and saves us a bunch of round-trips to the TMU by
loading a vector at a time.
Eric Anholt [Thu, 3 Jan 2019 19:31:37 +0000 (11:31 -0800)]
v3d: Remove dead switch cases and comments from v3d_nir_lower_io.
Moving things to NIR left this mess around. All we lower now is uniforms.
Eric Anholt [Thu, 3 Jan 2019 06:48:29 +0000 (22:48 -0800)]
v3d: Fix up VS output setup during precompiles.
I noticed that a VS I was debugging was missing all of its output stores
-- outputs_written was for POS, VAR0, VAR3, while the shader's variables
were POS, VAR9, and VAR12. I'm not sure what outputs_written is supposed
to be doing here, but we can just walk the declared variables and avoid
both this bug and the emission of extra stvpms for less-than-vec4
varyings.
Eric Anholt [Thu, 3 Jan 2019 01:34:11 +0000 (17:34 -0800)]
v3d: Reinstate the new shader-db output after v3d_compile() refactor.
I misplaced it in the rebase conflicts.
Caio Marcelo de Oliveira Filho [Wed, 19 Dec 2018 23:23:28 +0000 (15:23 -0800)]
nir: remove dead code from copy_prop_vars
When copy_prop_vars also took care of dead write handling, intrin was
used as part of store_to_entry. Now it isn't, so this assignment
isn't used really used. Add a comment clarifying what happens to
intrin.
Fixes:
4dfa7adc100 "nir: Remove handling of dead writes from copy_prop_vars"
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Thu, 3 Jan 2019 16:18:48 +0000 (16:18 +0000)]
i965: add CS stall on VF invalidation workaround
Even with the previous commit, hangs are still happening. The problem
there is that the VF cache invalidate do happen immediately without
waiting for previous rendering to complete. What happens is that we
invalidate the cache the moment the PIPE_CONTROL is parsed but we
still have old rendering in the pipe which continues to pull data into
the cache with the old high address bits. The later rendering with the
new high address bits then doesn't have the clean cache that it
expects/needs.
v2: Update commit message/explanation with Jason's
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Fixes:
a363bb2cd0e2a1 ("i965: Allocate VMA in userspace for full-PPGTT systems.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109072
Lionel Landwerlin [Thu, 3 Jan 2019 16:17:04 +0000 (16:17 +0000)]
i965: include draw_params/derived_draw_params for VF cache workaround
These buffers are using VB slots and should be included in the
workaround decision.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Fixes:
a363bb2cd0e2a1 ("i965: Allocate VMA in userspace for full-PPGTT systems.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109072
Lionel Landwerlin [Thu, 3 Jan 2019 16:14:50 +0000 (16:14 +0000)]
intel/blorp: emit VF caching workaround before 3DSTATE_VERTEX_BUFFERS
Probably no difference but it's nice to have i965 & blorp emit things
in the same order.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Thu, 3 Jan 2019 16:13:14 +0000 (16:13 +0000)]
i965: limit VF caching workaround to gen8/9/10
Documentation of the 3DSTATE_VERTEX_BUFFERS packet says this is only
needed before ICL.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Andres Gomez [Wed, 2 Jan 2019 13:21:17 +0000 (15:21 +0200)]
glsl/linker: complete documentation for assign_attribute_or_color_locations
Commit
27f1298b9d9 ("glsl/linker: validate attribute aliasing before optimizations")
forgot to complete the documentation.
Cc: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Gurchetan Singh [Thu, 3 Jan 2019 00:55:34 +0000 (16:55 -0800)]
virgl: remove empty file
Fixes: 174f53 ("virgl: consolidate transfer code")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Gurchetan Singh [Fri, 28 Dec 2018 23:07:25 +0000 (00:07 +0100)]
virgl: don't flush an empty range
Otherwise, the gl-1.0-long-dlist Piglit test crashes.
Fixes: db7757 ("virgl: modify how we handle GL_MAP_FLUSH_EXPLICIT_BIT")
Reported by airlied@
v2: Exit on any invalid range (Erik)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109190
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Jakob Bornecrantz <jakob@collabora.com>
Eric Engestrom [Thu, 3 Jan 2019 16:01:18 +0000 (16:01 +0000)]
docs: advertise distro-provided meson cross-files
Hopefully we can kick start the revolution and other distros will start
providing them as well :)
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Thu, 3 Jan 2019 15:44:42 +0000 (15:44 +0000)]
docs: fix the meson aarch64 cross-file
`gcc-ar` is preferred over the generic `ar`, and the `arm` family is
for 32-bit ARM [1].
[1] https://mesonbuild.com/Reference-tables.html#cpu-families
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Jakob Bornecrantz [Mon, 12 Nov 2018 14:55:43 +0000 (14:55 +0000)]
virgl/vtest: Use default socket name from protocol header
No functional change as the socket name is the same,
just removing the double definition of the path.
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Signed-off-by: Jakob Bornecrantz <jakob@collabora.com>
Rob Clark [Wed, 2 Jan 2019 18:24:31 +0000 (13:24 -0500)]
freedreno: fix staging resource size for arrays
A 2d-array texture (for example), should get the # of array elements
from box->depth, rather than depth0 which is minified.
Fixes dEQP-GLES3.functional.shaders.texture_functions.texture.sampler2darray_bias_float_fragment
with tiled textures.
Reported-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 2 Jan 2019 16:35:02 +0000 (11:35 -0500)]
freedreno: remove blit_via_copy_region()
If we hit the memcpy() path for copy_region(), that will try to do a
transfer_map(), which goes badly for blits to/from staging triggered
by transfer_map() or transfer_unmap().
We could possibly add fd_blit2() which has allow_transfer_map param,
and call that for staging blits. But I'm not really sure if trying
the blit via copy_region() is very useful. At least for newer gens
that implement fd_context::blit(), it probably isn't.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 2 Jan 2019 16:06:11 +0000 (11:06 -0500)]
freedreno/a6xx: rework blitter API
Switch over to using fd_context::blit(), in the same way that a5xx does.
The previous patch wires fd_resource_copy_region() up to the blitter so
a6xx no longer needs to bypass the core layer to accelerate this.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 2 Jan 2019 16:04:16 +0000 (11:04 -0500)]
freedreno: try blitter for fd_resource_copy_region()
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 2 Jan 2019 15:54:06 +0000 (10:54 -0500)]
freedreno: rework blit API
First step to unify the way fd5 and fd6 blitter works. Currently a6xx
bypasses the blit API in order to also accelerate resource_copy_region()
But this approach can lead to infinite recursion:
#0 fd_alloc_staging (ctx=0x5555936480, rsc=0x7fac485f90, level=0, box=0x7fbab29220) at ../src/gallium/drivers/freedreno/freedreno_resource.c:291
#1 0x0000007fbdebed04 in fd_resource_transfer_map (pctx=0x5555936480, prsc=0x7fac485f90, level=0, usage=258, box=0x7fbab29220, pptrans=0x7fbab29240) at ../src/gallium/drivers/freedreno/freedreno_resource.c:479
#2 0x0000007fbe5c5068 in u_transfer_helper_transfer_map (pctx=0x5555936480, prsc=0x7fac485f90, level=0, usage=258, box=0x7fbab29220, pptrans=0x7fbab29240) at ../src/gallium/auxiliary/util/u_transfer_helper.c:243
#3 0x0000007fbde2dcb8 in util_resource_copy_region (pipe=0x5555936480, dst=0x7fac485f90, dst_level=0, dst_x=0, dst_y=0, dst_z=0, src=0x7fac47c780, src_level=0, src_box_in=0x7fbab2945c) at ../src/gallium/auxiliary/util/u_surface.c:350
#4 0x0000007fbdf2282c in fd_resource_copy_region (pctx=0x5555936480, dst=0x7fac485f90, dst_level=0, dstx=0, dsty=0, dstz=0, src=0x7fac47c780, src_level=0, src_box=0x7fbab2945c) at ../src/gallium/drivers/freedreno/freedreno_blitter.c:173
#5 0x0000007fbdf085d4 in fd6_resource_copy_region (pctx=0x5555936480, dst=0x7fac485f90, dst_level=0, dstx=0, dsty=0, dstz=0, src=0x7fac47c780, src_level=0, src_box=0x7fbab2945c) at ../src/gallium/drivers/freedreno/a6xx/fd6_blitter.c:587
#6 0x0000007fbde2f3d0 in util_try_blit_via_copy_region (ctx=0x5555936480, blit=0x7fbab29430) at ../src/gallium/auxiliary/util/u_surface.c:864
#7 0x0000007fbdec02c4 in fd_blit (pctx=0x5555936480, blit_info=0x7fbab29588) at ../src/gallium/drivers/freedreno/freedreno_resource.c:993
#8 0x0000007fbdf08408 in fd6_blit (pctx=0x5555936480, info=0x7fbab29588) at ../src/gallium/drivers/freedreno/a6xx/fd6_blitter.c:546
#9 0x0000007fbdebdc74 in do_blit (ctx=0x5555936480, blit=0x7fbab29588, fallback=false) at ../src/gallium/drivers/freedreno/freedreno_resource.c:129
#10 0x0000007fbdebe58c in fd_blit_from_staging (ctx=0x5555936480, trans=0x7fac47b7e8) at ../src/gallium/drivers/freedreno/freedreno_resource.c:326
#11 0x0000007fbdebea38 in fd_resource_transfer_unmap (pctx=0x5555936480, ptrans=0x7fac47b7e8) at ../src/gallium/drivers/freedreno/freedreno_resource.c:416
#12 0x0000007fbe5c5c68 in u_transfer_helper_transfer_unmap (pctx=0x5555936480, ptrans=0x7fac47b7e8) at ../src/gallium/auxiliary/util/u_transfer_helper.c:516
#13 0x0000007fbde2de24 in util_resource_copy_region (pipe=0x5555936480, dst=0x7fac485f90, dst_level=0, dst_x=0, dst_y=0, dst_z=0, src=0x7fac47b8e0, src_level=0, src_box_in=0x7fbab2997c) at ../src/gallium/auxiliary/util/u_surface.c:376
#14 0x0000007fbdf2282c in fd_resource_copy_region (pctx=0x5555936480, dst=0x7fac485f90, dst_level=0, dstx=0, dsty=0, dstz=0, src=0x7fac47b8e0, src_level=0, src_box=0x7fbab2997c) at ../src/gallium/drivers/freedreno/freedreno_blitter.c:173
#15 0x0000007fbdf085d4 in fd6_resource_copy_region (pctx=0x5555936480, dst=0x7fac485f90, dst_level=0, dstx=0, dsty=0, dstz=0, src=0x7fac47b8e0, src_level=0, src_box=0x7fbab2997c) at ../src/gallium/drivers/freedreno/a6xx/fd6_blitter.c:587
...
Instead rework the API to push the fallback back to core code, so that
we can rework resource_copy_region() to have it's own fallback path,
and then finally convert fd6 over to work in the same way.
This also makes ctx->blit() optional, and cleans up some unnecessary
callers.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 26 Dec 2018 19:09:55 +0000 (14:09 -0500)]
freedreno: skip depth resolve if not written
For multi-pass rendering, it is common to keep the same depth buffer
from previous pass, to discard geometry that would be hidden by later
draws. In the later passes with depth-test enabled, but depth-write
disabled, there is no reason to do gmem2mem resolve.
TODO probably do something similar for stencil.. although stencil
buffer isn't used as commonly these days
Signed-off-by: Rob Clark <robdclark@gmail.com>
Timothy Arceri [Thu, 8 Dec 2016 02:25:00 +0000 (13:25 +1100)]
nir: merge some basic consecutive ifs
After trying multiple times to merge if-statements with phis
between them I've come to the conclusion that it cannot be done
without regressions. The problem is for some shaders we end up
with a whole bunch of phis for the merged ifs resulting in
increased register pressure.
So this patch just merges ifs that have no phis between them.
This seems to be consistent with what LLVM does so for radeonsi
we only see a change (although its a large change) in a single
shader.
Shader-db results i965 (SKL):
total instructions in shared programs:
13098176 ->
13098152 (<.01%)
instructions in affected programs: 1326 -> 1302 (-1.81%)
helped: 4
HURT: 0
total cycles in shared programs:
332032989 ->
332037583 (<.01%)
cycles in affected programs: 60665 -> 65259 (7.57%)
helped: 0
HURT: 4
The cycles estimates reported by shader-db for i965 seem inaccurate
as the only difference in the final code is the removal of the
redundent condition evaluations and jumps.
Also the biggest code reduction (~7%) for radeonsi was in a tomb
raider tressfx shader but for some reason this does not get merged
for i965.
Shader-db results radeonsi (VEGA):
Totals from affected shaders:
SGPRS: 232 -> 232 (0.00 %)
VGPRS: 164 -> 164 (0.00 %)
Spilled SGPRs: 59 -> 59 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 14584 -> 13520 (-7.30 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 13 -> 13 (0.00 %)
Wait states: 0 -> 0 (0.00 %)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Timothy Arceri [Tue, 20 Nov 2018 23:04:24 +0000 (10:04 +1100)]
nir: add rewrite_phi_predecessor_blocks() helper
This will also be used by the if merge pass in the following commit.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Timothy Arceri [Wed, 2 Jan 2019 05:00:12 +0000 (16:00 +1100)]
nir: simplify does_varying_match()
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Timothy Arceri [Wed, 2 Jan 2019 05:00:11 +0000 (16:00 +1100)]
nir: make use of does_varying_match() helper
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Timothy Arceri [Wed, 2 Jan 2019 05:00:10 +0000 (16:00 +1100)]
nir: make nir_opt_remove_phis_impl() static
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Eric Anholt [Wed, 26 Dec 2018 21:20:25 +0000 (13:20 -0800)]
v3d: Refactor compiler entrypoints.
Before, I had per-stage entryoints with some helpers shared between them.
As I extended for compute shaders and shader-db, it turned out that the
other common code in the middle wanted to be shared too.
Eric Anholt [Mon, 31 Dec 2018 20:18:34 +0000 (12:18 -0800)]
v3d: Handle dynamically uniform IF statements with uniform control flow.
Loops will be trickier, since we need some analysis to figure out if the
breaks/continues inside are uniform. Until we get that in NIR, this gets
us some quick wins.
total instructions in shared programs:
6192844 ->
6174162 (-0.30%)
instructions in affected programs: 487781 -> 469099 (-3.83%)
Eric Anholt [Sat, 29 Dec 2018 00:31:07 +0000 (16:31 -0800)]
v3d: Fold comparisons for IF conditions into the flags for the IF.
total instructions in shared programs:
6193810 ->
6192844 (-0.02%)
instructions in affected programs: 800373 -> 799407 (-0.12%)
Eric Anholt [Mon, 31 Dec 2018 21:09:45 +0000 (13:09 -0800)]
v3d: Don't try to fold non-SSA-src comparisons into bcsels.
There could have been a write of a src in between the comparison and the
bcsel that would invalidate the comparison.
Eric Anholt [Mon, 31 Dec 2018 21:05:06 +0000 (13:05 -0800)]
v3d: Move the "Find the ALU instruction generating our bool" out of bcsel.
This will be reused for if statements.
Eric Anholt [Fri, 28 Dec 2018 21:45:25 +0000 (13:45 -0800)]
v3d: Simplify the emission of comparisons for the bcsel optimization.
I wanted to reuse the comparison stuff for nir_ifs, but for that I just
want the flags and no destination value. Splitting the conditions from
the destinations ended up cleaning the existing code up, anyway.
Eric Anholt [Sun, 30 Dec 2018 16:59:54 +0000 (08:59 -0800)]
v3d: Don't forget to include RT writes in precompiles.
Looking at some assembly dumps for an optimization, we were clearly
missing important parts of the shader!
Eric Anholt [Mon, 31 Dec 2018 19:51:01 +0000 (11:51 -0800)]
v3d: Fix segfault when failing to compile a program.
We'll still fail at draw time, but this avoids a regression in shader-db
execution once I enable TLB writes in precompiles.
Fixes:
b38e4d313fc2 ("v3d: Create a state uploader for packing our shaders together.")
Marek Olšák [Fri, 14 Dec 2018 21:03:00 +0000 (16:03 -0500)]
radeonsi: always unmap texture CPU mappings on 32-bit CPU architectures
Team Fortress 2 32-bit version runs out of the CPU address space.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Fri, 14 Dec 2018 20:08:50 +0000 (15:08 -0500)]
radeonsi: remove unused variables in si_insert_input_ptr
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Sat, 10 Nov 2018 03:27:05 +0000 (22:27 -0500)]
radeonsi: use u_decomposed_prims_for_vertices instead of u_prims_for_vertices
It seems to be the same, but this doesn't use integer division with
a variable divisor.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Mon, 3 Dec 2018 19:58:08 +0000 (14:58 -0500)]
radeonsi: make si_cp_wait_mem more configurable
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Tue, 13 Nov 2018 02:29:27 +0000 (21:29 -0500)]
radeonsi: call si_fix_resource_usage for the GS copy shader as well
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Tue, 13 Nov 2018 01:38:46 +0000 (20:38 -0500)]
radeonsi: don't emit redundant PKT3_NUM_INSTANCES packets
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Caio Marcelo de Oliveira Filho [Wed, 19 Dec 2018 20:13:46 +0000 (12:13 -0800)]
nir: add a way to print the deref chain
Makes debugging easier when we care about the deref chain and not the
deref instruction itself. To make it take a const pointer, constify
some of the static functions in nir_print.c.
Reviewed-by: Eric Anholt <eric@anholt.net>
Dylan Baker [Tue, 1 Jan 2019 03:23:52 +0000 (19:23 -0800)]
meson: Error out if building nouveau and using LLVM without rtti
Nouveau requires rtti. Often LLVM is configured without rtti, and code
with and without cannot be linked safely. Lets just error out if nouveau
is requested and llvm is built without rtti.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109202
Fixes:
c5a97d658ec19cc02719d7f86c1b0715e3d9ffc4
("meson: fix builds against LLVM built without rtti")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Alexander von Gluck IV [Thu, 27 Dec 2018 20:41:47 +0000 (20:41 +0000)]
egl/haiku: Fix reference to disp vs dpy
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Fixes:
00992700c9a812a54563 "egl: set the EGLDevice when creating a display"
Iago Toral Quiroga [Thu, 31 May 2018 08:34:03 +0000 (10:34 +0200)]
compiler/spirv: use 32-bit polynomial approximation for 16-bit asin()
The 16-bit polynomial execution doesn't meet Khronos precision requirements.
Also, the half-float denorm range starts at 2^(-14) and with asin taking input
values in the range [0, 1], polynomial approximations can lead to flushing
relatively easy.
An alternative is to use the atan2 formula to compute asin, which is the
reference taken by Khronos to determine precision requirements, but that
ends up generating too many additional instructions when compared to the
polynomial approximation. Specifically, for the Intel case, doing this
adds +41 instructions to the program for each asin/acos call, which looks
like an undesirable trade off.
So for now we take the easy way out and fallback to using the 32-bit
polynomial approximation, which is better (faster) than the 16-bit atan2
implementation and gives us better precision that matches Khronos
requirements.
v2:
- Fallback to 32-bit using recursion (Jason).
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>