OSDN Git Service
Stephen Hines [Tue, 27 Aug 2013 22:18:19 +0000 (15:18 -0700)]
am
f31eb8ab: (-s ours) Merge "DO NOT MERGE - Allow global-merge option to be accessed externally."
* commit '
f31eb8ab038dabe0f70710696e0091b85f3a84e7':
DO NOT MERGE - Allow global-merge option to be accessed externally.
Stephen Hines [Tue, 27 Aug 2013 22:14:35 +0000 (22:14 +0000)]
Merge "DO NOT MERGE - Allow global-merge option to be accessed externally."
Stephen Hines [Thu, 11 Jul 2013 21:21:25 +0000 (14:21 -0700)]
DO NOT MERGE - Allow global-merge option to be accessed externally.
Change-Id: I39d1c5e05b5f1bbbf76f7491f7dc8cfa70a83611
Stephen Hines [Sat, 3 Aug 2013 00:40:53 +0000 (17:40 -0700)]
am
c7ef4e40: Fix Windows build issues for LLVM.
* commit '
c7ef4e40cf01397ebd25fc9622fc8eb9c61a547d':
Fix Windows build issues for LLVM.
Stephen Hines [Tue, 30 Jul 2013 18:21:59 +0000 (11:21 -0700)]
Fix Windows build issues for LLVM.
Remove HAVE_SYS_UIO_H redefinition due to Windows build conflicts.
Add dependency on imagehlp.lib/dll.
Change-Id: I41cb9331c1fbde849ff9dc6906cbe9d8ae6bbc50
The Android Open Source Project [Thu, 16 May 2013 12:43:25 +0000 (05:43 -0700)]
Reconcile with jb-mr2-release - do not merge
Change-Id: I05277f3fbd3b0bd9b67383c4549cd1256aacce2e
The Android Automerger [Thu, 18 Apr 2013 12:55:30 +0000 (05:55 -0700)]
merge in jb-mr2-release history after reset to jb-mr2-dev
Joey Gouly [Thu, 18 Apr 2013 00:41:36 +0000 (17:41 -0700)]
am
b84f869c: Change CloneFunctionInto to always clone Argument attributes induvidually, rather than checking if the source and destination have the same number of arguments and copying the attributes over directly.
* commit '
b84f869c110f972627adb7696b5e722fe6d724ba':
Change CloneFunctionInto to always clone Argument attributes induvidually, rather than checking if the source and destination have the same number of arguments and copying the attributes over directly.
Joey Gouly [Wed, 10 Apr 2013 10:37:38 +0000 (10:37 +0000)]
Change CloneFunctionInto to always clone Argument attributes induvidually,
rather than checking if the source and destination have the same number of
arguments and copying the attributes over directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179169
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The Android Open Source Project [Tue, 26 Mar 2013 17:49:17 +0000 (10:49 -0700)]
Reconcile with jb-mr2-release - do not merge
Change-Id: I4c24e31c6bac8aed141393c6ea953f759287aa0b
The Android Automerger [Mon, 25 Mar 2013 12:55:44 +0000 (05:55 -0700)]
merge in jb-mr2-release history after reset to jb-mr2-dev
Stephen Hines [Mon, 25 Mar 2013 07:27:53 +0000 (07:27 +0000)]
am
b497f3f2: Add missing libLLVMObject.a to .so build.
* commit '
b497f3f2348cfff41652a8b93fc55e2360c47eef':
Add missing libLLVMObject.a to .so build.
Stephen Hines [Mon, 25 Mar 2013 07:08:26 +0000 (00:08 -0700)]
Add missing libLLVMObject.a to .so build.
Change-Id: Ifbd7721989bae5da592069b7aace77165d528f8f
The Android Open Source Project [Wed, 20 Mar 2013 16:32:28 +0000 (09:32 -0700)]
Reconcile with jb-mr2-release - do not merge
Change-Id: I67897269ce1b443665f5b8333809984b5f851743
The Android Automerger [Wed, 20 Mar 2013 12:55:36 +0000 (05:55 -0700)]
merge in jb-mr2-release history after reset to jb-mr2-dev
Stephen Hines [Wed, 20 Mar 2013 04:33:55 +0000 (04:33 +0000)]
am
d212f3fd: Update LLVM for merge to r177342.
* commit '
d212f3fdfcfd01d5bc24ac4614b7e23478432f80':
Update LLVM for merge to r177342.
Stephen Hines [Wed, 20 Mar 2013 04:33:54 +0000 (04:33 +0000)]
am
2d4629c5: Merge branch \'upstream\' into merge_2013_03_18
* commit '
2d4629c5d7dcc6582fa7b85a517744f1a3654eba': (424 commits)
Change NULL to 0.
Register the flush function for each compile unit.
Remove trailing spaces.
Fix PPC unaligned 64-bit loads and stores
ARM cost model: Make some vector integer to float casts cheaper
ARM cost model: Correct cost for some cheap float to integer conversions
Extend global merge pass to optionally consider global constant variables. Also add some checks to not merge globals used within landing pad instructions or marked as "used".
Change test cases to handle unaligned references.
Remove unnecessary leading comment characters in lit-only file
Add SchedRW annotations to most of X86InstrSSE.td.
Annotate X86 arithmetic instructions with SchedRW lists.
Check whether a pointer is non-null (isKnownNonNull) in isKnownNonZero.
TableGen fix for the new machine model.
Include '.test' suffix in target specific lit configs that need it
Make the fields in the diagram match the descriptive text above them.
Update
Fix 80-col. violations in PPCCTRLoops
Fix large count and negative constant count handling in PPCCTRLoops
Cleanup initial-value constants in PPCCTRLoops
Fix integer comparison in DIEInteger::BestForm.
...
Stephen Hines [Wed, 20 Mar 2013 04:33:53 +0000 (04:33 +0000)]
am
cd4c0bff: Revert "Android uses cacheflush(long, long, long) for MIPS."
* commit '
cd4c0bff77a9b5617896982e99dc80f469e26e4f':
Revert "Android uses cacheflush(long, long, long) for MIPS."
Stephen Hines [Tue, 19 Mar 2013 00:55:03 +0000 (17:55 -0700)]
Update LLVM for merge to r177342.
Change-Id: Ie489c8fab15789330f6ac968087ba14953dfacca
Stephen Hines [Tue, 19 Mar 2013 00:36:31 +0000 (17:36 -0700)]
Merge branch 'upstream' into merge_2013_03_18
Stephen Hines [Tue, 19 Mar 2013 00:17:33 +0000 (17:17 -0700)]
Revert "Android uses cacheflush(long, long, long) for MIPS."
This reverts commit
f81e00be9486cb813cdabb73d533d0d5115c6d0f.
Jakub Staszak [Mon, 18 Mar 2013 23:08:01 +0000 (23:08 +0000)]
Change NULL to 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177342
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Bill Wendling [Mon, 18 Mar 2013 23:04:39 +0000 (23:04 +0000)]
Register the flush function for each compile unit.
For each compile unit, we want to register a function that will flush that
compile unit. Otherwise, __gcov_flush() would only flush the counters within the
current compile unit, and not any outside of it.
PR15191 & <rdar://problem/
13167507>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177340
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Jakub Staszak [Mon, 18 Mar 2013 23:04:30 +0000 (23:04 +0000)]
Remove trailing spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177339
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Hal Finkel [Mon, 18 Mar 2013 23:00:58 +0000 (23:00 +0000)]
Fix PPC unaligned 64-bit loads and stores
PPC64 supports unaligned loads and stores of 64-bit values, but
in order to use the r+i forms, the offset must be a multiple of 4.
Unfortunately, this cannot always be determined by examining the
immediate itself because it might be available only via a TOC entry.
In order to get around this issue, we additionally predicate the
selection of the r+i form on the alignment of the load or store
(forcing it to be at least 4 in order to select the r+i form).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177338
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Arnold Schwaighofer [Mon, 18 Mar 2013 22:47:09 +0000 (22:47 +0000)]
ARM cost model: Make some vector integer to float casts cheaper
The default logic marks them as too expensive.
For example, before this patch we estimated:
cost of 16 for instruction: %r = uitofp <4 x i16> %v0 to <4 x float>
While this translates to:
vmovl.u16 q8, d16
vcvt.f32.u32 q8, q8
All other costs are left to the values assigned by the fallback logic. Theses
costs are mostly reasonable in the sense that they get progressively more
expensive as the instruction sequences emitted get longer.
radar://
13445992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177334
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Arnold Schwaighofer [Mon, 18 Mar 2013 22:47:06 +0000 (22:47 +0000)]
ARM cost model: Correct cost for some cheap float to integer conversions
Fix cost of some "cheap" cast instructions. Before this patch we used to
estimate for example:
cost of 16 for instruction: %r = fptoui <4 x float> %v0 to <4 x i16>
While we would emit:
vcvt.s32.f32 q8, q8
vmovn.i32 d16, q8
vuzp.8 d16, d17
All other costs are left to the values assigned by the fallback logic. Theses
costs are mostly reasonable in the sense that they get progressively more
expensive as the instruction sequences emitted get longer.
radar://
13434072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177333
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Quentin Colombet [Mon, 18 Mar 2013 22:30:07 +0000 (22:30 +0000)]
Extend global merge pass to optionally consider global constant variables.
Also add some checks to not merge globals used within landing pad instructions or marked as "used".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177331
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Bill Schmidt [Mon, 18 Mar 2013 22:12:04 +0000 (22:12 +0000)]
Change test cases to handle unaligned references.
Hal Finkel recently added code to allow unaligned memory references
for PowerPC. Two tests were temporarily modified with
-disable-ppc-unaligned to keep them from failing. This patch adjusts
the expected code generation for the unaligned references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177328
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David Blaikie [Mon, 18 Mar 2013 22:08:16 +0000 (22:08 +0000)]
Remove unnecessary leading comment characters in lit-only file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177327
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Jakob Stoklund Olesen [Mon, 18 Mar 2013 22:01:35 +0000 (22:01 +0000)]
Add SchedRW annotations to most of X86InstrSSE.td.
We hitch a ride with the existing OpndItins class that was used to add
instruction itinerary classes in the many multiclasses in this file.
Use the link provided by the X86FoldableSchedWrite.Folded to find the
right SchedWrite for folded loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177326
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Jakob Stoklund Olesen [Mon, 18 Mar 2013 21:32:39 +0000 (21:32 +0000)]
Annotate X86 arithmetic instructions with SchedRW lists.
This new-style scheduling information is going to replace the
instruction iteneraries.
This also serves as a test case for Andy's fix in r177317.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177323
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Manman Ren [Mon, 18 Mar 2013 21:23:25 +0000 (21:23 +0000)]
Check whether a pointer is non-null (isKnownNonNull) in isKnownNonZero.
This handles the case where we have an inbounds GEP with alloca as the pointer.
This fixes the regression in PR12750 and rdar://
13286434.
Note that we can also fix this by handling some GEP cases in isKnownNonNull.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177321
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Andrew Trick [Mon, 18 Mar 2013 20:42:25 +0000 (20:42 +0000)]
TableGen fix for the new machine model.
Properly handle cases where a group of instructions have different
SchedRW lists with the same itinerary class.
This was supposed to work, but I left in an early break.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177317
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David Blaikie [Mon, 18 Mar 2013 20:31:44 +0000 (20:31 +0000)]
Include '.test' suffix in target specific lit configs that need it
Apparently my final cleanup to use a relevant suffix for these tests before
committing r176831 caused them to stop running since lit wasn't configured to
run tests with that suffix in those directories (why don't we just have a
global suffix list?). So, add the suffix to the relevant directories & fix the
test that has bitrotted over the last week due to my debug info schema changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177315
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Eric Christopher [Mon, 18 Mar 2013 20:21:47 +0000 (20:21 +0000)]
Make the fields in the diagram match the descriptive text above them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177314
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Bill Wendling [Mon, 18 Mar 2013 17:47:33 +0000 (17:47 +0000)]
Update
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177298
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Hal Finkel [Mon, 18 Mar 2013 17:40:46 +0000 (17:40 +0000)]
Fix 80-col. violations in PPCCTRLoops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177296
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Hal Finkel [Mon, 18 Mar 2013 17:40:44 +0000 (17:40 +0000)]
Fix large count and negative constant count handling in PPCCTRLoops
This commit fixes an assert that would occur on loops with large constant counts
(like looping for ((uint32_t) -1) iterations on PPC64). The existing code did
not handle counts that it computed to be negative (asserting instead), but
these can be created with valid inputs.
This bug was discovered by bugpoint while I was attempting to isolate a
completely different problem.
Also, in writing test cases for the negative-count problem, I discovered that
the ori/lsi handling was broken (there was a typo which caused the logic that
was supposed to detect these pairs and extract the iteration count to always
fail). This has now also been corrected (and is covered by one of the new test
cases).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177295
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Hal Finkel [Mon, 18 Mar 2013 17:40:27 +0000 (17:40 +0000)]
Cleanup initial-value constants in PPCCTRLoops
Because the initial-value constants had not been added to the list
of instructions considered for DCE the resulting code had redundant
constant-materialization instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177294
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Hans Wennborg [Mon, 18 Mar 2013 17:03:05 +0000 (17:03 +0000)]
Fix integer comparison in DIEInteger::BestForm.
The always-true "(int)Int == (signed)Int" comparison was found
while experimenting with a potential new Clang warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177290
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Matthew Curtis [Mon, 18 Mar 2013 13:08:24 +0000 (13:08 +0000)]
ReleaseNotes: Tweak hexagonv2/hexagonv3 removal note.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177284
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Benjamin Kramer [Mon, 18 Mar 2013 12:14:30 +0000 (12:14 +0000)]
Remove default copy ctor/assignment, makes AttributeSet trivially copyable.
And enables SmallVector's pod optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177281
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David Tweed [Mon, 18 Mar 2013 12:07:24 +0000 (12:07 +0000)]
Initially forgotten-to-svn-add test case for r177279.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177280
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David Tweed [Mon, 18 Mar 2013 11:54:44 +0000 (11:54 +0000)]
The optimization a + (-0.0f) -> a was being misapplied to a + (+0.0f) in the vector case (because
we weren't differntiating floating-point zeroinitializers from other zero-initializers)
which was causing problems for code relying upon a + (+0.0f) to, eg, flush denormals to
0. Make the scalar and vector cases have the same behaviour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177279
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Christian Konig [Mon, 18 Mar 2013 11:34:16 +0000 (11:34 +0000)]
R600/SI: implement indirect adressing for SI
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177277
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Christian Konig [Mon, 18 Mar 2013 11:34:10 +0000 (11:34 +0000)]
R600/SI: add float vector types
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177276
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Christian Konig [Mon, 18 Mar 2013 11:34:05 +0000 (11:34 +0000)]
R600/SI: add shl pattern
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177275
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Christian Konig [Mon, 18 Mar 2013 11:34:00 +0000 (11:34 +0000)]
R600/SI: add BUFFER_LOAD_DWORD pattern
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177274
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Christian Konig [Mon, 18 Mar 2013 11:33:55 +0000 (11:33 +0000)]
R600/SI: implement SI.load.const intrinsic
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177273
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Christian Konig [Mon, 18 Mar 2013 11:33:50 +0000 (11:33 +0000)]
R600/SI: enable all S_LOAD and S_BUFFER_LOAD opcodes
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177272
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Christian Konig [Mon, 18 Mar 2013 11:33:45 +0000 (11:33 +0000)]
R600/SI: fix inserting waits for all defines
Unfortunately the previous fix for inserting waits for unordered
defines wasn't sufficient, cause it's possible that even ordered
defines are only partially used (or not used at all).
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177271
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Kostya Serebryany [Mon, 18 Mar 2013 09:38:39 +0000 (09:38 +0000)]
[asan] when creating string constants, set unnamed_attr and align 1 so that equal strings are merged by the linker. Observed up to 1% binary size reduction. Thanks to Anton Korobeynikov for the suggestion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177264
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Chandler Carruth [Mon, 18 Mar 2013 08:36:46 +0000 (08:36 +0000)]
Mark internal classes as POD-like to get better behavior out of
SmallVector and DenseMap.
This speeds up SROA by 25% on PR15412.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177259
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Anton Korobeynikov [Mon, 18 Mar 2013 08:12:28 +0000 (08:12 +0000)]
TLS support for MinGW targets.
MinGW is almost completely compatible to MSVC, with the exception of the _tls_array global not being available.
Patch by David Nadlinger!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177257
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Anton Korobeynikov [Mon, 18 Mar 2013 08:10:10 +0000 (08:10 +0000)]
Windows TLS: Section name prefix to ensure correct order
The linker sorts the .tls$<xyz> sections by name, and we need
to make sure any extra sections we produce (e.g. for weak globals)
always end up between .tls$AAA and .tls$ZZZ, even if the name
starts with e.g. an underscore.
Patch by David Nadlinger!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177256
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Kostya Serebryany [Mon, 18 Mar 2013 08:05:29 +0000 (08:05 +0000)]
[asan] while generating the description of a global variable, emit the module name in a separate field, thus not duplicating this information if every description. This decreases the binary size (observed up to 3%). https://code.google.com/p/address-sanitizer/issues/detail?id=168 . This changes the asan API version. llvm-part
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177254
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Kostya Serebryany [Mon, 18 Mar 2013 07:33:49 +0000 (07:33 +0000)]
[asan] don't instrument functions with available_externally linkage. This saves a bit of compile time and reduces the number of redundant global strings generated by asan (https://code.google.com/p/address-sanitizer/issues/detail?id=167)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177250
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Jakob Stoklund Olesen [Mon, 18 Mar 2013 04:08:07 +0000 (04:08 +0000)]
Extract a method.
This computes the type of an instruction operand or result based on the
records in the instruction's ins and outs lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177244
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Craig Topper [Mon, 18 Mar 2013 03:34:55 +0000 (03:34 +0000)]
Post process ADC/SBB and use a shorter encoding if they use a sign extended immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177243
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Craig Topper [Mon, 18 Mar 2013 02:53:34 +0000 (02:53 +0000)]
Refactor some duplicated code into helper functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177242
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David Blaikie [Sun, 17 Mar 2013 21:32:54 +0000 (21:32 +0000)]
Fix the build broken in r177239
Seems some accidental C++11 crept in there. Reported by the C++98 buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177241
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Michael Gottesman [Sun, 17 Mar 2013 21:31:12 +0000 (21:31 +0000)]
Reduced dont-infinite-loop-during-block-escape-analysis.ll with bugpoint and moved it to retain-block-escape-analysis.ll.
*NOTE* I verified that the original bug behind
dont-infinite-loop-during-block-escape-analysis.ll occurs when using opt on
retain-block-escape-analysis.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177240
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David Blaikie [Sun, 17 Mar 2013 21:13:55 +0000 (21:13 +0000)]
Split out filename & directory from DIFile to start generalizing over DIScopes
This is the first step to making all DIScopes have a common metadata prefix (so
that things (using directives, for example) that can appear in any scope can be
added to that common prefix). DIFile is itself a DIScope so the common prefix
of all DIScopes cannot be a DIFile - instead it's the raw filename/directory
name pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177239
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David Blaikie [Sun, 17 Mar 2013 21:08:22 +0000 (21:08 +0000)]
Generalize debug info test to be resilient to changes in metadata node numbering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177238
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David Blaikie [Sun, 17 Mar 2013 20:28:12 +0000 (20:28 +0000)]
Improve DIFile debug info annotation by letting it fallback to DIScope
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177236
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Jakob Stoklund Olesen [Sun, 17 Mar 2013 17:26:09 +0000 (17:26 +0000)]
Use ArrayRef<MVT::SimpleValueType> when possible.
Not passing vector references around makes it possible to use
SmallVector in most places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177235
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Sylvestre Ledru [Sun, 17 Mar 2013 12:40:42 +0000 (12:40 +0000)]
To avoid symbol clash, undefine PPC here. PPC may be predefined on some hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177234
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Rafael Espindola [Sun, 17 Mar 2013 12:01:05 +0000 (12:01 +0000)]
Build LLVMgold.so on FreeBSD using cmake.
Patch by Stephen Checkoway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177233
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Michael Gottesman [Sun, 17 Mar 2013 08:42:58 +0000 (08:42 +0000)]
The promised test case for r175939.
This test makes sure that the ObjCARC escape analysis looks at the uses of
instructions which copy the block pointer value by checking all four cases where
that can occur.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177232
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Hal Finkel [Sun, 17 Mar 2013 04:43:44 +0000 (04:43 +0000)]
Improve PPC VR (Altivec) register spilling
This change cleans up two issues with Altivec register spilling:
1. The spilling code was inefficient (using two instructions, and add and a
load, when just one would do)
2. The code assumed that r0 would always be available (true for now, but this
will change)
The new code handles VR spilling just like GPR spills but forced into r+r mode.
As a result, when any VR spills are present, we must now always allocate the
register-scavenger spill slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177231
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Hal Finkel [Sat, 16 Mar 2013 23:02:31 +0000 (23:02 +0000)]
Remove FIXMEs in PPC test cases related to unaligned loads/stores
As pointed out by Bill in response to r177160, these two FIXMEs
can also be removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177229
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Hal Finkel [Sat, 16 Mar 2013 22:50:51 +0000 (22:50 +0000)]
Remove PPC avoidWriteAfterWrite callback
As a follow-up to r158719, remove PPCRegisterInfo::avoidWriteAfterWrite.
Jakob pointed out in response to r158719 that this callback is currently unused
and so this has no effect (and the speedups that I thought that I had observed
as a result of implementing this function must have been noise).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177228
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Andrew Trick [Sat, 16 Mar 2013 18:58:57 +0000 (18:58 +0000)]
Change the default latency for implicit defs.
Implicit defs are not currently positional and not modeled by the
per-operand machine model. Unfortunately, we treat defs that are part
of the architectural instruction description, like flags, the same as
other implicit defs. Really, they should have a fixed MachineInstr
layout and probably shouldn't be "implicit" at all.
For now, we'll change the default latency to be the max operand
latency. That will give flag setting operands full latency for x86
folded loads. Other kinds of "fake" implicit defs don't occur prior to
regalloc anyway, and we would like them to go away postRegAlloc as
well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177227
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Andrew Trick [Sat, 16 Mar 2013 18:58:55 +0000 (18:58 +0000)]
Machine model. Allow mixed itinerary classes and SchedRW lists.
We always supported a mixture of the old itinerary model and new
per-operand model, but it required a level of indirection to map
itinerary classes to SchedRW lists. This was done for ARM A9.
Now we want to define x86 SchedRW lists, with the goal of removing its
itinerary classes, but still support the itineraries in the mean
time. When I original developed the model, Atom did not have
itineraries, so there was no reason to expect this requirement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177226
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Sean Silva [Sat, 16 Mar 2013 16:58:20 +0000 (16:58 +0000)]
[docs] Discuss a potential bug to be aware of.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177224
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Aaron Ballman [Sat, 16 Mar 2013 15:00:51 +0000 (15:00 +0000)]
Test case for graceful handling of long file names on Windows. Patch thanks to Paul Robinson!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177223
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Craig Topper [Sat, 16 Mar 2013 03:44:31 +0000 (03:44 +0000)]
Add X86 code emitter support AVX encoded MRMDestReg instructions.
Previously we weren't skipping the VVVV encoded register. Based on patch by Michael Liao.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177221
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Jakob Stoklund Olesen [Sat, 16 Mar 2013 00:02:17 +0000 (00:02 +0000)]
Define more SchedWrites for annotating X86 instructions.
Since almost all X86 instructions can fold loads, use a multiclass to
define register/memory pairs of SchedWrites.
An X86FoldableSchedWrite represents the register version of an
instruction. It holds a reference to the SchedWrite to use when the
instruction folds a load.
This will be used inside multiclasses that define rr and rm instruction
versions together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177210
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Jakob Stoklund Olesen [Fri, 15 Mar 2013 22:51:13 +0000 (22:51 +0000)]
Add SchedRW as an Instruction field.
Don't require instructions to inherit Sched<...>. Sometimes it is more
convenient to say:
let SchedRW = ... in {
...
}
Which is now possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177199
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Daniel Dunbar [Fri, 15 Mar 2013 20:16:59 +0000 (20:16 +0000)]
[ADT] Fix StringSet::insert() to not allocate on every lookup.
- The previous implementation always constructed the StringMap entry, even if
the key was present in the set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177178
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Michael J. Spencer [Fri, 15 Mar 2013 19:25:47 +0000 (19:25 +0000)]
[Support][Path][Windows] Fix dangling else. Don't call CloseHandle when CloseFD is false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177175
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Arnold Schwaighofer [Fri, 15 Mar 2013 18:31:01 +0000 (18:31 +0000)]
ARM cost model: Fix costs for some vector selects
I was too pessimistic in r177105. Vector selects that fit into a legal register
type lower just fine. I was mislead by the code fragment that I was using. The
stores/loads that I saw in those cases came from lowering the conditional off
an address.
Changing the code fragment to:
%T0_3 = type <8 x i18>
%T1_3 = type <8 x i1>
define void @func_blend3(%T0_3* %loadaddr, %T0_3* %loadaddr2,
%T1_3* %blend, %T0_3* %storeaddr) {
%v0 = load %T0_3* %loadaddr
%v1 = load %T0_3* %loadaddr2
==> FROM:
;%c = load %T1_3* %blend
==> TO:
%c = icmp slt %T0_3 %v0, %v1
==> USE:
%r = select %T1_3 %c, %T0_3 %v0, %T0_3 %v1
store %T0_3 %r, %T0_3* %storeaddr
ret void
}
revealed this mistake.
radar://
13403975
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177170
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Silviu Baranga [Fri, 15 Mar 2013 18:28:25 +0000 (18:28 +0000)]
Adding an A15 specific optimization pass for interactions between S/D/Q registers. The pass handles all the required transformations pre-regalloc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177169
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Benjamin Kramer [Fri, 15 Mar 2013 17:27:39 +0000 (17:27 +0000)]
ARM: Fix an old refacto.
Fixes PR15520.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177167
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Hal Finkel [Fri, 15 Mar 2013 15:27:13 +0000 (15:27 +0000)]
Enable unaligned memory access on PPC for scalar types
Unaligned access is supported on PPC for non-vector types, and is generally
more efficient than manually expanding the loads and stores.
A few of the existing test cases were using expanded unaligned loads and stores
to test other features (like load/store with update), and for these test cases,
unaligned access remains disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177160
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Arnold Schwaighofer [Fri, 15 Mar 2013 15:10:47 +0000 (15:10 +0000)]
ARM cost model: Fix cost of fptrunc and fpext instructions
A vector fptrunc and fpext simply gets split into scalar instructions.
radar://
13192358
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177159
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Hal Finkel [Fri, 15 Mar 2013 13:21:21 +0000 (13:21 +0000)]
Protect PPC Altivec patterns with a predicate
In preparation for the addition of other SIMD ISA extensions (such as QPX) we
need to make sure that all Altivec patterns are properly predicated on having
Altivec support.
No functionality change intended (one test case needed to be updated b/c it
assumed that Altivec intrinsics would be supported without enabling Altivec
support).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177152
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Alexey Samsonov [Fri, 15 Mar 2013 07:27:49 +0000 (07:27 +0000)]
Fixup for r176933: more careful setup of path to llvm-symbolizer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177144
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Craig Topper [Fri, 15 Mar 2013 06:01:42 +0000 (06:01 +0000)]
Use NumBaseBits in a few more places in SmallBitVector instead of recalculating it. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177142
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Rafael Espindola [Fri, 15 Mar 2013 05:51:57 +0000 (05:51 +0000)]
Fix the FDE encoding to be relative on ELF.
This is a very late complement to r130637 which fixed this on x86_64. Fixes
pr15448.
Since it looks like that every elf architecture uses this encoding when using
cfi, make it the default for elf. Just exclude mips64el. It has a lovely
.ll -> .o test (ef_frame.ll) that tests that nothing changes in the binary
content of the .eh_frame produced by llc. Oblige it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177141
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Hal Finkel [Fri, 15 Mar 2013 05:06:04 +0000 (05:06 +0000)]
Allocate the RS spill slot for any PPC function with spills and a large stack frame
For spills into a large stack frame, the FI-elimination code uses the register
scavenger to obtain a free GPR for use with an r+r-addressed load or store.
When there are no available GPRs, the scavenger gets one by using its spill
slot. Previously, we were not always allocating that spill slot and the RS
would assert when the spill slot was needed.
I don't currently have a small test that triggered the assert, but I've
created a small regression test that verifies that the spill slot is now
added when the stack frame is sufficiently large.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177140
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Eric Christopher [Fri, 15 Mar 2013 00:43:00 +0000 (00:43 +0000)]
Turn anonymous type in anonymous union warning back on after cleaning up
issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177136
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Eric Christopher [Fri, 15 Mar 2013 00:42:55 +0000 (00:42 +0000)]
Silence anonymous type in anonymous union warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177135
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Nadav Rotem [Fri, 15 Mar 2013 00:10:23 +0000 (00:10 +0000)]
Add a triple to the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177131
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Nadav Rotem [Thu, 14 Mar 2013 23:49:44 +0000 (23:49 +0000)]
Unaligned loads should use the VMOVUPS opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177130
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David Blaikie [Thu, 14 Mar 2013 23:11:07 +0000 (23:11 +0000)]
Remove some unused variables to clean the Clang -Werror build
(these were added in r177089)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177129
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Akira Hatanaka [Thu, 14 Mar 2013 23:09:19 +0000 (23:09 +0000)]
[mips] Set isAllocatable bit of unallocatable register classes to 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177128
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Andrew Trick [Thu, 14 Mar 2013 22:47:01 +0000 (22:47 +0000)]
Fix r177112: Add ProcResGroup.
This is the other half of r177122 that I meant to commit at the same time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177123
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Jakob Stoklund Olesen [Thu, 14 Mar 2013 22:42:17 +0000 (22:42 +0000)]
Prepare for adding InstrSchedModel annotations to X86 instructions.
The new InstrSchedModel is easier to use than the instruction
itineraries. It will be used to model instruction latency and throughput
in modern Intel microarchitectures like Sandy Bridge.
InstrSchedModel should be able to coexist with instruction itinerary
classes, but for cleanliness we should switch the Atom processor model
to the new InstrSchedModel as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177122
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