OSDN Git Service
Bjorn Pettersson [Wed, 19 Jun 2019 14:27:51 +0000 (14:27 +0000)]
[ConstantFolding] Refactor ConstantFoldScalarCall. NFC
This patch splits ConstantFoldScalarCall into several
functions.
Benefits:
- Reduces indentation levels and avoids long if-statements.
- Makes it easier to add support for > 3 operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363810
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Simon Pilgrim [Wed, 19 Jun 2019 14:25:27 +0000 (14:25 +0000)]
[X86] Merge extract_subvector(*_EXTEND) and extract_subvector(*_EXTEND_VECTOR_INREG) handling. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363808
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Ulrich Weigand [Wed, 19 Jun 2019 14:20:00 +0000 (14:20 +0000)]
[SystemZ] Support vector load/store alignment hints
Vector load/store instructions support an optional alignment field
that the compiler can use to provide known alignment info to the
hardware. If the field is used (and the information is correct),
the hardware may be able (on some models) to perform faster memory
accesses than otherwise.
This patch adds support for alignment hints in the assembler and
disassembler, and fills in known alignment during codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363806
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Simon Pilgrim [Wed, 19 Jun 2019 13:58:02 +0000 (13:58 +0000)]
[TargetLowering] SimplifyDemandedBits SIGN_EXTEND_VECTOR_INREG -> ANY/ZERO_EXTEND_VECTOR_INREG
Simplify SIGN_EXTEND_VECTOR_INREG if the extended bits are not required/known zero.
Matches what we already do for SIGN_EXTEND.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363802
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Fangrui Song [Wed, 19 Jun 2019 13:51:29 +0000 (13:51 +0000)]
[llvm-dwarfdump] --gdb-index: fix uninitialized TuListOffset
The test only checks the existence of the `Types CU list` line.
Unfortunately I can't make a better test because
{gcc,clang} -fuse-ld={lld,gold} --gdb-index do not give me a non-empty types CU list.
Reviewed By: ikudrin
Differential Revision: https://reviews.llvm.org/D63537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363800
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Simon Pilgrim [Wed, 19 Jun 2019 13:00:54 +0000 (13:00 +0000)]
Revert rL363678 : AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsics
There may or may not be additional work to handle this correctly on
SI/CI.
........
Breaks EXPENSIVE_CHECKS buildbots - http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/78/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363797
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David Bolvansky [Wed, 19 Jun 2019 12:59:37 +0000 (12:59 +0000)]
[NFC] Added tests for D63534
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363796
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David Bolvansky [Wed, 19 Jun 2019 12:55:39 +0000 (12:55 +0000)]
[NFC] Added tests for cttz(abs(x)) -> cttz(x) fold
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363795
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Simon Pilgrim [Wed, 19 Jun 2019 12:41:37 +0000 (12:41 +0000)]
[DAGCombiner] Support (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2)) non-uniform folds.
Use matchBinaryPredicate instead of isConstOrConstSplat to let us handle non-uniform shift cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363793
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Simon Pilgrim [Wed, 19 Jun 2019 12:25:29 +0000 (12:25 +0000)]
[DAGCombiner] Support (shl (ext (shl x, c1)), c2) -> 0 non-uniform folds.
Use matchBinaryPredicate instead of isConstOrConstSplat to let us handle non-uniform shift cases.
This requires us to tweak matchBinaryPredicate to allow it to (optionally) handle constants with different type widths.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363792
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Simon Pilgrim [Wed, 19 Jun 2019 11:36:01 +0000 (11:36 +0000)]
[X86] Add non-uniform (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2)) test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363791
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Simon Pilgrim [Wed, 19 Jun 2019 11:31:26 +0000 (11:31 +0000)]
[DAGCombiner] visitSHL - pull out repeated shift amount VT. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363789
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Simon Pilgrim [Wed, 19 Jun 2019 11:17:48 +0000 (11:17 +0000)]
[DAGCombine] Fix (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2)) comment. NFCI.
We pre-extend, not post.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363787
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Orlando Cazalet-Hyams [Wed, 19 Jun 2019 10:50:47 +0000 (10:50 +0000)]
[DebugInfo@O2][LoopVectorize] pr39024: Vectorized code linenos step through loop even after completion
Summary:
Bug: https://bugs.llvm.org/show_bug.cgi?id=39024
The bug reports that a vectorized loop is stepped through 4 times and each step through the loop seemed to show a different path. I found two problems here:
A) An incorrect line number on a preheader block (for.body.preheader) instruction causes a step into the loop before it begins.
B) Instructions in the middle block have different line numbers which give the impression of another iteration.
In this patch I give all of the middle block instructions the line number of the scalar loop latch terminator branch. This seems to provide the smoothest debugging experience because the vectorized loops will always end on this line before dropping into the scalar loop. To solve problem A I have altered llvm::SplitBlockPredecessors to accommodate loop header blocks.
I have set up a separate review D61933 for a fix which is required for this patch.
Reviewers: samsonov, vsk, aprantl, probinson, anemet, hfinkel, jmorse
Reviewed By: hfinkel, jmorse
Subscribers: jmorse, javed.absar, eraman, kcc, bjope, jmellorcrummey, hfinkel, gbedwell, hiraditya, zzheng, llvm-commits
Tags: #llvm, #debug-info
Differential Revision: https://reviews.llvm.org/D60831
llvm-svn: 363046
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363786
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Jay Foad [Wed, 19 Jun 2019 10:28:48 +0000 (10:28 +0000)]
[ConstantFolding] Fix assertion failure on non-power-of-two vector load.
Summary:
The test case does an (out of bounds) load from a global constant with
type <3 x float>. InstSimplify tried to turn this into an integer load
of the whole alloc size of the vector, which is 128 bits due to
alignment padding, and then bitcast this to <3 x vector> which failed
an assertion due to the type size mismatch.
The fix is to do an integer load of the normal size of the vector, with
no alignment padding.
Reviewers: tpr, arsenm, majnemer, dstuttard
Reviewed By: arsenm
Subscribers: hfinkel, wdng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63375
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363784
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Lewis Revill [Wed, 19 Jun 2019 10:27:24 +0000 (10:27 +0000)]
[RISCV] Allow parsing immediates that use tilde & exclaim
This patch allows immediates (and CSR alias immediates) which start with
a tilde token or an exclaim (!) token to be parsed as intended.
Differential Revision: https://reviews.llvm.org/D57320
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363783
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Lewis Revill [Wed, 19 Jun 2019 10:11:13 +0000 (10:11 +0000)]
[RISCV] Fix failure to parse parenthesized immediates
Since the parser attempts to parse an operand as a register with
parentheses before parsing it as an immediate, immediates in
parentheses should not be parsed by parseRegister. However in the case
where the immediate does not start with an identifier, the LParen is not
unlexed and so the RParen causes an unexpected token error.
This patch adds the missing UnLex, and modifies the existing UnLex to
not use a buffered token, as it should always be unlexing an LParen.
Differential Revision: https://reviews.llvm.org/D57319
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363782
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Clement Courbet [Wed, 19 Jun 2019 10:00:36 +0000 (10:00 +0000)]
Fix r363773: Update Barcelona MCA tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363781
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Hans Wennborg [Wed, 19 Jun 2019 09:46:37 +0000 (09:46 +0000)]
Make TargetParserTest.ARMExtensionFeatures not run out of memory on 32-bit (PR42316)
The test still probably shouldn't run this loop 17 million times, but at
least now it won't run out of memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363780
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George Rimar [Wed, 19 Jun 2019 08:57:38 +0000 (08:57 +0000)]
[yaml2obj/obj2yaml] - Make RawContentSection::Info Optional<>
This allows to customize this field for "implicit" sections properly.
Differential revision: https://reviews.llvm.org/D63487
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363777
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Roman Lebedev [Wed, 19 Jun 2019 08:53:34 +0000 (08:53 +0000)]
[NFC][X86][MCA] Barcelona: add load/store/load-store-throughput tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363775
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Roman Lebedev [Wed, 19 Jun 2019 08:53:28 +0000 (08:53 +0000)]
[NFC][X86][MCA] BdVer2: add load-store-throughput test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363774
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Clement Courbet [Wed, 19 Jun 2019 08:44:31 +0000 (08:44 +0000)]
[X86] Add missing properties on llvm.x86.sse.{st,ld}mxcsr
Summary:
llvm.x86.sse.stmxcsr only writes to memory.
llvm.x86.sse.ldmxcsr only reads from memory, and might generate an FPE.
Reviewers: craig.topper, RKSimon
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363773
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Lewis Revill [Wed, 19 Jun 2019 08:40:59 +0000 (08:40 +0000)]
[RISCV] Add lowering of global TLS addresses
This patch adds lowering for global TLS addresses for the TLS models of
InitialExec, GlobalDynamic, LocalExec and LocalDynamic.
LocalExec support required using a 4-operand add instruction, which uses
the fourth operand to express a relocation on the symbol. The necessary
fixup is emitted when the instruction is emitted.
Differential Revision: https://reviews.llvm.org/D55305
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363771
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Hans Wennborg [Wed, 19 Jun 2019 07:39:53 +0000 (07:39 +0000)]
vs integration: bump version nbr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363769
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Hans Wennborg [Wed, 19 Jun 2019 07:37:53 +0000 (07:37 +0000)]
Revert r359557 "vs integration: vs2019 support"
Turns out this worked on my machine because I still had VS2017 installed, but
it didn't actually work in general.
Since the extension is unmaintained and MS is doing their own LLVM toolset
integration for VS2019, let's just revert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363768
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Yuanfang Chen [Wed, 19 Jun 2019 05:40:24 +0000 (05:40 +0000)]
Test commit access
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363763
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Alex Bradbury [Wed, 19 Jun 2019 03:18:48 +0000 (03:18 +0000)]
[RISCV] Fix test after r363757
r363757 renamed ExpandISelPseudo to FinalizeISel, so the RUN line in
select-optimize-multiple.mir needed updating to refer to finalize-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363762
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Chen Zheng [Wed, 19 Jun 2019 01:26:31 +0000 (01:26 +0000)]
[NFC] move some hardware loop checking code to a common place for other using.
Differential Revision: https://reviews.llvm.org/D63478
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363758
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Matt Arsenault [Wed, 19 Jun 2019 00:25:39 +0000 (00:25 +0000)]
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
This allows targets to make more decisions about reserved registers
after isel. For example, now it should be certain there are calls or
stack objects in the frame or not, which could have been introduced by
legalization.
Patch by Matthias Braun
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363757
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Thomas Lively [Wed, 19 Jun 2019 00:02:13 +0000 (00:02 +0000)]
[WebAssembly] Optimize ISel for SIMD Boolean reductions
Summary:
Converting the result *.{all,any}_true to a bool at the source level
generates LLVM IR that compares the result to 0. This check is
redundant since these instructions already return either 0 or 1 and
therefore conform to the BooleanContents setting for WebAssembly. This
CL adds patterns to detect and remove such redundant operations on the
result of Boolean reductions.
Reviewers: dschuff, aheejin
Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63529
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363756
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Daniel Sanders [Tue, 18 Jun 2019 23:34:46 +0000 (23:34 +0000)]
Re-commit r363744: [tblgen][disasm] Allow multiple encodings to disassemble to the same instruction
It seems macOS lets you have ArrayRef<const X> even though this is apparently
forbidden by the language standard (Thanks MSVC++ for the clear error message).
Removed the problematic const's to fix this.
(It also seems I'm not receiving buildbot emails anymore and I'm trying to find
out why. In the mean time I'll be polling lab.llvm.org to hopefully see if/when
failures occur)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363753
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Erik Pilkington [Tue, 18 Jun 2019 23:34:09 +0000 (23:34 +0000)]
[demangle] Special case clang's creative mangling of __uuidof expressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363752
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Evandro Menezes [Tue, 18 Jun 2019 23:31:10 +0000 (23:31 +0000)]
[test] Change comment wording (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363751
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Jordan Rupprecht [Tue, 18 Jun 2019 22:21:31 +0000 (22:21 +0000)]
Revert [tblgen][disasm] Allow multiple encodings to disassemble to the same instruction
This reverts r363744 (git commit
9b2252123d1e79d2b3594097a9d9cc60072b83d9)
This breaks many buildbots, e.g. http://lab.llvm.org:8011/builders/clang-atom-d525-fedora-rel/builds/203/steps/build%20stage%201/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363747
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Michael Trent [Tue, 18 Jun 2019 22:20:10 +0000 (22:20 +0000)]
Print dylib load kind (weak, reexport, etc) in llvm-objdump -m -dylibs-used
Summary:
Historically llvm-objdump prints the path to a dylib as well as the
dylib's compatibility version and current version number. This change
extends this information by adding the kind of dylib load: weak,
reexport, etc.
rdar://
51383512
Reviewers: pete, lhames
Reviewed By: pete
Subscribers: rupprecht, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363746
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Amara Emerson [Tue, 18 Jun 2019 22:08:40 +0000 (22:08 +0000)]
[GlobalISel][Localizer] Remove redundant set lookup.
After changing the algorithm to only process the entry block we never revisit
a processed instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363745
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Daniel Sanders [Tue, 18 Jun 2019 21:56:04 +0000 (21:56 +0000)]
[tblgen][disasm] Allow multiple encodings to disassemble to the same instruction
Summary:
Add an AdditionalEncoding class which can be used to define additional encodings
for a given instruction. This causes the disassembler to add an additional
encoding to its matching tables that map to the specified instruction.
Usage:
def ADD1 : Instruction {
bits<8> Reg;
bits<32> Inst;
let Size = 4;
let Inst{0-7} = Reg;
let Inst{8-14} = 0;
let Inst{15} = 1; // Continuation bit
let Inst{16-31} = 0;
...
}
def : AdditionalEncoding<ADD1> {
bits<8> Reg;
bits<16> Inst; // You can also have bits<32> and it will still be a 16-bit encoding
let Size = 2;
let Inst{0-3} = 0;
let Inst{4-7} = Reg;
let Inst{8-15} = 0;
...
}
with those definitions, llvm-mc will successfully disassemble both of these:
0x01 0x00
0x10 0x80 0x00 0x00
to:
ADD1 r1
Depends on D52366
Reviewers: bogner, charukcs
Reviewed By: bogner
Subscribers: nlguillemot, nhaehnle, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D52369
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363744
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Michael Liao [Tue, 18 Jun 2019 21:41:13 +0000 (21:41 +0000)]
Recommit [SROA] Enhance SROA to handle `addrspacecast`ed allocas
[SROA] Enhance SROA to handle `addrspacecast`ed allocas
- Fix typo in original change
- Add additional handling to ensure all return pointers are properly
casted.
Summary:
- After `addrspacecast` is allowed to be eliminated in SROA, the
adjusting of storage pointer (from `alloca) needs to handle the
potential different address spaces between the storage pointer (from
alloca) and the pointer being used.
Reviewers: arsenm
Subscribers: wdng, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63501
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363743
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Matt Arsenault [Tue, 18 Jun 2019 21:32:51 +0000 (21:32 +0000)]
InstCombine: Pre-commit test for reassociating nuw
D39417
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363741
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Huihui Zhang [Tue, 18 Jun 2019 20:55:09 +0000 (20:55 +0000)]
[ARM] Comply with rules on ARMv8-A thumb mode partial deprecation of IT.
Summary:
When identifing instructions that can be folded into a MOVCC instruction,
checking for a predicate operand is not enough, also need to check for
thumb2 function, with restrict-IT, is the machine instruction eligible for
ARMv8 IT or not.
Notes in ARMv8-A Architecture Reference Manual, section "Partial deprecation of IT"
https://usermanual.wiki/Pdf/ARM20Architecture20Reference20ManualARMv8.
1667877052.pdf
"ARMv8-A deprecates some uses of the T32 IT instruction. All uses of IT that apply to
instructions other than a single subsequent 16-bit instruction from a restricted set
are deprecated, as are explicit references to the PC within that single 16-bit
instruction. This permits the non-deprecated forms of IT and subsequent instructions
to be treated as a single 32-bit conditional instruction."
Reviewers: efriedma, lebedev.ri, t.p.northover, jmolloy, aemerson, compnerd, stoklund, ostannard
Reviewed By: ostannard
Subscribers: ostannard, javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363739
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Sam Elliott [Tue, 18 Jun 2019 20:38:08 +0000 (20:38 +0000)]
[RISCV] Prevent re-ordering some adds after shifts
Summary:
DAGCombine will normally turn a `(shl (add x, c1), c2)` into `(add (shl x, c2), c1 << c2)`, where `c1` and `c2` are constants. This can be prevented by a callback in TargetLowering.
On RISC-V, materialising the constant `c1 << c2` can be more expensive than materialising `c1`, because materialising the former may take more instructions, and may use a register, where materialising the latter would not.
This patch implements the hook in RISCVTargetLowering to prevent this transform, in the cases where:
- `c1` fits into the immediate field in an `addi` instruction.
- `c1` takes fewer instructions to materialise than `c1 << c2`.
In future, DAGCombine could do the check to see whether `c1` fits into an add immediate, which might simplify more targets hooks than just RISC-V.
Reviewers: asb, luismarques, efriedma
Reviewed By: asb
Subscribers: xbolva00, lebedev.ri, craig.topper, lewis-revill, Jim, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363736
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Jinsong Ji [Tue, 18 Jun 2019 20:24:49 +0000 (20:24 +0000)]
[MachinePipeliner][NFC] Do resource tracking log only when requested.
In most cases we don't need to do resource tracking debug,
so leave them off by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363733
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Sanjay Patel [Tue, 18 Jun 2019 20:13:35 +0000 (20:13 +0000)]
[x86] add another test for load splitting with extracted stores (PR42305); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363732
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Adrian Prantl [Tue, 18 Jun 2019 20:09:09 +0000 (20:09 +0000)]
Add debug location verification for !llvm.loop attachments.
This patch teaches the Verifier how to detect broken !llvm.loop
attachments as discussed in https://reviews.llvm.org/D60831. This
allows LLVM to warn and strip out the broken debug info before
attempting an LTO compilation with input generated by LLVM predating
https://reviews.llvm.org/rL361149.
rdar://problem/
51631158
Differential Revision: https://reviews.llvm.org/D63499
[Re-applies r363725 without changes after fixing a broken testcase.]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363731
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Adrian Prantl [Tue, 18 Jun 2019 20:07:53 +0000 (20:07 +0000)]
Fix broken debug info in in an !llvm.loop attachment in this testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363730
91177308-0d34-0410-b5e6-
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Stanislav Mekhanoshin [Tue, 18 Jun 2019 20:00:24 +0000 (20:00 +0000)]
[AMDGPU] gfx10 wave32 patterns
Differential Revision: https://reviews.llvm.org/D63511
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363729
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Adrian Prantl [Tue, 18 Jun 2019 19:54:17 +0000 (19:54 +0000)]
Revert Add debug location verification for !llvm.loop attachments.
This reverts r363725 (git commit
8ff822d61dacf5a9466755eedafd3eeb54abc00d)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363728
91177308-0d34-0410-b5e6-
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Gor Nishanov [Tue, 18 Jun 2019 19:49:48 +0000 (19:49 +0000)]
[coroutines] Add missing pass dependency.
Summary:
CoroSplit depends on CallGraphWrapperPass, but it was not explicitly adding it as a pass dependency.
This missing dependency can trigger errors / assertions / crashes in PMTopLevelManager::schedulePass() under certain configurations.
Author: ben-clayton
Reviewers: GorNishanov
Reviewed By: GorNishanov
Subscribers: capn, EricWF, modocache, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363727
91177308-0d34-0410-b5e6-
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Adrian Prantl [Tue, 18 Jun 2019 19:42:29 +0000 (19:42 +0000)]
Add debug location verification for !llvm.loop attachments.
This patch teaches the Verifier how to detect broken !llvm.loop
attachments as discussed in https://reviews.llvm.org/D60831. This
allows LLVM to warn and strip out the broken debug info before
attempting an LTO compilation with input generated by LLVM predating
https://reviews.llvm.org/rL361149.
rdar://problem/
51631158
Differential Revision: https://reviews.llvm.org/D63499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363725
91177308-0d34-0410-b5e6-
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Reid Kleckner [Tue, 18 Jun 2019 19:41:25 +0000 (19:41 +0000)]
[PDB] Ignore .debug$S subsections with high bit set
Some versions of the Visual C++ 2015 runtime have line tables with the
subsection kind of 0x800000F2. In cvinfo.h, 0x80000000 is documented to
be DEBUG_S_IGNORE. This appears to implement the intended behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363724
91177308-0d34-0410-b5e6-
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Stanislav Mekhanoshin [Tue, 18 Jun 2019 19:10:59 +0000 (19:10 +0000)]
[AMDGPU] gfx1010 disassembler changes for wave32
Differential Revision: https://reviews.llvm.org/D63506
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363721
91177308-0d34-0410-b5e6-
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Craig Topper [Tue, 18 Jun 2019 19:04:03 +0000 (19:04 +0000)]
[X86] Remove unnecessary line that makes v4f32 FP_ROUND Legal. NFC
FP_ROUND defaults to Legal for all MVT types and nothing changes
the v4f32 entry way from this default. If we needed this line
we'd also need one for v8f32 with AVX512 which we don't have.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363719
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Jordan Rupprecht [Tue, 18 Jun 2019 18:40:04 +0000 (18:40 +0000)]
Revert [SROA] Enhance SROA to handle `addrspacecast`ed allocas
This reverts r363711 (git commit
76a149ef8187310a60fd20481fdb2a10c8ba968e)
This causes stage2 build failures, e.g.:
http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/132/steps/stage%202%20build/logs/stdio
http://lab.llvm.org:8011/builders/ppc64le-lld-multistage-test/builds/87/steps/build-stage2-unified-tree/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363718
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 18 Jun 2019 18:22:30 +0000 (18:22 +0000)]
[TargetLowering] SimplifyDemandedBits - Cleanup ANY_EXTEND handling
Match SIGN_EXTEND + ZERO_EXTEND handling - will be adding ANY_EXTEND_VECTOR_INREG support in a future patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363716
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 18 Jun 2019 18:08:30 +0000 (18:08 +0000)]
[TargetLowering] SimplifyDemandedBits - Merge ZERO_EXTEND+ZERO_EXTEND_VECTOR_INREG handling
Other than adding consistent demanded elts handling which was a trivial addition, the other differences in functionality will be added in later patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363713
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Michael Liao [Tue, 18 Jun 2019 17:58:49 +0000 (17:58 +0000)]
[SROA] Enhance SROA to handle `addrspacecast`ed allocas
Summary:
- After `addrspacecast` is allowed to be eliminated in SROA, the
adjusting of storage pointer (from `alloca) needs to handle the
potential different address spaces between the storage pointer (from
alloca) and the pointer being used.
Reviewers: arsenm
Subscribers: wdng, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63501
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363711
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Simon Pilgrim [Tue, 18 Jun 2019 17:57:53 +0000 (17:57 +0000)]
[TargetLowering] SimplifyDemandedBits - Merge SIGN_EXTEND+SIGN_EXTEND_VECTOR_INREG handling
Other than adding consistent demanded elts handling which was a trivial addition, the other differences in functionality will be added in later patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363710
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Sanjay Patel [Tue, 18 Jun 2019 17:16:17 +0000 (17:16 +0000)]
[x86] add test for load splitting with extracted store (PR42305); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363704
91177308-0d34-0410-b5e6-
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Simon Atanasyan [Tue, 18 Jun 2019 17:00:08 +0000 (17:00 +0000)]
[mips] Add more strict predicates to the RSQRT_S_MM and TAILCALL_MM
This patch is one of a series of patches. The goal is to make P5600
scheduler model complete and turn on the `CompleteModel` flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363703
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Simon Atanasyan [Tue, 18 Jun 2019 16:59:57 +0000 (16:59 +0000)]
[mips] Add PTR_64 and GPR_64 predicates to some MIPS 64-bit instructions
Add `IsGP64bit` and `IsPTR64bit` to the list of `UnsupportedFeatures`
of the P5600 scheduling definitions. Also mark some MIPS 64-bit
instructions by PTR_64 and GPR_64 predicates. This reduces number
of "No schedule information for" and "lacks information for" errors
in case of marking this scheduler model as complete.
This patch is one of a series of patches. The goal is to make P5600
scheduler model complete and turn on the `CompleteModel` flag.
Differential Revision: https://reviews.llvm.org/D63237
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363702
91177308-0d34-0410-b5e6-
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Simon Atanasyan [Tue, 18 Jun 2019 16:59:47 +0000 (16:59 +0000)]
[mips] Set the hasNoSchedulingInfo flag for the `MipsAsmPseudoInst`
Set the hasNoSchedulingInfo flag for the`MipsAsmPseudoInst`. These
pseudo-instructions are never used by codegen. This flag allows to
reduce number of "No schedule information for" and "lacks information
for" errors in case of marking a scheduler model as complete.
This patch is one of a series of patches. The goal is to make P5600
scheduler model complete and turn on the `CompleteModel` flag.
Differential Revision: https://reviews.llvm.org/D63236
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363701
91177308-0d34-0410-b5e6-
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Adrian McCarthy [Tue, 18 Jun 2019 16:36:57 +0000 (16:36 +0000)]
Fix some lit test ResourceWarnings on Windows
When running LLDB lit tests on Windows, the system selects a debug version
of Python, which was issuing lots of ResourceWarnings about files that
weren't closed. There are two kinds of them, and each test triggered one
of each.
This patch fixes one kind by ensuring TestRunner explicitly close the
temporary files created for routing stderr. This is important on Windows
but has no net effect on Posix systems.
The remaining ResourceWarnings are more elusive; the bug may lie in
the Python library subprocess.py, and it may be Windows-specific.
Differential Revision: https://reviews.llvm.org/D63102
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363700
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Simon Tatham [Tue, 18 Jun 2019 16:19:59 +0000 (16:19 +0000)]
[ARM] Add MVE vector shift instructions.
This includes saturating and non-saturating shifts, both with
immediate shift count and with the shift counts given by another
vector register; VSHLC (in which the bits shifted out of each active
vector lane are shifted in to the next active lane); and also VMOVL,
which is enough like an immediate shift that it didn't fit too badly
in this category.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62672
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363696
91177308-0d34-0410-b5e6-
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Simon Tatham [Tue, 18 Jun 2019 15:51:46 +0000 (15:51 +0000)]
[ARM] Add MVE integer vector min/max instructions.
Summary:
These form a small family of their own, to go with the floating-point
VMINNM/VMAXNM instructions added in a previous commit.
They introduce the first of many special cases in the mnemonic
recognition code, because VMIN with the E suffix used by the VPT
predication system needs to avoid being interpreted as the nonexistent
instruction 'VMI' with an ordinary 'NE' condition suffix.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62671
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363695
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 18 Jun 2019 15:49:35 +0000 (15:49 +0000)]
[TargetLowering] SimplifyDemandedVectorElts - support MUL and ANY_EXTEND_VECTOR_INREG
Also fold ANY_EXTEND_VECTOR_INREG -> BITCAST if we only need the bottom element.
Fixes temporary regression introduced in rL363693.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363694
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 18 Jun 2019 15:30:50 +0000 (15:30 +0000)]
[X86][AVX] extract_subvector(any_extend(x)) -> any_extend_vector_inreg(x)
Part of fixing the X86 regression noted in D63281 - I've split this into X86 and generic parts - the generic commit will be coming shortly and will fix the vector-reduce-mul-widen.ll regression introduced here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363693
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Simon Tatham [Tue, 18 Jun 2019 15:05:42 +0000 (15:05 +0000)]
[ARM] Rename MVE instructions in Tablegen for consistency.
Summary:
Their names began with a mishmash of `MVE_`, `t2` and no prefix at
all. Now they all start with `MVE_`, which seems like a reasonable
choice on the grounds that (a) NEON is the thing they're most at risk
of being confused with, and (b) MVE implies Thumb-2, so a prefix
indicating MVE is strictly more specific than one indicating Thumb-2.
Reviewers: ostannard, SjoerdMeijer, dmgreen
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63492
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363690
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Lewis Revill [Tue, 18 Jun 2019 14:29:45 +0000 (14:29 +0000)]
[RISCV] Lower calls through PLT
This patch adds support for generating calls through the procedure
linkage table where required for a given ExternalSymbol or GlobalAddress
callee.
Differential Revision: https://reviews.llvm.org/D55304
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363686
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Simon Pilgrim [Tue, 18 Jun 2019 14:24:28 +0000 (14:24 +0000)]
Fix -Wunused-but-set-variable warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363685
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Fangrui Song [Tue, 18 Jun 2019 14:01:03 +0000 (14:01 +0000)]
[llvm-readobj] Allow --hex-dump/--string-dump to dump multiple sections
1) `-x foo` currently dumps one `foo`. This change makes it dump all `foo`.
2) `-x foo -x foo` currently dumps `foo` twice. This change makes it dump `foo` once.
In addition, if foo has section index 9, `-x foo -x 9` dumps `foo` once.
3) Give a warning instead of an error if `foo` does not exist.
The new behaviors match GNU readelf.
Also, print a new line as a separator between two section dumps.
GNU readelf uses two lines, but one seems good enough.
Reviewed By: grimar, jhenderson
Differential Revision: https://reviews.llvm.org/D63475
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363683
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Matt Arsenault [Tue, 18 Jun 2019 13:19:57 +0000 (13:19 +0000)]
AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsics
There may or may not be additional work to handle this correctly on
SI/CI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363678
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Andrea Di Biagio [Tue, 18 Jun 2019 12:59:46 +0000 (12:59 +0000)]
[MCA] Slightly refactor the bottleneck analysis view. NFCI
This patch slightly refactors data structures internally used by the bottleneck
analysis to track data and resource dependencies.
This patch also updates methods used to print out information about dependency
edges when in debug mode.
This is the last of a sequence of commits done in preparation for an upcoming
patch that fixes PR37494. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363677
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Matt Arsenault [Tue, 18 Jun 2019 12:48:36 +0000 (12:48 +0000)]
AMDGPU: Change API for checking for exec modification
Invert the name and return value to better reflect the imprecise
nature.
Force passing in the DefMI, since it's known in the 2 users and could
possibly fail for an arbitrary vreg.
Allow specifying a specific user instruction. Scan through use
instructions, instead of use operands. Add scan thresholds instead of
searching infinitely.
Stop using a set to track seen uses. I didn't understand this usage,
or why it would not check the last use. I don't think the use list has
any particular order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363675
91177308-0d34-0410-b5e6-
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Fangrui Song [Tue, 18 Jun 2019 12:30:06 +0000 (12:30 +0000)]
MCContext: Delete unused functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363674
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Nico Weber [Tue, 18 Jun 2019 12:29:04 +0000 (12:29 +0000)]
gn build: Merge r363658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363673
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Nico Weber [Tue, 18 Jun 2019 12:26:31 +0000 (12:26 +0000)]
gn build: Merge r363649
This reverts commit "gn build: Merge r363626" because r363626
was reverted in r363649.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363672
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 18 Jun 2019 12:24:02 +0000 (12:24 +0000)]
[SelectionDAG] Legalize vaargs that require vector splitting
This adds vector splitting for vaarg instructions during type legalization
Committed on behalf of @luke (Luke Lau)
Differential Revision: https://reviews.llvm.org/D60762
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363671
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Matt Arsenault [Tue, 18 Jun 2019 12:23:46 +0000 (12:23 +0000)]
AMDGPU: Fold readlane from copy of SGPR or imm
These may be inserted to assert uniformity somewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363670
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Matt Arsenault [Tue, 18 Jun 2019 12:23:45 +0000 (12:23 +0000)]
AMDGPU: Remove unnecessary check for virtual register
The copy was found by searching the uses of a virtual register, so
it's already known to be virtual.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363669
91177308-0d34-0410-b5e6-
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Matt Arsenault [Tue, 18 Jun 2019 12:23:44 +0000 (12:23 +0000)]
AMDGPU: Fix iterator crash in AMDGPUPromoteAlloca
The lifetime intrinsic was erased, which was the next iterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363668
91177308-0d34-0410-b5e6-
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Matt Arsenault [Tue, 18 Jun 2019 12:23:42 +0000 (12:23 +0000)]
AMDGPU/GlobalISel: RegBankSelect for amdgcn.div.scale
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363667
91177308-0d34-0410-b5e6-
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Sjoerd Meijer [Tue, 18 Jun 2019 12:13:11 +0000 (12:13 +0000)]
[ARM] Some Thumb2ITBlock clean ups. NFC
Some more refactoring, like registering the IT Block pass, less cryptic
variable names, and some simplification of loops.
Differential Revision: https://reviews.llvm.org/D63419
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363666
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Jonas Paulsson [Tue, 18 Jun 2019 12:10:02 +0000 (12:10 +0000)]
[SystemZ] Fix AHIMuxK pseudo expansion.
Do not emit a copy if the source and destination registers are the same.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363665
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Valery Pykhtin [Tue, 18 Jun 2019 11:43:17 +0000 (11:43 +0000)]
[AMDGPU] Speed up live-in virtual register set computaion in GCNScheduleDAGMILive.
Differential revision: https://reviews.llvm.org/D62401
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363661
91177308-0d34-0410-b5e6-
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Graham Hunter [Tue, 18 Jun 2019 10:11:56 +0000 (10:11 +0000)]
[SVE][IR] Scalable Vector IR Type with pr42210 fix
Recommit of D32530 with a few small changes:
- Stopped recursively walking through aggregates in
the verifier, so that we don't impose too much
overhead on large modules under LTO (see PR42210).
- Changed tests to match; the errors are slightly
different since they only report the array or
struct that actually contains a scalable vector,
rather than all aggregates which contain one in
a nested member.
- Corrected an older comment
Reviewers: thakis, rengolin, sdesmalen
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D63321
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363658
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 18 Jun 2019 10:10:53 +0000 (10:10 +0000)]
[X86] Regenerate promote.ll. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363657
91177308-0d34-0410-b5e6-
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Diogo N. Sampaio [Tue, 18 Jun 2019 10:04:36 +0000 (10:04 +0000)]
[NFC] Improve triple match of scripts that update tests
Summary:
The prior behavior of the triple matcher would stop
in the first matched triple. It was not possible to
create specific matches for sub-sets of a triple
(e.g aarch64-apple-darwin would never be used after
aarch64 was matched).
This patch:
1) Allows that specialized triples take priority,
considering that the string lenght of the triple
indentifies how specialized a triple is. If two
triples of same lenght match, the one matched first
prevails, preserving the old behavior.
2) Remove 20 duplicated triples of arm, thumb,
aarch64 options with same arguments, matching
the common prefix (aarch64, arm, thumb) of them.
3) Creates three new function matching regexes and
five triple options for arm64-apple-ios,
(arm|thumb)-apple-ios and thumb(v5)?-macho
Reviewers: lebedev.ri, RKSimon, MaskRay, gbedwell
Reviewed By: MaskRay
Subscribers: javed.absar, kristof.beyls, llvm-commits, carwil
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63145
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363656
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Simon Pilgrim [Tue, 18 Jun 2019 09:50:13 +0000 (09:50 +0000)]
[X86] Replace any_extend* vector extensions with zero_extend* equivalents
First step toward addressing the vector-reduce-mul-widen.ll regression in D63281 - we should replace ANY_EXTEND/ANY_EXTEND_VECTOR_INREG in X86ISelDAGToDAG to avoid having to add duplicate patterns when treating any extensions as legal.
In future patches this will also allow us to keep any extension nodes around a lot longer in the DAG, which should mean that we can keep better track of undef elements that otherwise become zeros that we think we have to keep......
Differential Revision: https://reviews.llvm.org/D63326
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363655
91177308-0d34-0410-b5e6-
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Jeremy Morse [Tue, 18 Jun 2019 08:52:38 +0000 (08:52 +0000)]
[DebugInfo][Docs] Document that prologue/epilogue variable location changes are ignored
This patch documents that LLVM does not describe all changes in variable
locations during the prologue and the epilogue. The debugger doesn't /
shouldn't step through that portion of the function anyway, and describing
every location through such stages would bloat location lists.
Perform some minor cleanup at the same time,
* Fix an enumerated list
* Document that dbg.declare intrinsics have their variable location recorded
in a MachineFunction table, not with DBG_VALUE meta-insts
* Adds frame-indexes to the list of things that can be operands to
DBG_VALUEs.
Differential Revision: https://reviews.llvm.org/D63083
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363654
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Yevgeny Rouban [Tue, 18 Jun 2019 06:50:52 +0000 (06:50 +0000)]
[SimplifyCFG] NFC, prof branch_weighs handling is simplified
Using the new SwitchInstProfUpdateWrapper this patch
simplifies 3 places of prof branch_weights handling.
Differential Revision: https://reviews.llvm.org/D62123
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363652
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Fangrui Song [Tue, 18 Jun 2019 06:35:18 +0000 (06:35 +0000)]
[llvm-objdump] Tidy up AMDGCNPrettyPrinter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363650
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Craig Topper [Tue, 18 Jun 2019 04:52:49 +0000 (04:52 +0000)]
[X86] Add i128 ctpop and i32/i64/i128 optsize test cases to popcnt.ll
Test cases for PR41151 and D59909.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363647
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Craig Topper [Tue, 18 Jun 2019 04:23:58 +0000 (04:23 +0000)]
[X86] Move code that shrinks immediates for ((x << C1) op C2) into a helper function. NFCI
Preliminary step for D59909
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363645
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Craig Topper [Tue, 18 Jun 2019 03:23:15 +0000 (03:23 +0000)]
[X86] Remove MOVDI2SSrm/MOV64toSDrm/MOVSS2DImr/MOVSDto64mr CodeGenOnly instructions.
The isel patterns for these use a bitcast and load/store, but
DAG combine should have canonicalized those away.
For the purposes of the memory folding table these opcodes can be
replaced by the MOVSSrm_alt/MOVSDrm_alt and MOVSSmr/MOVSDmr opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363644
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Craig Topper [Tue, 18 Jun 2019 03:23:11 +0000 (03:23 +0000)]
[X86] Introduce new MOVSSrm/MOVSDrm opcodes that use VR128 register class.
Rename the old versions that use FR32/FR64 to MOVSSrm_alt/MOVSDrm_alt.
Use the new versions in patterns that previously used a COPY_TO_REGCLASS
to VR128. These patterns expect the upper bits to be zero. The
current set up appears to work, but I'm not sure we should be
enforcing upper bits being zero through a COPY_TO_REGCLASS.
I wanted to flip the arrangement and use a COPY_TO_REGCLASS to
FR32/FR64 for the patterns that need an f32/f64 result, but that
complicated fastisel and globalisel.
I've been doing some experiments with reducing some isel patterns
and ended up in a situation where I had a
(SUBREG_TO_REG (COPY_TO_RECLASS (VMOVSSrm), VR128)) and our
post-isel peephole was unable to avoid using an instruction for
the SUBREG_TO_REG due to the COPY_TO_REGCLASS. Having a VR128
instruction removes the COPY_TO_REGCLASS that was breaking this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363643
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Tom Stellard [Tue, 18 Jun 2019 02:05:06 +0000 (02:05 +0000)]
GlobalISel: Remove redundant pass initialization
Summary:
All the GlobalISel passes are initialized when the target calls
initializeGlobalISel(), so we don't need to call the initializers
from the pass constructors.
Reviewers: qcolombet, t.p.northover, paquette, dsanders, aemerson, aditya_nandakumar
Reviewed By: aemerson
Subscribers: rovka, kristof.beyls, hiraditya, volkan, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363642
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Alex Brachet [Tue, 18 Jun 2019 00:39:10 +0000 (00:39 +0000)]
[llvm-strip] Error when using stdin twice
Summary: Implements bug [[ https://bugs.llvm.org/show_bug.cgi?id=42204 | 42204 ]]. llvm-strip now warns when the same input file is used more than once, and errors when stdin is used more than once.
Reviewers: jhenderson, rupprecht, espindola, alexshap
Reviewed By: jhenderson, rupprecht
Subscribers: emaste, arichardson, jakehehrlich, MaskRay, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63122
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363638
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Matt Arsenault [Mon, 17 Jun 2019 23:48:43 +0000 (23:48 +0000)]
GlobalISel: Use the original flags when lowering fneg to fsub
This was ignoring the flag on fneg, and using the source instruction's
flags. Also fixes tests missing from r358702.
Note the expansion itself isn't correct without nnan, but that should
be fixed separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363637
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Peter Collingbourne [Mon, 17 Jun 2019 23:39:51 +0000 (23:39 +0000)]
hwasan: Use bits [3..11) of the ring buffer entry address as the base stack tag.
This saves roughly 32 bytes of instructions per function with stack objects
and causes us to preserve enough information that we can recover the original
tags of all stack variables.
Now that stack tags are deterministic, we no longer need to pass
-hwasan-generate-tags-with-calls during check-hwasan. This also means that
the new stack tag generation mechanism is exercised by check-hwasan.
Differential Revision: https://reviews.llvm.org/D63360
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363636
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