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Simon Dardis [Tue, 10 Jan 2017 13:57:44 +0000 (13:57 +0000)]
Revert "[mips] Honour -mno-odd-spreg for vector splat"
This reverts commit r291556. It was a mixture of two differentials and
was missing a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291562
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Eugene Leviant [Tue, 10 Jan 2017 11:05:30 +0000 (11:05 +0000)]
RuntimeDyldELF: implement R_AARCH64_PREL64 reloc
Differential revision: https://reviews.llvm.org/D28122
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291558
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Simon Dardis [Tue, 10 Jan 2017 10:28:37 +0000 (10:28 +0000)]
[mips] Honour -mno-odd-spreg for vector splat
Previous the lowering of FILL_FW would use the MSA128W register class when
performing a vector splat. Instead it should be honouring -mno-odd-spreg and
only use the even registers when performing a splat from word to vector
register.
Logical follow-on from r230235.
This fixes PR/31369.
Reviewers: slthakur
Differential Revision: https://reviews.llvm.org/D28373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291556
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Craig Topper [Tue, 10 Jan 2017 07:42:57 +0000 (07:42 +0000)]
[DAGCombiner] Merge together duplicate checks for folding fold (select C, 1, X) -> (or C, X) and folding (select C, X, 0) -> (and C, X). Also be consistent about checking that both the condition and the result type are i1. NFC
I guess previously we just assumed if the result type was i1, then the condition type must also be i1?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291548
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Chris Bieneman [Tue, 10 Jan 2017 06:24:24 +0000 (06:24 +0000)]
[ObjectYAML] Missed one mixup in the debug_line test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291547
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Chris Bieneman [Tue, 10 Jan 2017 06:22:49 +0000 (06:22 +0000)]
[ObjectYAML] Support for DWARF line tables
One more try... relanding r291541 with a fix to properly gate MaxOpsPerInst on DWARF version.
Description from r291541:
This patch re-lands r291470, which failed on Linux bots. The issue (I believe) was undefined behavior because the size of llvm::dwarf::LineNumberOps was not explcitly specified or consistently respected. The updated patch adds an explcit underlying type to the enum and preserves the size more correctly.
Original description:
This patch adds support for the DWARF debug_lines section. The line table state machine opcodes are preserved, so this can be used to test the state machine evaluation directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291546
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Craig Topper [Tue, 10 Jan 2017 06:01:16 +0000 (06:01 +0000)]
AMD family 17h (znver1) enablement
Summary:
This patch enables the following
1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu).
2. ISAs that are enabled for "znver1" architecture.
3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used.
4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17.
5. For the time being, it uses the btver2 scheduler model.
6. Test file is updated to check this flag.
This item is linked to clang review item https://reviews.llvm.org/D28018
Patch by Ganesh Gopalasubramanian
Reviewers: RKSimon, craig.topper
Subscribers: vprasad, RKSimon, ashutosh.nema, llvm-commits
Differential Revision: https://reviews.llvm.org/D28017
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291543
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Chris Bieneman [Tue, 10 Jan 2017 05:31:23 +0000 (05:31 +0000)]
Revert "[ObjectYAML] Support for DWARF line tables"
This reverts commit r291541.
Still failing on a bot:
http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/47224/steps/test_llvm/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291542
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Chris Bieneman [Tue, 10 Jan 2017 05:25:24 +0000 (05:25 +0000)]
[ObjectYAML] Support for DWARF line tables
This patch re-lands r291470, which failed on Linux bots. The issue (I believe) was undefined behavior because the size of llvm::dwarf::LineNumberOps was not explcitly specified or consistently respected. The updated patch adds an explcit underlying type to the enum and preserves the size more correctly.
Original description:
This patch adds support for the DWARF debug_lines section. The line table state machine opcodes are preserved, so this can be used to test the state machine evaluation directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291541
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Dean Michael Berris [Tue, 10 Jan 2017 04:32:34 +0000 (04:32 +0000)]
[XRay] Use regular expression for finding symbols
Un-break the test in Windows.
Follow-up on D24376.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291538
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Craig Topper [Tue, 10 Jan 2017 04:12:24 +0000 (04:12 +0000)]
[X86] When lowering uniform shifts, use X86ISD::VZEXT instead of using a ZERO_EXTEND_VECTOR_INREG. If we emit the ZERO_EXTEND_VECTOR_INREG too late it doesn't get lowered properly and makes it through to isel and fails.
Fixes PR31593.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291535
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Craig Topper [Tue, 10 Jan 2017 04:12:19 +0000 (04:12 +0000)]
[DAGCombiner] Remove code for optimizing select (xor Cond, 0), X, Y -> select Cond, X, Y. Just let combine on the xor itself take care of it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291534
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Dean Michael Berris [Tue, 10 Jan 2017 03:21:54 +0000 (03:21 +0000)]
[XRay] Fixup includes for modules build
Remove unnecessary system header include.
Follow-up to D24376.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291533
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Xin Tong [Tue, 10 Jan 2017 03:13:52 +0000 (03:13 +0000)]
Fix a typo and also test a new machine for commit. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291532
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Dean Michael Berris [Tue, 10 Jan 2017 02:51:13 +0000 (02:51 +0000)]
[XRay] Don't include <unistd.h> unnecessarily
Follow-up to D24376.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291531
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Serge Pavlov [Tue, 10 Jan 2017 02:50:47 +0000 (02:50 +0000)]
[StructurizeCfg] Update dominator info.
In some cases StructurizeCfg updates root node, but dominator info
remains unchanges, it causes crash when expensive checks are enabled.
To cope with this problem a new method was added to DominatorTreeBase
that allows adding new root nodes, it is called in StructurizeCfg to
put dominator tree in sync.
This change fixes PR27488.
Differential Revision: https://reviews.llvm.org/D28114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291530
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Dean Michael Berris [Tue, 10 Jan 2017 02:38:11 +0000 (02:38 +0000)]
[XRay] Implement `llvm-xray convert` -- trace file conversion
This is the second part of a multi-part change to define additional
subcommands to the `llvm-xray` tool.
This change defines a conversion subcommand to take XRay log files, and
turns them from one format to another (binary or YAML). This currently
only supports the first version of the log file format, defined in the
compiler-rt runtime.
Depends on D21987.
Reviewers: dblaikie, echristo
Subscribers: mehdi_amini, dberris, beanz, llvm-commits
Differential Revision: https://reviews.llvm.org/D24376
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291529
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Evandro Menezes [Tue, 10 Jan 2017 01:08:01 +0000 (01:08 +0000)]
[CodeGen] Implement the SUnit::print() method
This method seems to have had a troubled life. This patch proposes that it
replaces the recently added helper function dumpSUIdentifier. This way, the
method can be used in other files using the SUnit class.
Differential revision: https://reviews.llvm.org/D28488
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291520
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Reid Kleckner [Tue, 10 Jan 2017 01:05:33 +0000 (01:05 +0000)]
Try once again to fix the MSVC build of AlignedCharArrayUnion
It was complaining about ambiguity between llvm::detail and
llvm::support::detail:
error C2872: 'detail': ambiguous symbol
note: could be 'llvm::detail'
note: or 'llvm::support::detail'
Standardize on llvm::support::detail to hide these symbols further.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291519
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Mehdi Amini [Tue, 10 Jan 2017 00:55:47 +0000 (00:55 +0000)]
[ThinLTO] Hash more part of the config to build cache entries
This has been fixed in the "new" LTO API used by Gold/LLD, this is
fixing the same issue in the libLTO API used by ld64 (amongst other)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291518
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Xin Tong [Tue, 10 Jan 2017 00:39:49 +0000 (00:39 +0000)]
Add an assert for hasLoopInvariantOperands
Summary: Add an assert for hasLoopInvariantOperands
Reviewers: danielcdh, sanjoy
Subscribers: mzolotukhin, llvm-commits
Differential Revision: https://reviews.llvm.org/D28501
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291516
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Reid Kleckner [Tue, 10 Jan 2017 00:29:05 +0000 (00:29 +0000)]
Revert the attempt to optimize the constexpr functions. MSVC does not handle this yet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291515
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Reid Kleckner [Tue, 10 Jan 2017 00:26:56 +0000 (00:26 +0000)]
Fix MSVC build of AlignedCharArrayUnion
Use constexpr recursion for alignof like we do for sizeof. Seems to work
with Clang and MSVC. Also, don't recurse twice to avoid slowdowns in
compilers that don't memoize constexpr results (Clang).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291514
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Sean Callanan [Mon, 9 Jan 2017 23:23:25 +0000 (23:23 +0000)]
Lift the 10-type limit for AlignedCharArrayUnion
This patch uses C++11 parameter packs and constexpr functions
to allow AlignedCharArrayUnion to hold an arbitrary number of
types.
Differential Revision: https://reviews.llvm.org/D28429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291503
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James Y Knight [Mon, 9 Jan 2017 23:11:25 +0000 (23:11 +0000)]
Commit a test for match-full-lines.
I unfortunately neglected to add it in r260540, but it has been
sitting in my working dir ever since. D'oh.
Modified to work with r290069, which made the CHECK patterns
themselves whitespace-sensitive as well, and remove the test added
then, as this tests both strict and non-strict modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291499
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Dan Gohman [Mon, 9 Jan 2017 23:09:38 +0000 (23:09 +0000)]
[WebAssembly] Add return type annotations in fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291498
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Rui Ueyama [Mon, 9 Jan 2017 22:55:00 +0000 (22:55 +0000)]
TarWriter: Fix a bug in Ustar header.
If we split a filename into `Name` and `Prefix`, `Prefix` is at most
145 bytes. We had a bug that didn't split a path correctly. This bug
was pointed out by Rafael in the post commit review.
This patch adds a unit test for TarWriter to verify the fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291494
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Eugene Zelenko [Mon, 9 Jan 2017 22:16:51 +0000 (22:16 +0000)]
[NVPTX] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291490
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Simon Pilgrim [Mon, 9 Jan 2017 22:13:51 +0000 (22:13 +0000)]
[X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291488
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Easwaran Raman [Mon, 9 Jan 2017 21:56:26 +0000 (21:56 +0000)]
Refactor inline threshold update code.
Functional change: Previously, if a callee is cold, we used ColdThreshold if it minimizes the existing threshold. This was irrespective of whether we were optimizing for minsize (-Oz) or not. But -Oz uses very low threshold to begin with and the inlining with -Oz is expected to be tuned for lowering code size, so there is no good reason to set an even lower threshold for cold callees. We now lower the threshold for cold callees only when -Oz is not used. For default values of -inlinethreshold and -inlinecold-threshold, this change has no effect and this simplifies the code.
NFC changes: Group all threshold updates that are guarded by !Caller->optForMinSize() and within that group threshold updates that require profile summary info.
Differential revision: https://reviews.llvm.org/D28369
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291487
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Davide Italiano [Mon, 9 Jan 2017 21:55:23 +0000 (21:55 +0000)]
[SimplifyLibCalls] pow(x, -0.5) -> 1.0 / sqrt(x).
Differential Revision: https://reviews.llvm.org/D28479
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291486
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Rafael Espindola [Mon, 9 Jan 2017 21:52:35 +0000 (21:52 +0000)]
Support outputting to /dev/null.
When writing to a non regular file we cannot rename to it. Since we
have to write, we may as well create a temporary file to avoid trying
to create an unique file in /dev when trying to write to /dev/null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291485
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Matthias Braun [Mon, 9 Jan 2017 21:38:17 +0000 (21:38 +0000)]
PeepholeOptimizer: Do not replace SubregToReg(bitcast like)
While we can usually replace bitcast like instructions
(MachineInstr::isBitcast()) with a COPY this is not legal if any of the
users uses SUBREG_TO_REG to assert the upper bits of the result are
zero.
Differential Revision: https://reviews.llvm.org/D28474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291483
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Matthias Braun [Mon, 9 Jan 2017 21:38:14 +0000 (21:38 +0000)]
Drive by typo fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291482
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Matthias Braun [Mon, 9 Jan 2017 21:38:10 +0000 (21:38 +0000)]
MachineInstr: Print name for subreg index in SUBREG_TO_REG
SUBREG_TO_REG takes a subregister index as 3rd operand, print the name
instead of a number. We already do the same for INSERT_SUBREG and
REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291481
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Rui Ueyama [Mon, 9 Jan 2017 21:20:42 +0000 (21:20 +0000)]
TarWriter: Set "00" to Ustar version field.
Most (maybe all?) tar commands can handle tar archives with blank
version fields, but POSIX requires "00" to be set to the field, so
doing it is good for compliance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291479
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Michael Kuperstein [Mon, 9 Jan 2017 21:04:46 +0000 (21:04 +0000)]
Revert r291092 because it introduces a crash.
See PR31589 for details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291478
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Vyacheslav Klochkov [Mon, 9 Jan 2017 20:26:17 +0000 (20:26 +0000)]
X86-specific path: Implemented the fusing of MUL+ADDSUB to FMADDSUB.
Differential Revision: https://reviews.llvm.org/D28087
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291473
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Sanjay Patel [Mon, 9 Jan 2017 20:18:30 +0000 (20:18 +0000)]
[InstCombine] add test to show missed fold using llvm.assume; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291472
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Chris Bieneman [Mon, 9 Jan 2017 20:04:55 +0000 (20:04 +0000)]
Revert "[ObjectYAML] Support for DWARF line tables"
This reverts commit r291470 due to failing bots:
http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/47209/steps/test_llvm/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291471
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Chris Bieneman [Mon, 9 Jan 2017 20:01:37 +0000 (20:01 +0000)]
[ObjectYAML] Support for DWARF line tables
This patch adds support for the DWARF debug_lines section. The line table state machine opcodes are preserved, so this can be used to test the state machine evaluation directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291470
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Sanjay Patel [Mon, 9 Jan 2017 19:43:26 +0000 (19:43 +0000)]
[InstCombine] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291469
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Sanjay Patel [Mon, 9 Jan 2017 19:31:20 +0000 (19:31 +0000)]
[ValueTracking] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291468
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Daniel Berlin [Mon, 9 Jan 2017 19:24:19 +0000 (19:24 +0000)]
Fix function regex in update_tests so it can handle {}'s in function args
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291467
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Sanjay Patel [Mon, 9 Jan 2017 19:18:46 +0000 (19:18 +0000)]
[InstCombine] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291464
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Sanjay Patel [Mon, 9 Jan 2017 19:13:38 +0000 (19:13 +0000)]
[InstCombine] remove unnecessary attribute comments from test files; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291463
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Matthew Simpson [Mon, 9 Jan 2017 19:05:29 +0000 (19:05 +0000)]
[LV] Fix-up external IV users after updating dominator tree
This patch delays the fix-up step for external induction variable users until
after the dominator tree has been properly updated. This should fix PR30742.
The SCEVExpander in InductionDescriptor::transform can generate code in the
wrong location if the dominator tree is not up-to-date. We should work towards
keeping the dominator tree up-to-date throughout the transformation.
Reference: https://llvm.org/bugs/show_bug.cgi?id=30742
Differential Revision: https://reviews.llvm.org/D28168
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291462
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Matt Arsenault [Mon, 9 Jan 2017 18:52:39 +0000 (18:52 +0000)]
AMDGPU: Add Assert[SZ]Ext during argument load creation
For i16 zeroext arguments when i16 was a legal type, the
known bits information from the truncate was lost. Insert
a zeroext so the known bits optimizations work with the 32-bit
loads.
Fixes code quality regressions vs. SI in min.ll test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291461
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Matt Arsenault [Mon, 9 Jan 2017 18:44:11 +0000 (18:44 +0000)]
Reapply r291025 ("AMDGPU: Remove unneccessary intermediate vector")
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291460
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Xin Tong [Mon, 9 Jan 2017 17:57:08 +0000 (17:57 +0000)]
Intrinsic::Bitreverse is safe to speculate
Summary: Intrinsic::Bitreverse is safe to speculate
Reviewers: hfinkel, mkuper, arsenm, jmolloy
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D28471
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291456
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Sumanth Gundapaneni [Mon, 9 Jan 2017 17:45:02 +0000 (17:45 +0000)]
In the below scenario, we must be able to skip the a DBG_VALUE instruction and
remove the dead store.
%vreg0<def> = L2_loadri_io <fi#15>, 0; mem:LD4[%dataF](align=4)
DBG_VALUE %vreg0, %noreg, !"dataF", <!184>; IntRegs:%vreg0
S2_storeri_io <fi#15>, 0, %vreg0; mem:ST4[%dataF]
In reality, this kind of stores are eliminated before Stack Slot Coloring pass,
possibly in instruction lowering
Differential Revision: https://reviews.llvm.org/D26616
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291455
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Simon Pilgrim [Mon, 9 Jan 2017 17:20:03 +0000 (17:20 +0000)]
[X86][AVX512] Enable v16i8/v32i8 vector shifts to use an extend+shift+truncate pattern.
Use the existing AVX2 v8i16 vector shift lowering for v16i8 (extending to v16i32) on AVX512 targets and v32i8 (extending to v32i16) on AVX512BW targets.
Cost model updates to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291451
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Sanjay Patel [Mon, 9 Jan 2017 16:27:56 +0000 (16:27 +0000)]
fix comment typos; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291447
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Simon Pilgrim [Mon, 9 Jan 2017 15:15:45 +0000 (15:15 +0000)]
[X86][AVX512DQ] Enable v16i16 vector shifts to use an extend+shift+truncate pattern.
Use the existing AVX2 v8i16 vector shift lowering for v16i16 on AVX512 targets (AVX512BW will have already have lowered with vpsravw).
Cost model updates to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291445
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Simon Pilgrim [Mon, 9 Jan 2017 14:36:09 +0000 (14:36 +0000)]
[X86][AVX512DQ] Added AVX512DQ to 128/256 bit vector shift tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291444
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Mohammed Agabaria [Mon, 9 Jan 2017 14:00:57 +0000 (14:00 +0000)]
[IR] Adding const_value_op_iterator for IR/User.h
const value op iterator is missing from User.h class.
Differential Revision: https://reviews.llvm.org/D28464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291443
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Amaury Sechet [Mon, 9 Jan 2017 13:54:51 +0000 (13:54 +0000)]
Some formatting in TargetMachineC. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291442
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Bjorn Pettersson [Mon, 9 Jan 2017 12:03:50 +0000 (12:03 +0000)]
[SelectionDAG] Fix in legalization of UMAX/SMAX/UMIN/SMIN. Solves PR31486.
Summary:
Originally
i64 = umax t8, Constant:i64<4>
was expanded into
i32,i32 = umax Constant:i32<0>, Constant:i32<0>
i32,i32 = umax t7, Constant:i32<4>
Now instead the two produced umax:es return i32 instead of i32, i32.
Thanks to Jan Vesely for help with the test case.
Patch by mikael.holmen at ericsson.com
Reviewers: bogner, jvesely, tstellarAMD, arsenm
Subscribers: test, wdng, RKSimon, arsenm, nhaehnle, llvm-commits
Differential Revision: https://reviews.llvm.org/D28135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291441
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Eugene Leviant [Mon, 9 Jan 2017 11:47:33 +0000 (11:47 +0000)]
RuntimeDyldELF: add missing test cases for AArch64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291438
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Pavel Labath [Mon, 9 Jan 2017 11:20:35 +0000 (11:20 +0000)]
Fix MSVC build failure introduced in r291431
MSVC does not like to reinterpret_cast to a uint64_t. Use a different cast
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291435
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Eugene Leviant [Mon, 9 Jan 2017 09:56:31 +0000 (09:56 +0000)]
RuntimeDyldELF: don't create thunk if not needed
This patch doesn't create thunk for branch operation when following conditions are met:
- Architecture is AArch64
- Relocation target is in the same object file
- Relocation target is close enough to be encoded in immediate offset
In such case we branch directly to the target instead of branching to thunk
Differential revision: https://reviews.llvm.org/D28108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291431
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Chandler Carruth [Mon, 9 Jan 2017 07:44:34 +0000 (07:44 +0000)]
[PM] Teach SCEV to invalidate itself when its dependencies become
invalid.
This fixes use-after-free bugs that will arise with any interesting use
of SCEV.
I've added a dedicated test that works diligently to trigger these kinds
of bugs in the new pass manager and also checks for them explicitly as
well as triggering ASan failures when things go squirly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291426
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Dan Gohman [Mon, 9 Jan 2017 06:21:28 +0000 (06:21 +0000)]
[WebAssembly] Fix the opcode values for i64.eq and i64.ne.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291424
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Jonas Paulsson [Mon, 9 Jan 2017 06:13:21 +0000 (06:13 +0000)]
Remove unused method in LoopVectorize.cpp.
computeInterleaveCount() is not defined/used and is therefore removed.
Review: Davide Italiano
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291423
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Daniel Berlin [Mon, 9 Jan 2017 05:34:29 +0000 (05:34 +0000)]
NewGVN: Fix PR 31573, a failure to verify memory congruency due to
not excluding ourselves when checking if any equivalent stores
exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291421
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Daniel Berlin [Mon, 9 Jan 2017 05:34:19 +0000 (05:34 +0000)]
NewGVN: Change a std::vector to SmallVector and cleanup naming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291420
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Craig Topper [Mon, 9 Jan 2017 04:19:34 +0000 (04:19 +0000)]
[AVX-512] Change another pattern that was using BLENDM to use masked moves. A future patch will conver it back to BLENDM if its beneficial to register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291419
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Craig Topper [Mon, 9 Jan 2017 02:44:34 +0000 (02:44 +0000)]
[AVX-512] Add patterns to use a zero masked VPTERNLOG instruction for vselects of all ones and all zeros.
Previously we emitted a VPTERNLOG and a separate masked move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291415
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Rui Ueyama [Mon, 9 Jan 2017 01:47:15 +0000 (01:47 +0000)]
Define sys::path::convert_to_slash
This patch moves convertToUnixPathSeparator from LLD to LLVM.
Differential Revision: https://reviews.llvm.org/D28444
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291414
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Mehdi Amini [Sun, 8 Jan 2017 22:30:43 +0000 (22:30 +0000)]
CommandLine option: Relax the assertion introduced in r290467 to allows for empty string
This is used in LDC for custom boolean commandline options, setArgStr
is called with an empty string before using AddLiteralOption.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291406
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Piotr Padlewski [Sun, 8 Jan 2017 22:26:06 +0000 (22:26 +0000)]
[MemDep] NFC walk invariant.group graph only down
Summary:
By using stripPointerCasts we can get to the root
value and then walk down the bitcast graph
Reviewers: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D28181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291405
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Davide Italiano [Sun, 8 Jan 2017 22:22:09 +0000 (22:22 +0000)]
[LCSSA] Fix some typos. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291404
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Craig Topper [Sun, 8 Jan 2017 21:32:30 +0000 (21:32 +0000)]
[AVX-512] If avx512dq is available use vpmovm2d/vpmovm2q instead of vselect of zeroes/ones when handling sign extends of i1 without VLX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291402
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Craig Topper [Sun, 8 Jan 2017 21:32:26 +0000 (21:32 +0000)]
[X86] Add avx512bw and avx512dq command lines to the vector compare results test.
This is preparation for improving a case with avx512dq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291401
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Davide Italiano [Sun, 8 Jan 2017 21:19:05 +0000 (21:19 +0000)]
[SCCP] Unknown instructions are sent to overdefined anyway. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291400
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Lang Hames [Sun, 8 Jan 2017 20:09:35 +0000 (20:09 +0000)]
[Orc][RPC] Lock the pending results data structure when installing new result
handlers, make abandonPendingResults public API.
This should make installing asynchronous result handlers thread safe.
The abandonPendingResults method is made public so that clients can disconnect
from a remote even if they have asynchronous handlers awaing results from that
remote. The asynchronous handlers will all receive "abandoned result" errors as
their argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291399
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Saleem Abdulrasool [Sun, 8 Jan 2017 19:14:15 +0000 (19:14 +0000)]
llvm-objdump: speed up -objc-meta-data
Running a Debug build of objdump -objc-meta-data with a large Mach-O file is
currently unnecessarily slow.
With some local test input, this change reduces the run time from 75-85s down
to 15-20s.
The two changes are:
Assert on pointer equality not array equality
Replace vector<pair<address, symbol>> with DenseMap<address, symbol>
Additionally, use a std::unique_ptr rather than handling the memory manually.
Patch by Dave Lee!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291398
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Simon Pilgrim [Sun, 8 Jan 2017 18:37:42 +0000 (18:37 +0000)]
Strip trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291395
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Saleem Abdulrasool [Sun, 8 Jan 2017 18:36:49 +0000 (18:36 +0000)]
unittest: remove extraneous ';'
Silences a warning from gcc:6. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291394
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Simon Pilgrim [Sun, 8 Jan 2017 16:45:39 +0000 (16:45 +0000)]
Fix line endings and strip trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291393
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Sanjay Patel [Sun, 8 Jan 2017 15:53:40 +0000 (15:53 +0000)]
[x86] fix usage of stale operands when lowering select
I noticed this problem as part of the ongoing attempt to canonicalize min/max ops in IR.
The debug output shows nodes like this:
t4: i32 = xor t2, Constant:i32<-1>
t21: i8 = setcc t4, Constant:i32<0>, setlt:ch
t14: i32 = select t21, t4, Constant:i32<-1>
And because the select is holding onto the t4 (xor) node while EmitTest creates a new
x86-specific xor node, the lowering results in:
t4: i32 = xor t2, Constant:i32<-1>
t25: i32,i32 = X86ISD::XOR t2, Constant:i32<-1>
t28: i32,glue = X86ISD::CMOV Constant:i32<-1>, t4, Constant:i8<15>, t25:1
Differential Revision: https://reviews.llvm.org/D28374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291392
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Simon Pilgrim [Sun, 8 Jan 2017 14:14:36 +0000 (14:14 +0000)]
[CostModel][X86] Fixed vXi8 uniform shift costs.
The 'fast' costs should only work for shifts by uniform constants (uniform non-constant are lowered using the slow default implementation).
Logical shifts were not taking into account that we must mask the psrlw result, so the costs needed to be doubled.
Added missing AVX2/AVX512BW costs as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291391
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Simon Pilgrim [Sun, 8 Jan 2017 13:12:03 +0000 (13:12 +0000)]
[CostModel][X86] Moved legal uniform shift costs earlier.
XOP was prematurely matching, doubling the cost of ashr/lshr uniform shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291390
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Craig Topper [Sun, 8 Jan 2017 05:46:21 +0000 (05:46 +0000)]
[AVX-512] Remove redundant patterns that select unaligned moves with zero masking for patterns that already use the aligned form. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291383
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Lang Hames [Sun, 8 Jan 2017 02:27:30 +0000 (02:27 +0000)]
[Orc][RPC] Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291381
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Lang Hames [Sun, 8 Jan 2017 01:13:47 +0000 (01:13 +0000)]
[Orc][RPC] Add an APICalls utility for grouping RPC funtions for registration.
APICalls allows groups of functions to be composed into an API that can be
registered as a unit with an RPC endpoint. Doing registration on a-whole API
basis (rather than per-function) allows missing API functions to be detected
early.
APICalls also allows Function membership to be tested at compile-time. This
allows clients to write static assertions that functions to be called are
members of registered APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291380
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Mehdi Amini [Sun, 8 Jan 2017 00:44:45 +0000 (00:44 +0000)]
[ThinLTO] Fix lazy-loading of Metadata attachment, which left some Fwd ref behind
The change in r291362 was too agressive. We still need to flush at the
end of the block because function local metadata can introduce fwd
ref as well.
(Bootstrap with ThinLTO was broken)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291379
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Mehdi Amini [Sun, 8 Jan 2017 00:30:27 +0000 (00:30 +0000)]
[ThinLTO] Expected<> return values need to be handled to avoid an assertion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291377
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Lang Hames [Sun, 8 Jan 2017 00:18:51 +0000 (00:18 +0000)]
[Orc][RPC] Add a class-method version of addHandler to MultiThreadedRPCEndpoint.
This brings MultiThreadedRPCEndpoint's addHandler API in-line with
SingleThreadedRPCEndpoint's.
This will be tested in an up-coming unit-test for MultiThreadedRPCEndpoint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291376
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Dylan McKay [Sat, 7 Jan 2017 23:39:47 +0000 (23:39 +0000)]
[AVR] Implement TargetLoweing::getRegisterByName
This allows the use of the 'read_register' intrinsics used by clang's
named register globals features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291375
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Lang Hames [Sat, 7 Jan 2017 22:48:12 +0000 (22:48 +0000)]
[Orc][RPC] Rename Single/MultiThreadedRPC to Single/MultithreadedRPCEndpoint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291374
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Lang Hames [Sat, 7 Jan 2017 22:27:52 +0000 (22:27 +0000)]
[Orc][RPC] Remove a redundant 'if' statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291373
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Simon Pilgrim [Sat, 7 Jan 2017 22:27:43 +0000 (22:27 +0000)]
[CostModel][X86] Update SSE41/AVX1 vXi32 SHL costs
SSE41 provides pmulld which allows the simpler pslld/paddd/cvttps2dq/pmulld pattern than SSE2's use of pmuludq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291372
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Craig Topper [Sat, 7 Jan 2017 22:20:34 +0000 (22:20 +0000)]
[AVX-512] Remove patterns from the other VBLENDM instructions. They are all redundant with masked move instructions.
We should probably teach the two address instruction pass to turn masked moves into BLENDM when its beneficial to the register allocator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291371
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Craig Topper [Sat, 7 Jan 2017 22:20:28 +0000 (22:20 +0000)]
[X86] Regenerate a test to remove tab characters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291370
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Craig Topper [Sat, 7 Jan 2017 22:20:26 +0000 (22:20 +0000)]
[AVX-512] Remove patterns from masked broadcast versions of BLENDM instructions.
All but (v2f64 broadcast f64) are handled with VBROADCAST instructions. The v2f64 version can be handled with VMOVDDUP.
We may want to consider converting to BLENDM instructions in the two address instruction pass if its beneficial to register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291369
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Craig Topper [Sat, 7 Jan 2017 22:20:23 +0000 (22:20 +0000)]
[AVX-512] Add masked forms of the alternate MOVDDUP patterns.
I'm not too sure how to get isel to select even all of the unmasked forms, but at least we have a consistent set now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291368
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Simon Pilgrim [Sat, 7 Jan 2017 22:08:09 +0000 (22:08 +0000)]
[CostModel][X86] Fix AVX2 v16i16 shift 'splat' costs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291366
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Simon Pilgrim [Sat, 7 Jan 2017 21:47:10 +0000 (21:47 +0000)]
[CostModel][X86] Match 256-bit vector shift 'splat' costs for AVX2 and above
We were matching against general vector shift costs before the uniform splat costs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291365
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Simon Pilgrim [Sat, 7 Jan 2017 21:33:00 +0000 (21:33 +0000)]
[CostModel][X86] Generalized cost calculation of SHL by constant -> MUL conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291364
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