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6 years ago[dwarfdump] Only print CU relative offset in verbose mode
Jonas Devlieghere [Wed, 7 Mar 2018 16:28:53 +0000 (16:28 +0000)]
[dwarfdump] Only print CU relative offset in verbose mode

Instead of only printing the CU-relative offset in non-verbose mode, it
makes more sense to only printed the resolved address. In verbose mode
we still print both.

Differential revision: https://reviews.llvm.org/D44148

rdar://33525475

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326903 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert "Reapply "[DWARFv5] Emit file 0 to the line table.""
Alexander Kornienko [Wed, 7 Mar 2018 16:27:44 +0000 (16:27 +0000)]
Revert "Reapply "[DWARFv5] Emit file 0 to the line table.""

This reverts commit r326839.

r326839 breaks assembly file parsing:

$ cat q.c
void g() {}
$ clang -S q.c -g
$ clang -g -c q.s
q.s:9:2: error: file number already allocated
     .file   1 "/tmp/test" "q.c"
     ^

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326902 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert rL326898: "Teach CorrelatedValuePropagation to reduce the width of udiv/urem...
Justin Lebar [Wed, 7 Mar 2018 16:05:43 +0000 (16:05 +0000)]
Revert rL326898: "Teach CorrelatedValuePropagation to reduce the width of udiv/urem instructions."

Breaks bootstrap builds: clang built with this patch asserts while
building MCDwarf.cpp: Assertion `castIsValid(op, S, Ty) && "Invalid
cast!"' failed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326900 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoTeach CorrelatedValuePropagation to reduce the width of udiv/urem instructions.
Justin Lebar [Wed, 7 Mar 2018 15:11:13 +0000 (15:11 +0000)]
Teach CorrelatedValuePropagation to reduce the width of udiv/urem instructions.

Summary:
If the operands of a udiv/urem can be proved to fit within a smaller
power-of-two-sized type, reduce the width of the udiv/urem.

Reviewers: spatel, sanjoy

Subscribers: llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D44102

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326898 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][X87] Add X87 fp80 conversion tests
Simon Pilgrim [Wed, 7 Mar 2018 14:13:14 +0000 (14:13 +0000)]
[X86][X87] Add X87 fp80 conversion tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326897 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[mips] Correct the definition of m(f|t)c(0|2)
Simon Dardis [Wed, 7 Mar 2018 11:39:48 +0000 (11:39 +0000)]
[mips] Correct the definition of m(f|t)c(0|2)

These instructions are defined as taking a GPR register and a
coprocessor register for ISAs up to MIPS32. MIPS32 extended the
definition to allow a selector--a value from 0 to 32--to access
another register.

These instructions are now internally defined as being MIPS-I
instructions, but are rejected for pre-MIPS32 ISA's if they have
an explicit selector which is non-zero. This deviates slightly from
GAS's behaviour which rejects assembly instructions with an
explicit selector for pre-MIPS32 ISAs.

E.g:

mfc0 $4, $5, 0
is rejected by GAS for MIPS-I to MIPS-V but will be accepted
with this patch for MIPS-I to MIPS-V.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D41662

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326890 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[LoadStoreVectorizer] Differentiate between <1 x T> and T
Sven van Haastregt [Wed, 7 Mar 2018 10:29:28 +0000 (10:29 +0000)]
[LoadStoreVectorizer] Differentiate between <1 x T> and T

The LoadStoreVectorizer thought that <1 x T> and T were the same types
when merging stores, leading to a crash later.

Patch by Erik Hogeman.

Differential Revision: https://reviews.llvm.org/D44014

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326884 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ARM] Fix for PR36577
Sjoerd Meijer [Wed, 7 Mar 2018 09:10:44 +0000 (09:10 +0000)]
[ARM] Fix for PR36577

Don't PerformSHLSimplify if the given node is used by a node that also uses a
constant because we may get stuck in an infinite combine loop.

bugzilla: https://bugs.llvm.org/show_bug.cgi?id=36577

Patch by Sam Parker.

Differential Revision: https://reviews.llvm.org/D44097

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326882 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SystemZ] NFC refactoring in SystemZHazardRecognizer.
Jonas Paulsson [Wed, 7 Mar 2018 08:57:09 +0000 (08:57 +0000)]
[SystemZ]  NFC refactoring in SystemZHazardRecognizer.

Use Reset() after emitting a call.

Review: Ulrich Weigand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326881 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SystemZ] Improve getCurrCycleIdx() in SystemZHazardRecognizer.
Jonas Paulsson [Wed, 7 Mar 2018 08:54:32 +0000 (08:54 +0000)]
[SystemZ]  Improve getCurrCycleIdx() in SystemZHazardRecognizer.

getCurrCycleIdx() returns the decoder cycle index which the next candidate SU
will be placed on.

This patch improves this method by passing the candidate SU to it so that if
SU will begin a new group, the index of that group is returned instead.

Review: Ulrich Weigand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326880 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SystemZ] NFC refactoring in SystemZHazardRecognizer.
Jonas Paulsson [Wed, 7 Mar 2018 08:45:09 +0000 (08:45 +0000)]
[SystemZ] NFC refactoring in SystemZHazardRecognizer.

Handle the not-taken branch in emitInstruction() where the TakenBranch
argument is available. This is cleaner than relying on EmitInstruction().

Review: Ulrich Weigand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326879 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SystemZ] Improved debug dumping during post-RA scheduling.
Jonas Paulsson [Wed, 7 Mar 2018 08:39:00 +0000 (08:39 +0000)]
[SystemZ]  Improved debug dumping during post-RA scheduling.

Review: Ulrich Weigand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326878 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Add IMUL scheduling info on sandybridge, fix it on >=haswell.
Clement Courbet [Wed, 7 Mar 2018 08:14:02 +0000 (08:14 +0000)]
[X86] Add IMUL scheduling info on sandybridge, fix it on >=haswell.

Summary:
Only IMUL16rri uses an extra P0156. IMUL32* and IMUL16rr only use
P1.
This was computed using https://github.com/google/EXEgesis/blob/master/exegesis/tools/compute_itineraries.cc

This can easily be validated by running perf on the following code:

```
int main(int argc, char**argv) {
  int a = argc;
  int b = argc;
  int c = argc;
  int d = argc;

  for (int i = 0; i < LOOP_ITERATIONS; ++i) {
    asm volatile(
      R"(
        .rept 10000
        imull $0x2, %%edx, %%eax
        imull $0x2, %%ecx, %%ebx
        imull $0x2, %%eax, %%edx
        imull $0x2, %%ebx, %%ecx
        .endr
      )"
      : "+a"(a), "+b"(b), "+c"(c), "+d"(d)
      :
      :);
  }
  return a+b+c+d;
}
```
-> test.cc

perf stat -x, -e cycles --pfm-events=uops_executed_port:port_0:u,uops_executed_port:port_1:u,uops_executed_port:port_2:u,uops_executed_port:port_3:u,uops_executed_port:port_4:u,uops_executed_port:port_5:u,uops_executed_port:port_6:u,uops_executed_port:port_7:u test

Reviewers: craig.topper, RKSimon, gadi.haber

Subscribers: llvm-commits, gchatelet, chandlerc

Differential Revision: https://reviews.llvm.org/D43460

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326877 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-pdbdump] Add guard for null pointers and remove unused code
Aaron Smith [Wed, 7 Mar 2018 02:23:08 +0000 (02:23 +0000)]
[llvm-pdbdump] Add guard for null pointers and remove unused code

Summary: This avoids crashing when a user tries to dump a pdb with the `-native` option.

Reviewers: zturner, llvm-commits, rnk

Reviewed By: zturner

Subscribers: mgrang

Differential Revision: https://reviews.llvm.org/D44117

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326863 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAdd early exit on reassociation of 0 expression.
Evgeny Stupachenko [Wed, 7 Mar 2018 02:17:08 +0000 (02:17 +0000)]
Add early exit on reassociation of 0 expression.

Summary:

Before the patch a try to reassociate ((v * 16) * 0) * 1 fall into infinite loop

Reviewers: pankajchawla

Differential Revision: http://reviews.llvm.org/D41467

From: Evgeny Stupachenko <evstupac@gmail.com>
                         <evgeny.v.stupachenko@intel.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326861 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[DebugInfoPDB] Add DIA implementation for getSrcLineOnTypeDefn
Aaron Smith [Wed, 7 Mar 2018 00:33:09 +0000 (00:33 +0000)]
[DebugInfoPDB] Add DIA implementation for getSrcLineOnTypeDefn

Summary: This helps to determine the line number for a PDB type with definition

Reviewers: zturner, llvm-commits, rnk

Reviewed By: zturner

Subscribers: rengolin, JDevlieghere

Differential Revision: https://reviews.llvm.org/D44119

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326857 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Transforms] Add missing header for InstructionCombining.cpp, in order to export...
Eugene Zelenko [Tue, 6 Mar 2018 23:06:13 +0000 (23:06 +0000)]
[Transforms] Add missing header for InstructionCombining.cpp, in order to export LLVMInitializeInstCombine as extern "C". Fixes PR35947.

Patch by Brenton Bostick.

Differential revision: https://reviews.llvm.org/D44140

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326843 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Fix a typo in Host.cpp that causes us to misidentify KNL, Silvermont, Goldmont...
Craig Topper [Tue, 6 Mar 2018 22:45:31 +0000 (22:45 +0000)]
[X86] Fix a typo in Host.cpp that causes us to misidentify KNL, Silvermont, Goldmont and probably other CPUs for -march=native

I think most of the Intel Core CPUs and recent AMD CPUs are unaffected. All the CPUs that have a "subtype" should work. The ones that were broken are the ones that are a "type" with no subtypes.

Fixes PR36619.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326840 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoReapply "[DWARFv5] Emit file 0 to the line table."
Paul Robinson [Tue, 6 Mar 2018 22:37:45 +0000 (22:37 +0000)]
Reapply "[DWARFv5] Emit file 0 to the line table."

Fixes the bug found by asan. Also XFAIL the new test for Darwin,
which is stuck on DWARF v2, and fix up other tests so they stop
failing on Windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326839 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[TargetLowering] Add vector BITCAST support to SimplifyDemandedVectorElts
Simon Pilgrim [Tue, 6 Mar 2018 22:32:01 +0000 (22:32 +0000)]
[TargetLowering] Add vector BITCAST support to SimplifyDemandedVectorElts

Notably helps cleanup after legalization of vector types

Differential Revision: https://reviews.llvm.org/D43674

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326838 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoDA: remove uses of GEP, only ask SCEV
Sebastian Pop [Tue, 6 Mar 2018 21:55:59 +0000 (21:55 +0000)]
DA: remove uses of GEP, only ask SCEV

It's been quite some time the Dependence Analysis (DA) is broken,
as it uses the GEP representation to "identify" multi-dimensional arrays.
It even wrongly detects multi-dimensional arrays in single nested loops:

from test/Analysis/DependenceAnalysis/Coupled.ll, example @couple6
;; for (long int i = 0; i < 50; i++) {
;; A[i][3*i - 6] = i;
;; *B++ = A[i][i];

DA used to detect two subscripts, which makes no sense in the LLVM IR
or in C/C++ semantics, as there are no guarantees as in Fortran of
subscripts not overlapping into a next array dimension:

maximum nesting levels = 1
SrcPtrSCEV = %A
DstPtrSCEV = %A
using GEPs
subscript 0
    src = {0,+,1}<nuw><nsw><%for.body>
    dst = {0,+,1}<nuw><nsw><%for.body>
    class = 1
    loops = {1}
subscript 1
    src = {-6,+,3}<nsw><%for.body>
    dst = {0,+,1}<nuw><nsw><%for.body>
    class = 1
    loops = {1}
Separable = {}
Coupled = {1}

With the current patch, DA will correctly work on only one dimension:

maximum nesting levels = 1
SrcSCEV = {(-2424 + %A)<nsw>,+,1212}<%for.body>
DstSCEV = {%A,+,404}<%for.body>
subscript 0
    src = {(-2424 + %A)<nsw>,+,1212}<%for.body>
    dst = {%A,+,404}<%for.body>
    class = 1
    loops = {1}
Separable = {0}
Coupled = {}

This change removes all uses of GEP from DA, and we now only rely
on the SCEV representation.

The patch does not turn on -da-delinearize by default, and so the DA analysis
will be more conservative in the case of multi-dimensional memory accesses in
nested loops.

I disabled some interchange tests, as the DA is not able to disambiguate
the dependence anymore. To make DA stronger, we may need to
compute a bound on the number of iterations based on the access functions
and array dimensions.

The patch cleans up all the CHECKs in test/Transforms/LoopInterchange/*.ll to
avoid checking for snippets of LLVM IR: this form of checking is very hard to
maintain. Instead, we now check for output of the pass that are more meaningful
than dozens of lines of LLVM IR. Some tests now require -debug messages and thus
only enabled with asserts.

Patch written by Sebastian Pop and Aditya Kumar.

Differential Revision: https://reviews.llvm.org/D35430

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326837 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoPrintStatistics() and PrintStatisticsJSON() should take StatLock
Daniel Sanders [Tue, 6 Mar 2018 21:16:42 +0000 (21:16 +0000)]
PrintStatistics() and PrintStatisticsJSON() should take StatLock

These two functions iterate over the list of statistics but don't take the lock
that protects the iterators from being invalidated by
StatisticInfo::addStatistic().

So far, this hasn't been an issue since (in-tree at least) these functions are
called by the StatisticInfo destructor so addStatistic() shouldn't be called
anymore. However, we do expose them in the public API.

Note that this only protects against iterator invalidation and does not protect
against ordering issues caused by statistic updates that race with
PrintStatistics()/PrintStatisticsJSON().

Thanks to Roman Tereshin for spotting it

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326834 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[TargetLowering] Rename DAGCombinerInfo::isAfterLegalizeVectorOps to DAGCombiner...
Craig Topper [Tue, 6 Mar 2018 19:44:52 +0000 (19:44 +0000)]
[TargetLowering] Rename DAGCombinerInfo::isAfterLegalizeVectorOps to DAGCombiner::isAfterLegalizeDAG since that's what it checks. NFC

The code checks Level == AfterLegalizeDAG which is the fourth and last of the possible DAG combine stages that we have.

There is a Level called AfterLegalVectorOps, but that's the third DAG combine and it doesn't always run.

A function called isAfterLegalVectorOps should imply it returns true in either of the DAG combines that runs after the legalize vector ops stage, but that's not what this function does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326832 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SymboleFilePDB] Put the test input back that my previous commit clobbered
Aaron Smith [Tue, 6 Mar 2018 19:36:17 +0000 (19:36 +0000)]
[SymboleFilePDB] Put the test input back that my previous commit clobbered

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326831 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Update more testcases
Krzysztof Parzyszek [Tue, 6 Mar 2018 19:15:58 +0000 (19:15 +0000)]
[Hexagon] Update more testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326830 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Remove {{ *}} from testcases
Krzysztof Parzyszek [Tue, 6 Mar 2018 19:07:21 +0000 (19:07 +0000)]
[Hexagon] Remove {{ *}} from testcases

The spaces in the instructions are now consistent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326829 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] simplify min/max canonicalization; NFCI
Sanjay Patel [Tue, 6 Mar 2018 19:01:18 +0000 (19:01 +0000)]
[InstCombine] simplify min/max canonicalization; NFCI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326828 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Reject registers that require a REX prefix in inline asm constraints in 32...
Craig Topper [Tue, 6 Mar 2018 18:56:33 +0000 (18:56 +0000)]
[X86] Reject registers that require a REX prefix in inline asm constraints in 32-bit mode

We don't currently reject r8-r15 or xmm8-32 or bpl/spl/sil/dil in 32-bit mode.

Differential Revision: https://reviews.llvm.org/D44031

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326826 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AMDGPU] Add default ISA version targets
Stanislav Mekhanoshin [Tue, 6 Mar 2018 18:33:55 +0000 (18:33 +0000)]
[AMDGPU] Add default ISA version targets

In case if -mattr used to modify feature set bits in llvm-mc call
getIsaVersion can fail to identify specific ISA due to test mismatch.
Adding default fallback tests which will always correctly report at
least major version.

Differential Revision: https://reviews.llvm.org/D44163

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326825 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CodeView] Emit UdtSourceLine information for enums
Aaron Smith [Tue, 6 Mar 2018 18:20:22 +0000 (18:20 +0000)]
[CodeView] Emit UdtSourceLine information for enums

Summary:
- Emit UdtSourceLine information for enums to match MSVC

- Add a method to add UDTSrcLine and call it for all Class/Struct/Union/Enum

- Update test cases to verify the changes

Reviewers: zturner, llvm-commits, rnk

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D44116

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326824 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[PatternMatch] define m_Not using m_Xor and cst_pred_ty
Sanjay Patel [Tue, 6 Mar 2018 18:19:42 +0000 (18:19 +0000)]
[PatternMatch] define m_Not using m_Xor and cst_pred_ty

Using cst_pred_ty in the definition allows us to match vectors with undef elements.

This is a continuation of an effort to make all pattern matchers allow undef elements in vectors:
rL325437
rL325466
D43792

Differential Revision: https://reviews.llvm.org/D44076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326823 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRefactor check for dllimport in the Verifier.
Rafael Espindola [Tue, 6 Mar 2018 17:19:23 +0000 (17:19 +0000)]
Refactor check for dllimport in the Verifier.

This avoids duplicated code and now also rejects dllimport aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326814 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ValueTracking] move helpers for SelectPatterns from InstCombine to ValueTracking
Sanjay Patel [Tue, 6 Mar 2018 16:57:55 +0000 (16:57 +0000)]
[ValueTracking] move helpers for SelectPatterns from InstCombine to ValueTracking

Most of the folds based on SelectPatternResult belong in InstSimplify rather than
InstCombine, so the helper code should be available to other passes/analysis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326812 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AArch64] define isExtractSubvectorCheap
Sebastian Pop [Tue, 6 Mar 2018 16:54:55 +0000 (16:54 +0000)]
[AArch64] define isExtractSubvectorCheap

Following the ARM-neon backend, define isExtractSubvectorCheap to return true
when extracting low and high part of a neon register.

The patch disables a test in llvm/test/CodeGen/AArch64/arm64-ext.ll This
testcase is fragile in the sense that it requires a BUILD_VECTOR to "survive"
all DAG transforms until ISelLowering. The testcase is supposed to check that
AArch64TargetLowering::ReconstructShuffle() works, and for that we need a
BUILD_VECTOR in ISelLowering. As we now transform the BUILD_VECTOR earlier into
an VEXT + vector_shuffle, we don't have the BUILD_VECTOR pattern when we get to
ISelLowering. As there is no way to disable the combiner to only exercise the
code in ISelLowering, the patch disables the testcase.

Differential revision: https://reviews.llvm.org/D43973

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326811 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Asm] Fix another layering violation in assmebly macro dumping
Oliver Stannard [Tue, 6 Mar 2018 16:51:17 +0000 (16:51 +0000)]
[Asm] Fix another layering violation in assmebly macro dumping

AsmToken is in the MCParser library, so we can't use its dump function from
MCAsmMacro in the MC library. Instead, just print the string, which we don't
need the MCParser library for.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326810 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Pipeliner] Test commit: fixed spelling mistake in comments
Roorda, Jan-Willem [Tue, 6 Mar 2018 16:26:01 +0000 (16:26 +0000)]
[Pipeliner] Test commit: fixed spelling mistake in comments

Reviewers: bcahoon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D44152

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326808 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AMDGPU] Fix lowering OpenCL enqueue_kernel
Yaxun Liu [Tue, 6 Mar 2018 16:04:39 +0000 (16:04 +0000)]
[AMDGPU] Fix lowering OpenCL enqueue_kernel

One addrspacecast disappeared in clang emitted IR for
block invoke function due to adoption of the new
addr space mapping.

Differential Revision: https://reviews.llvm.org/D43785

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326806 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ARM][Asm] Fix layering violation introduced by r326795
Oliver Stannard [Tue, 6 Mar 2018 15:32:34 +0000 (15:32 +0000)]
[ARM][Asm] Fix layering violation introduced by r326795

The MCAsmMacro::dump function is in the MCParser library, so can't be called
from the MC library.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326804 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ARM]Decoding MSR with unpredictable destination register causes an assert
Simi Pallipurath [Tue, 6 Mar 2018 15:21:19 +0000 (15:21 +0000)]
[ARM]Decoding MSR with unpredictable destination register causes an assert

This patch handling:

    Enable parsing of raw encodings of system registers .
    Allows UNPREDICTABLE sysregs to be decoded to a raw number in the same way that disasslib does, rather than llvm crashing.
    Disassemble msr/mrs with unpredictable sysregs as SoftFail.
    Fix regression due to SoftFailing some encodings.

Patch by Chris Ryder

Differential revision:https://reviews.llvm.org/D43374

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326803 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agotest commit: fix typo in comment
Simi Pallipurath [Tue, 6 Mar 2018 14:35:23 +0000 (14:35 +0000)]
test commit: fix typo in comment

This is  a simple change to do the test commit and verify commit access.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326800 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Asm] Add debug printing for assembler macros
Oliver Stannard [Tue, 6 Mar 2018 14:07:01 +0000 (14:07 +0000)]
[Asm] Add debug printing for assembler macros

This adds some debug printing (gated behind the "asm-macros" debug flag) which
can help tracing complicated assembly macros.

Differential revision: https://reviews.llvm.org/D43937

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326795 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Asm] Refactor debug printing of AsmToken
Oliver Stannard [Tue, 6 Mar 2018 14:02:14 +0000 (14:02 +0000)]
[Asm] Refactor debug printing of AsmToken

* Move printing from llvm-mc to the AsmToken class, so that it can be used elsewhere.
* Add 5 cases which were missed: BigNum, Comment, HashDirective, Space and
  BackSlash, and remove the default case so that -Wswitch will catch this error
  in future.

This is almost NFC, except for the fact that llvm-mc can now print those 5
tokens in -as-lex mode.

Differential revision: https://reviews.llvm.org/D43936

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326794 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CallSiteSplitting] Do not crash when BB's terminator changes.
Florian Hahn [Tue, 6 Mar 2018 14:00:58 +0000 (14:00 +0000)]
[CallSiteSplitting] Do not crash when BB's terminator changes.

Change doCallSiteSplitting to iterate until we reach the terminator instruction.
tryToSplitCallSite can replace BB's terminator in case BB is a successor of
itself. Then IE will be invalidated and we also have to check the current
terminator.

Reviewers: junbuml, davidxl, davide, fhahn

Reviewed By: fhahn, junbuml

Differential Revision: https://reviews.llvm.org/D43824

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326793 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoTableGen: Add !foldl operation
Nicolai Haehnle [Tue, 6 Mar 2018 13:49:16 +0000 (13:49 +0000)]
TableGen: Add !foldl operation

Change-Id: I63d67bf6e0b315e2d3360e47e3b62c9517f38987

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326790 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoTableGen: Remove the ResolveFirst mechanism
Nicolai Haehnle [Tue, 6 Mar 2018 13:49:06 +0000 (13:49 +0000)]
TableGen: Remove the ResolveFirst mechanism

Summary:
It is no longer used.

Change-Id: I1e47267d1975d43ad43acd6347f54e958e3b6c86

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43757

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326789 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoTableGen: Delay instantiating inline anonymous records
Nicolai Haehnle [Tue, 6 Mar 2018 13:49:01 +0000 (13:49 +0000)]
TableGen: Delay instantiating inline anonymous records

Summary:
Only instantiate anonymous records once all variable references in template
arguments have been resolved. This allows patterns like the new test case,
which in practice can appear in expressions like:

  class IntrinsicTypeProfile<list<LLVMType> ty, int shift> {
    list<LLVMType> types =
      !listconcat(ty, [llvm_any_ty, LLVMMatchType<shift>]);
  }

  class FooIntrinsic<IntrinsicTypeProfile P, ...>
    : Intrinsic<..., P.types, ...>;

Without this change, the anonymous LLVMMatchType instantiation would
never get resolved.

Another consequence of this change is that anonymous inline
instantiations are uniqued via the folding set of the newly introduced
VarDefInit.

Change-Id: I7a7041a20e297cf98c9109b28d85e64e176c932a

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43756

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326788 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoTableGen: Move getNewAnonymousName into RecordKeeper
Nicolai Haehnle [Tue, 6 Mar 2018 13:48:54 +0000 (13:48 +0000)]
TableGen: Move getNewAnonymousName into RecordKeeper

Summary:
So that we will be able to generate new anonymous names more easily
outside the parser as well.

Change-Id: I28f396a7bdbc3ff0c665d466abbd3d31376e21b4

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43755

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326787 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoTableGen: Explicitly check whether a record has been resolved
Nicolai Haehnle [Tue, 6 Mar 2018 13:48:47 +0000 (13:48 +0000)]
TableGen: Explicitly check whether a record has been resolved

Summary:
There are various places where resolving and constant folds can
get stuck, especially around casts. We don't always signal an
error for those, because in many cases they can legitimately
occur without being an error in the "untaken branch" of an !if.

Change-Id: I3befc0e4234c8e6cc61190504702918c9f29ce5c

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43754

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326786 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoTableGen: Allow !cast of records, cleanup conversion machinery
Nicolai Haehnle [Tue, 6 Mar 2018 13:48:39 +0000 (13:48 +0000)]
TableGen: Allow !cast of records, cleanup conversion machinery

Summary:
Distinguish two relationships between types: is-a and convertible-to.
For example, a bit is not an int or vice versa, but they can be
converted into each other (with range checks that you can think of
as "dynamic": unlike other type checks, those range checks do not
happen during parsing, but only once the final values have been
established).

Actually converting initializers between types is subtle: even
when values of type A can be converted to type B (e.g. int into
string), it may not be possible to do so with a concrete initializer
(e.g., a VarInit that refers to a variable of type int cannot
be immediately converted to a string).

For this reason, distinguish between getCastTo and convertInitializerTo:
the latter implements the actual conversion when appropriate, while
the former will first try to do the actual conversion and fall back
to introducing a !cast operation so that the conversion will be
delayed until variable references have been resolved.

To make the approach of adding !cast operations to work, !cast needs
to fallback to convertInitializerTo when the special string <-> record
logic does not apply.

This enables casting records to a subclass, although that new
functionality is only truly useful together with !isa, which will be
added in a later change.

The test is removed because it uses !srl on a bit sequence,
which cannot really be supported consistently, but luckily
isn't used anywhere either.

Change-Id: I98168bf52649176654ed2ec61a29bdb29970cfe7

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43753

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326785 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoTableGen: Simplify BitsInit::resolveReferences
Nicolai Haehnle [Tue, 6 Mar 2018 13:48:30 +0000 (13:48 +0000)]
TableGen: Simplify BitsInit::resolveReferences

Summary:
No functional change intended. The removed code has a loop for
recursive resolving, which is superseded by the recursive
resolving done by the Resolver implementations.

Add a test case which was broken by an earlier version of this
change.

Change-Id: Ib208d037b77a8bbb725977f1388601fc984723d8

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43655

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326784 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoTableGen: Generalize record types to fix typeIsConvertibleTo et al.
Nicolai Haehnle [Tue, 6 Mar 2018 13:48:20 +0000 (13:48 +0000)]
TableGen: Generalize record types to fix typeIsConvertibleTo et al.

Summary:
Allow RecordRecTy to represent the type "subclass of N superclasses",
where N may be zero. Furthermore, generate RecordRecTy instances only
with actual classes in the list.

Keeping track of multiple superclasses is required to resolve the type
of a list correctly in some cases. The old code relied on the incorrect
behavior of typeIsConvertibleTo, and an earlier version of this change
relied on a modified ordering of superclasses (it was committed in
r325884 and then reverted because unfortunately some of clang-tblgen's
backends depend on the ordering).

Previously, the DefInit for each Record would have a RecordRecTy of
that Record as its type. Now, all defs with the same superclasses will
share the same type.

This allows us to be more consistent about type checks involving records:

- typeIsConvertibleTo actually requires the LHS to be a subtype of the
  RHS

- resolveTypes will return the least supertype of given record types in
  all cases

- different record types in the two branches of an !if are handled
  correctly

Add a test that used to be accepted without flagging the obvious type
error.

Change-Id: Ib366db1a4e6a079f1a0851e469b402cddae76714

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43680

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326783 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFixup for rL326769 (RegState::Debug is being truncated to a bool)
Bjorn Pettersson [Tue, 6 Mar 2018 13:23:28 +0000 (13:23 +0000)]
Fixup for rL326769 (RegState::Debug is being truncated to a bool)

I obviously messed up arguments to MachineOperand::CreateReg
in rL326769. This should make it work as intended.

Thanks to RKSimon for spotting this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326780 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CloneFunction] Support BB == PredBB in DuplicateInstructionsInSplit.
Florian Hahn [Tue, 6 Mar 2018 13:12:32 +0000 (13:12 +0000)]
[CloneFunction] Support BB == PredBB in DuplicateInstructionsInSplit.

In case PredBB == BB and StopAt == BB's terminator, StopAt != &*BI will
fail, because BB's terminator instruction gets replaced.

By using BB.getTerminator() we get the current terminator which we can use
to compare.

Reviewers: sanjoy, anna, reames

Reviewed By: anna

Differential Revision: https://reviews.llvm.org/D43822

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326779 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AVR] Remove the earlyclobber flag from LDDWRdYQ
Dylan McKay [Tue, 6 Mar 2018 11:20:25 +0000 (11:20 +0000)]
[AVR] Remove the earlyclobber flag from LDDWRdYQ

Before I started maintaining the AVR backend, this instruction
never originally used to have an earlyclobber flag.

Some time afterwards (years ago), I must've added it back in, not realising that it
was left out for a reason.

This pseudo instrction exists solely to work around a long standing bug
in the register allocator.

Before this commit, the LDDWRdYQ pseudo was not actually working around
any bug. With the earlyclobber flag removed again, the LDDWRdYQ pseudo
now correctly works around PR13375 again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326774 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[DebugInfo] Discard invalid DBG_VALUE instructions in LiveDebugVariables
Bjorn Pettersson [Tue, 6 Mar 2018 08:47:07 +0000 (08:47 +0000)]
[DebugInfo] Discard invalid DBG_VALUE instructions in LiveDebugVariables

Summary:
This is a workaround for pr36417
https://bugs.llvm.org/show_bug.cgi?id=36417

LiveDebugVariables will now verify that the DBG_VALUE instructions
are sane (prior to register allocation) by asking LIS if a virtual
register used in the DBG_VALUE is live (or dead def) in the slot
index before the DBG_VALUE. If it isn't sane the DBG_VALUE is
discarded.

One pass that was identified as introducing non-sane DBG_VALUE
instructtons, when analysing pr36417, was the DAG->DAG Instruction
Selection. It sometimes inserts DBG_VALUE instructions referring to
a virtual register that is defined later in the same basic block.
So it is a use before def kind of problem. The DBG_VALUE is
typically inserted in the beginning of a basic block when this
happens. The problem can be seen in the test case
test/DebugInfo/X86/dbg-value-inlined-parameter.ll

Reviewers: aprantl, rnk, probinson

Reviewed By: aprantl

Subscribers: vsk, davide, alexcrichton, Ka-Ka, eraman, llvm-commits, JDevlieghere

Differential Revision: https://reviews.llvm.org/D43956

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326769 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[WebAssebmly] Remove reloc ordering constraint
Sam Clegg [Tue, 6 Mar 2018 07:13:10 +0000 (07:13 +0000)]
[WebAssebmly] Remove reloc ordering constraint

The MC layer doesn't currently emit relocations in offset
order for the entire code section so this check was causing
failures on the wasm waterfall.

Perhaps we can re-instate this check if we divide the relocations
per-function, or add extra ordering the MC object writer.

Differential Revision: https://reviews.llvm.org/D44136

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326765 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Handle EAX being live when calling chkstk for x86_64
Martin Storsjo [Tue, 6 Mar 2018 06:00:13 +0000 (06:00 +0000)]
[X86] Handle EAX being live when calling chkstk for x86_64

EAX can turn out to be alive here, when shrink wrapping is done
(which is allowed when using dwarf exceptions, contrary to the
normal case with WinCFI).

This fixes PR36487.

Differential Revision: https://reviews.llvm.org/D43968

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326764 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoUpdated docs in CrashRecoveryContext.h
Serge Pavlov [Tue, 6 Mar 2018 04:00:30 +0000 (04:00 +0000)]
Updated docs in CrashRecoveryContext.h

Differential Revision: https://reviews.llvm.org/D43200

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326763 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert "[DWARFv5] Emit file 0 to the line table."
Paul Robinson [Tue, 6 Mar 2018 03:15:21 +0000 (03:15 +0000)]
Revert "[DWARFv5] Emit file 0 to the line table."
Caused an asan failure.

This reverts commit d54883f081186cdcce74e6f98cfc0438579ec019.
aka r326758

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326762 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[MergeICmp] Simplify how BCECmpBlock instructions are blacklisted
Xin Tong [Tue, 6 Mar 2018 02:24:02 +0000 (02:24 +0000)]
[MergeICmp] Simplify how BCECmpBlock instructions are blacklisted

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326761 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[MergeICmp] Fix printing. NFC
Xin Tong [Tue, 6 Mar 2018 02:04:57 +0000 (02:04 +0000)]
[MergeICmp] Fix printing. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326760 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[DWARFv5] Emit file 0 to the line table.
Paul Robinson [Tue, 6 Mar 2018 01:59:56 +0000 (01:59 +0000)]
[DWARFv5] Emit file 0 to the line table.

DWARF v5 specifies that the root file (also given in the DW_AT_name
attribute of the compilation unit DIE) should be emitted explicitly to
the line table's list of files.  This makes the line table more
independent of the .debug_info section.

Differential Revision: https://reviews.llvm.org/D44054

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326758 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoDisable llvm-opt-fuzzer/exec-options.ll on Windows, it is too flaky
Reid Kleckner [Mon, 5 Mar 2018 23:18:13 +0000 (23:18 +0000)]
Disable llvm-opt-fuzzer/exec-options.ll on Windows, it is too flaky

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326752 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] cvttpd2dq lowering has been supported for some time
Simon Pilgrim [Mon, 5 Mar 2018 23:00:39 +0000 (23:00 +0000)]
[X86] cvttpd2dq lowering has been supported for some time

Tests in vec_fp_to_int.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326751 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstSimplify] remove redundant folds
Sanjay Patel [Mon, 5 Mar 2018 22:46:48 +0000 (22:46 +0000)]
[InstSimplify] remove redundant folds

The 'hasOneUse' check is a giveaway that something's not right.
We never need to check that in InstSimplify because we don't
create new instructions here.

These are all handled as icmp simplifies which then trigger
existing select simplifies, so there's no need to duplicate
a composite fold of the two.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326750 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoGlobalISel: IRTranslate llvm.fabs.* intrinsic
Volkan Keles [Mon, 5 Mar 2018 22:31:55 +0000 (22:31 +0000)]
GlobalISel: IRTranslate llvm.fabs.* intrinsic

Summary:
Fabs is a common floating-point operation, especially for some expansions. This patch adds
a new generic opcode for llvm.fabs.* intrinsic in order to avoid building/matching this intrinsic.

Reviewers: qcolombet, aditya_nandakumar, dsanders, rovka

Reviewed By: aditya_nandakumar

Subscribers: kristof.beyls, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D43864

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326749 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[RewriteStatepoints] Fix stale parse points
Daniel Neilson [Mon, 5 Mar 2018 22:27:30 +0000 (22:27 +0000)]
[RewriteStatepoints] Fix stale parse points

Summary:
RewriteStatepointsForGC collects parse points for further processing.
During the collection if a callsite is found in an unreachable block
(DominatorTree::isReachableFromEntry()) then all unreachable blocks are
removed by removeUnreachableBlocks(). Some of the removed blocks could
have been reachable according to DominatorTree::isReachableFromEntry().
In this case the collected parse points became stale and resulted in a
crash when accessed.

The fix is to unconditionally canonicalize the IR to
removeUnreachableBlocks and then collect the parse points.

The added test crashes with the old version and passes with this patch.

Patch by Yevgeny Rouban!

Reviewed by: Anna

Differential Revision: https://reviews.llvm.org/D43929

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326748 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Add silvermont fp arithmetic cost model tests
Simon Pilgrim [Mon, 5 Mar 2018 22:13:22 +0000 (22:13 +0000)]
[X86] Add silvermont fp arithmetic cost model tests

Add silvermont to existing high coverage tests instead of repeating in slm-arith-costs.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326747 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AMDGPU] Remove unused AMDOpenCL triple environment
Tony Tye [Mon, 5 Mar 2018 21:39:41 +0000 (21:39 +0000)]
[AMDGPU] Remove unused AMDOpenCL triple environment

Differential Revision: https://reviews.llvm.org/D43895

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326745 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AVR] Fix the test suite after r326500.
Dylan McKay [Mon, 5 Mar 2018 20:56:25 +0000 (20:56 +0000)]
[AVR] Fix the test suite after r326500.

r326500 subtly changed the way the instructions are printed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326742 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SLP] Additional tests for stores vectorization, NFC.
Alexey Bataev [Mon, 5 Mar 2018 20:20:12 +0000 (20:20 +0000)]
[SLP] Additional tests for stores vectorization, NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326740 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRe-commit: Make STATISTIC() values available programmatically
Daniel Sanders [Mon, 5 Mar 2018 19:38:16 +0000 (19:38 +0000)]
Re-commit: Make STATISTIC() values available programmatically

Summary:
It can be useful for tools to be able to retrieve the values of variables
declared via STATISTIC() directly without having to emit them and parse
them back. Use cases include:
* Needing to report specific statistics to a test harness
* Wanting to post-process statistics. For example, to produce a percentage of
  functions that were fully selected by GlobalISel

Make this possible by adding llvm::GetStatistics() which returns an
iterator_range that can be used to inspect the statistics that have been
touched during execution. When statistics are disabled (NDEBUG and not
LLVM_ENABLE_STATISTICS) this method will return an empty range.

This patch doesn't address the effect of multiple compilations within the same
process. In such situations, the statistics will be cumulative for all
compilations up to the GetStatistics() call.

Reviewers: qcolombet, rtereshin, aditya_nandakumar, bogner

Reviewed By: rtereshin, bogner

Subscribers: llvm-commits, mgorny

Differential Revision: https://reviews.llvm.org/D43901

This re-commit fixes a missing include of <vector> which it seems clang didn't
mind but G++ and MSVC objected to. It seems that, clang was ok with std::vector
only being forward declared at the point of use since it was fully defined
eventually but G++/MSVC both rejected it at the point of use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326738 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoOn Windows we need to be able to process response files with Windows-style
Dmitry Mikulin [Mon, 5 Mar 2018 19:34:33 +0000 (19:34 +0000)]
On Windows we need to be able to process response files with Windows-style
path names.

Differential Revision: https://reviews.llvm.org/D43988

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326737 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[PowerPC] Do not emit record-form rotates when record-form andi suffices
Nemanja Ivanovic [Mon, 5 Mar 2018 19:27:16 +0000 (19:27 +0000)]
[PowerPC] Do not emit record-form rotates when record-form andi suffices

Up until Power9, the performance profile for rlwinm., rldicl. and andi. looked
more or less equivalent. However with Power9, the rotates are still 2-way
cracked whereas the and-immediate is not.

This patch just ensures that we don't emit record-form rotates when an andi.
is adequate.

As first pointed out by Carrot in https://bugs.llvm.org/show_bug.cgi?id=30833
(this patch is a fix for that PR).

Differential Revision: https://reviews.llvm.org/D43977

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326736 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[x86] auto-generate full checks for fabs tests
Sanjay Patel [Mon, 5 Mar 2018 19:11:20 +0000 (19:11 +0000)]
[x86] auto-generate full checks for fabs tests

Also, change the x86-64 test to optimized and remove the
unnecessary platform specification from the RUN lines..

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326735 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoOn Windows expansion of regex file name patterns is the responsibility of each
Dmitry Mikulin [Mon, 5 Mar 2018 18:54:56 +0000 (18:54 +0000)]
On Windows expansion of regex file name patterns is the responsibility of each
tool. Fix ar to do that.

Differential Revision: https://reviews.llvm.org/D43987

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326734 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix an unused variable warning introduced by rr326703. NFC
Eric Liu [Mon, 5 Mar 2018 18:36:39 +0000 (18:36 +0000)]
Fix an unused variable warning introduced by rr326703. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326732 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-pdbdump] Dump restrict type qualifier
Aaron Smith [Mon, 5 Mar 2018 18:29:43 +0000 (18:29 +0000)]
[llvm-pdbdump] Dump restrict type qualifier

Reviewers: zturner, llvm-commits, rnk

Reviewed By: zturner

Subscribers: majnemer

Differential Revision: https://reviews.llvm.org/D43639

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326731 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] Don't blow up in foldICmpWithCastAndCast on vector icmp instructions.
Daniel Neilson [Mon, 5 Mar 2018 18:05:51 +0000 (18:05 +0000)]
[InstCombine] Don't blow up in foldICmpWithCastAndCast on vector icmp instructions.

Summary:
Presently, InstCombiner::foldICmpWithCastAndCast() implicitly assumes that it is
only invoked with icmp instructions of integer type. If that assumption is broken,
and it is called with an icmp of vector type, then it fails (asserts/crashes).

This patch addresses the deficiency. It allows it to simplify
icmp (ptrtoint x), (ptrtoint/c) of vector type into a compare of the inputs,
much as is done when the type is integer.

Reviewers: apilipenko, fedor.sergeev, mkazantsev, anna

Reviewed By: anna

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D44063

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326730 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] Add constant vector support to getMinimumFPType for visitFPTrunc.
Craig Topper [Mon, 5 Mar 2018 18:04:12 +0000 (18:04 +0000)]
[InstCombine] Add constant vector support to getMinimumFPType for visitFPTrunc.

This patch teaches getMinimumFPType to support shrinking a vector of ConstantFPs. This should improve our ability to combine vector fptrunc with fp binops.

Differential Revision: https://reviews.llvm.org/D43774

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326729 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert r326723: Make STATISTIC() values available programmatically
Daniel Sanders [Mon, 5 Mar 2018 17:52:43 +0000 (17:52 +0000)]
Revert r326723: Make STATISTIC() values available programmatically

Despite building cleanly on my machine in three separate configs, it's failing on pretty much all bots due to missing includes among other things. Investigating.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326726 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AArch64] Harden test case
Evandro Menezes [Mon, 5 Mar 2018 17:42:18 +0000 (17:42 +0000)]
[AArch64] Harden test case

NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326724 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoMake STATISTIC() values available programmatically
Daniel Sanders [Mon, 5 Mar 2018 17:41:45 +0000 (17:41 +0000)]
Make STATISTIC() values available programmatically

Summary:
It can be useful for tools to be able to retrieve the values of variables
declared via STATISTIC() directly without having to emit them and parse
them back. Use cases include:
* Needing to report specific statistics to a test harness
* Wanting to post-process statistics. For example, to produce a percentage of
  functions that were fully selected by GlobalISel

Make this possible by adding llvm::GetStatistics() which returns an
iterator_range that can be used to inspect the statistics that have been
touched during execution. When statistics are disabled (NDEBUG and not
LLVM_ENABLE_STATISTICS) this method will return an empty range.

This patch doesn't address the effect of multiple compilations within the same
process. In such situations, the statistics will be cumulative for all
compilations up to the GetStatistics() call.

Reviewers: qcolombet, rtereshin, aditya_nandakumar, bogner

Reviewed By: rtereshin, bogner

Subscribers: llvm-commits, mgorny

Differential Revision: https://reviews.llvm.org/D43901

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326723 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agofix PR36582
Sebastian Pop [Mon, 5 Mar 2018 17:35:49 +0000 (17:35 +0000)]
fix PR36582

The error occurs when reading i16 elements (as in the testcase) from a v8i8
with a pattern of <0,2,4,6>. As all the data in the vector is accessed, the
operation is not a VUZP. The patch stops the pattern recognition of VUZP when
EXTRACT_VECTOR_ELT has a different element type than BUILD_VECTOR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326722 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[IPSCCP] Add getCompare which returns either true, false, undef or null.
Florian Hahn [Mon, 5 Mar 2018 17:33:50 +0000 (17:33 +0000)]
[IPSCCP] Add getCompare which returns either true, false, undef or null.

getCompare returns true, false or undef constants if the comparison can
be evaluated, or nullptr if it cannot. This is in line with what
ConstantExpr::getCompare returns. It also allows us to use
ConstantExpr::getCompare for comparing constants.

Reviewers: davide, mssimpso, dberlin, anna

Reviewed By: davide

Differential Revision: https://reviews.llvm.org/D43761

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326720 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AArch64] Improve code generation of constant vectors
Evandro Menezes [Mon, 5 Mar 2018 17:02:47 +0000 (17:02 +0000)]
[AArch64] Improve code generation of constant vectors

Use the whole gammut of constant immediates available to set up a vector.
Instead of using, for example, `mov w0, #0xffff; dup v0.4s, w0`, which
transfers between register files, use the more efficient `movi v0.4s, #-1`
instead.  Not limited to just a few values, but any immediate value that can
be encoded by all the variants of `FMOV`, `MOVI`, `MVNI`, thus eliminating
the need to there be patterns to optimize special cases.

Differential revision: https://reviews.llvm.org/D42133

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326718 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[MachineScheduler] Dump SUnits before calling SchedImpl->initialize()
Jonas Paulsson [Mon, 5 Mar 2018 16:31:49 +0000 (16:31 +0000)]
[MachineScheduler] Dump SUnits before calling SchedImpl->initialize()

This is a NFC simple patch that changes the DEBUG dumping in the
MachineScheduler so that the dumping of the built SUnits is done before the
SchedImpl->initialize() is called.

This is better on SystemZ, since it has a strategy that does some dumping at
the start of the region, and it is not possible to easily read it if it is
output above a long list of SU.

Review: Javed Absar
https://reviews.llvm.org/D44089

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326716 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAMDGPU/GlobalISel: Add InstrMapping for G_EXTRACT
Matt Arsenault [Mon, 5 Mar 2018 16:25:18 +0000 (16:25 +0000)]
AMDGPU/GlobalISel: Add InstrMapping for G_EXTRACT

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326715 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAMDGPU/GlobalISel: Make some G_EXTRACTs legal
Matt Arsenault [Mon, 5 Mar 2018 16:25:15 +0000 (16:25 +0000)]
AMDGPU/GlobalISel: Make some G_EXTRACTs legal

As far as I can tell legalization of weird sizes for the
output type isn't implemented.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326714 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAMDGPU: Fix build warning about override
Matt Arsenault [Mon, 5 Mar 2018 16:25:10 +0000 (16:25 +0000)]
AMDGPU: Fix build warning about override

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326713 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CVP] fix formatting; NFC
Sanjay Patel [Mon, 5 Mar 2018 16:08:34 +0000 (16:08 +0000)]
[CVP] fix formatting; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326711 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFuzzer: remove temporary files after we're done with them.
Tim Northover [Mon, 5 Mar 2018 15:49:00 +0000 (15:49 +0000)]
Fuzzer: remove temporary files after we're done with them.

These were just copies of the relevant fuzzer binary with (presumably)
meaningful suffixes, but accounted for more than 10% of my build
directory (> 8GB). Hard drive space is cheap, but not that cheap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326710 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoTableGen: Resolve all template args simultaneously in ResolveMulticlassDefARgs
Nicolai Haehnle [Mon, 5 Mar 2018 15:21:19 +0000 (15:21 +0000)]
TableGen: Resolve all template args simultaneously in ResolveMulticlassDefARgs

Summary:
Use the new resolver interface more explicitly, and avoid traversing
all the initializers multiple times.

Change-Id: I679e86988b309d19f25e6cca8b0b14ea150198a6

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43654

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326708 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoTableGen: Resolve all template args simultaneously in AddSubMultiClass
Nicolai Haehnle [Mon, 5 Mar 2018 15:21:15 +0000 (15:21 +0000)]
TableGen: Resolve all template args simultaneously in AddSubMultiClass

Summary:
Use the new resolver interface more explicitly, and avoid traversing
all the initializers multiple times.

Change-Id: Ia4dcc6d42dd8b65e6079d318c6a202f36f320fee

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43653

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326707 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoTableGen: Resolve all template args simultaneously in AddSubClass
Nicolai Haehnle [Mon, 5 Mar 2018 15:21:11 +0000 (15:21 +0000)]
TableGen: Resolve all template args simultaneously in AddSubClass

Summary:
Use the new resolver interface more explicitly, and avoid traversing
all the initializers multiple times.

Add a test case for a pattern that was broken by an earlier version
of this change.

An additional change is that we now remove *all* template arguments
after resolving them.

Change-Id: I86c828c8cc84c18b052dfe0f64c0d5cbf3c4e13c

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43652

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326706 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoTableGen: Reimplement !foreach using the resolving mechanism
Nicolai Haehnle [Mon, 5 Mar 2018 15:21:04 +0000 (15:21 +0000)]
TableGen: Reimplement !foreach using the resolving mechanism

Summary:
This changes the syntax of !foreach so that the first "parameter" is
a new syntactic variable: !foreach(x, lst, expr) will define the
variable x within the scope of expr, and evaluation of the !foreach
will substitute elements of the given list (or dag) for x in expr.

Aside from leading to a nicer syntax, this allows more complex
expressions where x is deeply nested, or even constant expressions
in which x does not occur at all.

!foreach is currently not actually used anywhere in trunk, but I
plan to use it in the AMDGPU backend. If out-of-tree targets are
using it, they can adjust to the new syntax very easily.

Change-Id: Ib966694d8ab6542279d6bc358b6f4d767945a805

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits, tpr

Differential Revision: https://reviews.llvm.org/D43651

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326705 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoTableGen: Introduce an abstract variable resolver interface
Nicolai Haehnle [Mon, 5 Mar 2018 15:20:51 +0000 (15:20 +0000)]
TableGen: Introduce an abstract variable resolver interface

Summary:
The intention is to allow us to more easily restructure how resolving is
done, e.g. resolving multiple variables simultaneously, or using the
resolving mechanism to implement !foreach.

Change-Id: I4b976b54a32e240ad4f562f7eb86a4d663a20ea8

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43564

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326704 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoPass Divergence Analysis data to Selection DAG to drive divergence
Alexander Timofeev [Mon, 5 Mar 2018 15:12:21 +0000 (15:12 +0000)]
Pass Divergence Analysis data to Selection DAG to drive divergence
dependent instruction selection.

Differential revision: https://reviews.llvm.org/D35267

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326703 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Power9] Add more missing instructions to the Power 9 scheduler
Stefan Pintilie [Mon, 5 Mar 2018 14:34:59 +0000 (14:34 +0000)]
[Power9] Add more missing instructions to the Power 9 scheduler

Adding more instructions using InstRW so that we can move away from ItinRW
and ultimately have a complete Power 9 scheduler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326701 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoTableGen: Allow NAME in template arguments in defm in multiclass
Nicolai Haehnle [Mon, 5 Mar 2018 14:01:38 +0000 (14:01 +0000)]
TableGen: Allow NAME in template arguments in defm in multiclass

Summary:
NAME has already worked for def in a multiclass, since the (protoype)
record including its NAME variable is created before parsing the
superclasses. Since defm's do not have an associated single record,
support for NAME has to be implemented differently here.

Original test cases provided by Artem Belevich (tra)

Change-Id: I933b74f328c0ff202e7dc23a35b78f3505760cc9

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43656

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326700 91177308-0d34-0410-b5e6-96231b3b80d8