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John Brawn [Tue, 3 Oct 2017 13:08:22 +0000 (13:08 +0000)]
[CGP] Make optimizeMemoryInst capable of handling multiple AddrModes
Currently optimizeMemoryInst requires that all of the AddrModes it sees are
identical. This patch makes it capable of tracking multiple AddrModes, so long
as they differ in at most one field.
This patch does nothing by itself, but later patches will make use of it to
insert or reuse phi or select instructions for the differing fields.
Differential Revision: https://reviews.llvm.org/D38278
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314795
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John Brawn [Tue, 3 Oct 2017 13:04:15 +0000 (13:04 +0000)]
[CGP] In optimizeMemoryInst handle select similarly to phi
This lets us optimize away selects that perform the same address computation in
two different ways and is also the first step towards being able to handle
selects between two different, but compatible, address computations.
Differential Revision: https://reviews.llvm.org/D38242
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314794
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Oliver Stannard [Tue, 3 Oct 2017 12:45:18 +0000 (12:45 +0000)]
[ARM, Asm] Fix ubsan failure caused by out-of-range enum value
In this code, we use ~0U as a sentinel value for any operand class that doesn't
have a user-friendly error message, but this value isn't in range of the
MatchClassKind enum, so we need to ensure it does not get passed to isSubclass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314793
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Simon Pilgrim [Tue, 3 Oct 2017 12:41:39 +0000 (12:41 +0000)]
[X86][SSE] Add support for decoding PACKSS/PACKUS shuffles masks with UNDEF
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314792
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Oliver Stannard [Tue, 3 Oct 2017 12:28:28 +0000 (12:28 +0000)]
[ARM, Asm] Remove dead code causing MSan failure.
r314779 caused ErrorInfo to be red uninitialised, but also made this code dead,
so it can just be removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314791
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Simon Pilgrim [Tue, 3 Oct 2017 12:01:31 +0000 (12:01 +0000)]
[X86][SSE] Add support for lowering shuffles to PACKSS/PACKUS
If the upper bits of a truncation shuffle patterns have at least the minimum number of sign/zero bits on their inputs then we can safely use PACKSS/PACKUS as shuffles.
Partial fix for https://bugs.llvm.org/show_bug.cgi?id=34773
Differential Revision: https://reviews.llvm.org/D38472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314788
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Evgeny Astigeevich [Tue, 3 Oct 2017 12:00:40 +0000 (12:00 +0000)]
[InlineCost, NFC] Extract code dealing with inbounds GEPs from visitGetElementPtr into a function
The code responsible for analysis of inbounds GEPs is extracted into a separate
function: CallAnalyzer::canFoldInboundsGEP. With the patch SROA
enabling/disabling code is localized at one place instead of spreading across
the code of CallAnalyzer::visitGetElementPtr.
Differential Revision: https://reviews.llvm.org/D38233
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314787
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Sam Clegg [Tue, 3 Oct 2017 11:20:28 +0000 (11:20 +0000)]
[WebAssembly] MC: Support for init_array and fini_array
Differential Revision: https://reviews.llvm.org/D37757
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314783
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Sean Eveson [Tue, 3 Oct 2017 11:05:28 +0000 (11:05 +0000)]
[llvm-cov] Hide files with no coverage from the index when filtering by name
Differential Revision: https://reviews.llvm.org/D38457
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314782
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Bjorn Pettersson [Tue, 3 Oct 2017 11:03:02 +0000 (11:03 +0000)]
[DebugInfo] Handle endianness when moving debug info for split integer values (reapplied)
Summary:
Take the target's endianness into account when splitting the
debug information in DAGTypeLegalizer::SetExpandedInteger.
This patch fixes so that, for big-endian targets, the fragment
expression corresponding to the high part of a split integer
value is placed at offset 0, in order to correctly represent
the memory address order.
I have attached a PPC32 reproducer where the resulting DWARF
pieces for a 64-bit integer were incorrectly reversed.
Original patch was reverted due to using -stop-after=isel in
the test case (but that is only working when AMDGPU target
is included in the llc build). The test case has now been
updated to use -stop-before=expand-isel-pseudos instead.
Patch by: dstenb
Reviewers: JDevlieghere, aprantl, dblaikie
Reviewed By: JDevlieghere, aprantl, dblaikie
Subscribers: nemanjai
Differential Revision: https://reviews.llvm.org/D38172
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314781
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Oliver Stannard [Tue, 3 Oct 2017 10:26:11 +0000 (10:26 +0000)]
[ARM] Use new assembler diags for ARM
This converts the ARM AsmParser to use the new assembly matcher error
reporting mechanism, which allows errors to be reported for multiple
instruction encodings when it is ambiguous which one the user intended
to use.
By itself this doesn't improve many error messages, because we don't have
diagnostic text for most operand types, but as we add that then this will allow
more of those diagnostic strings to be used when they are relevant.
Differential revision: https://reviews.llvm.org/D31530
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314779
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Simon Pilgrim [Tue, 3 Oct 2017 10:01:02 +0000 (10:01 +0000)]
Remove unused variable. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314778
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Simon Pilgrim [Tue, 3 Oct 2017 09:54:03 +0000 (09:54 +0000)]
[X86][SSE] Add support for shuffle combining from PACKSS/PACKUS
Mentioned in D38472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314777
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Simon Pilgrim [Tue, 3 Oct 2017 09:41:00 +0000 (09:41 +0000)]
[X86][SSE] Add support for PACKSS/PACKUS constant folding
Pulled out of D38472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314776
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Javed Absar [Tue, 3 Oct 2017 09:35:04 +0000 (09:35 +0000)]
[MiSched] - Simplify ProcResEntry access
Reviewed by: @MatzeB
Differential Revision: https://reviews.llvm.org/D38447
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314775
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Oliver Stannard [Tue, 3 Oct 2017 09:33:12 +0000 (09:33 +0000)]
[Assembler] Report multiple near misses for invalid instructions
The current table-generated assembly instruction matcher returns a
64-bit error code when matching fails. Since multiple instruction
encodings with the same mnemonic can fail for different reasons, it uses
some heuristics to decide which message is important.
This heuristic does not work well for targets that have many encodings
with the same mnemonic but different operands, or which have different
versions of instructions controlled by subtarget features, as it is hard
to know which encoding the user was intending to use.
Instead of trying to improve the heuristic in the table-generated
matcher, this patch changes it to report a list of near-miss encodings.
This list contains an entry for each encoding with the correct mnemonic,
but with exactly one thing preventing it from being valid. This thing
could be a single invalid operand, a missing target feature or a failed
target-specific validation function.
The target-specific assembly parser can then report an error message
giving multiple options for instruction variants that the user may have
been trying to use. For example, I am working on a patch to use this for
ARM, which can give this error for an invalid instruction for ARMv6-M:
<stdin>:8:3: error: invalid instruction, multiple near-miss encodings found
adds r0, r1, #0x8
^
<stdin>:8:3: note: for one encoding: instruction requires: thumb2
adds r0, r1, #0x8
^
<stdin>:8:16: note: for one encoding: expected an integer in range [0, 7]
adds r0, r1, #0x8
^
<stdin>:8:16: note: for one encoding: expected a register in range [r0, r7]
adds r0, r1, #0x8
^
This also allows the target-specific assembly parser to apply its own
heuristics to suppress some errors. For example, the error "instruction
requires: arm-mode" is never going to be useful when targeting an
M-profile architecture (which does not have ARM mode).
This patch just adds the target-independent mechanism for doing this,
all targets still use the old mechanism. I've added a bit in the
AsmParser tablegen class to allow targets to switch to this new
mechanism. To use this, the target-specific assembly parser will have to
be modified for the change in signature of MatchInstructionImpl, and to
report errors based on the list of near-misses.
Differential revision: https://reviews.llvm.org/D27620
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314774
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Sjoerd Meijer [Tue, 3 Oct 2017 08:54:15 +0000 (08:54 +0000)]
ISel type legalization: add debug messages. NFCI.
This adds some more debug messages to the type legalizer and functions
like PromoteNode, ExpandNode, ExpandLibCall in an attempt to make
the debug messages a little bit more informative and useful.
Differential Revision: https://reviews.llvm.org/D38450
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314773
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Alex Bradbury [Tue, 3 Oct 2017 08:41:59 +0000 (08:41 +0000)]
[llvm-readobj][RISCV] Pretty-print RISCV e_flags
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314772
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Alex Bradbury [Tue, 3 Oct 2017 08:03:14 +0000 (08:03 +0000)]
[RISCV] Add missed test case for r314770
Differential Revision: https://reviews.llvm.org/D38311
Patch by https://reviews.llvm.org/D38311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314771
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Alex Bradbury [Tue, 3 Oct 2017 08:00:47 +0000 (08:00 +0000)]
[RISCV] Parse RISC-V eflags in ObjectYAML
Differential Revision: https://reviews.llvm.org/D38311
Patch by Chih-Mao Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314770
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Hiroshi Inoue [Tue, 3 Oct 2017 07:28:58 +0000 (07:28 +0000)]
[trivial] fix format, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314769
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Shoaib Meenai [Tue, 3 Oct 2017 06:35:55 +0000 (06:35 +0000)]
[ObjectYAML] Handle SHF_COMPRESSED
This was previously being silently dropped by obj2yaml and caused
parsing errors with yaml2obj.
Differential Revision: https://reviews.llvm.org/D38490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314768
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Martin Storsjo [Tue, 3 Oct 2017 06:29:58 +0000 (06:29 +0000)]
[X86] Provide the LSDA pointer with RIP relative addressing if necessary
This makes sure the LSDA pointer isn't truncated to 32 bit.
Make LowerINTRINSIC_WO_CHAIN a member function instead of a static
function, so that it can use the getGlobalWrapperKind method.
This solves the second half of the issues mentioned in PR34720.
Differential Revision: https://reviews.llvm.org/D38343
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314767
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Mikael Holmen [Tue, 3 Oct 2017 06:03:49 +0000 (06:03 +0000)]
[Lint] Avoid failed assertion by fetching the proper pointer type
Summary:
When checking if a constant expression is a noop cast we fetched the
IntPtrType by doing DL->getIntPtrType(V->getType())). However, there can
be cases where V doesn't return a pointer, and then getIntPtrType()
triggers an assertion.
Now we pass DataLayout to isNoopCast so the method itself can determine
what the IntPtrType is.
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D37894
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314763
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Craig Topper [Tue, 3 Oct 2017 05:31:07 +0000 (05:31 +0000)]
[InstCombine] Change a bunch of methods to take APInts by reference instead of pointer.
This allows us to remove a bunch of dereferences and only have a few dereferences at the call sites.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314762
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Craig Topper [Tue, 3 Oct 2017 04:55:04 +0000 (04:55 +0000)]
[InstCombine] Replace an equality compare of two APInt pointers with a compare of the APInts themselves.
Apparently this works by virtue of the fact that the pointers are pointers to the APInts stored inside of the ConstantInt objects. But I really don't think we should be relying on that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314761
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Quentin Colombet [Tue, 3 Oct 2017 04:53:56 +0000 (04:53 +0000)]
[Legalizer] Add support for G_OR NarrowScalar.
Legalize bitwise OR:
A = BinOp<Ty> B, C
into:
B1, ..., BN = G_UNMERGE_VALUES B
C1, ..., CN = G_UNMERGE_VALUES C
A1 = BinOp<Ty/N> B1, C2
...
AN = BinOp<Ty/N> BN, CN
A = G_MERGE_VALUES A1, ..., AN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314760
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Craig Topper [Tue, 3 Oct 2017 03:47:34 +0000 (03:47 +0000)]
[X86] Add AVX512 check lines to the cost model truncate test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314758
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Rui Ueyama [Tue, 3 Oct 2017 03:09:05 +0000 (03:09 +0000)]
Rewrite a function so that it doesn't use pointers to pointers. NFC.
Previous code was a bit puzzling because of its use of pointers.
In this patch, we pass a vector and its offsets, instead of pointers to
vector elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314756
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Peter Collingbourne [Tue, 3 Oct 2017 00:44:21 +0000 (00:44 +0000)]
LTO: Improve error reporting when adding a cache entry.
Move error handling code next to the code that returns the error,
and change the error message in order to distinguish it from a similar
error message elsewhere in this file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314745
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Daniel Berlin [Tue, 3 Oct 2017 00:26:21 +0000 (00:26 +0000)]
SparseSolver: Rename getOrInitValueState to getValueState, matching what SCCP calls it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314744
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Matt Arsenault [Tue, 3 Oct 2017 00:06:41 +0000 (00:06 +0000)]
AMDGPU: Remove global isGCN predicates
These are problematic because they apply to everything,
and can easily clobber whatever more specific predicate
you are trying to add to a function.
Currently instructions use SubtargetPredicate/PredicateControl
to apply this to patterns applied to an instruction definition,
but not to free standing Pats. Add a wrapper around Pat
so the special PredicateControls requirements can be appended
to the final predicate list like how Mips does it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314742
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Haicheng Wu [Mon, 2 Oct 2017 23:43:52 +0000 (23:43 +0000)]
[InstSimplify] teach SimplifySelectInst() to fold more vector selects
Call ConstantFoldSelectInstruction() to fold cases like below
select <2 x i1><i1 true, i1 false>, <2 x i8> <i8 0, i8 1>, <2 x i8> <i8 2, i8 3>
All operands are constants and the condition has mixed true and false conditions.
Differential Revision: https://reviews.llvm.org/D38369
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314741
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Davide Italiano [Mon, 2 Oct 2017 23:39:20 +0000 (23:39 +0000)]
[PassManager] Retire cl::opt that have been set for a while. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314740
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Tim Shen [Mon, 2 Oct 2017 23:20:06 +0000 (23:20 +0000)]
[PowerPC] Revert r314666.
See https://reviews.llvm.org/D38172.
I tried to XFAIL it, but sometimes XPASS triggers the bot. Simply
revert it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314739
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Daniel Berlin [Mon, 2 Oct 2017 22:49:49 +0000 (22:49 +0000)]
Template the sparse propagation solver instead of using void pointers
Summary:
This avoids using void * as the type of the lattice value and ugly casts needed to make that happen.
(If folks want to use references, etc, they can use a reference_wrapper).
Reviewers: davide, mssimpso
Subscribers: sanjoy, llvm-commits
Differential Revision: https://reviews.llvm.org/D38476
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314734
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Tim Shen [Mon, 2 Oct 2017 22:40:32 +0000 (22:40 +0000)]
[PowerPC] Temporarily disable the test introduced by r314666
See https://reviews.llvm.org/D38172 for details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314732
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Geoff Berry [Mon, 2 Oct 2017 22:01:37 +0000 (22:01 +0000)]
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
Issues addressed since original review:
- Avoid bug in regalloc greedy/machine verifier when forwarding to use
in an instruction that re-defines the same virtual register.
- Fixed bug when forwarding to use in EarlyClobber instruction slot.
- Fixed incorrect forwarding to register definitions that showed up in
explicit_uses() iterator (e.g. in INLINEASM).
- Moved removal of dead instructions found by
LiveIntervals::shrinkToUses() outside of loop iterating over
instructions to avoid instructions being deleted while pointed to by
iterator.
- Fixed ARMLoadStoreOptimizer bug exposed by this change in r311907.
- The pass no longer forwards COPYs to physical register uses, since
doing so can break code that implicitly relies on the physical
register number of the use.
- The pass no longer forwards COPYs to undef uses, since doing so
can break the machine verifier by creating LiveRanges that don't
end on a use (since the undef operand is not considered a use).
[MachineCopyPropagation] Extend pass to do COPY source forwarding
This change extends MachineCopyPropagation to do COPY source forwarding.
This change also extends the MachineCopyPropagation pass to be able to
be run during register allocation, after physical registers have been
assigned, but before the virtual registers have been re-written, which
allows it to remove virtual register COPY LiveIntervals that become dead
through the forwarding of all of their uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314729
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Michael Liao [Mon, 2 Oct 2017 21:54:38 +0000 (21:54 +0000)]
Remove trailing whitespace to trigger re-cmaking
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314728
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Craig Topper [Mon, 2 Oct 2017 21:46:58 +0000 (21:46 +0000)]
[X86] Run dos2unix on two disassembler tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314727
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Amjad Aboud [Mon, 2 Oct 2017 21:46:37 +0000 (21:46 +0000)]
[X86][NFC] Add X86CmovConverterPass to the pass registry.
Differential Revision: https://reviews.llvm.org/D38355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314726
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Adrian Prantl [Mon, 2 Oct 2017 21:21:09 +0000 (21:21 +0000)]
llvm-dwarfdump: support the --ignore-case option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314723
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Michael Liao [Mon, 2 Oct 2017 21:00:52 +0000 (21:00 +0000)]
Remove dead file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314720
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Konstantin Zhuravlyov [Mon, 2 Oct 2017 20:49:58 +0000 (20:49 +0000)]
Add ELFOSABI_FIRST_ARCH, ELFOSABI_LAST_ARCH and start using those in llvm-readobj
Differential Revision: https://reviews.llvm.org/D38418
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314717
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Matt Arsenault [Mon, 2 Oct 2017 20:31:18 +0000 (20:31 +0000)]
AMDGPU: Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314715
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Matt Arsenault [Mon, 2 Oct 2017 20:31:16 +0000 (20:31 +0000)]
AMDGPU: Fix potentially incorrectly matching check lines
These check lines are supposed to make sure the new d16
load instructions aren't used, but the expected instruction
name is a prefix of the incorrect instruction name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314714
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Sanjay Patel [Mon, 2 Oct 2017 20:16:59 +0000 (20:16 +0000)]
[InstCombine] auto-generate complete checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314712
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Sanjay Patel [Mon, 2 Oct 2017 20:07:15 +0000 (20:07 +0000)]
[InstCombine] add icmp (shr X, Y), 0 test; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314710
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Hans Wennborg [Mon, 2 Oct 2017 19:48:28 +0000 (19:48 +0000)]
Fix two header comments. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314709
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Walter Lee [Mon, 2 Oct 2017 18:50:48 +0000 (18:50 +0000)]
Add support for Myriad ma2x8x series of CPUs
Summary: Also add support for some older Myriad CPUs that were missing.
Reviewers: jyknight
Subscribers: fedor.sergeev
Differential Revision: https://reviews.llvm.org/D37552
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314705
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Adrian Prantl [Mon, 2 Oct 2017 18:31:29 +0000 (18:31 +0000)]
Move the stripping of invalid debug info from the Verifier to AutoUpgrade.
This came out of a recent discussion on llvm-dev
(https://reviews.llvm.org/D38042). Currently the Verifier will strip
the debug info metadata from a module if it finds the dbeug info to be
malformed. This feature is very valuable since it allows us to improve
the Verifier by making it stricter without breaking bcompatibility,
but arguable the Verifier pass should not be modifying the IR. This
patch moves the stripping of broken debug info into AutoUpgrade
(UpgradeDebugInfo to be precise), which is a much better location for
this since the stripping of malformed (i.e., produced by older, buggy
versions of Clang) is a (harsh) form of AutoUpgrade.
This change is mostly NFC in nature, the one big difference is the
behavior when LLVM module passes are introducing malformed debug
info. Prior to this patch, a NoAsserts build would have printed a
warning and stripped the debug info, after this patch the Verifier
will report a fatal error. I believe this behavior is actually more
desirable anyway.
Differential Revision: https://reviews.llvm.org/D38184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314699
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Sanjay Patel [Mon, 2 Oct 2017 18:26:44 +0000 (18:26 +0000)]
[InstCombine] remove one-use restriction for icmp (shr exact X, C1), C2 --> icmp X, (C2<<C1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314698
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Sanjay Patel [Mon, 2 Oct 2017 18:16:17 +0000 (18:16 +0000)]
[InstCombine] add icmp (lshr X, C1), C2 test; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314696
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Dehao Chen [Mon, 2 Oct 2017 18:13:14 +0000 (18:13 +0000)]
Update getMergedLocation to check the instruction type and merge properly.
Summary: If the merged instruction is call instruction, we need to set the scope to the closes common scope between 2 locations, otherwise it will cause trouble when the call is getting inlined.
Reviewers: dblaikie, aprantl
Reviewed By: dblaikie, aprantl
Subscribers: llvm-commits, sanjoy
Differential Revision: https://reviews.llvm.org/D37877
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314694
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Hans Wennborg [Mon, 2 Oct 2017 17:44:47 +0000 (17:44 +0000)]
CodeView symbol dumper: use symbolic names for registers
https://reviews.llvm.org/D38469
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314690
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Stanislav Mekhanoshin [Mon, 2 Oct 2017 16:57:07 +0000 (16:57 +0000)]
Eliminate ftrunc if source is know to be rounded
Differential Revision: https://reviews.llvm.org/D38421
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314688
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Jonas Devlieghere [Mon, 2 Oct 2017 16:02:04 +0000 (16:02 +0000)]
[dwarfdump] Add -show-form
This enables printing of DWARF form types after the DWARF attribute
types.
Differential revision: https://reviews.llvm.org/D38459
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314685
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Simon Pilgrim [Mon, 2 Oct 2017 15:43:26 +0000 (15:43 +0000)]
[X86][SSE] Add PACKSS/PACKUS constant folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314682
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Simon Pilgrim [Mon, 2 Oct 2017 15:22:35 +0000 (15:22 +0000)]
Regenerate test (missing broadcast constant comments). NFCI.
Still avoiding the floating point comments to prevent linux/windows discrepancies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314681
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Simon Pilgrim [Mon, 2 Oct 2017 15:21:14 +0000 (15:21 +0000)]
Regenerate test (missing broadcast constant comments). NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314680
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Simon Pilgrim [Mon, 2 Oct 2017 15:16:30 +0000 (15:16 +0000)]
Regenerate test. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314679
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Sanjay Patel [Mon, 2 Oct 2017 15:02:06 +0000 (15:02 +0000)]
use range-for-loops; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314676
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Coby Tayree [Mon, 2 Oct 2017 14:36:31 +0000 (14:36 +0000)]
[AsmParser] Support GAS's .print directive
Differential Revision: https://reviews.llvm.org/D38448
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314674
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Sanjay Patel [Mon, 2 Oct 2017 14:03:17 +0000 (14:03 +0000)]
remove duplicate comments, reposition related functions; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314669
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Bjorn Pettersson [Mon, 2 Oct 2017 12:46:38 +0000 (12:46 +0000)]
[X86][SSE] Fix -Wsign-compare problems introduced in r314658
The refactoring in
"[X86][SSE] Add createPackShuffleMask helper function. NFCI."
resulted in warning when compiling the code (seen in build bots).
This patch restores some types from int to unsigned to avoid
those warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314667
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Bjorn Pettersson [Mon, 2 Oct 2017 12:46:32 +0000 (12:46 +0000)]
[Debug info] Handle endianness when moving debug info for split integer values
Summary:
Take the target's endianness into account when splitting the
debug information in DAGTypeLegalizer::SetExpandedInteger.
This patch fixes so that, for big-endian targets, the fragment
expression corresponding to the high part of a split integer
value is placed at offset 0, in order to correctly represent
the memory address order.
I have attached a PPC32 reproducer where the resulting DWARF
pieces for a 64-bit integer were incorrectly reversed.
Patch by: dstenb
Reviewers: JDevlieghere, aprantl, dblaikie
Reviewed By: JDevlieghere, aprantl, dblaikie
Subscribers: nemanjai
Differential Revision: https://reviews.llvm.org/D38172
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314666
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Simon Pilgrim [Mon, 2 Oct 2017 10:12:51 +0000 (10:12 +0000)]
[X86][SSE] Add createPackShuffleMask helper function. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314658
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Simon Pilgrim [Mon, 2 Oct 2017 09:45:08 +0000 (09:45 +0000)]
[X86][SSE] matchBinaryVectorShuffle - add support for different src/dst value shuffle types
Preparation for support for combining to PACKSS/PACKUS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314656
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Hiroshi Inoue [Mon, 2 Oct 2017 09:24:00 +0000 (09:24 +0000)]
[PowerPC] support ZERO_EXTEND in tryBitPermutation
This patch add a support of ISD::ZERO_EXTEND in PPCDAGToDAGISel::tryBitPermutation to increase the opportunity to use rotate-and-mask by reordering ZEXT and ANDI.
Since tryBitPermutation stops analyzing nodes if it hits a ZEXT node while traversing SDNodes, we want to avoid ZEXT between two nodes that can be folded into a rotate-and-mask instruction.
For example, we allow these nodes
t9: i32 = add t7, Constant:i32<1>
t11: i32 = and t9, Constant:i32<255>
t12: i64 = zero_extend t11
t14: i64 = shl t12, Constant:i64<2>
to be folded into a rotate-and-mask instruction.
Such case often happens in array accesses with logical AND operation in the index, e.g. array[i & 0xFF];
Differential Revision: https://reviews.llvm.org/D37514
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314655
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Simon Pilgrim [Mon, 2 Oct 2017 09:10:50 +0000 (09:10 +0000)]
Fix typo in comment. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314653
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Simon Pilgrim [Mon, 2 Oct 2017 09:08:45 +0000 (09:08 +0000)]
[X86] Cleanup uses of computeKnownBits by using MaskedValueIsZero helper instead. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314652
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Michael Zuckerman [Mon, 2 Oct 2017 07:35:25 +0000 (07:35 +0000)]
[X86][LLVM]Expanding Supports lowerInterleaved{store|load}() in X86InterleavedAccess (VF64 stride 3-4)
I continue to support different VF interleaved and in this pass for this patch,
I added the vf64 stride3 support for both load and store.
I also added support fot the stride4 store.
Reviewers:
1. zvi
2. dorit
3. igorb
4. guyblank
Differential Revision: https://reviews.llvm.org/D37687
Change-Id: I3d238efedf217d1768b348d710de1efa2f19d27b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314651
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Craig Topper [Mon, 2 Oct 2017 05:46:53 +0000 (05:46 +0000)]
[X86] Fix copy pasto in X86FastISel::fastEmitInst_rrrr.
The 4th operand was not being constrained and the third operand was being constrained twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314648
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Craig Topper [Mon, 2 Oct 2017 05:46:52 +0000 (05:46 +0000)]
[X86] Use a bool flag instead of assigning an unsigned to two different values that we only use in an equality comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314647
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Craig Topper [Mon, 2 Oct 2017 00:44:50 +0000 (00:44 +0000)]
[X86] Use _NOREX MOVZX instructions for some patterns even in 32-bit mode.
This unifies the patterns between both modes. This should be effectively NFC since all the available registers in 32-bit mode statisfy this constraint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314643
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Ron Lieberman [Mon, 2 Oct 2017 00:34:07 +0000 (00:34 +0000)]
[Hexagon] Check vector elements for equivalence in the HexagonVectorLoopCarriedReuse pass
If the two instructions being compared for equivalence have corresponding operands
that are integer constants, then check their values to determine equivalence.
Patch by Suyog Sarda!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314642
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Ron Lieberman [Mon, 2 Oct 2017 00:16:15 +0000 (00:16 +0000)]
[Hexagon] Patch to Extract i1 element from vector of i1
This patch extracts 1 element from vector consisting
of elements of size 1 bit at given index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314641
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Craig Topper [Sun, 1 Oct 2017 23:53:54 +0000 (23:53 +0000)]
[InstCombine] Use APInt for all the math in foldICmpDivConstant
Summary: This currently uses ConstantExpr to do its math, but as noted in a TODO it can all be done directly on APInt.
Reviewers: spatel, majnemer
Reviewed By: majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38440
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314640
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Craig Topper [Sun, 1 Oct 2017 23:53:53 +0000 (23:53 +0000)]
[X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem
Summary:
Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable.
For the register®ister form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register®ister form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem.
I believe this supercedes D38025 which was trying to switch the register®ister form back to pre-PR22995.
Reviewers: aymanmus, RKSimon, zvi
Reviewed By: aymanmus
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38120
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314639
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Craig Topper [Sun, 1 Oct 2017 23:53:50 +0000 (23:53 +0000)]
[X86] Remove a couple unnecessary COPY_TO_REGCLASS from some output patterns where the instruction already produces the correct register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314638
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Simon Pilgrim [Sun, 1 Oct 2017 18:43:48 +0000 (18:43 +0000)]
[X86][SSE] Add faux shuffle combining support for PACKUS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314631
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Simon Pilgrim [Sun, 1 Oct 2017 18:17:39 +0000 (18:17 +0000)]
[X86][AVX2] Simplify PACKUS combine test
Trying to use a AND mask is tricky as after legalization its nigh impossible for computeKnownBits to do anything with it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314630
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Simon Pilgrim [Sun, 1 Oct 2017 17:54:55 +0000 (17:54 +0000)]
[X86][SSE] Improve shuffle combining of PACKSS instructions.
Support unary packing and fix the faux shuffle mask for vectors larger than 128 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314629
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Simon Pilgrim [Sun, 1 Oct 2017 17:30:44 +0000 (17:30 +0000)]
[X86][SSE] Add shuffle combining tests with PACKSS/PACKUS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314628
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Sanjay Patel [Sun, 1 Oct 2017 14:39:10 +0000 (14:39 +0000)]
[x86] formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314627
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Jina Nahias [Sun, 1 Oct 2017 14:25:21 +0000 (14:25 +0000)]
pre-commit adding test for broadcastm pattern
Differential Revision: https://reviews.llvm.org/D38312
Change-Id: Ifbc4189549f2f59995019a86f85f989c04e4d37d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314626
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Daniel Jasper [Sun, 1 Oct 2017 09:53:53 +0000 (09:53 +0000)]
Revert r314579: "Recommi r314561 after fixing over-debug assertion".
And follow-up r314585.
Leads to segfaults. I'll forward reproduction instructions to the patch
author.
Also, for a recommit, still add the original patch description.
Otherwise, it becomes really tedious to find out what a patch actually
does. The fact that it is a recommit with a fix is somewhat secondary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314622
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Michael Zuckerman [Sun, 1 Oct 2017 09:37:38 +0000 (09:37 +0000)]
Adding test for interleved, case stride 4 vf64 store<NFC>.
Change-Id: I9ea62aac81b763c83d26613dca6fcd846997a017
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314621
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Michal Gorny [Sun, 1 Oct 2017 07:13:25 +0000 (07:13 +0000)]
[lit] Fix running lit tests in unconfigured source dir
Fix llvm_tools_dir attribute access not to fail when the variable is not
present. This directory is not really necessary to run lit tests,
and the code already accounts for it being None.
The reference was added in r313407, and it breaks the stand-alone lit
package in Gentoo.
Differential Revision: https://reviews.llvm.org/D38442
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314620
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Dehao Chen [Sun, 1 Oct 2017 05:24:51 +0000 (05:24 +0000)]
Separate the logic when handling indirect calls in SamplePGO ThinLTO compile phase and other phases.
Summary: In SamplePGO ThinLTO compile phase, we will not invoke ICP as it may introduce confusion to the 2nd annotation. This patch extracted that logic and makes it clearer before profile annotation. In the mean time, we need to make function importing process both inlined callsites as well as not promoted indirect callsites.
Reviewers: tejohnson
Reviewed By: tejohnson
Subscribers: sanjoy, mehdi_amini, llvm-commits, inglorion
Differential Revision: https://reviews.llvm.org/D38094
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314619
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Xin Tong [Sun, 1 Oct 2017 00:10:52 +0000 (00:10 +0000)]
Fix typo. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314615
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Xin Tong [Sun, 1 Oct 2017 00:09:53 +0000 (00:09 +0000)]
Revert "Fix typo [NFC]"
This reverts commit
e60b5028619be1c81bd039d63a0627dac32d38f9.
Incorrectly include changes that are not typo fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314614
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Xin Tong [Sun, 1 Oct 2017 00:07:24 +0000 (00:07 +0000)]
Fix typo [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314613
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Daniel Berlin [Sat, 30 Sep 2017 23:51:55 +0000 (23:51 +0000)]
NewGVN: Fix PR 34473, by not using ExactlyEqualsExpression for finding
phi of ops users.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314612
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Daniel Berlin [Sat, 30 Sep 2017 23:51:54 +0000 (23:51 +0000)]
NewGVN: Evaluate phi of ops expressions before creating phi node
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314611
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Daniel Berlin [Sat, 30 Sep 2017 23:51:53 +0000 (23:51 +0000)]
NewGVN: Allow dependent PHI of ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314610
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Daniel Berlin [Sat, 30 Sep 2017 23:51:04 +0000 (23:51 +0000)]
NewGVN: Make OpIsSafeForPhiOfOps non-recursive
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314609
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Simon Pilgrim [Sat, 30 Sep 2017 22:27:46 +0000 (22:27 +0000)]
Regenerate mul combine tests to update broadcast comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314607
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Dehao Chen [Sat, 30 Sep 2017 20:46:15 +0000 (20:46 +0000)]
Refactor the SamplePGO profile annotation logic to extract inlineCallInstruction. (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314601
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Simon Pilgrim [Sat, 30 Sep 2017 17:57:34 +0000 (17:57 +0000)]
[X86][SSE] Fold (VSRAI (VSHLI X, C1), C1) --> X iff NumSignBits(X) > C1
Remove sign extend in register style pattern if the sign is already extended enough
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314599
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