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Jonas Devlieghere [Thu, 28 Jun 2018 17:56:27 +0000 (17:56 +0000)]
Revert "[OrcMCJIT] Fix test after r335508 causing it to fail on green dragon"
This reverts commit
a6b904daa1d55e31187c85e5b54ef2ddc37fa713.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335893
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Zachary Turner [Thu, 28 Jun 2018 17:55:54 +0000 (17:55 +0000)]
2 VS natvis improvements.
Optional<T> was broken due to a change in the class's internals.
That is fixed, and additionally a visualizer is added for
Expected<T>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335892
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Zachary Turner [Thu, 28 Jun 2018 17:52:06 +0000 (17:52 +0000)]
Set line ending style of llvm.natvis to CRLF.
This file is used by MSVC which is obviously a Windows-only tool and prefers windows line endings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335889
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Sanjay Patel [Thu, 28 Jun 2018 17:48:04 +0000 (17:48 +0000)]
[InstCombine] allow shl+mul combos with shuffle (select) fold (PR37806)
This is an enhancement to D48401 that was discussed in:
https://bugs.llvm.org/show_bug.cgi?id=37806
We can convert a shift-left-by-constant into a multiply (we canonicalize IR in the other
direction because that's generally better of course). This allows us to remove the shuffle
as we do in the regular opcodes-are-the-same cases.
This requires a small hack to make sure we don't introduce any extra poison:
https://rise4fun.com/Alive/ZGv
Other examples of opcodes where this would work are add+sub and fadd+fsub, but we already
canonicalize those subs into adds, so there's nothing to do for those cases AFAICT. There
are planned enhancements for opcode transforms such or -> add.
Note that there's a different fold needed if we've already managed to simplify away a binop
as seen in the test based on PR37806, but we manage to get that one case here because this
fold is positioned above the demanded elements fold currently.
Differential Revision: https://reviews.llvm.org/D48485
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335888
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Jessica Paquette [Thu, 28 Jun 2018 17:45:43 +0000 (17:45 +0000)]
[MachineOutliner] Define MachineOutliner support in TargetOptions
Targets should be able to define whether or not they support the outliner
without the outliner being added to the pass pipeline. Before this, the
outliner pass would be added, and ask the target whether or not it supports the
outliner.
After this, it's possible to query the target in TargetPassConfig, before the
outliner pass is created. This ensures that passing -enable-machine-outliner
will not modify the pass pipeline of any target that does not support it.
https://reviews.llvm.org/D48683
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335887
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Simon Pilgrim [Thu, 28 Jun 2018 17:33:41 +0000 (17:33 +0000)]
[DAGCombiner] Ensure we use the correct CC result type in visitSDIV (REAPPLIED)
We could get away with it for constant folded cases, but not for rL335719.
Thanks to Krzysztof Parzyszek for noticing.
Reapply original commit rL335821 which was reverted at rL335871 due to a WebAssembly bug that was fixed at rL335884.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335886
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Matt Davis [Thu, 28 Jun 2018 17:33:24 +0000 (17:33 +0000)]
[llvm-mca] Delete Pipeline's copy ctor and assignement operator.
Prevent copying of the Pipeline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335885
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Simon Pilgrim [Thu, 28 Jun 2018 17:27:09 +0000 (17:27 +0000)]
[WebAssembly] Add getSetCCResultType placeholder override to handle vector compare results.
Necessary to get the rL335821 bugfix (which was reverted at rL335871) un-reverted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335884
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Jessica Paquette [Thu, 28 Jun 2018 17:26:19 +0000 (17:26 +0000)]
Revert "[MachineOutliner] Add always and never options to -enable-machine-outliner"
I accidentally committed this instead of D48683 because I haven't had coffee
yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335883
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Jessica Paquette [Thu, 28 Jun 2018 17:26:18 +0000 (17:26 +0000)]
Revert "[MachineOutliner] Never add the outliner in -O0"
This reverts commit
9c7c10e4073a0bc6a759ce5cd33afbac74930091.
It relies on r335872 since that introduces the machine outliner
flags test. I meant to commit D48683 in that commit, but got mixed
up and committed D48682 instead. So, I'm reverting this and
r335872, since D48682 hasn't made it through review yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335882
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Jessica Paquette [Thu, 28 Jun 2018 17:05:57 +0000 (17:05 +0000)]
[MachineOutliner] Never add the outliner in -O0
We shouldn't add the outliner when compiling at -O0 even if
-enable-machine-outliner is passed in. This makes sure that we
don't add it in this case.
This also updates machine-outliner-flags to reflect the change
and improves the comment describing what that test does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335879
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Matthias Braun [Thu, 28 Jun 2018 17:00:45 +0000 (17:00 +0000)]
SelectionDAGBuilder, mach-o: Skip trap after noreturn call (for Mach-O)
Add NoTrapAfterNoreturn target option which skips emission of traps
behind noreturn calls even if TrapUnreachable is enabled.
Enable the feature on Mach-O to save code size; Comments suggest it is
not possible to enable it for the other users of TrapUnreachable.
rdar://
41530228
DifferentialRevision: https://reviews.llvm.org/D48674
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335877
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Jessica Paquette [Thu, 28 Jun 2018 16:39:42 +0000 (16:39 +0000)]
[MachineOutliner] Add always and never options to -enable-machine-outliner
To enable the MachineOutliner by default on AArch64, we need to be able to
disable the MachineOutliner and also provide an option to "always" enable the
outliner.
This adds that capability. It allows the user to still use the old
-enable-machine-outliner option, which defaults to "always". This is building
up to allowing the user to specify "always" versus the target-default
outlining behaviour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335872
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Haojian Wu [Thu, 28 Jun 2018 16:25:57 +0000 (16:25 +0000)]
Revert "[DAGCombiner] Ensure we use the correct CC result type in visitSDIV"
This reverts commit r335821.
This crashes the webassembly test, run "ninja check-llvm-codegen-webassembly" to reproduce.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335871
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Simon Pilgrim [Thu, 28 Jun 2018 16:24:13 +0000 (16:24 +0000)]
[llvm-mca][x86] Add FMA4 resource tests
We should be ensuring we have (near) complete test coverage of instructions, at least for the generic model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335870
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Simon Pilgrim [Thu, 28 Jun 2018 16:21:22 +0000 (16:21 +0000)]
[llvm-mca][x86] Add 3dnow! resource tests
We should be ensuring we have (near) complete test coverage of instructions, at least for the generic model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335869
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Stanislav Mekhanoshin [Thu, 28 Jun 2018 15:59:18 +0000 (15:59 +0000)]
[AMDGPU] Early expansion of 32 bit udiv/urem
This allows hoisting of a common code, for instance if denominator
is loop invariant. Current change is expansion only, adding licm to
the target pass list going to be a separate patch. Given this patch
changes to codegen are minor as the expansion is similar to that on
DAG. DAG expansion still must remain for R600.
Differential Revision: https://reviews.llvm.org/D48586
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335868
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Andrea Di Biagio [Thu, 28 Jun 2018 15:50:26 +0000 (15:50 +0000)]
[llvm-mca] Use a WriteRef to describe register writes in class RegisterFile.
This patch introduces a new class named WriteRef. A WriteRef is used by the
RegisterFile to keep track of register definitions. Internally it wraps a
WriteState, as well as the source index of the defining instruction.
This patch allows the tool to propagate additional information to support future
analysis on data dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335867
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Stanislav Mekhanoshin [Thu, 28 Jun 2018 15:24:46 +0000 (15:24 +0000)]
[AMDGPU] Overload llvm.amdgcn.fmad.ftz to support f16
Differential Revision: https://reviews.llvm.org/D48677
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335866
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John Brawn [Thu, 28 Jun 2018 15:17:07 +0000 (15:17 +0000)]
[PhiValues] Adjust unit test to invalidate instructions before deleting them
This should fix a sanitizer buildbot failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335862
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Alexey Bataev [Thu, 28 Jun 2018 15:14:58 +0000 (15:14 +0000)]
[DEBUG_INFO, NVPTX] Add test for .debug_loc section, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335861
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Jonas Devlieghere [Thu, 28 Jun 2018 15:01:42 +0000 (15:01 +0000)]
[dsymutil] Use UnitListTy consistently (NFC)
Use the UnitListTy typedef consistently throughout the Dwarf linker and
pass it by const reference where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335860
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John Brawn [Thu, 28 Jun 2018 14:13:06 +0000 (14:13 +0000)]
Add a PhiValuesAnalysis pass to calculate the underlying values of phis
This pass is being added in order to make the information available to BasicAA,
which can't do caching of this information itself, but possibly this information
may be useful for other passes.
Incorporates code based on Daniel Berlin's implementation of Tarjan's algorithm.
Differential Revision: https://reviews.llvm.org/D47893
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335857
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Benjamin Kramer [Thu, 28 Jun 2018 13:15:03 +0000 (13:15 +0000)]
Revert "Add support for generating a call graph profile from Branch Frequency Info."
This reverts commits r335794 and r335797. Breaks ThinLTO+FDO selfhost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335851
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Sjoerd Meijer [Thu, 28 Jun 2018 12:55:29 +0000 (12:55 +0000)]
[ARM] Parallel DSP Pass
Armv6 introduced instructions to perform 32-bit SIMD operations. The purpose of
this pass is to do some straightforward IR pattern matching to create ACLE DSP
intrinsics, which map on these 32-bit SIMD operations.
Currently, only the SMLAD instruction gets recognised. This instruction
performs two multiplications with 16-bit operands, and stores the result in an
accumulator. We will follow this up with patches to recognise SMLAD in more
cases, and also to generate other DSP instructions (like e.g. SADD16).
Patch by: Sam Parker and Sjoerd Meijer
Differential Revision: https://reviews.llvm.org/D48128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335850
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Pavel Labath [Thu, 28 Jun 2018 12:10:21 +0000 (12:10 +0000)]
Revert "ADT: Move ArrayRef comparison operators into the class"
This reverts commit r335839, because it breaks the MSVC build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335844
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Pavel Labath [Thu, 28 Jun 2018 11:45:28 +0000 (11:45 +0000)]
ADT: Move ArrayRef comparison operators into the class
Summary:
This allows the implicit ArrayRef conversions to kick in when e.g.
comparing ArrayRef to a SmallVector.
Reviewers: zturner, dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48632
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335839
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Andrea Di Biagio [Thu, 28 Jun 2018 11:20:14 +0000 (11:20 +0000)]
[llvm-mca] Refactor method RegisterFile::collectWrites(). NFCI
Rather than calling std::find in a loop, just sort the vector and remove
duplicate entries at the end of the function.
Also, move the debug print at the end of the function, and query the
MCRegisterInfo to print register names rather than physreg IDs.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335837
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Jesper Antonsson [Thu, 28 Jun 2018 10:55:04 +0000 (10:55 +0000)]
Comment change to verify commit rights. NFC.
Summary: Just a silly one-character correction.
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48709
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335832
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Hans Wennborg [Thu, 28 Jun 2018 10:24:38 +0000 (10:24 +0000)]
s/TablesChecked/TableChecked/ after r335823
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335831
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Matt Arsenault [Thu, 28 Jun 2018 10:18:55 +0000 (10:18 +0000)]
AMDGPU: Remove MFI::ABIArgOffset
We have too many mechanisms for tracking the various offsets
used for kernel arguments, so remove one. There's still a lot of
confusion with these because there are two different "implicit"
argument areas located at the beginning and end of the kernarg
segment.
Additionally, the offset was determined based on the memory
size of the split element types. This would break in a future
commit where v3i32 is decomposed into separate i32 pieces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335830
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Matt Arsenault [Thu, 28 Jun 2018 10:18:36 +0000 (10:18 +0000)]
AMDGPU: Error on calls from graphics shaders
In principle nothing should stop these from working, but
work is necessary to create an ABI for dealing with the stack
related registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335829
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Matt Arsenault [Thu, 28 Jun 2018 10:18:23 +0000 (10:18 +0000)]
AMDGPU: Fix AMDGPUCodeGenPrepare using uninitialized AMDGPUAS struct
Not sure how this wasn't noticed before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335828
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Matt Arsenault [Thu, 28 Jun 2018 10:18:11 +0000 (10:18 +0000)]
AMDGPU: Fix assert on aggregate type kernel arguments
Just fix the crash for now by not doing the optimization since
figuring out how to properly convert the bits for an arbitrary
struct is a pain.
Also fix a crash when there is only an empty struct argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335827
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Benjamin Kramer [Thu, 28 Jun 2018 10:03:45 +0000 (10:03 +0000)]
Unify sorted asserts to use the existing atomic pattern
These are all benign races and only visible in !NDEBUG. tsan complains
about it, but a simple atomic bool is sufficient to make it happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335823
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Simon Pilgrim [Thu, 28 Jun 2018 09:54:28 +0000 (09:54 +0000)]
[DAGCombiner] Ensure we use the correct CC result type in visitSDIV
We could get away with it for constant folded cases, but not for rL335719.
Thanks to Krzysztof Parzyszek for noticing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335821
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Florian Hahn [Thu, 28 Jun 2018 09:53:38 +0000 (09:53 +0000)]
[SCCP] Mark CFG as preserved.
SCCP does not change the CFG, so we can mark it as preserved.
Reviewers: dberlin, efriedma, davide
Reviewed By: davide
Differential Revision: https://reviews.llvm.org/D47149
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335820
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Simon Pilgrim [Thu, 28 Jun 2018 09:29:08 +0000 (09:29 +0000)]
[DAGCombiner] Remove unused variable. NFCI.
Noticed in D45806 review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335817
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Max Kazantsev [Thu, 28 Jun 2018 08:20:03 +0000 (08:20 +0000)]
[IndVarSimplify] Ignore unreachable users of truncs
If a trunc has a user in a block which is not reachable from entry,
we can safely perform trunc elimination as if this user didn't exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335816
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Clement Courbet [Thu, 28 Jun 2018 07:41:16 +0000 (07:41 +0000)]
[llvm-exegesis] Add partial X87 support.
Summary:
This enables the X86-specific X86FloatingPointStackifierPass, and allow
llvm-exegesis to generate and measure X87 latency/uops for some FP ops.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335815
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Petar Jovanovic [Thu, 28 Jun 2018 04:50:40 +0000 (04:50 +0000)]
[DwarfDebug] Remove unused argument (NFC)
Remove unused ByteStreamer argument from function emitDebugLocValue.
Patch by Nikola Prica.
Differential Revision: https://reviews.llvm.org/D48590
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335811
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Petr Hosek [Thu, 28 Jun 2018 03:11:52 +0000 (03:11 +0000)]
Support for multiarch runtimes layout
This change adds a support for multiarch style runtimes layout, so in
addition to the existing layout where runtimes get installed to:
lib/clang/$version/lib/$os
Clang now allows runtimes to be installed to:
lib/clang/$version/$target/lib
This also includes libc++, libc++abi and libunwind; today those are
assumed to be in Clang library directory built for host, with the
new layout it is possible to install libc++, libc++abi and libunwind
into the runtime directory built for different targets.
The use of new layout is enabled by setting the
LLVM_ENABLE_RUNTIME_TARGET_DIR CMake variable and is supported by both
projects and runtimes layouts. The runtimes CMake build has been further
modified to use the new layout when building runtimes for multiple
targets.
Differential Revision: https://reviews.llvm.org/D45604
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335809
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Craig Topper [Thu, 28 Jun 2018 01:45:44 +0000 (01:45 +0000)]
[X86] Use PatFrag with hardcoded numbers for FROUND_NO_EXC/FROUND_CURRENT instead of ImmLeafs with predicates where one of the two numbers was hardcoded.
This more efficient for the isel table generator since we can use CheckChildInteger instead of MoveChild, CheckPredicate, MoveParent. This reduced the table size by 1-2K.
I wish there was a way to share the values with X86BaseInfo.h and still use a PatFrag like this. These numbers are fixed by the X86 intrinsic spec going back many years and we should never need to change them. So we shouldn't waste table bytes to support sharing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335806
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Craig Topper [Thu, 28 Jun 2018 00:47:41 +0000 (00:47 +0000)]
[X86] Change how we prefer shift by immediate over folding a load into a shift.
BMI2 added new shift by register instructions that have the ability to fold a load.
Normally without doing anything special isel would prefer folding a load over folding an immediate because the load folding pattern has higher "complexity". This would require an instruction to move the immediate into a register. We would rather fold the immediate instead and have a separate instruction for the load.
We used to enforce this priority by artificially lowering the complexity of the load pattern.
This patch changes this to instead reject the load fold in isProfitableToFoldLoad if there is an immediate. This is more consistent with other binops and feels less hacky.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335804
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Alex Lorenz [Thu, 28 Jun 2018 00:39:09 +0000 (00:39 +0000)]
[cmake][xcode-toolchain] add support for major Xcode version >= 10
The regex that extracts the Xcode version should support major versions with two
digits.
rdar://
41465184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335801
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Michael J. Spencer [Thu, 28 Jun 2018 00:12:04 +0000 (00:12 +0000)]
[CGProfile] Fix unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335797
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Michael J. Spencer [Wed, 27 Jun 2018 23:58:08 +0000 (23:58 +0000)]
Add support for generating a call graph profile from Branch Frequency Info.
=== Generating the CG Profile ===
The CGProfile module pass simply gets the block profile count for each BB and scans for call instructions. For each call instruction it adds an edge from the current function to the called function with the current BB block profile count as the weight.
After scanning all the functions, it generates an appending module flag containing the data. The format looks like:
```
!llvm.module.flags = !{!0}
!0 = !{i32 5, !"CG Profile", !1}
!1 = !{!2, !3, !4} ; List of edges
!2 = !{void ()* @a, void ()* @b, i64 32} ; Edge from a to b with a weight of 32
!3 = !{void (i1)* @freq, void ()* @a, i64 11}
!4 = !{void (i1)* @freq, void ()* @b, i64 20}
```
Differential Revision: https://reviews.llvm.org/D48105
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335794
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Zachary Turner [Wed, 27 Jun 2018 21:18:15 +0000 (21:18 +0000)]
Move some code from PDBFileBuilder to MSFBuilder.
The code to emit the pieces of the MSF file were actually in
PDBFileBuilder. Move this to MSFBuilder so that we can
theoretically emit an MSF without having a PDB file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335789
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Benjamin Kramer [Wed, 27 Jun 2018 21:01:53 +0000 (21:01 +0000)]
[X86] Make folding table checking threadsafe
This is a benign race, but tsan likes to complain about it. Just make it
happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335788
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Craig Topper [Wed, 27 Jun 2018 20:58:46 +0000 (20:58 +0000)]
[X86] In X86DAGToDAGISel::PreprocessISelDAG, make sure we don't access N after we delete it.
If we turn X86ISD::AND into ISD::AND, we delete N. But we were continuing onto the next block of code even though N no longer existed.
Just happened to notice it. I assume asan didn't notice it because we explicitly unpoison deleted nodes and give them a DELETE_NODE opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335787
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Sameer AbuAsal [Wed, 27 Jun 2018 20:51:42 +0000 (20:51 +0000)]
[RISCV] Add machine function pass to merge base + offset
Summary:
In r333455 we added a peephole to fix the corner cases that result
from separating base + offset lowering of global address.The
peephole didn't handle some of the cases because it only has a basic
block view instead of a function level view.
This patch replaces that logic with a machine function pass. In
addition to handling the original cases it handles uses of the global
address across blocks in function and folding an offset from LW\SW
instruction. This pass won't run for OptNone compilation, so there
will be a negative impact overall vs the old approach at O0.
Reviewers: asb, apazos, mgrang
Reviewed By: asb
Subscribers: MartinMosbeck, brucehoult, the_o, rogfer01, mgorny, rbar, johnrusso, simoncook, niosHD, kito-cheng, shiva0217, zzheng, llvm-commits, edward-jones
Differential Revision: https://reviews.llvm.org/D47857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335786
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Fangrui Song [Wed, 27 Jun 2018 20:45:11 +0000 (20:45 +0000)]
[llvm-objdump] Add -x --all-headers options
Reviewers: paulsemel, echristo
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48622
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335785
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Sanjay Patel [Wed, 27 Jun 2018 20:23:47 +0000 (20:23 +0000)]
[InstCombine] add tests for vector-select-of-binops with 2 variables; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335778
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Paul Robinson [Wed, 27 Jun 2018 19:58:28 +0000 (19:58 +0000)]
Document the git config for Windows to do line-endings correctly.
Differential Revision: https://reviews.llvm.org/D48494
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335775
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Nirav Dave [Wed, 27 Jun 2018 19:41:25 +0000 (19:41 +0000)]
[DAGCombine] Disable TokenFactor simplifications when optnone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335773
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Michael Kruse [Wed, 27 Jun 2018 19:39:03 +0000 (19:39 +0000)]
[ADT] drop_begin: use adl_begin/adl_end. NFC.
Summary:
The instantiation of the drop_begin function template usually fails because the functions begin() and end() do not exist. Only when using on a container from the std namespace (or `llvm::iterator_range`s of something derived from `std::iterator`), they are matched to std::begin() and std::end() due to Koenig-lookup.
Explicitly use llvm::adl_begin and llvm::adl_end to make drop_begin applicable to anything iterable (including C-style arrays).
A solution for general `llvm::iterator_range`s was already tried in r244620, but got reverted in r244621 due to MSVC not liking it.
Reviewers: dblaikie, grosbach, aaron.ballman, ruiu
Reviewed By: dblaikie, aaron.ballman
Subscribers: aaron.ballman, llvm-commits
Differential Revision: https://reviews.llvm.org/D48598
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335772
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Fangrui Song [Wed, 27 Jun 2018 19:35:50 +0000 (19:35 +0000)]
[WebAssembly] Try fixing test/CodeGen/WebAssembly/vector_sdiv.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335771
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Fangrui Song [Wed, 27 Jun 2018 19:12:07 +0000 (19:12 +0000)]
[X86] Fix unmatched parenthesis in r335768
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335769
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Craig Topper [Wed, 27 Jun 2018 19:03:36 +0000 (19:03 +0000)]
[X86] Teach the disassembler to use %eiz/%riz instead of NoRegister when the SIB byte is present, but doesn't encode an index register and there was another shorter encoding that would achieve the same result.
The %eiz/%riz are dummy registers that force the encoder to emit a SIB byte when it normally wouldn't. By emitting them in the disassembly output we ensure that assembling the disassembler output would also produce a SIB byte.
This should match the behavior of objdump from binutils.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335768
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Daniel Sanders [Wed, 27 Jun 2018 19:03:21 +0000 (19:03 +0000)]
[globalisel][legalizer] Add AtomicOrdering to LegalityQuery and use it in AArch64
Now that we have the ability to legalize based on MMO's. Add support for
legalizing based on AtomicOrdering and use it to correct the legalization
of the atomic instructions.
Also extend all() to be a variadic template as this ruleset now requires
3 and 4 argument versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335767
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Teresa Johnson [Wed, 27 Jun 2018 19:00:35 +0000 (19:00 +0000)]
[ThinLTO] Fix test
Fix test changes added in r335760. Even though we are invoking llvm-lto2
in single threaded mode, the order of processing the modules in the
backend is apparently not deterministic. Handle the expected debug
messages in any order. (The determinism would be good to fix, but not
related to this change.)
This also undoes the change I made in r335764 to help debug this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335766
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Teresa Johnson [Wed, 27 Jun 2018 18:36:53 +0000 (18:36 +0000)]
[ThinLTO] Modify test to help diagnose bot failures
I am getting bot failures from r335760 that are difficult to diagnose
since the stderr is getting redirected to FileCheck. Save and dump the
debug output to stderr to help debug the issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335764
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Sanjay Patel [Wed, 27 Jun 2018 18:16:40 +0000 (18:16 +0000)]
[DAGCombiner] restrict (float)((int) f) --> ftrunc with no-signed-zeros
As noted in the D44909 review, the transform from (fptosi+sitofp) to ftrunc
can produce -0.0 where the original code does not:
#include <stdio.h>
int main(int argc) {
float x;
x = -0.8 * argc;
printf("%f\n", (float)((int)x));
return 0;
}
$ clang -O0 -mavx fp.c ; ./a.out
0.000000
$ clang -O1 -mavx fp.c ; ./a.out
-0.000000
Ideally, we'd use IR/node flags to predicate the transform, but the IR parser
doesn't currently allow fast-math-flags on the cast instructions. So for now,
just use the function attribute that corresponds to clang's "-fno-signed-zeros"
option.
Differential Revision: https://reviews.llvm.org/D48085
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335761
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Teresa Johnson [Wed, 27 Jun 2018 18:03:39 +0000 (18:03 +0000)]
[ThinLTO] Print names in function import debug messages when available
Summary:
Rather than just print the GUID, when it is available in the index,
print the global name as well in the function import thin link debug
messages. Names will be available when the combined index is being
built by the same process, e.g. a linker or "llvm-lto2 run".
Reviewers: davidxl
Subscribers: mehdi_amini, inglorion, eraman, steven_wu, llvm-commits
Differential Revision: https://reviews.llvm.org/D48612
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335760
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Justin Bogner [Wed, 27 Jun 2018 17:58:32 +0000 (17:58 +0000)]
[Object] Allow iterating over an IRObjectFile's modules
If you've already loaded an IRObjectFile and need access to the
Modules themselves you shouldn't have to reparse a byte stream to do
it. Adds an accessor for the modules in IRObjectFile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335759
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Jessica Paquette [Wed, 27 Jun 2018 17:43:27 +0000 (17:43 +0000)]
[MachineOutliner] Don't outline sequences where x16/x17/nzcv are live across
It isn't safe to outline sequences of instructions where x16/x17/nzcv live
across the sequence.
This teaches the outliner to check whether or not a specific canidate has
x16/x17/nzcv live across it and discard the candidate in the case that that is
true.
https://bugs.llvm.org/show_bug.cgi?id=37573
https://reviews.llvm.org/D47655
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335758
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Sanjay Patel [Wed, 27 Jun 2018 17:21:57 +0000 (17:21 +0000)]
[InstCombine] add more tests for shuffle with different binops; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335756
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Craig Topper [Wed, 27 Jun 2018 16:47:39 +0000 (16:47 +0000)]
[X86] Use bts/btr/btc for single bit set/clear/complement of a variable bit position
If we are just modifying a single bit at a variable bit position we can use the BT* instructions to make the change instead of shifting a 1(or rotating a -1) and doing a binop. These instruction also ignore the upper bits of their index input so we can also remove an and if one is present on the index.
Fixes PR37938.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335754
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Craig Topper [Wed, 27 Jun 2018 16:47:36 +0000 (16:47 +0000)]
[X86] Add test cases for D48606.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335753
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Jakub Kuderski [Wed, 27 Jun 2018 16:34:30 +0000 (16:34 +0000)]
[AliasSet] Fix UnknownInstructions printing
Summary:
AliasSet::print uses `I->printAsOperand` to print UnknownInstructions. The problem is that not all UnknownInstructions have names (e.g. call instructions). When such instructions are printed, they appear as `<badref>` in AliasSets, which is very confusing, as the values are perfectly valid.
This patch fixes that by printing UnknownInstructions without a name using `print` instead of `printAsOperand`.
Reviewers: asbirlea, chandlerc, sanjoy, grosser
Reviewed By: asbirlea
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48609
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335751
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Jonas Devlieghere [Wed, 27 Jun 2018 16:13:40 +0000 (16:13 +0000)]
[dsymutil] Move abstractions into separate files (NFC)
This patch splits off some abstractions used by dsymutil's dwarf linker
and moves them into separate header and implementation files. This
almost halves the number of LOC in DwarfLinker.cpp and makes it a lot
easier to understand what functionality lives where.
Differential revision: https://reviews.llvm.org/D48647
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335749
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Matt Davis [Wed, 27 Jun 2018 16:09:33 +0000 (16:09 +0000)]
[llvm-mca] Register listeners with stages; remove Pipeline dependency from Stage.
Summary:
This patch removes a few callbacks from Pipeline. It comes at the cost of
registering Listeners with all Stages. Not all stages need listeners or issue
callbacks, this registration is a bit redundant. However, as we build-out the
API, this redundancy can disappear.
The main purpose here is to move callback code from the Pipeline and into the
stages that actually issue those callbacks. This removes the back-pointer to
the Pipeline that was put into a few Stage subclasses.
Reviewers: andreadb, courbet, RKSimon
Reviewed By: andreadb, courbet
Subscribers: tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D48576
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335748
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Simon Pilgrim [Wed, 27 Jun 2018 16:00:53 +0000 (16:00 +0000)]
[X86][SSE] Add missing AVX512 rotation tests
Increase coverage to make sure we're not doing anything stupid without AVX512BW
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335746
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Craig Topper [Wed, 27 Jun 2018 15:57:53 +0000 (15:57 +0000)]
[X86] Rename the autoupgraded of packed fp compare and fpclass intrinsics that don't take a mask as input to exclude '.mask.' from their name.
I think the intrinsics named 'avx512.mask.' should refer to the previous behavior of taking a mask argument in the intrinsic instead of using a 'select' or 'and' instruction in IR to accomplish the masking. This is more consistent with the goal that eventually we will have no intrinsics that have masking builtin. When we reach that goal, we should have no intrinsics named "avx512.mask".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335744
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Stanislav Mekhanoshin [Wed, 27 Jun 2018 15:33:33 +0000 (15:33 +0000)]
[AMDGPU] Convert rcp to rcp_iflag
If a source of rcp instruction is a result of any conversion from
an integer convert it into rcp_iflag instruction. No FP exception
can ever happen except division by zero if a single precision rcp
argument is a representation of an integral number.
Differential Revision: https://reviews.llvm.org/D48569
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335742
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Luke Geeson [Wed, 27 Jun 2018 14:34:40 +0000 (14:34 +0000)]
[AArch64] Reverting FP16 vcvth_n_s64_f16 to fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335737
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Adhemerval Zanella [Wed, 27 Jun 2018 13:58:46 +0000 (13:58 +0000)]
[AArch64] Add custom lowering for v4i8 trunc store
This patch adds a custom trunc store lowering for v4i8 vector types.
Since there is not v.4b register, the v4i8 is promoted to v4i16 (v.4h)
and default action for v4i8 is to extract each element and issue 4
byte stores.
A better strategy would be to extended the promoted v4i16 to v8i16
(with undef elements) and extract and store the word lane which
represents the v4i8 subvectores. The construction:
define void @foo(<4 x i16> %x, i8* nocapture %p) {
%0 = trunc <4 x i16> %x to <4 x i8>
%1 = bitcast i8* %p to <4 x i8>*
store <4 x i8> %0, <4 x i8>* %1, align 4, !tbaa !2
ret void
}
Can be optimized from:
umov w8, v0.h[3]
umov w9, v0.h[2]
umov w10, v0.h[1]
umov w11, v0.h[0]
strb w8, [x0, #3]
strb w9, [x0, #2]
strb w10, [x0, #1]
strb w11, [x0]
ret
To:
xtn v0.8b, v0.8h
str s0, [x0]
ret
The patch also adjust the memory cost for autovectorization, so the C
code:
void foo (const int *src, int width, unsigned char *dst)
{
for (int i = 0; i < width; i++)
*dst++ = *src++;
}
can be vectorized to:
.LBB0_4: // %vector.body
// =>This Inner Loop Header: Depth=1
ldr q0, [x0], #16
subs x12, x12, #4 // =4
xtn v0.4h, v0.4s
xtn v0.8b, v0.8h
st1 { v0.s }[0], [x2], #4
b.ne .LBB0_4
Instead of byte operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335735
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Ivan A. Kosarev [Wed, 27 Jun 2018 13:57:52 +0000 (13:57 +0000)]
[NEON] Support vldNq intrinsics in AArch32 (LLVM part)
This patch adds support for the q versions of the dup
(load-to-all-lanes) NEON intrinsics, such as vld2q_dup_f16() for
example.
Currently, non-q versions of the dup intrinsics are implemented
in clang by generating IR that first loads the elements of the
structure into the first lane with the lane (to-single-lane)
intrinsics, and then propagating it other lanes. There are at
least two problems with this approach. First, there are no
double-spaced to-single-lane byte-element instructions. For
example, there is no such instruction as 'vld2.8 { d0[0], d2[0]
}, [r0]'. That means we cannot rely on the to-single-lane
intrinsics and instructions to implement the q versions of the
dup intrinsics. Note that to-all-lanes instructions do support
all sizes of data items, including bytes.
The second problem with the current approach is that we need a
separate vdup instruction to propagate the structure to each
lane. So for vld4q_dup_f16() we would need four vdup instructions
in addition to the initial vld instruction.
This patch introduces dup LLVM intrinsics and reworks handling of
the currently supported (non-q) NEON dup intrinsics to expand
them into those LLVM intrinsics, thus eliminating the need for
using to-single-lane intrinsics and instructions.
Additionally, this patch adds support for u64 and s64 dup NEON
intrinsics. These are marked as Arch64-only in the ARM NEON
Reference, but it seems there are no reasons to not support them
in AArch32 mode. Please correct, if that is wrong.
That's what we generate with this patch applied:
vld2q_dup_f16:
vld2.16 {d0[], d2[]}, [r0]
vld2.16 {d1[], d3[]}, [r0]
vld3q_dup_f16:
vld3.16 {d0[], d2[], d4[]}, [r0]
vld3.16 {d1[], d3[], d5[]}, [r0]
vld4q_dup_f16:
vld4.16 {d0[], d2[], d4[], d6[]}, [r0]
vld4.16 {d1[], d3[], d5[], d7[]}, [r0]
Differential Revision: https://reviews.llvm.org/D48439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335733
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Florian Hahn [Wed, 27 Jun 2018 12:57:51 +0000 (12:57 +0000)]
[ValueLattice] Return false if value range did not change in mergeIn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335729
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Simon Pilgrim [Wed, 27 Jun 2018 12:45:31 +0000 (12:45 +0000)]
[DAGCombiner] visitSDIV - add special case handling for (sdiv X, 1) -> X in pow2 expansion
For divisor = 1, perform a select of X - reduces scalarisation of simple SDIVs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335727
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Nico Weber [Wed, 27 Jun 2018 11:52:30 +0000 (11:52 +0000)]
Build TaskQueueTest in threads=on builds, fixes regression from r335608.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335724
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Andrea Di Biagio [Wed, 27 Jun 2018 11:17:07 +0000 (11:17 +0000)]
[llvm-mca] Avoid calling method update() on instructions that are already in the IS_READY state. NFCI
When promoting instructions from the wait queue to the ready queue, we should
check if an instruction has already reached the IS_READY state before
calling method update().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335722
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Simon Pilgrim [Wed, 27 Jun 2018 10:59:36 +0000 (10:59 +0000)]
[X86][SSE] Include MIN_SIGNED element in non-uniform SDIV pow2 tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335721
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Simon Pilgrim [Wed, 27 Jun 2018 10:51:55 +0000 (10:51 +0000)]
[DAGCombiner] visitSDIV - simplify pow2 handling. NFCI.
Use the builtin constant folding of getNode() etc. instead of doing it manually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335720
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Simon Pilgrim [Wed, 27 Jun 2018 10:21:06 +0000 (10:21 +0000)]
[DAGCombiner] Fold SDIV(%X, MIN_SIGNED) -> SELECT(%X == MIN_SIGNED, 1, 0)
Fixes PR37569.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335719
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Simon Pilgrim [Wed, 27 Jun 2018 09:41:22 +0000 (09:41 +0000)]
[DAGCombiner] Don't accept signbit sdiv divisors in sdiv-by-pow2 vector expansion (PR37569)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335717
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Luke Geeson [Wed, 27 Jun 2018 09:23:38 +0000 (09:23 +0000)]
Removing empty CodeGen dir in root
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335716
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Luke Geeson [Wed, 27 Jun 2018 09:20:13 +0000 (09:20 +0000)]
[AArch64] Remove Duplicate FP16 Patterns with same encoding, match on existing patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335715
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Konstantin Zhuravlyov [Wed, 27 Jun 2018 05:36:03 +0000 (05:36 +0000)]
AMDGPU/NFC: Fix typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335707
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Konstantin Zhuravlyov [Wed, 27 Jun 2018 05:18:50 +0000 (05:18 +0000)]
AMDHSA: Rename RESERVED -> RESERVED0, mark gfx9-specific field
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335706
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Konstantin Zhuravlyov [Wed, 27 Jun 2018 04:56:00 +0000 (04:56 +0000)]
AMDHSA/NFC: Address missed review feedback from
https://reviews.llvm.org/D47566
Change wording from "Must be backwards compatible" to
"Must match hardware definition" for enums that are
defined by hardware.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335705
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Petr Hosek [Wed, 27 Jun 2018 03:35:53 +0000 (03:35 +0000)]
[CMake] Provide direct support for building sanitized runtimes
This avoids having to rely on magic separators and special parsing.
Differential Revision: https://reviews.llvm.org/D48061
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335704
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Petr Hosek [Wed, 27 Jun 2018 03:14:41 +0000 (03:14 +0000)]
[CMake] Use variables rather than ":" delimiters
This is a more idiomatic CMake.
Differential Revision: https://reviews.llvm.org/D37644
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335703
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Justin Bogner [Wed, 27 Jun 2018 00:54:36 +0000 (00:54 +0000)]
[ADT] Pass DerivedT from pointe{e,r}_iterator to iterator_adaptor_base
These were passing the wrong type into iterator_adaptor_base if T was
anything but the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335698
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Matt Davis [Wed, 27 Jun 2018 00:54:11 +0000 (00:54 +0000)]
[llvm-mca] Add a comment to Stage::execute and fix a spelling error. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335697
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Vedant Kumar [Wed, 27 Jun 2018 00:47:53 +0000 (00:47 +0000)]
[InstCombine] Avoid creating mis-sized dbg.values in commonCastTransforms()
This prevents InstCombine from creating mis-sized dbg.values when
replacing a sequence of casts with a simpler cast. For example, in:
(fptrunc (floor (fpext X))) -> (floorf X)
We no longer emit dbg.value(X) (with a 32-bit float operand) to describe
(fpext X) (which is a 64-bit float).
This was diagnosed by the debugify check added in r335682.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335696
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Vedant Kumar [Wed, 27 Jun 2018 00:47:52 +0000 (00:47 +0000)]
[Debugify] Handle failure to get fragment size when checking dbg.values
It's not possible to get the fragment size of some dbg.values. Teach the
mis-sized dbg.value diagnostic to detect this scenario and bail out.
Tested with:
$ find test/Transforms -print -exec opt -debugify-each -instcombine {} \;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335695
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Craig Topper [Wed, 27 Jun 2018 00:42:24 +0000 (00:42 +0000)]
[X86] Don't store register and memory FMA3 opcodes in the same X86InstrFMA3Group.
Nothing was using this relationship. By splitting them we no longer need to worry about register or memory entries being empty in a group.
The memory folding tables in X86InstrInfo.cpp can be used to access this relationship if needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335694
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Vedant Kumar [Tue, 26 Jun 2018 22:46:41 +0000 (22:46 +0000)]
[Debugify] Diagnose mis-sized dbg.values
Report an error in -check-debugify when the size of a dbg.value operand
doesn't match up with the size of the variable it describes.
Eventually this check should be moved into the IR verifier. For the
moment, it's useful to include the check in -check-debugify as a means
of catching regressions and finding existing bugs.
Here are some instances of bugs the new check finds in the -O2 pipeline
(all in InstCombine):
1) A float is used where a double is expected:
ERROR: dbg.value operand has size 32, but its variable has size 64:
call void @llvm.dbg.value(metadata float %expf, metadata !12, metadata
!DIExpression()), !dbg !15
2) An i8 is used where an i32 is expected:
ERROR: dbg.value operand has size 8, but its variable has size 32:
call void @llvm.dbg.value(metadata i8 %t4, metadata !14, metadata
!DIExpression()), !dbg !24
3) A <4 x i32> is used where something twice as large is expected
(perhaps a <4 x i64>, I haven't double-checked):
ERROR: dbg.value operand has size 128, but its variable has size 256:
call void @llvm.dbg.value(metadata <4 x i32> %4, metadata !40, metadata
!DIExpression()), !dbg !95
Differential Revision: https://reviews.llvm.org/D48408
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335682
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Evgeniy Stepanov [Tue, 26 Jun 2018 22:43:48 +0000 (22:43 +0000)]
Revert "[asan] Instrument comdat globals on COFF targets"
Causes false positive ODR violation reports on __llvm_profile_raw_version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335681
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