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Jason Ekstrand [Fri, 12 May 2017 02:00:45 +0000 (19:00 -0700)]
intel/genxml: Rename the CC_VIEWPORT pointer on gen4-5
It isn't a pointer to "color calc state", that's the packet it's in.
It's a pointer to the CC viewport state.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 12 May 2017 01:59:11 +0000 (18:59 -0700)]
intel/genxml: Sampler state is a pointer on gen4-5
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 12 May 2017 20:33:10 +0000 (13:33 -0700)]
intel/genxml: Suffix KSP0 fields on Iron Lake
Iron Lake introduced the multiple KSP thing and so you have KSP0-3.
However, the genxml didn't have an index on the first "Kernel Start
Pointer" or "GRF Register Count". Add one to match gen6+. While we're
here, we drop the brackets from the other "GRF Register Count" fields.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Fri, 12 May 2017 01:58:05 +0000 (18:58 -0700)]
intel/genxml: Make a bunch of things offsets on gen4-5
Most things on gen4-5 are addresses because we don't have dynamic state
base address and we don't have instruction state base on gen4. However,
whoever converted things to addresses got a little over-excited and
converted too much.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Sat, 13 May 2017 20:01:06 +0000 (13:01 -0700)]
intel/isl: Add gen4_filter_tiling
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Sat, 13 May 2017 06:12:12 +0000 (23:12 -0700)]
intel/isl: Add support for setting component write disables
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 16 May 2017 16:27:16 +0000 (09:27 -0700)]
intel/isl: Add support for gen4 cube maps to get_image_offset_sa
Gen4 cube maps are a 2-D surface with ISL_DIM_LAYOUT_GEN4_3D which is a
bit weird but accurate none the less.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 12 May 2017 20:31:05 +0000 (13:31 -0700)]
intel/isl: Don't request space for stencil/hiz packets unless needed
On Iron Lake, the packets exist but we never emit them so there's no
need for us to ask the driver to make batch space for them.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 16 May 2017 21:58:00 +0000 (14:58 -0700)]
i965/blorp: Properly handle mt->first_level
The guts of blorp and ISL don't understand i965's partial miptrees.
Instead, we need to subtract off first_level before we hand anything off
to blorp.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 16 May 2017 21:59:41 +0000 (14:59 -0700)]
i965/miptree: Take first_level into account when converting to ISL
ISL doesn't have a concept of a partial miptree. Instead, we need to
subtract off first_level.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Sun, 14 May 2017 00:00:39 +0000 (17:00 -0700)]
intel/blorp: Move the gen7 stencil format workaround to blorp_blit
It's not needed for blorp_copy because it already overrides formats.
It's also not needed for blorp_clear because it clears stencil as
stencil.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 15 May 2017 20:27:16 +0000 (13:27 -0700)]
i965: Use blorp_copy for doing r8 stencil updates on HSW
The blorp_copy entrypoint is designed for doing memcpy like operations
which is what we need to do here while blorp_blit is for handling format
conversion and scaling. Using blorp_copy is much simpler and prevents
us from getting formats wrong. While we're here, we get rid of the
layers_per_blit thing since stencil always uses interleaved MSAA.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Sat, 13 May 2017 17:30:19 +0000 (10:30 -0700)]
i965/blorp: Do and end-of-pipe sync on both sides of fast-clear ops
We've discovered in the Vulkan driver that simply doing the end-of-pipe
sync afterwards is insufficient. The specific requirement stated in the
PRM is that you have to do one every time you transition between the
tree modes of "clear", "render", and "resolve". This is GL, so we could
track it but any attempt to do so would most likely get it wrong. For
now, it's easier to just assume that every fast-clear op is an island
and do the sync both before and after.
This also removes the unneeded flush and stall after slow-clear
operations.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: "17.0 17.1" <mesa-stable@lists.freedesktop.org>
Eric Engestrom [Fri, 26 May 2017 10:59:20 +0000 (11:59 +0100)]
amd/common: add missing libdrm include path
Fixes:
de9dd4f9f1bb5984c554 ("ac/radeonsi: move struct radeon_info to ac_gpu_info.h")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Andres Gomez [Thu, 25 May 2017 09:26:18 +0000 (11:26 +0200)]
docs: small release calendar fixes
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Dave Airlie [Fri, 26 May 2017 06:34:31 +0000 (16:34 +1000)]
Revert "amd/common: add vcn dec ip info query"
This reverts commit
524d4fff9e0e58e812e71bc5ba2c92ffa73bee16.
This commit breaks amdgpu on kernels with no DEC IP support.
Caught by the airlied CI system.
Dave Airlie [Fri, 26 May 2017 06:34:51 +0000 (16:34 +1000)]
Revert "amd/common: set vcn dec as hw decode as well"
This reverts commit
50d322be2f30bb935ee52b3b3649785975771110.
A previous patch breaks amdgpu on non-vcn decode systems,
but have to revert this first.
Rob Herring [Tue, 23 May 2017 19:00:02 +0000 (14:00 -0500)]
util: remove unneeded Android ifdef from ralloc.c
SIZE_MAX has been defined in stdint.h on Android since 2013, so this ifdef
is no longer needed.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Rob Herring [Tue, 23 May 2017 18:58:24 +0000 (13:58 -0500)]
nouveau: drop Android 4.4 and earlier support
Support for Android 4.4 and earlier has already been removed from mesa.
Remove this remaining piece from nouveau, too.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Rob Herring [Tue, 23 May 2017 19:43:30 +0000 (14:43 -0500)]
i965: use mmap64 for Android
Simplify the handling of mmap for Android by using mmap64 instead. mmap64
may have not existed for Android when this was written, but it's been
around since 2013.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Rob Herring [Tue, 23 May 2017 18:54:19 +0000 (13:54 -0500)]
gallium/os: use mmap64 for Android
Simplify the handling of mmap for Android by using mmap64 instead. mmap64
may have not existed for Android when this was written, but it's been
around since 2013.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Rob Herring [Tue, 23 May 2017 19:41:22 +0000 (14:41 -0500)]
Android: generate an error if building on Android 4.4 or earlier
Since commit
7a5b5f52260 ("Android: drop Android 4.4 (KitKat) support"),
Android 4.4 or earlier is no longer supported, so exit with an error if we
try building on it.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Brian Paul [Sat, 29 Apr 2017 03:57:56 +0000 (21:57 -0600)]
st/wgl: whitespace, formatting fixes in stw_device.c
Trivial.
Brian Paul [Mon, 22 May 2017 12:52:45 +0000 (06:52 -0600)]
glsl: Fix g++ initializer order warning
Fixes this warning:
In file included from ../../../src/compiler/glsl/ir.cpp:25:0:
../../../src/compiler/glsl/ir.h: In constructor 'ir_swizzle::ir_swizzle(ir_rvalue*, ir_swizzle_mask)':
../../../src/compiler/glsl/ir.h:1955:20: warning: 'ir_swizzle::mask' will be initialized after [-Wreorder]
ir_swizzle_mask mask;
^
../../../src/compiler/glsl/ir.h:1954:15: warning: 'ir_rvalue* ir_swizzle::val' [-Wreorder]
ir_rvalue *val;
^
../../../src/compiler/glsl/ir.cpp:1592:1: warning: when initialized here [-Wreorder]
ir_swizzle::ir_swizzle(ir_rvalue *val, ir_swizzle_mask mask)
^
Reviewed-by: Matt Turner <mattst88@gmail.com>
Leo Liu [Mon, 17 Apr 2017 16:37:44 +0000 (12:37 -0400)]
radeonsi: enable vcn decode
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Mon, 17 Apr 2017 16:24:30 +0000 (12:24 -0400)]
winsys/amdgpu: add vcn dec cs support
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Fri, 5 May 2017 14:54:01 +0000 (10:54 -0400)]
amd/common: set vcn dec as hw decode as well
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Wed, 3 May 2017 18:06:35 +0000 (14:06 -0400)]
amd/common: add vcn dec ip info query
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Mon, 17 Apr 2017 16:14:00 +0000 (12:14 -0400)]
radeon: rename has_uvd info to has_hw_decode
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Wed, 3 May 2017 13:54:28 +0000 (09:54 -0400)]
radeon/vcn: add decode message for mpeg4 codec
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Wed, 3 May 2017 13:52:03 +0000 (09:52 -0400)]
radeon/vcn: add decode message for mpeg2 codec
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Wed, 3 May 2017 13:48:55 +0000 (09:48 -0400)]
radeon/vcn: add decode message for vc1 codec
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Wed, 3 May 2017 13:40:44 +0000 (09:40 -0400)]
radeon/vcn: add decode message for hevc codec
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Tue, 2 May 2017 20:39:51 +0000 (16:39 -0400)]
radeon/vcn: add decode message decode for avc codec
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Tue, 2 May 2017 20:26:23 +0000 (16:26 -0400)]
radeon/vcn: add decode message feedback
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Tue, 2 May 2017 20:22:26 +0000 (16:22 -0400)]
radeon/vcn: add decode message destroy
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Tue, 2 May 2017 20:20:46 +0000 (16:20 -0400)]
radeon/vcn: add decode message create
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Tue, 2 May 2017 20:15:15 +0000 (16:15 -0400)]
radeon/vcn: add common decode part
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Mon, 17 Apr 2017 15:49:50 +0000 (11:49 -0400)]
radeon/winsys: add vcn dec ring type
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Mon, 17 Apr 2017 15:49:10 +0000 (11:49 -0400)]
radeon/winsys: add uvd enc ring type
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Tue, 2 May 2017 19:48:21 +0000 (15:48 -0400)]
radeon/vcn: add vcn decode interface
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Wed, 24 May 2017 15:57:28 +0000 (11:57 -0400)]
configure.ac: update libdrm amdgpu version requirement to 2.4.81
VCN decode has a new interface, and that depends on the latest libdrm
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Emil Velikov [Thu, 25 May 2017 07:52:14 +0000 (08:52 +0100)]
docs: update calendar, add news item and link release notes for 17.1.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 25 May 2017 07:18:59 +0000 (08:18 +0100)]
docs: add sha256 checksums for 17.1.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
092c485b8ed127a15f52434857c37e8021775775)
Emil Velikov [Thu, 25 May 2017 07:11:42 +0000 (08:11 +0100)]
docs: add release notes for 17.1.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
ca0a148a4d09d850f63c82011ac49a311e43e502)
Timothy Arceri [Tue, 23 May 2017 12:01:53 +0000 (22:01 +1000)]
mesa: remove unrequired double calc
type_size() will already handle this correctly for us.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Tue, 23 May 2017 12:01:52 +0000 (22:01 +1000)]
mesa: remove redundant modulus operation
The if check above means we can only get here if size is less than 4.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Tue, 23 May 2017 19:16:56 +0000 (13:16 -0600)]
svga: init svga_screen::swc_mutex with mtx_recursive
If the SVGA3D_BindGBSurface() call in svga_buffer_hw_storage_unmap()
fails, we'll flush and that might involve unmapping other buffers.
That leads to a recursive lock on svga_screen::swc_mutex and causes
a deadlock. Fix this by initializing the mutex with mtx_recursive.
Note that this only happened on Linux, not Windows. On Windows, the
mutex functions are implemented with Win32 critical sections which
support recursive locking.
Also add a comment about this.
Fixes VMware bug
1831549 (Unigine Tropics demo freeze on Linux).
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Neha Bhende<bhenden@vmware.com>
Brian Paul [Tue, 23 May 2017 14:21:57 +0000 (08:21 -0600)]
svga: move logging initialization code into new function
Plus a few other minor clean-ups.
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Brian Paul [Tue, 23 May 2017 14:16:38 +0000 (08:16 -0600)]
svga: init local vars to silence uninitialized use warnings
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Brian Paul [Tue, 23 May 2017 13:45:12 +0000 (07:45 -0600)]
svga: log the process command line to the vmware.log file
This is useful for Piglit when thousands of tests are run and we want
to determine which test triggered a device error.
v2: only log command line info if the new SVGA_EXTRA_LOGGING env var is set
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Sinclair Yeh [Thu, 4 Aug 2016 19:57:06 +0000 (12:57 -0700)]
svga: Limit svga message capability to newer compilers
The assembly code used by the SVGA message feature doesn't
build properly with older compilers, so limit it to only
gcc 5.3.0 and newer.
Also modified the stubs to avoid "unused variable" warnings.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Brian Paul [Thu, 19 May 2016 10:11:51 +0000 (11:11 +0100)]
svga: Fix MSVC build.
This let us compile the code with MSVC, but it no-ops the log function.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Sinclair Yeh [Tue, 23 May 2017 13:42:08 +0000 (07:42 -0600)]
svga: Add the ability to log messages to vmware.log on the host.
For now this capability only exists in the SVGA driver but
can be exported later if other modules, e.g. winsys, wants
to use it for logging.
Reviewed-by: Brian Paul <brianp@vmware.com>
Brian Paul [Mon, 22 May 2017 16:30:16 +0000 (10:30 -0600)]
Revert "gallium: remove unused PIPE_CC_GCC_VERSION"
This reverts commit
e60928f4c4bd4484821d83f2b16a910ea9f5f9d9.
PIPE_CC_GCC_VERSION is used by some of our in-house code which hasn't
been upstreamed yet.
Lionel Landwerlin [Wed, 24 May 2017 01:04:34 +0000 (02:04 +0100)]
aubinator: report error on unknown device id
Since we're going to stop aubinator without a valid device id, better
report an error. This also silences a Coverity warning.
CID:
1405004
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Lionel Landwerlin [Wed, 24 May 2017 01:02:30 +0000 (02:02 +0100)]
aubinator: be consistent on exit code
We're using both exit(1) & exit(EXIT_FAILURE), settle for one, same
for success.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Lionel Landwerlin [Wed, 24 May 2017 00:48:36 +0000 (01:48 +0100)]
aubinator: fix double free
1;4601;0c
Free previously allocated filename outside the for loop.
CID:
1405014
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Christian König [Tue, 23 May 2017 16:40:18 +0000 (18:40 +0200)]
winsys/amdgpu: align VA allocations to fragment size v2
BOs larger than the minimum fragment size should have their VA
alignet to at least the fragment size for optimal performance.
v2: drop unused leftover from initial implementation
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Tue, 23 May 2017 13:31:35 +0000 (15:31 +0200)]
tgsi: remove unused tgsi_is_passthrough_shader()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Eric Engestrom [Wed, 24 May 2017 07:30:59 +0000 (08:30 +0100)]
configure.ac: rephrase 'GLX w/o X11' error message
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Jason Ekstrand [Wed, 17 May 2017 18:54:24 +0000 (11:54 -0700)]
anv: Require vertex buffers to come from a 32-bit heap
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Wed, 17 May 2017 18:54:12 +0000 (11:54 -0700)]
anv: Advertise both 32-bit and 48-bit heaps when we have enough memory
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Wed, 17 May 2017 18:42:36 +0000 (11:42 -0700)]
anv: Refactor memory type setup
This makes us walk over the heaps one at a time and add the types for
LLC and !LLC to each heap.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Wed, 17 May 2017 18:38:16 +0000 (11:38 -0700)]
anv: Make supports_48bit_addresses a heap property
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Wed, 17 May 2017 18:31:02 +0000 (11:31 -0700)]
anv: Stop setting BO flags in bo_init_new
The idea behind doing this was to make it easier to set various flags.
However, we have enough custom flag settings floating around the driver
that this is more of a nuisance than a help. This commit has the
following functional changes:
1) The workaround_bo created in anv_CreateDevice loses both flags.
This shouldn't matter because it's very small and entirely internal
to the driver.
2) The bo created in anv_CreateDmaBufImageINTEL loses the
EXEC_OBJECT_ASYNC flag. In retrospect, it never should have gotten
EXEC_OBJECT_ASYNC in the first place.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Wed, 17 May 2017 18:16:57 +0000 (11:16 -0700)]
anv: Set image memory types based on the type count
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Wed, 17 May 2017 18:14:06 +0000 (11:14 -0700)]
anv: Add valid_bufer_usage to the memory type metadata
Instead of returning valid types as just a number, we now walk the list
and check the buffer's usage against the usage flags we store in the new
anv_memory_type structure. Currently, valid_buffer_usage == ~0.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Wed, 17 May 2017 18:13:01 +0000 (11:13 -0700)]
anv: Determine the type of mapping based on type metadata
Before, we were just comparing the type index to 0. Now we actually
look the type up in the table and check its properties to determine what
kind of mapping we want to do.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Wed, 17 May 2017 17:55:41 +0000 (10:55 -0700)]
anv: Set up memory types and heaps during physical device init
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Thu, 18 May 2017 17:57:42 +0000 (10:57 -0700)]
anv: Predicate 48bit support on gen >= 8
This doesn't matter right now since it only affects whether or not we
set the kernel bit but, if we ever do anything else based on it, we'll
want it to be correct per-gen.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Thu, 18 May 2017 18:31:48 +0000 (11:31 -0700)]
anv/image: Get rid of the memset(aux, 0, sizeof(aux)) hack
Up until now, we've been memsetting the auxiliary surface to 0 at
BindImageMemory time to ensure that it is properly initialized.
However, this isn't correct because apps are allowed to freely alias
memory between different images and buffers so long as they properly
track whether or not a particular image is valid and, if it isn't,
transition from UNINITIALIZED to something else before using it. We
now implement those transitions so we can drop the hack.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Thu, 18 May 2017 18:30:47 +0000 (11:30 -0700)]
anv: Handle transitioning depth from UNDEFINED to other layouts
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Thu, 18 May 2017 02:02:42 +0000 (19:02 -0700)]
anv: Handle color layout transitions from the UNINITIALIZED layout
This causes dEQP-VK.api.copy_and_blit.resolve_image.partial.* to start
failing due to test bugs. See CL 1031 for a test fix.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Axel Davy [Sun, 21 May 2017 22:19:01 +0000 (00:19 +0200)]
st/nine: Fix a regression and syntax cleanup
A few cleanups and in particular initializing properly
the new pipe_draw_info fields.
This should fix the regression caused by
330d0607ed60fd3edca192e54b4246310f06652f
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101088
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Ian Romanick [Mon, 22 May 2017 18:14:32 +0000 (11:14 -0700)]
mesa: Remove GL_APPLE_vertex_array_object stubs
Mark the functions 'exec="skip"' in the XML instead. libGL will still
have the functions, but the driver won't try to use them. I verified
that this commit works with piglit's 'object-namespace-pollution glClear
vertex-array' on x64 with a driver built from mesa-12.0.3 tag.
In fairness, this test also works with a libGL built from
7927d03. I
believe it continues to work because on non-Windows platforms we
generate some extra, dummy dispatch functions that can be used when a
driver requests a function unknown to libGL. This was done to provide
some "forward" compatibility with drivers that need more functions.
This doesn't work on Windows because the Windows calling convention is
for the callee to clean up the stack. That's the theory anyway.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Wed, 17 May 2017 18:25:59 +0000 (20:25 +0200)]
gallium/radeon: pipe AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS into gallium HUD
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Rob Clark [Tue, 23 May 2017 16:05:12 +0000 (12:05 -0400)]
freedreno/ir3: switch to NIR by default
Now that we lower vars to regs, we no longer regress for anything that
does complex dereferences. (With tgsi, derefers are already lowered
before tgsi_to_nir, but not with glsl_to_nir.) In fact it actually
fixes a few things to bypass tgsi.
So make NIR the default (finally!)
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sun, 21 May 2017 16:40:30 +0000 (12:40 -0400)]
freedreno/ir3: lower arrays to regs
Instead of using load/store_var intrinsics, which can have complex
derefs in the case of multi-dimensional arrays, lower these to regs
and handle the direct/indirect loads in get_src() and stores in
put_dst().
This should let us switch to using nir by default.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sun, 21 May 2017 16:33:45 +0000 (12:33 -0400)]
freedreno/ir3: add put_dst()
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sun, 21 May 2017 15:59:51 +0000 (11:59 -0400)]
freedreno/ir3: code-motion
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sat, 20 May 2017 15:18:08 +0000 (11:18 -0400)]
freedreno/ir3: fix cmdline compiler
standalone_compiler_cleanup() frees the glsl types, among other things,
so it needs to come after nir->ir3. But since we exit after dumping the
disassembly, it is easier to just not call it at all.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 22 May 2017 18:18:19 +0000 (14:18 -0400)]
freedreno/ir3: add missing nir_opt_copy_prop_vars() pass
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 23 May 2017 13:09:41 +0000 (09:09 -0400)]
freedreno/ir3: need different compiler options for a5xx
vertex_id_zero_based differs..
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sat, 20 May 2017 13:54:08 +0000 (09:54 -0400)]
freedreno/a5xx: remove copapasta from a4xx
Won't ever hit this w/ a420 gpu, so this is dead code. Need to get astc
working to know whether to rip this out entirely or not.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 19 May 2017 13:39:52 +0000 (09:39 -0400)]
freedreno: only support SSBOs with nir
tgsi_to_nir does not support them. Note that compute shaders already
force nir.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 17 May 2017 16:46:17 +0000 (12:46 -0400)]
freedreno/a5xx: add some missing texture formats
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 17 May 2017 14:17:10 +0000 (10:17 -0400)]
freedreno/a5xx: provoking vertex
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 17 May 2017 14:02:30 +0000 (10:02 -0400)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 15 May 2017 19:53:12 +0000 (15:53 -0400)]
nir/lower-atomics-to-ssbo: remove atomic_uint arrays too
Maybe there is a better way to do this. But by the time we get to
assigning uniform locs, we want the atomic_uint's to all be gone,
otherwise we assert in st_glsl_attrib_type_size().
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 15 May 2017 19:38:39 +0000 (15:38 -0400)]
nir/lower-atomics-to-ssbo: fix num_components
Fixes some piglits like arb_shader_atomic_counters-active-counters
Signed-off-by: Rob Clark <robdclark@gmail.com>
Timothy Arceri [Sat, 20 May 2017 01:27:32 +0000 (11:27 +1000)]
radeon: pass flags that can change shaders to disk_cache_create()
I wasn't sure if I should filter the flags so that we only use
flags that actually change the shader output. To avoid manual
updates we just pass in everything for now.
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Sat, 20 May 2017 01:06:25 +0000 (11:06 +1000)]
util/disk_cache: add new driver_flags param to cache keys
This will be used for things such as adding driver specific environment
variables to the key. Allowing us to set environment vars that change
the shader and not have the driver ignore them if it finds existing
shaders in the cache.
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Jose Fonseca [Mon, 22 May 2017 17:04:12 +0000 (18:04 +0100)]
u_format_test: Ignore S3TC errors.
This prevents spurious failures when libtxc-dxtn-s2tc is installed.
Note: lp_test_format doesn't need any change since we were already
ignoring S3TC failures there.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Rhys Kidd <rhyskidd@gmail.com>
Nanley Chery [Fri, 19 May 2017 23:39:25 +0000 (16:39 -0700)]
docs: Document ASTC extension support for SKL and BXT
v2: Remove the '+' after bxt
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Nanley Chery [Sat, 22 Apr 2017 00:15:16 +0000 (17:15 -0700)]
i965: Enable ASTC HDR for Broxton
This platform passes the following GLES3 tests:
ES3-CTS.functional.texture.compressed.astc.endpoint_value_hdr_cem_*
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Nanley Chery [Tue, 16 May 2017 23:20:59 +0000 (16:20 -0700)]
intel/isl: Add ASTC HDR to format lists and helpers
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Bas Nieuwenhuizen [Sun, 14 May 2017 12:40:02 +0000 (14:40 +0200)]
radv: Add compute HTILE fast clear.
Not really what the fast depth clear does, no matter whether you use
EXPCLEAR or not. Seems the fast clear using the DB HW always touches
the main buffer.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 20 May 2017 21:45:56 +0000 (23:45 +0200)]
radv: Use correct clear words for HTILE.
Did some RE'ing what several HTILE words give when read from a descriptor
with HTILE compression enabled.
Seems to align with -pro usage for D16 too.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Mon, 15 May 2017 21:00:17 +0000 (23:00 +0200)]
radv: Add queue masks for htile usage determination.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>