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Craig Topper [Sun, 31 Jul 2016 20:20:05 +0000 (20:20 +0000)]
[AVX512] Always use EVEX encodings for 128/256-bit move instructions in getLoadStoreRegOpcode if VLX is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277305
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Craig Topper [Sun, 31 Jul 2016 20:20:01 +0000 (20:20 +0000)]
[AVX512] Add VLX packed move instructions to the execution dependency fix pass and update tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277304
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Craig Topper [Sun, 31 Jul 2016 20:19:55 +0000 (20:19 +0000)]
[AVX512] Move FR32X/FR64X handling in getLoadStoreRegOpcode into the main switch. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277303
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Craig Topper [Sun, 31 Jul 2016 20:19:53 +0000 (20:19 +0000)]
[AVX512] Stop treating VR512 specially in getLoadStoreRegOpcode and use the regular switch which already tried to handle it, but was unreachable. This has the added benefit of enabling aligned loads/stores if the stack is aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277302
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Craig Topper [Sun, 31 Jul 2016 20:19:50 +0000 (20:19 +0000)]
[AVX512] Add X86::VR512RegClassID to X86RegisterInfo::getLargestLegalSuperClass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277301
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Simon Pilgrim [Sun, 31 Jul 2016 19:50:45 +0000 (19:50 +0000)]
[X86] Improve 64-bit shifts on 32-bit targets (PR14593)
As discussed on PR14593, this patch adds support for lowering to SHLD/SHRD from the patterns generated by DAGTypeLegalizer::ExpandShiftWithKnownAmountBit.
Differential Revision: https://reviews.llvm.org/D23000
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277299
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David Majnemer [Sun, 31 Jul 2016 19:40:02 +0000 (19:40 +0000)]
[COFF] Expose iterators for ImportAddressTableRVA
Patch by Bandzi Michal!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277298
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David Majnemer [Sun, 31 Jul 2016 19:25:21 +0000 (19:25 +0000)]
[COFF] Remove a duplicate import_directory_table_entry definition
We had import_directory_table_entry and
coff_import_directory_table_entry, remove one. Also, factor out the
logic which determins if a descriptor is a terminator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277296
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David Majnemer [Sun, 31 Jul 2016 19:25:16 +0000 (19:25 +0000)]
[bugpoint] Add a -Os option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277295
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Simon Pilgrim [Sun, 31 Jul 2016 17:51:37 +0000 (17:51 +0000)]
[X86] Add tests for the lowering SHLD/SHRD from manual pattern similar to those generated by ExpandShiftWithKnownAmountBit
Test for add(v,v) as well as shl(v,1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277293
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Craig Topper [Sun, 31 Jul 2016 17:15:07 +0000 (17:15 +0000)]
[AVX-512] Don't let ExeDependencyFix pass convert VPANDD/Q to VPANDPS/PD unless DQI instructions are supported. Same for ANDN, OR, and XOR.
Thanks to Igor Breger for pointing out my mistake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277292
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Simon Pilgrim [Sun, 31 Jul 2016 17:11:49 +0000 (17:11 +0000)]
[X86] Add tests for the lowering SHLD/SHRD from manual patterns
As discussed on D23000
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277291
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Amjad Aboud [Sun, 31 Jul 2016 14:41:50 +0000 (14:41 +0000)]
Fixed "copy-paste" mistake from revision 255245.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277290
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Elena Demikhovsky [Sun, 31 Jul 2016 06:48:01 +0000 (06:48 +0000)]
AVX-512: Removed AssertZext node before TRUNCATE
Removed AssertZext node, which was inserted between X86ISD::SETCC and "truncate to i1".
Differential Revision: https://reviews.llvm.org/D22850
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277289
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Chandler Carruth [Sun, 31 Jul 2016 02:19:13 +0000 (02:19 +0000)]
[ADT] Add 'consume_front' and 'consume_back' methods to StringRef which
are very handy when parsing text.
They are essentially a combination of startswith and a self-modifying
drop_front, or endswith and drop_back respectively.
Differential Revision: https://reviews.llvm.org/D22723
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277288
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Davide Italiano [Sat, 30 Jul 2016 22:07:21 +0000 (22:07 +0000)]
[HexagonConstPropagation] Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277285
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Davide Italiano [Sat, 30 Jul 2016 22:07:18 +0000 (22:07 +0000)]
[HexagonBitSimplify] Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277284
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Davide Italiano [Sat, 30 Jul 2016 22:07:15 +0000 (22:07 +0000)]
[ARMConstantIslandPass] Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277283
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Lang Hames [Sat, 30 Jul 2016 21:34:04 +0000 (21:34 +0000)]
[Support] Add doxygen @code tags to example code in Error comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277282
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Simon Pilgrim [Sat, 30 Jul 2016 21:01:34 +0000 (21:01 +0000)]
[SLPVectorizer][X86] Added vXi8/vXi16 sitofp/uitofp tests
Dropped useless 2i32-2f32 test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277281
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Simon Pilgrim [Sat, 30 Jul 2016 20:53:21 +0000 (20:53 +0000)]
Strip trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277280
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Simon Pilgrim [Sat, 30 Jul 2016 20:51:26 +0000 (20:51 +0000)]
[X86] Use peekThroughOneUseBitcasts helper function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277279
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Simon Pilgrim [Sat, 30 Jul 2016 20:28:02 +0000 (20:28 +0000)]
[X86][SSE] Regenerate vshift tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277278
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Simon Pilgrim [Sat, 30 Jul 2016 18:43:30 +0000 (18:43 +0000)]
[SLPVectorizer][X86] Added SITOFP/UITOFP vectorization tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277275
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Simon Pilgrim [Sat, 30 Jul 2016 16:29:19 +0000 (16:29 +0000)]
[X86][AVX] Added signum example test functions from PR13248
These are good examples of missed combine opportunities with zero/all bit vector compare results
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277274
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Simon Pilgrim [Sat, 30 Jul 2016 16:01:30 +0000 (16:01 +0000)]
[X86][X87] Add vector arithmetic tests for targets with sse disabled
To make sure the X86_64 target isn't doing anything stupid
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277272
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Simon Pilgrim [Sat, 30 Jul 2016 14:06:59 +0000 (14:06 +0000)]
[X86][SSE] Let 64-bit targets use the fast 2i32-2f32 UINT_TO_FP conversion as well as 32-bit
The 2i32-2i64 legalization means that we can use the slightly quicker double bits + fptrunc approach for the same results
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277271
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Hubert Tong [Sat, 30 Jul 2016 14:01:00 +0000 (14:01 +0000)]
TrailingObjects::FixedSizeStorage constexpr fixes + tests
Summary:
This change fixes issues with `LLVM_CONSTEXPR` functions and
`TrailingObjects::FixedSizeStorage`. In particular, some of the
functions marked `LLVM_CONSTEXPR` used by `FixedSizeStorage` were not
implemented such that they evaluate successfully as part of a constant
expression despite constant arguments.
This change also implements a more traditional template-meta path to
accommodate MSVC, and adds unit tests for `FixedSizeStorage`.
Drive-by fix: the access control for members of `TrailingObjectsImpl` is
tightened.
Reviewers: faisalv, rsmith, aaron.ballman
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D22668
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277270
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Hubert Tong [Sat, 30 Jul 2016 13:38:51 +0000 (13:38 +0000)]
MathExtras.h: add LLVM_CONSTEXPR where simple
Summary:
This change adds `LLVM_CONSTEXPR` to functions selected as follows:
- the body is already valid under C++11 for a `constexpr` function,
- the evaluation of the function, given constant arguments, will not
fail during the evaluation of a constant expression, and
- the above properties are easily verifiable at a glance.
Note: the evaluation of the function cannot fail if the instantiation
triggers a static assertion failure.
Reviewers: faisalv, rsmith, aaron.ballman
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D22824
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277269
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Benjamin Kramer [Sat, 30 Jul 2016 13:25:37 +0000 (13:25 +0000)]
[Hexagon] Perform bit arithmetic on unsigned to avoid accidentally shifting negative values.
Found by ubsan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277268
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Benjamin Kramer [Sat, 30 Jul 2016 12:05:17 +0000 (12:05 +0000)]
Update modulemap for Msf -> MSF rename.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277267
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Benjamin Kramer [Sat, 30 Jul 2016 11:31:24 +0000 (11:31 +0000)]
[X86] Fix lifetime of SMRange temporaries.
Found by asan -fsanitize-address-use-after-scope.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277266
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Benjamin Kramer [Sat, 30 Jul 2016 11:31:16 +0000 (11:31 +0000)]
[AMDGPU] Fix lifetime of SmallVector temporaries.
Found by asan -fsanitize-address-use-after-scope.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277265
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Matt Arsenault [Sat, 30 Jul 2016 01:40:36 +0000 (01:40 +0000)]
AMDGPU: Fix shouldConvertConstantLoadToIntImm behavior
This should really be true for any immediate, not just
inline ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277260
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Matt Arsenault [Sat, 30 Jul 2016 01:40:34 +0000 (01:40 +0000)]
AMDGPU: Set s_setpc_b64 as a terminator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277259
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Matt Arsenault [Sat, 30 Jul 2016 01:40:30 +0000 (01:40 +0000)]
AMDGPU: Remove unused pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277258
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Lang Hames [Sat, 30 Jul 2016 00:57:54 +0000 (00:57 +0000)]
[Orc] Add support for updating stub targets to CompileOnDemandLayer.
This makes it possible to implement re-optimization on top of the
CompileOnDemandLayer.
Test case to come in a future patch: This will need an execution test, and
execution tests require a full working stack. The best option is to plumb this
API up to the C Bindings stack and add a C bindings test for this.
Patch by Sean Ogden. Thanks Sean!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277257
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Hans Wennborg [Sat, 30 Jul 2016 00:08:45 +0000 (00:08 +0000)]
Remove empty DebugInfo/Msf dirs. It seems these were left over from
the renaming from 'Msf' to 'MSF' in r277213.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277254
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Weiming Zhao [Fri, 29 Jul 2016 23:33:48 +0000 (23:33 +0000)]
DAG: avoid duplicated truncating for sign extended operand
Summary:
When performing cmp for EQ/NE and the operand is sign extended, we can
avoid the truncaton if the bits to be tested are no less than origianl
bits.
Reviewers: eli.friedman
Subscribers: eli.friedman, aemerson, nemanjai, t.p.northover, llvm-commits
Differential Revision: https://reviews.llvm.org/D22933
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277252
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Lang Hames [Fri, 29 Jul 2016 23:17:53 +0000 (23:17 +0000)]
[Support] Add storage specifier for MachO::NListType.
This should fix UB warnings from the sanitizer bots: LLD performs bit
manipulations on enums of this type, and these are UB if the underlying
storage type isn't specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277251
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Tim Northover [Fri, 29 Jul 2016 22:41:55 +0000 (22:41 +0000)]
GlobalISel: translate "unreachable" (into nothing)
Easiest instruction ever!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277225
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Tim Northover [Fri, 29 Jul 2016 22:32:36 +0000 (22:32 +0000)]
GlobalISel: support translation of intrinsic calls.
These come in two variants for now: G_INTRINSIC and G_INTRINSIC_W_SIDE_EFFECTS.
We may decide to split the latter up with finer-grained restrictions later, if
necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277224
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Kevin Enderby [Fri, 29 Jul 2016 22:32:02 +0000 (22:32 +0000)]
Think this will fix issues with the error messages generated for malformed-archives.test
in r277177 and added back this test which was deleted in r277196 while
I tracked down these problems.
Changed from constructing Twine's to std::string's as Twine's don't work
across statements. Also removed a few unneeded Twine() constructions.
Fix the write_escaped() calls to not pass the unintended second argument
fixing the warning on the ld-x86_64-win7 bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277223
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Krzysztof Parzyszek [Fri, 29 Jul 2016 21:49:42 +0000 (21:49 +0000)]
[Hexagon] Referencify MachineInstr in HexagonInstrInfo, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277220
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Michael Kuperstein [Fri, 29 Jul 2016 21:45:51 +0000 (21:45 +0000)]
[X86] Match PSADBW in straight-line code
Up until now, we only had code to match PSADBW patterns that look like what
comes out of the loop vectorizer - a partial reduction inside the loop body
that gets fed into a horizontal operation in a different basic block.
This adds support for straight-line patterns, like those generated by the
SLP vectorizer.
Differential Revision: https://reviews.llvm.org/D22889
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277219
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Michael Kuperstein [Fri, 29 Jul 2016 21:44:33 +0000 (21:44 +0000)]
[Hexagon] Fix test that uses -debug-only to require asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277218
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Rui Ueyama [Fri, 29 Jul 2016 21:38:00 +0000 (21:38 +0000)]
pdbdump: Dump Free Page Map contents.
Differential Revision: https://reviews.llvm.org/D22974
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277216
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Simon Pilgrim [Fri, 29 Jul 2016 21:05:10 +0000 (21:05 +0000)]
[X86][AVX] Fix VBROADCASTF128 selection bug (PR28770)
Support for lowering to VBROADCASTF128 etc. in D22460 was not correctly ensuring that the only users of the 128-bit vector load were the insertions of the vector into the lower/upper subvectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277214
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Zachary Turner [Fri, 29 Jul 2016 20:56:36 +0000 (20:56 +0000)]
[msf] Resubmit "Rename Msf -> MSF".
Previously this change was submitted from a Windows machine, so
changes made to the case of filenames and directory names did
not survive the commit, and as a result the CMake source file
names and the on-disk file names did not match on case-sensitive
file systems.
I'm resubmitting this patch from a Linux system, which hopefully
allows the case changes to make it through unfettered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277213
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Tim Northover [Fri, 29 Jul 2016 20:32:59 +0000 (20:32 +0000)]
CodeGen: add new "intrinsic" MachineOperand kind.
This will be used during GlobalISel, where we need a more robust and readable
way to write tests than a simple immediate ID.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277209
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Eli Bendersky [Fri, 29 Jul 2016 19:35:22 +0000 (19:35 +0000)]
Add a REQUIRES: assert on a Lanai test that uses a -debug-only flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277204
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Adam Nemet [Fri, 29 Jul 2016 19:29:47 +0000 (19:29 +0000)]
[LoopUnroll] Include hotness of region in opt remark
LoopUnroll is a loop pass, so the analysis of OptimizationRemarkEmitter
is added to the common function analysis passes that loop passes
depend on.
The BFI and indirectly BPI used in this pass is computed lazily so no
overhead should be observed unless -pass-remarks-with-hotness is used.
This is how the patch affects the O3 pipeline:
Dominator Tree Construction
Natural Loop Information
Canonicalize natural loops
Loop-Closed SSA Form Pass
Basic Alias Analysis (stateless AA impl)
Function Alias Analysis Results
Scalar Evolution Analysis
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ Optimization Remark Emitter
Loop Pass Manager
Rotate Loops
Loop Invariant Code Motion
Unswitch loops
Simplify the CFG
Dominator Tree Construction
Basic Alias Analysis (stateless AA impl)
Function Alias Analysis Results
Combine redundant instructions
Natural Loop Information
Canonicalize natural loops
Loop-Closed SSA Form Pass
Scalar Evolution Analysis
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ Optimization Remark Emitter
Loop Pass Manager
Induction Variable Simplification
Recognize loop idioms
Delete dead loops
Unroll loops
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277203
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Ahmed Bougacha [Fri, 29 Jul 2016 19:19:32 +0000 (19:19 +0000)]
[GlobalISel] Add missing link components to r277160 unittest. NFC.
It broke a shared builder:
http://lab.llvm.org:8011/builders/llvm-mips-linux/builds/17320
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277201
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Simon Pilgrim [Fri, 29 Jul 2016 18:58:57 +0000 (18:58 +0000)]
Fixed line endings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277199
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Simon Pilgrim [Fri, 29 Jul 2016 18:57:32 +0000 (18:57 +0000)]
Fixed (incorrectly firing) MSVC unused variable warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277198
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David Majnemer [Fri, 29 Jul 2016 18:48:27 +0000 (18:48 +0000)]
[ConstantFolding] Handle bitcasts of undef fp vector elements
We used the wrong type for constructing a zero vector element which led
to type mismatches.
This fixes PR28771.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277197
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Kevin Enderby [Fri, 29 Jul 2016 18:46:24 +0000 (18:46 +0000)]
Remove the test/tools/llvm-objdump/malformed-archives.test for
now while I investagate the bot failures with this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277196
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Simon Pilgrim [Fri, 29 Jul 2016 18:43:59 +0000 (18:43 +0000)]
Fixed MSVC out of range shift warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277195
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Zachary Turner [Fri, 29 Jul 2016 18:38:47 +0000 (18:38 +0000)]
Revert "[msf] Rename Msf to MSF."
This reverts commit
4d1557ffac41e079bcb1abbcf04f512474dcd6fe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277194
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Piotr Padlewski [Fri, 29 Jul 2016 18:28:07 +0000 (18:28 +0000)]
Fixing broken MSVS builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277191
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Zachary Turner [Fri, 29 Jul 2016 18:24:26 +0000 (18:24 +0000)]
[msf] Rename Msf to MSF.
In a previous patch, it was suggested to use all caps instead of
rolling caps for initialisms, so this patch changes everything
to do this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277190
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Andrew Kaylor [Fri, 29 Jul 2016 18:23:18 +0000 (18:23 +0000)]
Recommitting r275284: add support to inline __builtin_mempcpy
Patch by Sunita Marathe
Third try, now following fixes to MSan to handle mempcy in such a way that this commit won't break the MSan buildbots. (Thanks, Evegenii!)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277189
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Tim Northover [Fri, 29 Jul 2016 18:11:21 +0000 (18:11 +0000)]
GlobalISel: make translate* functions take the most specialized class possible.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277188
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Kyle Butt [Fri, 29 Jul 2016 18:09:28 +0000 (18:09 +0000)]
Codegen: MachineBlockPlacement Improve probability layout.
The following pattern was being layed out poorly:
A
/ \
B C
/ \ / \
D E ? (Doesn't matter)
Where A->B is far more likely than A->C, and prob(B->D) = prob(B->E)
The current algorithm gives:
A,B,C,E (D goes on worklist)
It does this even if C has a frequency count of 0. This patch
adjusts the layout calculation so that if freq(B->E) >> freq(C->E)
then we go ahead and layout E rather than C. Fallthrough half the time
is better than fallthrough never, or fallthrough very rarely. The
resulting layout is:
A,B,E, (C and D are in a worklist)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277187
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Kyle Butt [Fri, 29 Jul 2016 18:09:25 +0000 (18:09 +0000)]
Tests: Add branch weights to non-layout tests.
Add branch weights to a few tests that aren't testing layout to make them less
sensitive to changes in the layout algorithm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277186
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Tim Northover [Fri, 29 Jul 2016 17:58:00 +0000 (17:58 +0000)]
GlobalISel: add generic conditional branch.
Just the basic equivalent to DAG's condbr for now, we'll get to things like
br_cc when we start doing more legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277184
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Krzysztof Parzyszek [Fri, 29 Jul 2016 17:55:37 +0000 (17:55 +0000)]
[Hexagon] Testcase for not merging stores into a misaligned store
The DAG combiner will try to merge consecutive stores into a bigger
store, unless the resulting store is not fast. Misaligned vector stores
are allowed on Hexagon, but are not fast. Add a testcase to make sure
this type of merging does not occur.
Patch by Pranav Bhandarkar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277182
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Krzysztof Parzyszek [Fri, 29 Jul 2016 17:50:47 +0000 (17:50 +0000)]
Revert r277178, the actual change had already been applied
Will submit another patch with the testcase only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277180
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Krzysztof Parzyszek [Fri, 29 Jul 2016 17:45:16 +0000 (17:45 +0000)]
[Hexagon] Misaligned loads and stores are not fast
The DAG combiner tries to merge stores to adjacent vector wide memory
locations by creating stores which are integral multiples of the vector
width. Discourage this by informing it that this is slow. This should
not affect legalization passes, because all of them ignore the "Fast"
argument.
Patch by Pranav Bhandarkar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277178
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Kevin Enderby [Fri, 29 Jul 2016 17:44:13 +0000 (17:44 +0000)]
The next step along the way to getting good error messages for bad archives.
As mentioned in commit log for r276686 this next step is adding a new
method in the ArchiveMemberHeader class to get the full name that
does proper error checking, and can be use for error messages.
To do this the name of ArchiveMemberHeader::getName() is changed to
ArchiveMemberHeader::getRawName() to be consistent with
Archive::Child::getRawName(). Then the “new” method is the addition
of a new implementation of ArchiveMemberHeader::getName() which gets
the full name and provides proper error checking. Which is mostly a rewrite
of what was Archive::Child::getName() and cleaning up incorrect uses of
llvm_unreachable() in the code which were actually just cases of errors
in the input Archives.
Then Archive::Child::getName() is changed to return Expected<> and use
the new implementation of ArchiveMemberHeader::getName() .
Also needed to change Archive::getMemoryBufferRef() with these
changes to return Expected<> as well to propagate Errors up.
As well as changing Archive::isThinMember() to return Expected<> .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277177
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Tim Northover [Fri, 29 Jul 2016 17:43:52 +0000 (17:43 +0000)]
CodeGen: improve MachineInstrBuilder & MachineIRBuilder interface
For MachineInstrBuilder, having to manually use RegState::Define is ugly and
makes register definitions clunkier than they need to be, so this adds two
convenience functions: addDef and addUse.
For MachineIRBuilder, we want to avoid BuildMI's first-reg-is-def rule because
it's hidden away and causes bugs. So this patch switches buildInstr to
returning a MachineInstrBuilder and adding *all* operands via addDef/addUse.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277176
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Ahmed Bougacha [Fri, 29 Jul 2016 16:56:25 +0000 (16:56 +0000)]
[AArch64][GlobalISel] Select G_XOR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277173
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Ahmed Bougacha [Fri, 29 Jul 2016 16:56:20 +0000 (16:56 +0000)]
[GlobalISel] Add G_XOR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277172
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Ahmed Bougacha [Fri, 29 Jul 2016 16:56:16 +0000 (16:56 +0000)]
[AArch64][GlobalISel] Select G_LOAD/G_STORE.
Mostly straightforward as we ignore addressing modes and just
use the base + unsigned immediate offset (always 0) variants.
This currently fails to select extloads because we have yet to
agree on a representation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277171
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Ahmed Bougacha [Fri, 29 Jul 2016 16:56:12 +0000 (16:56 +0000)]
[GlobalISel] Add LLT raw_ostream operator<< overload.
Helpful when debugging; will be used in the following commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277170
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Brendon Cahoon [Fri, 29 Jul 2016 16:44:44 +0000 (16:44 +0000)]
MachinePipeliner pass that implements Swing Modulo Scheduling
Software pipelining is an optimization for improving ILP by
overlapping loop iterations. Swing Modulo Scheduling (SMS) is
an implementation of software pipelining that attempts to
reduce register pressure and generate efficient pipelines with
a low compile-time cost.
This implementaion of SMS is a target-independent back-end pass.
When enabled, the pass should run just prior to the register
allocation pass, while the machine IR is in SSA form. If the pass
is successful, then the original loop is replaced by the optimized
loop. The optimized loop contains one or more prolog blocks, the
pipelined kernel, and one or more epilog blocks.
This pass is enabled for Hexagon only. To enable for other targets,
a couple of target specific hooks must be implemented, and the
pass needs to be called from the target's TargetMachine
implementation.
Differential Review: http://reviews.llvm.org/D16829
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277169
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Krzysztof Parzyszek [Fri, 29 Jul 2016 16:44:27 +0000 (16:44 +0000)]
[Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVX
If the mask of a vector shuffle has alternating odd or even numbers
starting with 1 or 0 respectively up to the largest possible index
for the given type in the given HVX mode (single of double) we can
generate vpacko or vpacke instruction respectively.
E.g.
%42 = shufflevector <32 x i16> %37, <32 x i16> %41,
<32 x i32> <i32 1, i32 3, ..., i32 63>
is %42.h = vpacko(%41.w, %37.w)
Patch by Pranav Bhandarkar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277168
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Matt Masten [Fri, 29 Jul 2016 16:42:44 +0000 (16:42 +0000)]
Initial support for vectorization using svml (short vector math library).
Differential Revision: https://reviews.llvm.org/D19544
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277166
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Ahmed Bougacha [Fri, 29 Jul 2016 16:11:06 +0000 (16:11 +0000)]
[GlobalISel] Auto-brief LowLevelType. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277163
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Ahmed Bougacha [Fri, 29 Jul 2016 16:11:04 +0000 (16:11 +0000)]
[GlobalISel] Add LLT::operator!=().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277162
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Ahmed Bougacha [Fri, 29 Jul 2016 16:11:02 +0000 (16:11 +0000)]
[GlobalISel] Fix LLT::unsized to match LLT(LabelTy).
When coming from an IR label type, we set a 0 NumElements, but not
when constructing an LLT using unsized(), causing comparisons to fail.
Pick one variant and fix the other.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277161
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Ahmed Bougacha [Fri, 29 Jul 2016 16:10:57 +0000 (16:10 +0000)]
[GlobalISel] Add unittests for LowLevelType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277160
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Paul Robinson [Fri, 29 Jul 2016 16:05:50 +0000 (16:05 +0000)]
Reinstate optnone test for GVN Hoisting, removed in r276479.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277158
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Nirav Dave [Fri, 29 Jul 2016 15:24:06 +0000 (15:24 +0000)]
Remove inline-comment-2.ll until I can debug why it fails on some builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277152
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Krzysztof Parzyszek [Fri, 29 Jul 2016 15:15:35 +0000 (15:15 +0000)]
[Hexagon] Improve balancing of address calculation
Rebalances address calculation trees and applies Hexagon-specific
optimizations to the trees to improve instruction selection.
Patch by Tobias Edler von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277151
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Nirav Dave [Fri, 29 Jul 2016 15:12:00 +0000 (15:12 +0000)]
Fix inline-comment-2.ll triple
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277149
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David L Kreitzer [Fri, 29 Jul 2016 15:09:54 +0000 (15:09 +0000)]
Avoid unnecessary 32-bit to 64-bit zero extensions following
32-bit CMOV instructions on x86_64. The 32-bit CMOV implicitly
zero extends.
Differential Revision: https://reviews.llvm.org/D22941
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277148
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Nirav Dave [Fri, 29 Jul 2016 14:42:00 +0000 (14:42 +0000)]
[MC] When emitting output hash comments always use standard line comment seperator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277146
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Krzysztof Parzyszek [Fri, 29 Jul 2016 14:04:17 +0000 (14:04 +0000)]
Fix license information in the file header
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277145
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Krzysztof Parzyszek [Fri, 29 Jul 2016 13:59:55 +0000 (13:59 +0000)]
Add missing files to r277143
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277144
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Krzysztof Parzyszek [Fri, 29 Jul 2016 13:59:09 +0000 (13:59 +0000)]
[Hexagon] Implement DFA based hazard recognizer
The post register allocator scheduler can generate poor schedules
because the scoreboard hazard recognizer is unable to identify
hazards for Hexagon precisely. Instead, Hexagon should use a DFA
based hazard recognizer.
Patch by Brendon Cahoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277143
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Daniel Sanders [Fri, 29 Jul 2016 12:27:28 +0000 (12:27 +0000)]
Re-commit: [mips][fastisel] Handle 0-4 arguments without SelectionDAG.
Summary:
Implements fastLowerArguments() to avoid the need to fall back on
SelectionDAG for 0-4 argument functions that don't do tricky things like
passing double in a pair of i32's.
This allows us to move all except one test to -fast-isel-abort=3. The
remaining one has function prototypes of the form 'i32 (i32, double, double)'
which requires floats to be passed in GPR's.
The previous commit had an uninitialized variable that caused the incoming
argument region to have undefined size. This has been fixed.
Reviewers: sdardis
Subscribers: dsanders, llvm-commits, sdardis
Differential Revision: https://reviews.llvm.org/D22680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277136
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Nirav Dave [Fri, 29 Jul 2016 11:49:32 +0000 (11:49 +0000)]
Cleanup TransferDbgValues
[DAG] Check debug values for invalidation before transferring and mark
old debug values invalid when transferring to another SDValue.
This fixes PR28613.
Reviewers: jyknight, hans, dblaikie, echristo
Subscribers: yaron.keren, ismail, llvm-commits
Differential Revision: https://reviews.llvm.org/D22858
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277135
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Simon Pilgrim [Fri, 29 Jul 2016 10:23:10 +0000 (10:23 +0000)]
[X86][SSE] Optimize the truncation of vector comparison results with PACKSS
We currently default to using either generic shuffles or MASK+PACKUS/PACKSS to truncate all integer vectors. For vector comparisons, we know that the result will be either all or zero bits in every element, which can be efficiently truncated by directly using PACKSS to repeatedly halve the size of each element.
Due to the limited input values (-1 or 0) we don't need to account for vector element size, so for simplicity we just use the PACKSS(vXi16,vXi16) implementation in all cases. Additionally for AVX2 PACKSS of 256bit data we must perform a PERMQ shuffle to reorder the data into the correct order. I did investigate performing a single shuffle after all the PACKSS calls but the need to cross 128bit lanes makes this difficult to achieve efficiently.
We avoid performing this on AVX512 as it should have better alternative truncation instructions.
Differential Revision: https://reviews.llvm.org/D22814
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277132
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Simon Pilgrim [Fri, 29 Jul 2016 10:03:39 +0000 (10:03 +0000)]
Fixed MSVC out of range shift warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277130
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Sjoerd Meijer [Fri, 29 Jul 2016 09:57:37 +0000 (09:57 +0000)]
Fix for commit rL277126 that broke a build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277129
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Prakhar Bahuguna [Fri, 29 Jul 2016 09:16:46 +0000 (09:16 +0000)]
[Thumb] Emit Thumb move in both Thumb modes for struct_byval predicates
Summary:
The MOV/MOVT instructions being chosen for struct_byval predicates was
conditional only on Thumb2, resulting in an ARM MOV/MOVT instruction
being incorrectly emitted in Thumb1 mode. This is especially apparent
with v8-m.base targets. This patch ensures that Thumb instructions are
emitted in both Thumb modes.
Reviewers: rengolin, t.p.northover
Subscribers: llvm-commits, aemerson, rengolin
Differential Revision: https://reviews.llvm.org/D22865
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277128
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Jacques Pienaar [Fri, 29 Jul 2016 08:50:23 +0000 (08:50 +0000)]
[lanai] Update for Target API (TargetRegistry::RegisterMCAsmBackend) change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277127
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Sjoerd Meijer [Fri, 29 Jul 2016 08:16:16 +0000 (08:16 +0000)]
TargetInstrInfo: add virtual function getInstSizeInBytes
This adds a target hook getInstSizeInBytes to TargetInstrInfo that a lot of
subclasses already implement.
Differential Revision: https://reviews.llvm.org/D22885
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277126
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Craig Topper [Fri, 29 Jul 2016 06:06:04 +0000 (06:06 +0000)]
[AVX512] Mark EVEX VMOVSSrm and VMOVSDrm as canFoldAsLoad and isReMaterializable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277120
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