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Lang Hames [Wed, 26 Sep 2018 02:39:42 +0000 (02:39 +0000)]
[ORC] Add support for multithreaded compiles to LLJIT and LLLazyJIT.
LLJIT and LLLazyJIT can now be constructed with an optional NumCompileThreads
arguments. If this is non-zero then a thread-pool will be created with the
given number of threads, and compile tasks will be dispatched to the thread
pool.
To enable testing of this feature, two new flags are added to lli:
(1) -compile-threads=N (N = 0 by default) controls the number of compile threads
to use.
(2) -thread-entry can be used to execute code on additional threads. For each
-thread-entry argument supplied (multiple are allowed) a new thread will be
created and the given symbol called. These additional thread entry points are
called after static constructors are run, but before main.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343058
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Lang Hames [Wed, 26 Sep 2018 02:01:39 +0000 (02:01 +0000)]
[ORC] Include-what-you-use fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343057
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Lang Hames [Wed, 26 Sep 2018 01:54:13 +0000 (01:54 +0000)]
[ORC] Fix a missing include in r343055.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343056
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Lang Hames [Wed, 26 Sep 2018 01:24:12 +0000 (01:24 +0000)]
[ORC] Add ThreadSafeModule and ThreadSafeContext wrappers to support concurrent
compilation of IR in the JIT.
ThreadSafeContext is a pair of an LLVMContext and a mutex that can be used to
lock that context when it needs to be accessed from multiple threads.
ThreadSafeModule is a pair of a unique_ptr<Module> and a
shared_ptr<ThreadSafeContext>. This allows the lifetime of a ThreadSafeContext
to be managed automatically in terms of the ThreadSafeModules that refer to it:
Once all modules using a ThreadSafeContext are destructed, and providing the
client has not held on to a copy of shared context pointer, the context will be
automatically destructed.
This scheme is necessary due to the following constraits: (1) We need multiple
contexts for multithreaded compilation (at least one per compile thread plus
one to store any IR not currently being compiled, though one context per module
is simpler). (2) We need to free contexts that are no longer being used so that
the JIT does not leak memory over time. (3) Module lifetimes are not
predictable (modules are compiled as needed depending on the flow of JIT'd
code) so there is no single point where contexts could be reclaimed.
JIT clients not using concurrency can safely use one ThreadSafeContext for all
ThreadSafeModules.
JIT clients who want to be able to compile concurrently should use a different
ThreadSafeContext for each module, or call setCloneToNewContextOnEmit on their
top-level IRLayer. The former reduces compile latency (since no clone step is
needed) at the cost of additional memory overhead for uncompiled modules (as
every uncompiled module will duplicate the LLVM types, constants and metadata
that have been shared).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343055
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Vyacheslav Zakharin [Wed, 26 Sep 2018 01:03:21 +0000 (01:03 +0000)]
Remove LoopID metadata from the branch instruction
that follows the peeled iterations.
Differential Revision: https://reviews.llvm.org/D52176
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343054
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Zhaoshi Zheng [Wed, 26 Sep 2018 00:59:09 +0000 (00:59 +0000)]
Revert "Revert "[ConstHoist] Do not rebase single (or few) dependent constant""
This reverts commit
bd7b44f35ee9fbe365eb25ce55437ea793b39346.
Reland r342994: disabled the optimization and explicitly enable it in test.
-mllvm -consthoist-min-num-to-rebase<unsigned>=0
[ConstHoist] Do not rebase single (or few) dependent constant
If an instance (InsertionPoint or IP) of Base constant A has only one or few
rebased constants depending on it, do NOT rebase. One extra ADD instruction is
required to materialize each rebased constant, assuming A and the rebased have
the same materialization cost.
Differential Revision: https://reviews.llvm.org/D52243
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343053
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Thomas Lively [Wed, 26 Sep 2018 00:34:36 +0000 (00:34 +0000)]
[WebAssembly] SIMD conversions
Summary:
Lowers (s|u)itofp and fpto(s|u)i instructions for vectors. The fp to
int conversions produce poison values if their arguments are out of
the convertible range, so a future CL will have to add an LLVM
intrinsic to make the saturating behavior of this conversion usable.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52372
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343052
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Craig Topper [Tue, 25 Sep 2018 23:52:07 +0000 (23:52 +0000)]
[DAGCombiner] Remove unnecessary check for visitSDIVLike/visitUDIVLike returning a UDIVREM or SDIVREM node.
This shouldn't be possible and is a leftover from when we used to recursively call combine here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343049
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Stanislav Mekhanoshin [Tue, 25 Sep 2018 23:33:18 +0000 (23:33 +0000)]
[AMDGPU] Fix ds combine with subregs
Differential Revision: https://reviews.llvm.org/D52522
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343047
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Craig Topper [Tue, 25 Sep 2018 23:28:27 +0000 (23:28 +0000)]
[X86] Allow movmskpd/ps ISD nodes to be created and selected with integer input types.
This removes an int->fp bitcast between the surrounding code and the movmsk. I had already added a hack to combineMOVMSK to try to look through this bitcast to improve the SimplifyDemandedBits there.
But I found an additional issue where the bitcast was preventing combineMOVMSK from being called again after earlier nodes in the DAG are optimized. The bitcast gets revisted, but not the user of the bitcast. By using integer types throughout, the bitcast doesn't get in the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343046
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Craig Topper [Tue, 25 Sep 2018 23:28:24 +0000 (23:28 +0000)]
[X86] Add some more movmsk test cases. NFC
These IR patterns represent the exact behavior of a movmsk instruction using (zext (bitcast (icmp slt X, 0))).
For the v4i32/v8i32/v2i64/v4i64 we currently emit a PCMPGT for the icmp slt which is unnecessary since we only care about the sign bit of the result. This is because of the int->fp bitcast we put on the input to the movmsk nodes for these cases. I'll be fixing this in a future patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343045
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Lang Hames [Tue, 25 Sep 2018 22:57:44 +0000 (22:57 +0000)]
[ORC] Add an asynchronous jit-link function, jitLinkForORC, to RuntimeDyld and
switch RTDyldObjectLinkingLayer2 to use it.
RuntimeDyld::loadObject is currently a blocking operation. This means that any
JIT'd code whose call-graph contains an embedded complete K graph will require
at least K threads to link, which precludes the use of a fixed sized thread
pool for concurrent JITing of arbitrary code (whatever K the thread-pool is set
at, any code with a K+1 complete subgraph will deadlock at JIT-link time).
To address this issue, this commmit introduces a function called jitLinkForORC
that uses continuation-passing style to pass the fix-up and finalization steps
to the asynchronous symbol resolver interface so that linking can be performed
without blocking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343043
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Sanjay Patel [Tue, 25 Sep 2018 22:48:58 +0000 (22:48 +0000)]
[InstCombine] add fneg variation of shuffle-binop fold; NFC
If the fsub in this pattern was replaced by an actual fneg
instruction, we would need to add a fold to recognize that
because fneg would not be a binop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343041
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Changpeng Fang [Tue, 25 Sep 2018 21:21:18 +0000 (21:21 +0000)]
AMDGPU: Add Selection patterns to support add of one bit.
Summary:
We generate s_xor to lower add of i1s in general cases, and s_not to
lower add with a one-bit imm of -1 (true).
Reviewers:
rampitec
Differential Revision:
https://reviews.llvm.org/D52518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343030
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Anna Thomas [Tue, 25 Sep 2018 20:57:20 +0000 (20:57 +0000)]
[LV][LAA] Vectorize loop invariant values stored into loop invariant address
Summary:
We are overly conservative in loop vectorizer with respect to stores to loop
invariant addresses.
More details in https://bugs.llvm.org/show_bug.cgi?id=38546
This is the first part of the fix where we start with vectorizing loop invariant
values to loop invariant addresses.
This also includes changes to ORE for stores to invariant address.
Reviewers: anemet, Ayal, mkuper, mssimpso
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D50665
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343028
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Craig Topper [Tue, 25 Sep 2018 20:55:55 +0000 (20:55 +0000)]
[MCAsmParser] Move AltMacroMode tracking out of MCAsmLexer
The Lexer doesn't use this state itself. It is only set and used by AsmParser so it seems like it should just be part of AsmParser.
Differential Revision: https://reviews.llvm.org/D52515
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343027
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Simon Pilgrim [Tue, 25 Sep 2018 20:52:08 +0000 (20:52 +0000)]
[X86] combineUIntToFP - Fix UINT_TO_FP(vXi1) comment (PR39078)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343026
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Lang Hames [Tue, 25 Sep 2018 20:48:57 +0000 (20:48 +0000)]
Remove 'orc' namespace from MSVCErrorWorkarounds.h, fix some typos that were
breaking windows builds.
The 'orc' namespace was accidentally left in when the workarounds were moved
out of orc in r343011.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343025
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Lang Hames [Tue, 25 Sep 2018 20:16:06 +0000 (20:16 +0000)]
Fix a missing includes and a use of the MSVC promise/future workaround that
were left out of r343011/r343012.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343022
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Teresa Johnson [Tue, 25 Sep 2018 20:14:40 +0000 (20:14 +0000)]
[ThinLTO] Efficiency fix for writing type id records in per-module indexes
Summary:
In D49565/r337503, the type id record writing was fixed so that only
referenced type ids were emitted into each per-module index for ThinLTO
distributed builds. However, this still left an efficiency issue: each
per-module index checked all type ids for membership in the referenced
set, yielding O(M*N) performance (M indexes and N type ids).
Change the TypeIdMap in the summary to be indexed by GUID, to facilitate
correlating with type identifier GUIDs referenced in the function
summary TypeIdInfo structures. This allowed simplifying other
places where a map from type id GUID to type id map entry was previously
being used to aid this correlation.
Also fix AsmWriter code to handle the rare case of type id GUID
collision.
For a large internal application, this reduced the thin link time by
almost 15%.
Reviewers: pcc, vitalybuka
Subscribers: mehdi_amini, inglorion, steven_wu, dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D51330
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343021
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Craig Topper [Tue, 25 Sep 2018 20:13:55 +0000 (20:13 +0000)]
[MC] Return a std::string instead of taking it as an out parameter. Make two parser methods into static functions at file scope. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343020
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Heejin Ahn [Tue, 25 Sep 2018 19:56:44 +0000 (19:56 +0000)]
Unify landing pad information adding routines (NFC)
Summary:
We have `llvm::addLandingPadInfo` and `MachineFunction::addLandingPad`,
both of which add landing pad information to populate `LandingPadInfo`
but are called from different locations, which was confusing. This patch
unifies them with one `MachineFunction::addLandingPad` function, which
now has functionlities of both functions.
Reviewers: rnk
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343018
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Lang Hames [Tue, 25 Sep 2018 19:48:46 +0000 (19:48 +0000)]
[ORC] Reapply r342939 with a fix for MSVC's promise/future restrictions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343012
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Lang Hames [Tue, 25 Sep 2018 19:48:44 +0000 (19:48 +0000)]
Move MSVC workarounds for future<Error>/future<Expected<T>> out of ORC and into
a header in support.
MSVC's std::future implementation requires types to be default constructible,
but Error and Expected are not. This issue came up once before in ORC's
RPCUtils.h header and was worked around there but came up again in r342939, so
I am moving the workaround to Support to make it available to other clients.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343011
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Craig Topper [Tue, 25 Sep 2018 19:37:35 +0000 (19:37 +0000)]
[MC] Fix bad indentation and 80 column violations. Use StringRef::front instead of dereferencing StringRef::begin. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343010
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Sanjay Patel [Tue, 25 Sep 2018 19:09:34 +0000 (19:09 +0000)]
[x86] avoid 256-bit andnp that requires insert/extract with AVX1 (PR37449)
This is the final (I hope!) problem pattern mentioned in PR37749:
https://bugs.llvm.org/show_bug.cgi?id=37749
We are trying to avoid an AVX1 sinkhole caused by having 256-bit bitwise logic ops but no other 256-bit integer ops.
We've already solved the simple logic ops, but 'andn' is an x86 special. I looked at alternative solutions like
extending the generic DAG combine or trying to wait until the ANDNP node is created, but those are bigger patches
that can over-reach. Ie, splitting to 128-bit does not look like a win in most cases with >1 256-bit op.
The pattern matching is cluttered with bitcasts because of our i64 element canonicalization. For the affected test,
we have this vector-type-legalized sequence:
t29: v8i32 = concat_vectors t27, t28
t30: v4i64 = bitcast t29
t18: v8i32 = BUILD_VECTOR Constant:i32<-1>, Constant:i32<-1>, ...
t31: v4i64 = bitcast t18
t32: v4i64 = xor t30, t31
t9: v8i32 = BUILD_VECTOR Constant:i32<255>, Constant:i32<255>, ...
t34: v4i64 = bitcast t9
t35: v4i64 = and t32, t34
t36: v8i32 = bitcast t35
t37: v4i32 = extract_subvector t36, Constant:i64<0>
t38: v4i32 = extract_subvector t36, Constant:i64<4>
Differential Revision: https://reviews.llvm.org/D52318
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343008
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Yury Delendik [Tue, 25 Sep 2018 18:59:34 +0000 (18:59 +0000)]
[WebAssembly] Move/clone DBG_VALUE during WebAssemblyRegStackify pass
Summary:
The MoveForSingleUse or MoveAndTeeForMultiUse functions move wasm instructions,
however DBG_VALUE stay unchanged -- moving or cloning these.
Reviewers: dschuff
Reviewed By: dschuff
Subscribers: mattd, MatzeB, dschuff, sbc100, jgravelle-google, aheejin, sunfish, llvm-commits, aardappel
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D49034
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343007
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Jessica Paquette [Tue, 25 Sep 2018 18:41:40 +0000 (18:41 +0000)]
Revert "[ConstHoist] Do not rebase single (or few) dependent constant"
This caused a couple test failures on a bot:
CodeGen/X86/constant-hoisting-bfi.ll
Transforms/ConstantHoisting/X86/ehpad.ll
Example:
http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental/53575/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343005
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Daniil Fukalov [Tue, 25 Sep 2018 18:37:38 +0000 (18:37 +0000)]
[RegAllocGreedy] avoid using physreg candidates that cannot be correctly spilled
For the AMDGPU target if a MBB contains exec mask restore preamble, SplitEditor may get state when it cannot insert a spill instruction.
E.g. for a MIR
bb.100:
%1 = S_OR_SAVEEXEC_B64 %2, implicit-def $exec, implicit-def $scc, implicit $exec
and if the regalloc will try to allocate a virtreg to the physreg already assigned to virtreg %1, it should insert spill instruction before the S_OR_SAVEEXEC_B64 instruction.
But it is not possible since can generate incorrect code in terms of exec mask.
The change makes regalloc to ignore such physreg candidates.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D52052
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343004
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Craig Topper [Tue, 25 Sep 2018 18:33:00 +0000 (18:33 +0000)]
[MC] Replace NULL constant in code with nullptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343003
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Daniel Sanders [Tue, 25 Sep 2018 17:59:02 +0000 (17:59 +0000)]
[globalisel][tblgen] Table optimization should consider the C++ code in C++ predicates
This fixes PR39045
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342997
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Zhaoshi Zheng [Tue, 25 Sep 2018 17:45:37 +0000 (17:45 +0000)]
[ConstHoist] Do not rebase single (or few) dependent constant
If an instance (InsertionPoint or IP) of Base constant A has only one or few
rebased constants depending on it, do NOT rebase. One extra ADD instruction is
required to materialize each rebased constant, assuming A and the rebased have
the same materialization cost.
Differential Revision: https://reviews.llvm.org/D52243
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342994
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Justin Bogner [Tue, 25 Sep 2018 17:29:30 +0000 (17:29 +0000)]
Revert "[DebugInfo] Do not generate address info for removed debug labels."
The added test is failing on macOS:
http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental/53550/
This reverts r342943.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342993
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Craig Topper [Tue, 25 Sep 2018 16:27:12 +0000 (16:27 +0000)]
[X86] Add AVX512 support to combineVectorSizedSetCCEquality.
Reviewers: spatel, RKSimon
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52424
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342989
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Sanjay Patel [Tue, 25 Sep 2018 15:57:37 +0000 (15:57 +0000)]
[InstCombine] narrow binops on concatenated vectors (PR33026)
The motivating case from:
https://bugs.llvm.org/show_bug.cgi?id=33026
...has no shuffles now. This kind of pattern may occur during
vectorization when targets have lumpy ISAs like SSE/AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342988
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Nirav Dave [Tue, 25 Sep 2018 15:30:47 +0000 (15:30 +0000)]
[ARM] Share predecessor bookkeeping in CombineBaseUpdate. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342987
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Nirav Dave [Tue, 25 Sep 2018 15:30:22 +0000 (15:30 +0000)]
[AArch64] Share search bookkeeping in combines. NFCI.
Share predecessor search bookkeeping in both perform PostLD1Combine
and performNEONPostLDSTCombine. This should be approximately a 4x and
2x performance improvement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342986
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Nirav Dave [Tue, 25 Sep 2018 15:29:57 +0000 (15:29 +0000)]
[LegalizeDAG] Prune Predecessor check in ExpandExtractFromVectorThroughStack. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342985
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Nirav Dave [Tue, 25 Sep 2018 15:29:30 +0000 (15:29 +0000)]
[DAGCombine] Improve Predecessor check in SimplifySelectOps. NFCI.
Reuse search space bookkeeping across multiple predecessor checks
qdone to avoid redundancy. This should cut search cost by ~4x.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342984
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Nirav Dave [Tue, 25 Sep 2018 15:29:04 +0000 (15:29 +0000)]
[DAGCombine] Share predecessor bookkeeping in CombineToPostIndexedLoadStore. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342983
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Guillaume Chatelet [Tue, 25 Sep 2018 15:15:54 +0000 (15:15 +0000)]
[llvm-exegesis] Serializes registers initial values.
Summary: Adds the registers initial values to the YAML output of llvm-exegesis.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52460
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342982
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Guillaume Chatelet [Tue, 25 Sep 2018 14:48:24 +0000 (14:48 +0000)]
[llvm-exegesis] Fix missing document separator in YAML output.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52496
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342981
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Nirav Dave [Tue, 25 Sep 2018 14:43:05 +0000 (14:43 +0000)]
[DAGCombine] Don't fold dependent loads across SELECT_CC.
DAGCombine will try to fold two loads that feed a SELECT or SELECT_CC
after the select, resulting in a select of an address and a single
load after.
If either of the loads depend on the other, this is not legal as it
could introduce cycles. However, it only checked this if the opcode
was a SELECT, and not for a SELECT_CC.
Unfortunately, the only reproducer I have for this is for our
downstream target. I've tried getting it to trigger on an upstream one
but haven't been successful.
Patch thanks to Bevin Hansson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342980
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Clement Courbet [Tue, 25 Sep 2018 13:59:35 +0000 (13:59 +0000)]
[llvm-exegesis] Add lit tests (v2).
Summary: This revisits rL342953 by adding detection of host support.
Reviewers: gchatelet, lebedev.ri, alexshap
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342975
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Guillaume Chatelet [Tue, 25 Sep 2018 13:18:10 +0000 (13:18 +0000)]
[llvm-exegesis] Fix broken test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342971
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Simon Pilgrim [Tue, 25 Sep 2018 13:01:26 +0000 (13:01 +0000)]
Revert rL342916: [X86] Remove shift/rotate by CL memory (RMW) overrides
As suggested by Craig Topper - I'm going to look at cleaning up the RMW sequences instead.
The uops are slightly different to the register variant, so requires a +1uop tweak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342969
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Guillaume Chatelet [Tue, 25 Sep 2018 12:18:08 +0000 (12:18 +0000)]
[llvm-exegesis][NFC] Rewrite of the YAML serialization.
Summary: This is a NFC in preparation of exporting the initial registers as part of the YAML dump
Reviewers: courbet
Reviewed By: courbet
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342967
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Hans Wennborg [Tue, 25 Sep 2018 12:08:56 +0000 (12:08 +0000)]
Revert r342637 "[ADT] Try again to use the same version of llvm::Optional on all compilers"
and also revert follow-ups r342643 and r342723.
This caused Clang to be miscompiled by GCC 4.8.4 (Unbuntu 14.04's
default compiler) and break the Chromium build (see
https://crbug.com/888061).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342966
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David Green [Tue, 25 Sep 2018 10:08:47 +0000 (10:08 +0000)]
[LoopUnroll] Add check to Latch's terminator in UnrollRuntimeLoopRemainder
In this patch, I'm adding an extra check to the Latch's terminator in llvm::UnrollRuntimeLoopRemainder,
similar to how it is already done in the llvm::UnrollLoop.
The compiler would crash if this function is called with a malformed loop.
Patch by Rodrigo Caetano Rocha!
Differential Revision: https://reviews.llvm.org/D51486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342958
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Sameer Sahasrabuddhe [Tue, 25 Sep 2018 09:39:21 +0000 (09:39 +0000)]
[AMDGPU] restore r342722 which was reverted with r342743
[AMDGPU] lower-switch in preISel as a workaround for legacy DA
Summary:
The default target of the switch instruction may sometimes be an
"unreachable" block, when it is guaranteed that one of the cases is
always taken. The dominator tree concludes that such a switch
instruction does not have an immediate post dominator. This confuses
divergence analysis, which is unable to propagate sync dependence to
the targets of the switch instruction.
As a workaround, the AMDGPU target now invokes lower-switch as a
preISel pass. LowerSwitch is designed to handle the unreachable
default target correctly, allowing the divergence analysis to locate
the correct immediate dominator of the now-lowered switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342956
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Clement Courbet [Tue, 25 Sep 2018 09:36:44 +0000 (09:36 +0000)]
Revert rL342953 "[llvm-exegesis] Add lit tests."
We also need to make sure that we're on the right subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342955
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Clement Courbet [Tue, 25 Sep 2018 09:27:43 +0000 (09:27 +0000)]
[llvm-exegesis] Add lit tests.
Summary:
Right now we only have unit tests. This will allow testing the whole
tool. Even though We can't really check actual values, this will avoid
regressions such as PR39055.
Reviewers: gchatelet, alexshap
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52407
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342953
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Heejin Ahn [Tue, 25 Sep 2018 08:25:29 +0000 (08:25 +0000)]
[llvm-exegesis] Add MCParser to LLVM_LINK_COMPONENTS
We need this to make builds with `-DBUILD_SHARED_LIBS=ON` work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342952
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Fangrui Song [Tue, 25 Sep 2018 08:06:32 +0000 (08:06 +0000)]
Add macro LLVM_ATTRIBUTE_REINITIALIZES
Summary:
This marks legitimate use-after-move (e.g. `Found.clear()` in rC342925)
which would otherwise be caught by bugprone-use-after-move.
bugprone-use-after-move recognizes this attribute after rCTE339571.
Reviewers: aaron.ballman, rsmith, mboehme, hokein
Reviewed By: mboehme
Subscribers: kristina, llvm-commits
Differential Revision: https://reviews.llvm.org/D52451
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342949
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Clement Courbet [Tue, 25 Sep 2018 07:48:38 +0000 (07:48 +0000)]
[llvm-exegesis] Fix doc in r342947.
llvm-exegesis.rst was using invalid indentation for bullet points.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342948
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Clement Courbet [Tue, 25 Sep 2018 07:31:44 +0000 (07:31 +0000)]
[llvm-exegesis] Allow benchmarking arbitrary code snippets.
Summary:
This is a step towards fixing PR38048.
Note that right now the measurements are given per instruction. We'll
need to give measurements a per code snippet and update the analysis (PR38731).
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52041
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342947
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Stefan Maksimovic [Tue, 25 Sep 2018 06:27:49 +0000 (06:27 +0000)]
[mips] Correct MUL pattern for mips64
Guard existing pattern with a predicate, introduce a new one for revision 6.
Differential Revision: https://reviews.llvm.org/D51684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342946
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Fangrui Song [Tue, 25 Sep 2018 06:19:31 +0000 (06:19 +0000)]
Use unique_ptr to hold AsmInfo,MRI,MII,STI
Reviewers: pcc, dblaikie
Reviewed By: dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342945
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Mikael Holmen [Tue, 25 Sep 2018 06:10:04 +0000 (06:10 +0000)]
Use TRI->regsOverlap() in MachineBasicBlock::computeRegisterLiveness
Summary:
For the loop that used MCRegAliasIterator this should be NFC.
For the loop that previously used MCSubRegIterator we should
now detect more cases where the register is actually live out that
we previously missed.
Reviewers: MatzeB, arsenm
Reviewed By: MatzeB
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D52410
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342944
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Hsiangkai Wang [Tue, 25 Sep 2018 06:09:50 +0000 (06:09 +0000)]
[DebugInfo] Do not generate address info for removed debug labels.
In some senario, LLVM will remove llvm.dbg.labels in IR. For example,
when the labels are in unreachable blocks, these labels will not
be generated in LLVM IR. In the case, these debug labels will have
address zero as their address. It is not legal address for debugger to
set breakpoints or query sources. So, the patch inhibits the address info
(DW_AT_low_pc) of removed labels.
Differential Revision: https://reviews.llvm.org/D51908
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342943
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Justin Bogner [Tue, 25 Sep 2018 05:16:44 +0000 (05:16 +0000)]
[MachineCopyPropagation] Reimplement CopyTracker in terms of register units
Change the copy tracker to keep a single map of register units instead
of 3 maps of registers. This gives a very significant compile time
performance improvement to the pass. I measured a 30-40% decrease in
time spent in MCP on x86 and AArch64 and much more significant
improvements on out of tree targets with more registers.
Differential Revision: https://reviews.llvm.org/D52374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342942
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Lang Hames [Tue, 25 Sep 2018 04:54:03 +0000 (04:54 +0000)]
Revert "[ORC] Switch to asynchronous resolution in JITSymbolResolver."
This reverts commit r342939.
MSVC's promise/future implementation does not like types that are not default
constructible. Reverting while I figure out a solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342941
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Justin Bogner [Tue, 25 Sep 2018 04:45:25 +0000 (04:45 +0000)]
[MachineCopyPropagation] Rework how we manage RegMask clobbers
Instead of updating the CopyTracker's maps each time we come across a
RegMask, defer checking for this kind of interference until we're
actually trying to propagate a copy. This avoids the need to
repeatedly iterate over maps in the cases where we don't end up doing
any work.
This is a slight compile time improvement for MachineCopyPropagation
as is, but it also enables a much bigger improvement that I'll follow
up with soon.
Differential Revision: https://reviews.llvm.org/D52370
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342940
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Lang Hames [Tue, 25 Sep 2018 04:43:38 +0000 (04:43 +0000)]
[ORC] Switch to asynchronous resolution in JITSymbolResolver.
Asynchronous resolution (where the caller receives a callback once the requested
set of symbols are resolved) is a core part of the new concurrent ORC APIs. This
change extends the asynchronous resolution model down to RuntimeDyld, which is
necessary to prevent deadlocks when compiling/linking on a fixed number of
threads: If RuntimeDyld's linking process were a blocking operation, then any
complete K-graph in a program will require at least K threads to link in the
worst case, as each thread would block waiting for all the others to complete.
Using callbacks instead allows the work to be passed between dependent threads
until it is complete.
For backwards compatibility, all existing RuntimeDyld functions will continue
to operate in blocking mode as before. This change will enable the introduction
of a new async finalization process in a subsequent patch to enable asynchronous
JIT linking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342939
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Thomas Lively [Tue, 25 Sep 2018 03:39:28 +0000 (03:39 +0000)]
[WebAssembly] SIMD sqrt
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342937
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Stanislav Mekhanoshin [Tue, 25 Sep 2018 01:24:54 +0000 (01:24 +0000)]
[AMDGPU] Remove useless check from test. NFC.
The check for assignment of zero is practically useless
while the assignment moves around with different scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342935
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Craig Topper [Tue, 25 Sep 2018 00:16:57 +0000 (00:16 +0000)]
[X86] Don't create FILD ISD nodes when X87 is disabled.
The included test case previously asserted because the type legalizer tried to soften the FILD ISD node.
Fixes PR38819.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342934
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Craig Topper [Tue, 25 Sep 2018 00:16:54 +0000 (00:16 +0000)]
[X86] Remove superfluous curly braces. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342933
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Craig Topper [Tue, 25 Sep 2018 00:16:52 +0000 (00:16 +0000)]
[X86] Update comment. Use 'glued' instead of 'flagged' NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342932
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Thomas Lively [Mon, 24 Sep 2018 23:42:07 +0000 (23:42 +0000)]
[WebAssembly][NFC] Fix hardcoded stack indices in tests
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52388
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342928
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Artem Belevich [Mon, 24 Sep 2018 23:10:44 +0000 (23:10 +0000)]
[CUDA] Added basic support for compiling with CUDA-10.0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342924
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Evgeniy Stepanov [Mon, 24 Sep 2018 23:03:34 +0000 (23:03 +0000)]
[hwasan] Record and display stack history in stack-based reports.
Summary:
Display a list of recent stack frames (not a stack trace!) when
tag-mismatch is detected on a stack address.
The implementation uses alignment tricks to get both the address of
the history buffer, and the base address of the shadow with a single
8-byte load. See the comment in hwasan_thread_list.h for more
details.
Developed in collaboration with Kostya Serebryany.
Reviewers: kcc
Subscribers: srhines, kubamracek, mgorny, hiraditya, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D52249
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342923
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Evgeniy Stepanov [Mon, 24 Sep 2018 22:50:32 +0000 (22:50 +0000)]
Revert "[hwasan] Record and display stack history in stack-based reports."
This reverts commit r342921: test failures on clang-cmake-arm* bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342922
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Evgeniy Stepanov [Mon, 24 Sep 2018 21:38:42 +0000 (21:38 +0000)]
[hwasan] Record and display stack history in stack-based reports.
Summary:
Display a list of recent stack frames (not a stack trace!) when
tag-mismatch is detected on a stack address.
The implementation uses alignment tricks to get both the address of
the history buffer, and the base address of the shadow with a single
8-byte load. See the comment in hwasan_thread_list.h for more
details.
Developed in collaboration with Kostya Serebryany.
Reviewers: kcc
Subscribers: srhines, kubamracek, mgorny, hiraditya, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D52249
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342921
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Christy Lee [Mon, 24 Sep 2018 20:47:12 +0000 (20:47 +0000)]
Re-submitting changes in D51550 because it failed to patch.
Reviewers: javed.absar, trentxintong, courbet
Reviewed By: trentxintong
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342919
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Sanjay Patel [Mon, 24 Sep 2018 20:41:22 +0000 (20:41 +0000)]
[InstCombine] add bitcast+extelt helper function; NFC
We can handle patterns where the elements have different
sizes, so refactoring ahead of trying to add another blob
within these clauses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342918
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Simon Pilgrim [Mon, 24 Sep 2018 20:11:50 +0000 (20:11 +0000)]
[X86] Remove shift/rotate by CL memory (RMW) overrides
The uops are slightly different to the register variant, so requires a +1uop tweak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342916
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Craig Topper [Mon, 24 Sep 2018 18:55:41 +0000 (18:55 +0000)]
[X86] Infer 64bit feature support from the CPUID results in getHostCPUFeatures.
After r341022, we more strictly check the 64bit feature in X86Subtargets constructor when a 64-bit triple is used. If we don't infer this feature for autodetected CPUs we might incorrectly report an error if the CPU name wasn't autodetected to a CPU that supports 64-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342914
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Stefan Pintilie [Mon, 24 Sep 2018 18:14:13 +0000 (18:14 +0000)]
[Power9] [LLVM] Add __float128 exponent GET and SET builtins
Added
__builtin_vsx_scalar_extract_expq
__builtin_vsx_scalar_insert_exp_qp
Builtins should behave the same way as in GCC.
Differential Revision: https://reviews.llvm.org/D48185
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342910
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Simon Pilgrim [Mon, 24 Sep 2018 17:26:31 +0000 (17:26 +0000)]
[X86][AVX] Add truncation as shuffle test for PR31451
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342908
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Christy Lee [Mon, 24 Sep 2018 17:26:30 +0000 (17:26 +0000)]
Reland r342494 after fixing LIT checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342907
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Sanjay Patel [Mon, 24 Sep 2018 17:18:32 +0000 (17:18 +0000)]
[Analysis] add comment to generalize finding a scalar op from vector; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342906
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Sanjay Patel [Mon, 24 Sep 2018 17:17:16 +0000 (17:17 +0000)]
[InstCombine] add/move tests for extractelement; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342905
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Simon Pilgrim [Mon, 24 Sep 2018 16:58:26 +0000 (16:58 +0000)]
[X86] Remove WriteDiv/WriteIDiv schedule overrides - use classes directly. NFCI.
We're missing quite a bit of data for these instruction, removing the overrides makes this obvious - inconsistent reg/mem variants is a concern as well.
Also, we have Divider resources (HWDivider etc.) but they aren't actually used consistently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342904
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Sanjay Patel [Mon, 24 Sep 2018 16:39:03 +0000 (16:39 +0000)]
[InstCombine] improve variable name and use 'match'; NFC
'width' of a vector usually refers to the bit-width.
https://bugs.llvm.org/show_bug.cgi?id=39016
shows a case where we could extend this fold to handle
a case where the number of elements in the bitcasted
vector is not equal to the resulting value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342902
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Evandro Menezes [Mon, 24 Sep 2018 16:35:14 +0000 (16:35 +0000)]
[ARM] Adjust the cost model for Exynos
Tune `MaxInterleaveFactor` and `LdStMultipleTiming`and remove
`PartialUpdateClearance` for the Exynos processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342900
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Evandro Menezes [Mon, 24 Sep 2018 16:35:09 +0000 (16:35 +0000)]
[ARM] Adjust the feature set for Exynos
Enable crypto and literals fusion for the Exynos processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342899
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Zhaoshi Zheng [Mon, 24 Sep 2018 16:15:23 +0000 (16:15 +0000)]
[Thumb1] Any imm8 should have cost of 1
A simple MOVS rd, imm8 can materialize [-128, 127] in signed i8 type or
[0, 255] in unsigned i8 type on Thumb1.
Differential Revision: https://reviews.llvm.org/D52257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342898
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Fedor Sergeev [Mon, 24 Sep 2018 16:08:15 +0000 (16:08 +0000)]
[New PM][PassInstrumentation] IR printing support for New Pass Manager
Implementing -print-before-all/-print-after-all/-filter-print-func support
through PassInstrumentation callbacks.
- PrintIR routines implement printing callbacks.
- StandardInstrumentations class provides a central place to manage all
the "standard" in-tree pass instrumentations. Currently it registers
PrintIR callbacks.
Reviewers: chandlerc, paquette, philip.pfaffe
Differential Revision: https://reviews.llvm.org/D50923
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342896
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Simon Pilgrim [Mon, 24 Sep 2018 15:21:57 +0000 (15:21 +0000)]
[X86] Split WriteIMul into 8/16/32/64 implementations (PR36931)
Split WriteIMul by size and also by IMUL multiply-by-imm and multiply-by-reg cases.
This removes all the scheduler overrides for gpr multiplies and stops WriteMULH being ignored for BMI2 MULX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342892
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Luke Cheeseman [Mon, 24 Sep 2018 15:13:48 +0000 (15:13 +0000)]
[Arm][AsmParser] Restrict register list size for VSTM/VLDM
- The assembler accepts VSTM/VLDM with register lists (specifically double registers lists) with more than 16 registers specified
- The Arm architecture reference manual says this instruction must not contain more than 16 registers when the registers are doubleword registers
- This addresses one of the concerns in https://bugs.llvm.org/show_bug.cgi?id=38389
Differential Revision: https://reviews.llvm.org/D52082
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342891
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Sanjay Patel [Mon, 24 Sep 2018 14:47:15 +0000 (14:47 +0000)]
[DAGCombiner] use UADDO to optimize saturated unsigned add
This is a preliminary step towards solving PR14613:
https://bugs.llvm.org/show_bug.cgi?id=14613
If we have an 'add' instruction that sets flags, we can use that to eliminate an
explicit compare instruction or some other instruction (cmn) that sets flags for
use in the later select.
As shown in the unchanged tests that use 'icmp ugt %x, %a', we're effectively
reversing an IR icmp canonicalization that replaces a variable operand with a
constant:
https://rise4fun.com/Alive/V1Q
But we're not using 'uaddo' in those cases via DAG transforms. This happens in
CGP after D8889 without checking target lowering to see if the op is supported.
So AArch already shows 'uaddo' codegen for the i8/i16/i32/i64 test variants with
"using_cmp_sum" in the title. That's the pattern that CGP matches as an unsigned
saturated add and converts to uaddo without checking target capabilities.
This patch is gated by isOperationLegalOrCustom(ISD::UADDO, VT), so we see only
see AArch diffs for i32/i64 in the tests with "using_cmp_notval" in the title
(unlike x86 which sees improvements for all sizes because all sizes are 'custom').
But the AArch code (like x86) looks better when translated to 'uaddo' in all cases.
So someone that is involved with AArch may want to set i8/i16 to 'custom' for UADDO,
so this patch will fire on those tests.
Another possibility given the existing behavior: we could remove the legal-or-custom
check altogether because we're assuming that a UADDO sequence is canonical/optimal
before we ever reach here. But that seems like a bug to me. If the target doesn't
have an add-with-flags op, then it's not likely that we'll get optimal DAG combining
using a UADDO node. This is similar justification for why we don't canonicalize IR to
the overflow math intrinsic sibling (llvm.uadd.with.overflow) for UADDO in the first
place.
Differential Revision: https://reviews.llvm.org/D51929
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342886
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Petar Jovanovic [Mon, 24 Sep 2018 14:14:19 +0000 (14:14 +0000)]
[Mips][FastISel] Fix selectBranch on icmp i1
The r337288 tried to fix result of icmp i1 when its input is not sanitized
by falling back to DagISel. While it now produces the correct result for
bit 0, the other bits can still hold arbitrary value which is not supported
by MipsFastISel branch lowering. This patch fixes the issue by falling back
to DagISel in this case.
Patch by Dragan Mladjenovic.
Differential Revision: https://reviews.llvm.org/D52045
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342884
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Zaara Syeda [Mon, 24 Sep 2018 14:01:16 +0000 (14:01 +0000)]
[PowerPC] Support operand modifier 'x' in inline asm
gcc uses operand modifier 'x' in inline asm for VSX registers.
Without this modifier, instructions which use VSX numbering for their
operands are printed as VMX registers. This patch adds support for the
operand modifier 'x'.
Differential Revision: https://reviews.llvm.org/D52244
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342882
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Jonas Devlieghere [Mon, 24 Sep 2018 13:56:36 +0000 (13:56 +0000)]
[dsymutil] Set LSan blacklist whenever sanitizers are enabled.
LSan can be enabled by itself or as part of the address sanitizer.
Rather than checking the enabled sanitizers for both, just set the LSan
env options whenever a sanitizer is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342881
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Roman Lebedev [Mon, 24 Sep 2018 13:24:20 +0000 (13:24 +0000)]
[NFC][CodeGen][X86][AArch64] More tests for 'bit field extract' w/ constants
It would be best to introduce ISD::BitFieldExtract,
because clearly more than one backend faces the same problem.
But for now let's solve this in the x86-specific DAG combine.
https://bugs.llvm.org/show_bug.cgi?id=38938
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342880
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Matt Arsenault [Mon, 24 Sep 2018 13:18:15 +0000 (13:18 +0000)]
AMDGPU: Fix private handling for allowsMisalignedMemoryAccesses
If the alignment is at least 4, this should report true.
Something still seems off with how < 4-byte types are
handled here though.
Fixing this seems to change how some combines get
to where they get, but somehow isn't changing the net
result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342879
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Matt Arsenault [Mon, 24 Sep 2018 12:47:17 +0000 (12:47 +0000)]
Fix some missing opcodes in bcanalyzer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342878
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Andrea Di Biagio [Mon, 24 Sep 2018 12:45:26 +0000 (12:45 +0000)]
[llvm-mca] Improve code comments in LSUnit.{h, cpp}. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342877
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Sjoerd Meijer [Mon, 24 Sep 2018 12:02:50 +0000 (12:02 +0000)]
[ARM] Do not fuse VADD and VMUL on the Cortex-M4 and Cortex-M33
A sequence of VMUL and VADD instructions always give the same or better
performance than a fused VMLA instruction on the Cortex-M4 and Cortex-M33.
Executing the VMUL and VADD back-to-back requires the same cycles, but
having separate instructions allows scheduling to avoid the hazard between
these 2 instructions.
Differential Revision: https://reviews.llvm.org/D52289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342874
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