OSDN Git Service
Chad Rosier [Fri, 1 Apr 2016 17:34:38 +0000 (17:34 +0000)]
[AArch64] Fix a typo. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265160
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David Majnemer [Fri, 1 Apr 2016 17:28:17 +0000 (17:28 +0000)]
[InstCombine] Don't sink an instr after a catchswitch
A catchswitch is a terminator, instructions cannot be inserted after it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265158
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David Majnemer [Fri, 1 Apr 2016 17:28:15 +0000 (17:28 +0000)]
[SLPVectorizer] Don't insert an extractelement before a catchswitch
A catchswitch cannot be preceded by another instruction in the same
basic block (other than a PHI node).
Instead, insert the extract element right after the materialization of
the vectorized value. This isn't optimal but is a reasonable compromise
given the constraints of WinEH.
This fixes PR27163.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265157
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Rong Xu [Fri, 1 Apr 2016 16:43:30 +0000 (16:43 +0000)]
[PGO] Refactor PGOFuncName meta data code to be used in clang
Refactor the code that gets and creates PGOFuncName meta data so that it can be
used in clang's value profile annotation.
Differential Revision: http://reviews.llvm.org/D18623
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265149
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Sanjay Patel [Fri, 1 Apr 2016 16:27:14 +0000 (16:27 +0000)]
[x86] avoid intermediate splat for non-zero memsets (PR27100)
Follow-up to D18566 - where we noticed that an intermediate splat was being
generated for memsets of non-zero chars.
That was because we told getMemsetStores() to use a 32-bit vector element type,
and it happily obliged by producing that constant using an integer multiply.
The tests that were added in the last patch are now equivalent for AVX1 and AVX2
(no splats, just a vector load), but we have PR27141 to track that splat difference.
In the new tests, the splat via shuffling looks ok to me, but there might be some
room for improvement depending on uarch there.
Note that the SSE1/2 paths are not changed in this patch. That can be a follow-up.
This patch should resolve PR27100.
Differential Revision: http://reviews.llvm.org/D18676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265148
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Benjamin Kramer [Fri, 1 Apr 2016 15:51:51 +0000 (15:51 +0000)]
[ADT] Make StringMap's tombstone aligned.
This avoids undefined behavior when casting pointers to it. Also make
sure that we don't cast to a derived StringMapEntry before checking for
tombstone, as that may have different alignment requirements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265145
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Vedant Kumar [Fri, 1 Apr 2016 15:45:33 +0000 (15:45 +0000)]
[PGOProfile] Rename a test to make it more reusable, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265144
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Valery Pykhtin [Fri, 1 Apr 2016 13:13:12 +0000 (13:13 +0000)]
[AMDGPU] fix MADAK/MADMK instructions operand namings to match encoding fields.
$vsrc1 -> $src1, $k -> $imm
Differential Revision: http://reviews.llvm.org/D18659
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265141
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Andrea Di Biagio [Fri, 1 Apr 2016 12:25:44 +0000 (12:25 +0000)]
[x86] Remove redundant call to setTargetDAGCombine for BUILD_VECTOR node type.
Since revision 235394, we no longer perform target specific combines on
build_vector nodes. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265138
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Simon Pilgrim [Fri, 1 Apr 2016 11:57:51 +0000 (11:57 +0000)]
[X86][AVX512] Regenerated intrinsics tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265135
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Sagar Thakur [Fri, 1 Apr 2016 11:55:33 +0000 (11:55 +0000)]
[MIPS][LLVM-MC] Fix JR encoding for MIPSR6 ISA
Summary: The assembler was picking the wrong JR variant because the pre-R6 one was still enabled at R6.
Author: nitesh.jain
Reviewers: vkalintiris, dsanders
Subscribers: dsanders, llvm-commits, mohit.bhakkad, sagar, bhushan, jaydeep
Differential: D18387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265134
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Benjamin Kramer [Fri, 1 Apr 2016 11:49:59 +0000 (11:49 +0000)]
[ThinLTO] Fix uninitialized flags.
Found by msan. Patch by Adrian Kuegel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265133
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Andrey Turetskiy [Fri, 1 Apr 2016 10:16:15 +0000 (10:16 +0000)]
[X86] Introduce Lakemont CPU.
Add a new Intel MCU CPU Lakemont, which doesn't support X87.
Differential Revision: http://reviews.llvm.org/D18650
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265128
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James Molloy [Fri, 1 Apr 2016 09:40:47 +0000 (09:40 +0000)]
Fix for pr24346: arm asm label calculation error in sub
Some ARM instructions encode 32-bit immediates as a 8-bit integer (0-255)
and a 4-bit rotation (0-30, even) in its least significant 12 bits. The
original fixup, FK_Data_4, patches the instruction by the value bit-to-bit,
regardless of the encoding. For example, assuming the label L1 and L2 are
0x0 and 0x104 respectively, the following instruction:
add r0, r0, #(L2 - L1) ; expects 0x104, i.e., 260
would be assembled to the following, which adds 1 to r0, instead of 260:
e2800104 add r0, r0, #4, 2 ; equivalently 1
The new fixup kind fixup_arm_mod_imm takes care of the encoding:
e2800f41 add r0, r0, #260
Patch by Ting-Yuan Huang!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265122
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Oliver Stannard [Fri, 1 Apr 2016 09:14:50 +0000 (09:14 +0000)]
[AArch64] Better errors for out-of-range fixups
When a fixup that can be resolved by the assembler is out of range, we should
report an error in the source, rather than crashing.
Differential Revision: http://reviews.llvm.org/D18402
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265120
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Mehdi Amini [Fri, 1 Apr 2016 08:22:59 +0000 (08:22 +0000)]
ThinLTO: move ObjCARCContractPass in the CodeGen pipeline
This is to be coherent with Full LTO.
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265118
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Jeroen Ketema [Fri, 1 Apr 2016 07:56:17 +0000 (07:56 +0000)]
[OCaml] Use LLVMCreateMessage with constant strings when calling llvm_raise
The llvm_string_of_message function, called by llvm_raise, calls
LLVMDisposeMessage, which expects the message to be dynamically
allocated; it fails freeing the message otherwise. So always
dynamically allocate with LLVMCreateMessage.
Differential Revision: http://reviews.llvm.org/D18675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265116
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Jeroen Ketema [Fri, 1 Apr 2016 07:54:24 +0000 (07:54 +0000)]
[OCaml] Reinstate data_layout
Expose LLVMCreateTargetMachineData as data_layout.
As r263530 did for go. From that commit: "LLVMGetTargetDataLayout was
removed from the C API, and then TargetMachine.TargetData was removed.
Later, LLVMCreateTargetMachineData was added to the C API"
Differential Revision: http://reviews.llvm.org/D18677
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265115
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Mehdi Amini [Fri, 1 Apr 2016 06:47:02 +0000 (06:47 +0000)]
Add a libLTO API to stop/restart ThinLTO between optimizations and CodeGen
This allows the linker to instruct ThinLTO to perform only the
optimization part or only the codegen part of the process.
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265113
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Chuang-Yu Cheng [Fri, 1 Apr 2016 06:44:32 +0000 (06:44 +0000)]
[PPC64] Bug fix: when enabling sibling-call-opt and shrink-wrapping, the tail call branch instruction might disappear
Bug Pattern:
# BB#0: # %entry
cmpldi 3, 0
beq- 0, .LBB0_2
# BB#1: # %exit
lwz 4, 0(3)
#TC_RETURNd8 LVComputationKind 0
.LBB0_2: # %cond.false
mflr 0
std 0, 16(1)
stdu 1, -96(1)
.Ltmp0:
.cfi_def_cfa_offset 96
.Ltmp1:
.cfi_offset lr, 16
bl __assert_fail
nop
The branch instruction for tail call return is not generated, because the
shrink-wrapping pass choosing a new Restore Point: %cond.false, so %exit
block is not sent to emitEpilogue, that's why the branch is not generated.
Thanks Kit's opinions!
Reviewers: nemanjai hfinkel tjablin kbarton
http://reviews.llvm.org/D17606
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265112
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Mehdi Amini [Fri, 1 Apr 2016 05:33:11 +0000 (05:33 +0000)]
Add a module Hash in the bitcode and the combined index, implementing a kind of "build-id"
This is intended to be used for ThinLTO incremental build.
Differential Revision: http://reviews.llvm.org/D18213
This is a recommit of r265095 after fixing the Windows issues.
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265111
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Mehdi Amini [Fri, 1 Apr 2016 05:19:14 +0000 (05:19 +0000)]
Fix MSVC warning "comparison of integers of different signs" (NFC)
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265110
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Mehdi Amini [Fri, 1 Apr 2016 05:12:24 +0000 (05:12 +0000)]
Fix S390 big endian detection
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265109
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Mehdi Amini [Fri, 1 Apr 2016 05:12:18 +0000 (05:12 +0000)]
Const correctness in raw_sha1_ostream (NFC)
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265108
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Mehdi Amini [Fri, 1 Apr 2016 04:30:16 +0000 (04:30 +0000)]
Add support for computing SHA1 in LLVM
Provide a class to generate a SHA1 from a sequence of bytes, and
a convenience raw_ostream adaptor.
This will be used to provide a "build-id" by hashing the Module
block when writing bitcode. ThinLTO will use this information for
incremental build.
Reapply r265094 which was reverted in r265102 because it broke
MSVC bots (constexpr is not supported).
http://reviews.llvm.org/D16325
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265107
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Sean Silva [Fri, 1 Apr 2016 03:54:03 +0000 (03:54 +0000)]
Improve CHECK-NOT robustness of dllexport tests
This changes some dllexport tests, to verify that some symbols that
should not be exported are not, in a way that improves the robustness
of CHECK-SAME interaction with CHECK-NOT.
We plan to enable dllimport/dllexport support for the PS4, and these
changes are for points we noticed in our internal testing.
Patch by Warren Ristow!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265106
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Michael Kuperstein [Fri, 1 Apr 2016 03:45:08 +0000 (03:45 +0000)]
Use range-based for loops. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265105
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Mehdi Amini [Fri, 1 Apr 2016 03:03:21 +0000 (03:03 +0000)]
Revert "Add support for computing SHA1 in LLVM"
This reverts commit r265096, r265095, and r265094.
Windows build is broken, and the validation does not pass.
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265102
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Sanjoy Das [Fri, 1 Apr 2016 02:51:30 +0000 (02:51 +0000)]
Don't insert stackrestore on deoptimizing returns
They're not necessary (since the stack pointer is trivially restored on
return), and the way LLVM inserts the stackrestore calls breaks the
IR (we get a stackrestore between the deoptimize call and the return).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265101
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Sanjoy Das [Fri, 1 Apr 2016 02:51:26 +0000 (02:51 +0000)]
Don't insert lifetime end markers on deoptimizing returns
They're not necessary (since the lifetime of the alloca is trivially
over due to the return), and the way LLVM inserts the lifetime.end
markers breaks the IR (we get a lifetime end marker between the
deoptimize call and the return).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265100
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Sanjoy Das [Fri, 1 Apr 2016 02:51:21 +0000 (02:51 +0000)]
Don't use an i64 return type with webkit_jscc
Re-enable an assertion enabled by Justin Lebar in rL265092. rL265092
was breaking test/CodeGen/X86/deopt-intrinsic.ll because webkit_jscc
does not like non-i64 return types. Change the test case to not do
that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265099
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Matthias Braun [Fri, 1 Apr 2016 02:49:17 +0000 (02:49 +0000)]
AArch64ISelLowering: Remove unused variables/arguments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265098
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Chuang-Yu Cheng [Fri, 1 Apr 2016 02:05:29 +0000 (02:05 +0000)]
Fix Sub-register Rewriting in Aggressive Anti-Dependence Breaker
Previously, HandleLastUse would delete RegRef information for sub-registers
if they were dead even if their corresponding super-register were still live.
If the super-register were later renamed, then the definitions of the
sub-register would not be updated appropriately. This patch alters the
behavior so that RegInfo information for sub-registers is only deleted when
the sub-register and super-register are both dead.
This resolves PR26775. This is the mirror image of Hal's r227311 commit.
Author: Tom Jablin (tjablin)
Reviewers: kbarton uweigand nemanjai hfinkel
http://reviews.llvm.org/D18448
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265097
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Mehdi Amini [Fri, 1 Apr 2016 01:37:52 +0000 (01:37 +0000)]
Add missing test for the "Module hash in bitcode" added in r265095
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265096
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Mehdi Amini [Fri, 1 Apr 2016 01:30:06 +0000 (01:30 +0000)]
Add a module Hash in the bitcode and the combined index, implementing a kind of "build-id"
This is intended to be used for ThinLTO incremental build.
Differential Revision: http://reviews.llvm.org/D18213
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265095
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Mehdi Amini [Fri, 1 Apr 2016 01:29:54 +0000 (01:29 +0000)]
Add support for computing SHA1 in LLVM
Provide a class to generate a SHA1 from a sequence of bytes, and
a convenience raw_ostream adaptor.
This will be used to provide a "build-id" by hashing the Module
block when writing bitcode. ThinLTO will use this information for
incremental build.
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265094
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Justin Lebar [Fri, 1 Apr 2016 01:23:23 +0000 (01:23 +0000)]
Revert "Protect some assertions with NDEBUG rather than DEBUG()."
This reverts r265092, because it breaks CodeGen/X86/deopt-intrinsic.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265093
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Justin Lebar [Fri, 1 Apr 2016 01:09:12 +0000 (01:09 +0000)]
Protect some assertions with NDEBUG rather than DEBUG().
DEBUG() only runs if you pass -debug, but these assertions are generally
useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265092
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Justin Lebar [Fri, 1 Apr 2016 01:09:10 +0000 (01:09 +0000)]
[NVPTX] Add a truncate DAG node to some calls.
Summary:
Previously, we were running afoul of the assertion
EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && "LowerCall emitted a value with the wrong type!"
in SelectionDAGBuilder.cpp when running the NVPTX/i8-param.ll test.
This is because our backend (for some reason) treats small return values
as i32, but it wasn't ever truncating the i32 back down to the expected
width in the DAG.
Unclear to me whether this fixes any actual bugs -- in this test, at
least, the generated code is unchanged.
Reviewers: jingyue
Subscribers: llvm-commits, tra, jholewinski
Differential Revision: http://reviews.llvm.org/D17872
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265091
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Justin Lebar [Fri, 1 Apr 2016 01:09:07 +0000 (01:09 +0000)]
[NVPTX] Read __CUDA_FTZ from module flags in NVVMReflect.
Summary:
Previously the NVVMReflect pass would read its configuration from
command-line flags or a static configuration given to the pass at
instantiation time.
This doesn't quite work for clang's use-case. It needs to pass a value
for __CUDA_FTZ down on a per-module basis. We use a module flag for
this, so the NVVMReflect pass needs to be updated to read said flag.
Reviewers: tra, rnk
Subscribers: cfe-commits, jholewinski
Differential Revision: http://reviews.llvm.org/D18672
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265090
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Justin Lebar [Fri, 1 Apr 2016 01:09:05 +0000 (01:09 +0000)]
[NVPTX] Annotate some instructions as hasSideEffects = 0.
Summary:
Tablegen tries to infer this from the selection DAG patterns defined for
the instructions, but it can't always.
An instructive example is CLZr64. CLZr32 is correctly inferred to have
no side-effects, but the selection DAG pattern for CLZr64 is slightly
more complicated, and in particular the ctlz DAG node is not at the root
of the pattern. Thus tablegen can't infer that CLZr64 has no
side-effects.
Reviewers: jholewinski
Subscribers: jholewinski, tra, llvm-commits
Differential Revision: http://reviews.llvm.org/D17472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265089
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Justin Lebar [Fri, 1 Apr 2016 01:09:03 +0000 (01:09 +0000)]
[ifcnv] Add brief comment explaining what ifcnv is.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265088
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Mehdi Amini [Fri, 1 Apr 2016 00:52:05 +0000 (00:52 +0000)]
Fix Windows build (typo in disk_space() implementation)
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265087
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Akira Hatanaka [Fri, 1 Apr 2016 00:34:39 +0000 (00:34 +0000)]
[LoopVectorize] Don't unconditionally print vectorization diagnostics
when compiling with LTO.
r244523 a new class DiagnosticInfoOptimizationRemarkAnalysisAliasing for
optimization analysis remarks related to pointer aliasing without
guarding it in isDiagnosticEnabled in LLVMContext.cpp. This caused the
diagnostic message to be printed unconditionally when compiling with
LTO.
This commit cleans up isDiagnosticEnabled and makes sure all the
vectorization optimization remarks are guarded.
rdar://problem/
25382153
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265084
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Mehdi Amini [Fri, 1 Apr 2016 00:18:08 +0000 (00:18 +0000)]
Add disk_space() to llvm::fs
Summary: Adapted from Boost::filesystem.
(This is a reapply by reverting commit r265080 and fixing the WinAPI part)
Differential Revision: http://reviews.llvm.org/D18467
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265082
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Adrian Prantl [Fri, 1 Apr 2016 00:16:49 +0000 (00:16 +0000)]
testcase gardening: update the emissionKind enum to the new syntax. (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265081
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Mehdi Amini [Fri, 1 Apr 2016 00:13:31 +0000 (00:13 +0000)]
Revert "Add disk_space() to llvm::fs"
This reverts commit r265074 and r265068.
Breaks windows build
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265080
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Adrian Prantl [Fri, 1 Apr 2016 00:00:27 +0000 (00:00 +0000)]
Fix a captialization error in r265077.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265079
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Adrian Prantl [Thu, 31 Mar 2016 23:56:58 +0000 (23:56 +0000)]
Move the DebugEmissionKind enum from DIBuilder into DICompileUnit.
This mostly cosmetic patch moves the DebugEmissionKind enum from DIBuilder
into DICompileUnit. DIBuilder is not the right place for this enum to live
in — a metadata consumer should not have to include DIBuilder.h.
I also added a Verifier check that checks that the emission kind of a
DICompileUnit is actually legal.
http://reviews.llvm.org/D18612
<rdar://problem/
25427165>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265077
91177308-0d34-0410-b5e6-
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Hans Wennborg [Thu, 31 Mar 2016 23:55:16 +0000 (23:55 +0000)]
Follow-up to r265036: I got these iterators mixed up
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265076
91177308-0d34-0410-b5e6-
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Mehdi Amini [Thu, 31 Mar 2016 23:27:37 +0000 (23:27 +0000)]
clang-format the large enum definitions in LLVMBitCodes.h
Suggestion from Duncan in a review thread.
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265075
91177308-0d34-0410-b5e6-
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Mehdi Amini [Thu, 31 Mar 2016 23:14:45 +0000 (23:14 +0000)]
Use const ref instead of value for Twine in the disk_space() API
Thanks Rui for noticing!
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265074
91177308-0d34-0410-b5e6-
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Matthias Braun [Thu, 31 Mar 2016 23:08:55 +0000 (23:08 +0000)]
lit: python3 compatibility fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265070
91177308-0d34-0410-b5e6-
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Peter Collingbourne [Thu, 31 Mar 2016 23:07:50 +0000 (23:07 +0000)]
Create thin archive in GNU format to fix test on OS X.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265069
91177308-0d34-0410-b5e6-
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Mehdi Amini [Thu, 31 Mar 2016 23:05:26 +0000 (23:05 +0000)]
Add disk_space() to llvm::fs
Summary: Adapted from Boost::filesystem.
(This is a reapply by reverting commit r265062 and fixing the WinAPI part)
Differential Revision: http://reviews.llvm.org/D18467
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265068
91177308-0d34-0410-b5e6-
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Tim Shen [Thu, 31 Mar 2016 22:32:10 +0000 (22:32 +0000)]
Move asm-printer-topological-order.ll to PowerPC backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265067
91177308-0d34-0410-b5e6-
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Peter Collingbourne [Thu, 31 Mar 2016 22:08:57 +0000 (22:08 +0000)]
Object: Add function for moving thin archive object buffer vector out of Archive.
Differential Revision: http://reviews.llvm.org/D18664
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265066
91177308-0d34-0410-b5e6-
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Peter Collingbourne [Thu, 31 Mar 2016 22:08:31 +0000 (22:08 +0000)]
Object: Correctly read thin archives containing absolute paths.
Differential Revision: http://reviews.llvm.org/D18666
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265065
91177308-0d34-0410-b5e6-
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Tim Shen [Thu, 31 Mar 2016 22:08:19 +0000 (22:08 +0000)]
[AsmPrinter] Print aliases in topological order
Print aliases in topological order, that is, for any alias a = b,
b must be printed before a. This is because on some targets (e.g. PowerPC)
linker expects aliases in such an order to generate correct TOC information.
GCC also prints aliases in topological order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265064
91177308-0d34-0410-b5e6-
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Chandler Carruth [Thu, 31 Mar 2016 21:55:58 +0000 (21:55 +0000)]
Fix PR26940 where compiles times regressed massively.
Patch by Jonas Paulsson. Original description:
Bugfix in buildSchedGraph() to make -dag-maps-huge-region work properly
I found that the reduction of the maps did in fact never happen in this
test case. This was because *all* the stores / loads were made with
addresses from arguments and they thus became "unknown" stores / loads.
Fixed by removing continue statements and making sure that the test for
reduction always takes place.
Differential Revision: http://reviews.llvm.org/D18673
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265063
91177308-0d34-0410-b5e6-
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Mehdi Amini [Thu, 31 Mar 2016 21:55:35 +0000 (21:55 +0000)]
Revert "Add disk_space() to llvm::fs"
Breaks windows bot.
This reverts commit r265050.
This reverts commit r265055.
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265062
91177308-0d34-0410-b5e6-
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Evgeniy Stepanov [Thu, 31 Mar 2016 21:55:11 +0000 (21:55 +0000)]
Preserve blockaddress use edges in the module splitter.
"blockaddress" can not apply to an external function. All
blockaddress constant uses must belong to the same module as the
definition of the target function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265061
91177308-0d34-0410-b5e6-
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David Majnemer [Thu, 31 Mar 2016 21:29:57 +0000 (21:29 +0000)]
[NVPTX] Infer __nvvm_reflect as nounwind, readnone
This patch simply mirrors the attributes we give to @llvm.nvvm.reflect
to the __nvvm_reflect libdevice call. This shaves about 30% of the code
in libdevice away because of CSE opportunities. It's also helps us
figure out that libdevice implementations of transcendental functions
don't have side-effects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265060
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 31 Mar 2016 21:13:49 +0000 (21:13 +0000)]
Wdocumentation parameter fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265055
91177308-0d34-0410-b5e6-
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Sanjay Patel [Thu, 31 Mar 2016 21:00:48 +0000 (21:00 +0000)]
fix typo; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265054
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 31 Mar 2016 20:57:36 +0000 (20:57 +0000)]
Fixed signed/unsigned warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265052
91177308-0d34-0410-b5e6-
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Jun Bum Lim [Thu, 31 Mar 2016 20:53:47 +0000 (20:53 +0000)]
[AArch64] Allow loads with imp-def to be handled in getMemOpBaseRegImmOfsWidth()
Summary:
This change will allow loads with imp-def to be clustered in machine-scheduler pass.
areMemAccessesTriviallyDisjoint() can also handle loads with imp-def.
Reviewers: mcrosier, jmolloy, t.p.northover
Subscribers: aemerson, rengolin, mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D18665
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265051
91177308-0d34-0410-b5e6-
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Mehdi Amini [Thu, 31 Mar 2016 20:48:27 +0000 (20:48 +0000)]
Add disk_space() to llvm::fs
Summary: Adapted from Boost::filesystem.
Reviewers: bruno, silvas
Subscribers: tberghammer, danalbert, llvm-commits, srhines
Differential Revision: http://reviews.llvm.org/D18467
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265050
91177308-0d34-0410-b5e6-
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Hal Finkel [Thu, 31 Mar 2016 20:45:00 +0000 (20:45 +0000)]
[PowerPC] Cleanup test/CodeGen/PowerPC/qpx-load-splat.ll
Removing unnecessary attributes and metadata...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265049
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Sanjay Patel [Thu, 31 Mar 2016 20:40:32 +0000 (20:40 +0000)]
[x86] add memset tests to show another potential improvement
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265048
91177308-0d34-0410-b5e6-
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Hal Finkel [Thu, 31 Mar 2016 20:39:41 +0000 (20:39 +0000)]
[PowerPC] Add a late MI-level pass for QPX load/splat simplification
Chapter 3 of the QPX manual states that, "Scalar floating-point load
instructions, defined in the Power ISA, cause a replication of the source data
across all elements of the target register." Thus, if we have a load followed
by a QPX splat (from the first lane), the splat is redundant. This adds a late
MI-level pass to remove the redundant splats in some of these cases
(specifically when both occur in the same basic block).
This optimization is scheduled just prior to post-RA scheduling. It can't happen
before anything that might replace the load with some already-computed quantity
(i.e. store-to-load forwarding).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265047
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Hans Wennborg [Thu, 31 Mar 2016 20:27:30 +0000 (20:27 +0000)]
Revert r265039 "[X86] Merge adjacent stack adjustments in eliminateCallFramePseudoInstr (PR27140)"
I think it might have caused these build breakages:
http://lab.llvm.org:8011/builders/clang-x86-win2008-selfhost/builds/7234/steps/build%20stage%202/logs/stdio
http://lab.llvm.org:8011/builders/sanitizer-windows/builds/19566/steps/run%20tests/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265046
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Simon Pilgrim [Thu, 31 Mar 2016 20:26:30 +0000 (20:26 +0000)]
[X86][SSE] Some basic tests for variable shuffles
We don't really support non-constant shuffle masks, but these tests are for cases where BUILD_VECTOR is made up from vector extracts (as well as undef/zero scalars).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265045
91177308-0d34-0410-b5e6-
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Evgeniy Stepanov [Thu, 31 Mar 2016 20:21:31 +0000 (20:21 +0000)]
Preserve extern_weak linkage in CloneModule.
Only force "extern" linkage if the function used to be a definition
in the source module. Declarations keep their original linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265043
91177308-0d34-0410-b5e6-
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Chris Bieneman [Thu, 31 Mar 2016 20:03:19 +0000 (20:03 +0000)]
[CMake] Provide the ability to skip stripping when generating dSYMs
For debugging it is useful to be able to generate dSYM files but not strip the executables. This change adds the ability to skip stripping by setting LLVM_EXTERNALIZE_DEBUGINFO_SKIP_STRIP=On.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265041
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Thu, 31 Mar 2016 19:42:04 +0000 (19:42 +0000)]
[ARM] Expand v1i64 and v2i64 ctpop.
The default is legal, which results in 'Cannot select' errors. This is
triggered during selfhost due to a recent cost model change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265040
91177308-0d34-0410-b5e6-
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Hans Wennborg [Thu, 31 Mar 2016 19:26:24 +0000 (19:26 +0000)]
[X86] Merge adjacent stack adjustments in eliminateCallFramePseudoInstr (PR27140)
For code such as:
void f(int, int);
void g() {
f(1, 2);
}
compiled for 32-bit X86 Linux, Clang would previously generate:
subl $12, %esp
subl $8, %esp
pushl $2
pushl $1
calll f
addl $16, %esp
addl $12, %esp
retl
This patch fixes that by merging adjacent stack adjustments in
eliminateCallFramePseudoInstr().
Differential Revision: http://reviews.llvm.org/D18627
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265039
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Hans Wennborg [Thu, 31 Mar 2016 18:33:38 +0000 (18:33 +0000)]
Change eliminateCallFramePseudoInstr() to return an iterator
This will become necessary in a subsequent change to make this method
merge adjacent stack adjustments, i.e. it might erase the previous
and/or next instruction.
It also greatly simplifies the calls to this function from Prolog-
EpilogInserter. Previously, that had a bunch of logic to resume iteration
after the call; now it just continues with the returned iterator.
Note that this changes the behaviour of PEI a little. Previously,
it attempted to re-visit the new instruction created by
eliminateCallFramePseudoInstr(). That code was added in r36625,
but I can't see any reason for it: the new instructions will obviously
not be pseudo instructions, they will not have FrameIndex operands,
and we have already accounted for the stack adjustment.
Differential Revision: http://reviews.llvm.org/D18627
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265036
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Thu, 31 Mar 2016 18:22:55 +0000 (18:22 +0000)]
[lit][googletest] Handle upstream gtest output
Summary:
Upstream googletest prints "Running main() from gtest_main.cc" to stdout prior
to running tests. LLVM removed that print statement in r61540. If a user were
to use lit to run tests that use upstream googletest, however, lit
reports "Running main()" as an invalid test name.
To avoid such a failure, add an extra conditional to `formats/googletest.py`.
Also add tests to demonstrate the modified behavior.
Reviewers: abdulras, ddunbar
Subscribers: ddunbar, llvm-commits, kastiglione
Differential Revision: http://reviews.llvm.org/D18606
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265034
91177308-0d34-0410-b5e6-
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Jacques Pienaar [Thu, 31 Mar 2016 17:58:55 +0000 (17:58 +0000)]
[lanai] isBrImm should accept any non-constant immediate.
isBrImm should accept any non-constant immediate. Previously it was only accepting LanaiMCExpr ones which was wrong.
Differential Revision: http://reviews.llvm.org/D18571
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265032
91177308-0d34-0410-b5e6-
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Ehsan Amiri [Thu, 31 Mar 2016 17:47:17 +0000 (17:47 +0000)]
[PPC] basic support for Power 9 direct move instructions
http://reviews.llvm.org/D18097
Initial support does not include any patterns to generate this instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265031
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Rong Xu [Thu, 31 Mar 2016 17:39:33 +0000 (17:39 +0000)]
[PGO] use emplace_back. NFC.
Use emplace_back instead of push_back for simplicity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265030
91177308-0d34-0410-b5e6-
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Sanjay Patel [Thu, 31 Mar 2016 17:30:06 +0000 (17:30 +0000)]
[x86] use SSE/AVX ops for non-zero memsets (PR27100)
Move the memset check down to the CPU-with-slow-SSE-unaligned-memops case: this allows fast
targets to take advantage of SSE/AVX instructions and prevents slow targets from stepping
into a codegen sinkhole while trying to splat a byte into an XMM reg.
Follow-on bugs exposed by the current codegen are:
https://llvm.org/bugs/show_bug.cgi?id=27141
https://llvm.org/bugs/show_bug.cgi?id=27143
Differential Revision: http://reviews.llvm.org/D18566
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265029
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Valery Pykhtin [Thu, 31 Mar 2016 17:28:46 +0000 (17:28 +0000)]
[AMDGPU] enable few disassembler tests that were mistakenly marked as FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265028
91177308-0d34-0410-b5e6-
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Hans Wennborg [Thu, 31 Mar 2016 16:42:10 +0000 (16:42 +0000)]
More checks in win32-seh-nested-finally.ll after comment on r264966
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265027
91177308-0d34-0410-b5e6-
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Ulrich Weigand [Thu, 31 Mar 2016 16:38:57 +0000 (16:38 +0000)]
[PowerPC] Attempt to fix fast-isel-i64offset.ll failure
The test case added in r265023 is failing on ninja-x64-msvc-RA-centos6.
Update the test to make less specific assumptions on code generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265026
91177308-0d34-0410-b5e6-
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Xinliang David Li [Thu, 31 Mar 2016 16:22:17 +0000 (16:22 +0000)]
Minor code cleanup /NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265025
91177308-0d34-0410-b5e6-
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Stephan Bergmann [Thu, 31 Mar 2016 15:42:01 +0000 (15:42 +0000)]
Don't use potentially invalidated iterator
If the lhs is evaluated before the rhs, FuncletI's operator-> can trigger the
assert(isHandleInSync() && "invalid iterator access!");
at include/llvm/ADT/DenseMap.h:1061. (Happens e.g. when compiled with GCC 6.)
Differential Revision: http://reviews.llvm.org/D18440
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265024
91177308-0d34-0410-b5e6-
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Ulrich Weigand [Thu, 31 Mar 2016 15:37:06 +0000 (15:37 +0000)]
[PowerPC] Correctly compute 64-bit offsets in fast isel
PPCSimplifyAddress contains this code:
IntegerType *OffsetTy = ((VT == MVT::i32) ? Type::getInt32Ty(*Context)
: Type::getInt64Ty(*Context));
to determine the type to be used for an index register, if one needs
to be created. However, the "VT" here is the type of the data being
loaded or stored, *not* the type of an address. This means that if
a data element of type i32 is accessed using an index that does not
not fit into 32 bits, a wrong address is computed here.
Note that PPCFastISel is only ever used on 64-bit currently, so the type
of an address is actually *always* MVT::i64. Other parts of the code,
even in this same PPCSimplifyAddress routine, already rely on that fact.
Thus, this patch changes the code to simply unconditionally use
Type::getInt64Ty(*Context) as OffsetTy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265023
91177308-0d34-0410-b5e6-
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Nemanja Ivanovic [Thu, 31 Mar 2016 15:26:37 +0000 (15:26 +0000)]
[PowerPC] Basic support for P9 atomic loads and stores
This patch corresponds to review:
http://reviews.llvm.org/D18032
This patch provides asm implementation for the following instructions:
lwat, ldat, stwat, stdat, ldmx, mcrxrx
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265022
91177308-0d34-0410-b5e6-
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Jun Bum Lim [Thu, 31 Mar 2016 14:47:24 +0000 (14:47 +0000)]
[AArch64] Handle missing store pair opportunity
Summary:
This change will handle missing store pair opportunity where the first store
instruction stores zero followed by the non-zero store. For example, this change
will convert :
str wzr, [x8]
str w1, [x8, #4]
into:
stp wzr, w1, [x8]
Reviewers: jmolloy, t.p.northover, mcrosier
Subscribers: flyingforyou, aemerson, rengolin, mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D18570
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265021
91177308-0d34-0410-b5e6-
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Ulrich Weigand [Thu, 31 Mar 2016 14:44:50 +0000 (14:44 +0000)]
[PowerPC] Remove incorrect use of COPY_TO_REGCLASS in fast isel
The fast isel pass currently emits a COPY_TO_REGCLASS node to convert
from a F4RC to a F8RC register class during conversion of a
floating-point number to integer. There is actually no support in the
common code instruction printers to emit COPY_TO_REGCLASS nodes, so the
PowerPC back-end has special code there to simply ignore
COPY_TO_REGCLASS.
This is correct *if and only if* the source and destination registers of
COPY_TO_REGCLASS are the same (except for the different register class).
But nothing guarantees this to be the case, and if the register
allocator does end up allocating source and destination to different
registers after all, the back-end simply generates incorrect code. I've
included a test case that shows such incorrect code generation.
However, it seems that COPY_TO_REGCLASS is actually not intended to be
used at the MI layer at all. It is used during SelectionDAG, but always
lowered to a plain COPY before emitting MI. Other back-end's fast isel
passes never emit COPY_TO_REGCLASS at all. I suspect it is simply wrong
for the PowerPC back-end to emit it here.
This patch changes the PowerPC back-end to directly emit COPY instead of
COPY_TO_REGCLASS and removes the special handling in the instruction
printers.
Differential Revision: http://reviews.llvm.org/D18605
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265020
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Daniel Sanders [Thu, 31 Mar 2016 14:34:00 +0000 (14:34 +0000)]
[mips] Range check simm16
Summary:
There are too many instructions to exhaustively test so addiu and lwc2 are
used as representative examples.
It should be noted that many memory instructions that should have simm16
range checking do not because it is also necessary to support the macro
of the same name which accepts simm32. The range checks for these occur in
the macro expansion.
Reviewers: vkalintiris
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D18437
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265019
91177308-0d34-0410-b5e6-
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Daniel Sanders [Thu, 31 Mar 2016 14:23:20 +0000 (14:23 +0000)]
[mips] Range check simm11 and mem_simm11.
Summary:
ldc2/sdc2 now emit slightly worse diagnostics for MIPS-I. The problem
is that they don't trigger the custom parser because all the candidates
are disabled by feature bits. On all other subtargets, the diagnostics are
accurate but are subject to the usual issues of needing to report multiple
ways to correct the code (e.g. smaller offset, enable a CPU feature) but
only being able to report one error.
Reviewers: vkalintiris
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D18436
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265018
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Dmitry Polukhin [Thu, 31 Mar 2016 14:16:21 +0000 (14:16 +0000)]
[IFUNC] Introduce GlobalIndirectSymbol as a base class for alias and ifunc
This patch is a part of http://reviews.llvm.org/D15525
GlobalIndirectSymbol class contains common implementation for both
aliases and ifuncs. This patch should be NFC change that just prepare
common code for ifunc support.
Differential Revision: http://reviews.llvm.org/D18433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265016
91177308-0d34-0410-b5e6-
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Sam Kolton [Thu, 31 Mar 2016 14:15:04 +0000 (14:15 +0000)]
[AMDGPU] Disassembler: support for DPP
Review: http://reviews.llvm.org/D18642
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265015
91177308-0d34-0410-b5e6-
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Daniel Sanders [Thu, 31 Mar 2016 14:12:01 +0000 (14:12 +0000)]
[mips] Split mem_msa into range checked mem_simm10 and mem_simm10_lsl[123]
Summary:
Also, made test_mi10.s formatting consistent with the majority of the
MC tests.
Reviewers: vkalintiris
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D18435
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265014
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Nirav Dave [Thu, 31 Mar 2016 13:40:55 +0000 (13:40 +0000)]
Prevent X86ISelLowering from merging volatile loads
Change isConsecutiveLoads to check that loads are non-volatile as this
is a requirement for any load merges. Propagate change to two callers.
Reviewers: RKSimon
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D18546
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265013
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Daniel Sanders [Thu, 31 Mar 2016 13:15:23 +0000 (13:15 +0000)]
[mips] Range check simm9 and fix a bug this revealed.
Summary:
The bug was that microMIPS's [ls]w[lr]e instructions claimed to support a
12-bit offset when it is only 9-bit.
Reviewers: vkalintiris
Subscribers: llvm-commits, dsanders
Differential Revision: http://reviews.llvm.org/D18434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265010
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Benjamin Kramer [Thu, 31 Mar 2016 10:42:40 +0000 (10:42 +0000)]
[TTI] Let the cost model estimate ctpop costs based on legality
PPC has a vector popcount, this lets the vectorizer use the correct cost
for it. Tweak X86 test to use an intrinsic that's actually scalarized (we
have a somewhat efficient lowering for vector popcount using SSE, the
cost model finds that now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265005
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