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Charlie Turner [Thu, 24 Sep 2015 10:24:58 +0000 (10:24 +0000)]
[InstCombine] Recognize another bswap idiom.
Summary:
The byte-swap recognizer can now notice that this
```
uint32_t bswap(uint32_t x)
{
x = (x & 0x0000FFFF) << 16 | (x & 0xFFFF0000) >> 16;
x = (x & 0x00FF00FF) << 8 | (x & 0xFF00FF00) >> 8;
return x;
}
```
is a bswap. Fixes PR23863.
Reviewers: nlewycky, hfinkel, hans, jmolloy, rengolin
Subscribers: majnemer, rengolin, llvm-commits
Differential Revision: http://reviews.llvm.org/D12637
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248482
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Matt Arsenault [Thu, 24 Sep 2015 08:36:14 +0000 (08:36 +0000)]
Introduce target hook for optimizing register copies
Allow a target to do something other than search for copies
that will avoid cross register bank copies.
Implement for SI by only rewriting the most basic copies,
so it should look through anything like a subregister extract.
I'm not entirely satisified with this because it seems like
eliminating a reg_sequence that isn't fully used should work
generically for all targets without them having to override
something. However, it seems to be tricky to have a simple
implementation of this without rewriting to invalid kinds
of subregister copies on some targets.
I'm not sure if there is currently a generic way to easily check
if a subregister index would be valid for the current use.
The current set of TargetRegisterInfo::get*Class functions don't
quite behave like I would expect (e.g. getSubClassWithSubReg
returns the maximal register class rather than the minimal), so
I'm not sure how to make the generic test keep searching if
SrcRC:SrcSubReg is a valid replacement for DefRC:DefSubReg. Making
the default implementation to check for simple copies breaks
a variety of ARM and x86 tests by producing illegal subregister uses.
The ARM tests are not actually changed since it should still be using
the same sharesSameRegisterFile implementation, this just relaxes
them to not check for specific registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248478
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Matt Arsenault [Thu, 24 Sep 2015 07:51:28 +0000 (07:51 +0000)]
AMDGPU: Return after instruction is processed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248476
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Matt Arsenault [Thu, 24 Sep 2015 07:51:25 +0000 (07:51 +0000)]
AMDGPU: Remove another unnecessary check from commuteInstruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248475
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Matt Arsenault [Thu, 24 Sep 2015 07:51:23 +0000 (07:51 +0000)]
AMDGPU: Add readonly to InstrMapping functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248474
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Matt Arsenault [Thu, 24 Sep 2015 07:51:20 +0000 (07:51 +0000)]
TableGen: Add LLVM_READONLY to generated InstrMapping functions
These just read from a generated table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248473
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Matt Arsenault [Thu, 24 Sep 2015 07:51:17 +0000 (07:51 +0000)]
AMDGPU: Fix printing trailing whitespace for mubuf atomics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248472
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Matt Arsenault [Thu, 24 Sep 2015 07:51:12 +0000 (07:51 +0000)]
Remove dead declaration
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248471
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Matt Arsenault [Thu, 24 Sep 2015 07:22:38 +0000 (07:22 +0000)]
Use new TokenFactor chain when merging stores
If the stores are storing values from loads which partially
alias the stores, we could end up placing the merged loads
and stores on the same chain which has the potential to break.
Each store may have a different chain dependency on only some
of the original loads. Create a new TokenFactor to capture all
of the required dependencies of the stores rather than assuming
all stores can use the same chain.
The testcase is a situation where this happens, although
it does not have an observable change from this. The DAG nodes
just happened to not be reordered before despite this missing
chain dependency.
This is based on an off-list report for an out of tree target
which regressed due to r246307 and I haven't managed to find a case
where the nodes do end up reordered with an in tree target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248468
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Matt Arsenault [Thu, 24 Sep 2015 07:16:37 +0000 (07:16 +0000)]
AMDGPU: Reduce number of copies emitted
Instead of always inserting a copy in case
the super register is itself a subregister,
only extract to the super reg class if this is
actually the case.
This shouldn't really change codegen, but
makes looking at the output of SIFixSGPRCopies
easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248467
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Justin Bogner [Thu, 24 Sep 2015 05:29:31 +0000 (05:29 +0000)]
Fix a think-o in which functions these should surround
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248465
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Justin Bogner [Thu, 24 Sep 2015 05:20:04 +0000 (05:20 +0000)]
Add some NDEBUG checks I accidentally dropped in r248462
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248464
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Justin Bogner [Thu, 24 Sep 2015 04:59:24 +0000 (04:59 +0000)]
BasicAA: Move BasicAAResult::alias out-of-line. NFC
This makes the header more readable and cleans up some unnecessary
header differences between NDEBUG and !NDEBUG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248462
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Michael Zolotukhin [Thu, 24 Sep 2015 03:50:17 +0000 (03:50 +0000)]
Add CFG Simplification pass after Loop Unswitching.
Loop unswitching produces conditional branches with constant condition,
and it's beneficial for later passes to clean this up with simplify-cfg.
We do this after the second invocation of loop-unswitch, but not after
the first one. Not doing so might cause problem for passes like
LoopUnroll, whose estimate of loop body size would be less accurate.
Reviewers: hfinkel
Differential Revision: http://reviews.llvm.org/D13064
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248460
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Evgeniy Stepanov [Thu, 24 Sep 2015 01:23:51 +0000 (01:23 +0000)]
[safestack] Fix compiler crash in the presence of stack restores.
A use can be emitted before def in a function with stack restore
points but no static allocas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248455
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Sanjoy Das [Thu, 24 Sep 2015 01:00:49 +0000 (01:00 +0000)]
[IR] Teach `llvm::User` to co-allocate a descriptor.
Summary:
With this change, subclasses of `llvm::User` will be able to co-allocate
a variable number of bytes (called a "descriptor") with the `llvm::User`
instance. The co-allocated descriptor can later be accessed using
`llvm::User::getDescriptor`. This will be used in later changes to
implement operand bundles.
This change steals one bit from `NumUserOperands`, but given that it is
still 28 bits wide I don't think this will be a practical issue.
This change does not allow allocating hung off uses with descriptors.
This only for simplicity, not for any fundamental reason; and we can
easily add this functionality later if needed.
Reviewers: reames, chandlerc, dexonsmith, kmod, majnemer, pete, JosephTremoulet
Subscribers: pete, sanjoy, llvm-commits
Differential Revision: http://reviews.llvm.org/D12455
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248453
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Adrian Prantl [Thu, 24 Sep 2015 00:35:14 +0000 (00:35 +0000)]
Add REQUIRES: default_triple to these testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248452
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Rui Ueyama [Thu, 24 Sep 2015 00:23:07 +0000 (00:23 +0000)]
Remove iterator_range::end.
Because the current proposal does not include that member function,
and we are trying to keep in line with that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248451
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Rui Ueyama [Wed, 23 Sep 2015 23:58:29 +0000 (23:58 +0000)]
Add iterator_range::end() predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248447
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Michael Zolotukhin [Wed, 23 Sep 2015 23:12:43 +0000 (23:12 +0000)]
[Unroll] When completely unrolling the loop, replace conditinal branches with unconditional.
Nothing is expected to change, except we do less redundant work in
clean-up.
Reviewers: hfinkel
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D12951
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248444
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Wei Mi [Wed, 23 Sep 2015 22:40:45 +0000 (22:40 +0000)]
Put profile variables of COMDAT functions to it's own COMDAT group.
In -fprofile-instr-generate compilation, to remove the redundant profile
variables for the COMDAT functions, these variables are placed in the same
COMDAT group as its associated function. This way when the COMDAT function
is not picked by the linker, those profile variables will also not be
output in the final binary. This may cause warning when mix link objects
built w and wo -fprofile-instr-generate.
This patch puts the profile variables for COMDAT functions to its own COMDAT
group to avoid the problem.
Patch by xur.
Differential Revision: http://reviews.llvm.org/D12248
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248440
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Sanjay Patel [Wed, 23 Sep 2015 22:28:18 +0000 (22:28 +0000)]
set div/rem default values to 'expensive' in TargetTransformInfo's cost model
...because that's what the cost model was intended to do.
As discussed in D12882, this fix has a temporary unintended consequence for
SimplifyCFG: it causes us to not speculate an fdiv. However, two wrongs make
PR24818 right, and two wrongs make PR24343 act right even though it's really
still wrong.
I intend to correct SimplifyCFG and add to CodeGenPrepare to account for this
cost model change and preserve the righteousness for the bug report cases.
https://llvm.org/bugs/show_bug.cgi?id=24818
https://llvm.org/bugs/show_bug.cgi?id=24343
Differential Revision: http://reviews.llvm.org/D12882
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248439
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Tim Northover [Wed, 23 Sep 2015 22:21:09 +0000 (22:21 +0000)]
ARM: fix folding stack adjustment (again again again...)
This time, the issue is that we weren't accounting for the possibility that
aligned DPRs could have been stored after the final "push" in a prologue. When
that happened we effectively moved a "sub sp, #N" from below the aligned stores
to above them, and everything went to pot.
To make it worse, I'd actually committed something testing that we produced
wrong code, so the test update is tiny.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248437
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Adrian Prantl [Wed, 23 Sep 2015 20:44:37 +0000 (20:44 +0000)]
dsymutil: Don't prune forward declarations inside a module definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248428
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Adrian Prantl [Wed, 23 Sep 2015 19:53:10 +0000 (19:53 +0000)]
Fix this dsymutil testcase by not passing in a path to the modulemap file,
so the lookup works as expected after prepending the oso-prepend-path.
This manifested only on Windows, because "/" is not a relative path there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248423
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Philip Reames [Wed, 23 Sep 2015 19:48:43 +0000 (19:48 +0000)]
Remove handling of AddrSpaceCast in stripAndAccumulateInBoundsConstantOffsets
Patch by: simoncook
Unlike BitCasts, AddrSpaceCasts do not always produce an output the same size as its input, which was previously assumed. This fixes cases where two address spaces do not have the same size pointer, as an assertion failure would occur when trying to prove deferenceability. LoopUnswitch is used in the particular test, but LICM also exhibits the same problem.
Differential Revision: http://reviews.llvm.org/D13008
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248422
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Lawrence Hu [Wed, 23 Sep 2015 19:25:30 +0000 (19:25 +0000)]
Swap loop invariant GEP with loop variant GEP to allow more LICM.
This patch changes the order of GEPs generated by Splitting GEPs
pass, specially when one of the GEPs has constant and the base is
loop invariant, then we will generate the GEP with constant first
when beneficial, to expose more cases for LICM.
If originally Splitting GEP generate the following:
do.body.i:
%idxprom.i = sext i32 %shr.i to i64
%2 = bitcast %typeD* %s to i8*
%3 = shl i64 %idxprom.i, 2
%uglygep = getelementptr i8, i8* %2, i64 %3
%uglygep7 = getelementptr i8, i8* %uglygep, i64 1032
...
Now it genereates:
do.body.i:
%idxprom.i = sext i32 %shr.i to i64
%2 = bitcast %typeD* %s to i8*
%3 = shl i64 %idxprom.i, 2
%uglygep = getelementptr i8, i8* %2, i64 1032
%uglygep7 = getelementptr i8, i8* %uglygep, i64 %3
...
For no-loop cases, the original way of generating GEPs seems to
expose more CSE cases, so we don't change the logic for no-loop
cases, and only limit our change to the specific case we are
interested in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248420
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Akira Hatanaka [Wed, 23 Sep 2015 18:40:57 +0000 (18:40 +0000)]
[InstCombine] Preserve metadata when merging loads that are phi
arguments.
Make sure InstCombiner::FoldPHIArgLoadIntoPHI doesn't drop the following
metadata:
MD_tbaa
MD_alias_scope
MD_noalias
MD_invariant_load
MD_nonnull
MD_range
rdar://problem/
17617709
Differential Revision: http://reviews.llvm.org/D12710
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248419
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Philip Reames [Wed, 23 Sep 2015 18:39:37 +0000 (18:39 +0000)]
[docs] Update DominatorTree docs to clarify expectations around unreachable blocks
Note: I'm am not trying to describe what "should be"; I'm only describing what is true today.
This came out of my recent question to llvm-dev titled: When can the dominator tree not contain a node for a basic block?
Differential Revision: http://reviews.llvm.org/D13078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248417
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Sanjay Patel [Wed, 23 Sep 2015 18:33:42 +0000 (18:33 +0000)]
[x86] replace integer 'xor' ops with packed SSE FP 'xor' ops when operating on FP scalars
Turn this:
movd %xmm0, %eax
movd %xmm1, %ecx
xorl %eax, %ecx
movd %ecx, %xmm0
into this:
xorps %xmm1, %xmm0
This is related to, but does not solve:
https://llvm.org/bugs/show_bug.cgi?id=22428
This is an extension of:
http://reviews.llvm.org/rL248395
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248415
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Sanjay Patel [Wed, 23 Sep 2015 18:19:07 +0000 (18:19 +0000)]
[x86] replace integer 'or' ops with packed SSE FP 'or' ops when operating on FP scalars
Turn this:
movd %xmm0, %eax
movd %xmm1, %ecx
orl %eax, %ecx
movd %ecx, %xmm0
into this:
orps %xmm1, %xmm0
This is related to, but does not solve:
https://llvm.org/bugs/show_bug.cgi?id=22428
This is an extension of:
http://reviews.llvm.org/rL248395
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248409
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Adrian Prantl [Wed, 23 Sep 2015 18:09:01 +0000 (18:09 +0000)]
Fix the order of operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248406
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Evgeniy Stepanov [Wed, 23 Sep 2015 18:07:56 +0000 (18:07 +0000)]
Android support for SafeStack.
Add two new ways of accessing the unsafe stack pointer:
* At a fixed offset from the thread TLS base. This is very similar to
StackProtector cookies, but we plan to extend it to other backends
(ARM in particular) soon. Bionic-side implementation here:
https://android-review.googlesource.com/170988.
* Via a function call, as a fallback for platforms that provide
neither a fixed TLS slot, nor a reasonable TLS implementation (i.e.
not emutls).
This is a re-commit of a change in r248357 that was reverted in
r248358.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248405
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Sanjay Patel [Wed, 23 Sep 2015 18:03:37 +0000 (18:03 +0000)]
move call to convertIntLogicToFPLogic up; NFCI
The BEXTR comments didn't make sense before, we may want to extend the
FP logic transform to work on vectors, and this way is more beautiful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248404
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Adrian Prantl [Wed, 23 Sep 2015 17:59:45 +0000 (17:59 +0000)]
Temporarily make testcase more verbose to debug a msvc buildbot failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248403
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Chen Li [Wed, 23 Sep 2015 17:58:44 +0000 (17:58 +0000)]
[Bug 24848] Use range metadata to constant fold comparisons with constant values
Summary:
This is the first part of fixing bug 24848 https://llvm.org/bugs/show_bug.cgi?id=24848.
When range metadata is provided, it should be used to constant fold comparisons with constant values.
Reviewers: sanjoy, hfinkel
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D12988
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248402
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Sanjay Patel [Wed, 23 Sep 2015 17:39:41 +0000 (17:39 +0000)]
[x86] move code for converting int logic to FP logic to a helper function; NFCI
This is a follow-on to:
http://reviews.llvm.org/rL248395
so we can add the call to the or/xor combines too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248399
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Adrian Prantl [Wed, 23 Sep 2015 17:35:52 +0000 (17:35 +0000)]
dsymutil: Resolve forward decls for types defined in clang modules.
This patch extends llvm-dsymutil's ODR type uniquing machinery to also
resolve forward decls for types defined in clang modules.
http://reviews.llvm.org/D13038
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248398
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Adrian Prantl [Wed, 23 Sep 2015 17:11:10 +0000 (17:11 +0000)]
dsymutil: print a warning when there is a module hash mismatch.
This also updates the module binaries in the test directory because
their module hash mismatched.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248396
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Sanjay Patel [Wed, 23 Sep 2015 17:00:06 +0000 (17:00 +0000)]
[x86] replace integer 'and' ops with packed SSE FP 'and' ops when operating on FP scalars
Turn this:
movd %xmm0, %eax
movd %xmm1, %ecx
andl %eax, %ecx
movd %ecx, %xmm0
into this:
andps %xmm1, %xmm0
This is related to, but does not solve:
https://llvm.org/bugs/show_bug.cgi?id=22428
Differential Revision: http://reviews.llvm.org/D13065
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248395
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Dan Gohman [Wed, 23 Sep 2015 16:59:10 +0000 (16:59 +0000)]
[WebAssembly] Fix hasAddr64 being used before being initializer.
This reverts r248388 and fixes the underlying bug: hasAddr64 was initialized
in runOnMachineFunction, but runOnMachineFunction isn't ever called in
CodeGen/WebAssembly/global.ll since that testcase has no functions. The fix
here is to use AsmPrinter's getPointerSize() as needed to determine the
pointer size instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248394
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Vedant Kumar [Wed, 23 Sep 2015 15:49:08 +0000 (15:49 +0000)]
[Inline] Use AssumptionCache from the right Function
This changes the behavior of AddAligntmentAssumptions to match its
comment. I.e, prove the asserted alignment in the context of the caller,
not the callee.
Thanks to Mehdi Amini for seeing the issue here! Also to Artur Pilipenko
who also saw a fix for the issue.
rdar://
22521387
Differential Revision: http://reviews.llvm.org/D12997
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248390
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Alexander Kornienko [Wed, 23 Sep 2015 15:41:25 +0000 (15:41 +0000)]
Fix CodeGen/WebAssembly/global.ll test under ASAN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248388
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David Majnemer [Wed, 23 Sep 2015 15:41:09 +0000 (15:41 +0000)]
[DeadArgElim] Split the invoke successor edge
Invoking a function which returns an aggregate can sometimes be
transformed to return a scalar value. However, this means that we need
to create an insertvalue instruction(s) to recreate the correct
aggregate type. We achieved this by inserting an insertvalue
instruction at the invoke's normal successor. However, this is not
feasible if the normal successor uses the invoke's return value inside a
PHI node.
Instead, split the edge between the invoke and the unwind successor and
create the insertvalue instruction in the new basic block. The new
basic block's successor will be the old invoke successor which leaves
us with IR which is well behaved.
This fixes PR24906.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248387
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Chad Rosier [Wed, 23 Sep 2015 13:51:44 +0000 (13:51 +0000)]
[AArch64] Refactor pre- and post-index merge fuctions into a single function. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248377
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Igor Laevsky [Wed, 23 Sep 2015 11:38:44 +0000 (11:38 +0000)]
[DeadStoreElimination] Remove dead zero store to calloc initialized memory
This change allows dead store elimination to remove zero and null stores into memory freshly allocated with calloc-like function.
Differential Revision: http://reviews.llvm.org/D13021
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248374
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Benjamin Kramer [Wed, 23 Sep 2015 10:38:59 +0000 (10:38 +0000)]
[dsymutil] Plug a memory leak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248372
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Oliver Stannard [Wed, 23 Sep 2015 09:19:54 +0000 (09:19 +0000)]
[ARM] Add option to force fast-isel
The ARM backend has some logic that only allows the fast-isel to be enabled for
subtargets where it is known to be stable. This adds a backend option to
override this and force the fast-isel to be used for any target, to allow it to
be tested.
This is an ARM-specific option, because no other backend disables the fast-isel
on a per-subtarget basis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248369
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 23 Sep 2015 08:48:33 +0000 (08:48 +0000)]
[X86][SSE] Replace 128-bit SSE41 PMOVSX intrinsics with native IR
This patches removes the x86.sse41.pmovsx* intrinsics, provides a suitable upgrade path and updates relevant tests to sign extend a subvector instead.
LLVM counterpart to D12835
Differential Revision: http://reviews.llvm.org/D13002
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248368
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Sanjoy Das [Wed, 23 Sep 2015 01:59:04 +0000 (01:59 +0000)]
[SCEV] Introduce ScalarEvolution::getOne and getZero.
Summary:
It is fairly common to call SE->getConstant(Ty, 0) or
SE->getConstant(Ty, 1); this change makes such uses a little bit
briefer.
I've refactored the call sites I could find easily to use getZero /
getOne.
Reviewers: hfinkel, majnemer, reames
Subscribers: sanjoy, llvm-commits
Differential Revision: http://reviews.llvm.org/D12947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248362
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Evgeniy Stepanov [Wed, 23 Sep 2015 01:23:22 +0000 (01:23 +0000)]
Revert "Android support for SafeStack."
test/Transforms/SafeStack/abi.ll breaks when target is not supported;
needs refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248358
91177308-0d34-0410-b5e6-
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Evgeniy Stepanov [Wed, 23 Sep 2015 01:03:51 +0000 (01:03 +0000)]
Android support for SafeStack.
Add two new ways of accessing the unsafe stack pointer:
* At a fixed offset from the thread TLS base. This is very similar to
StackProtector cookies, but we plan to extend it to other backends
(ARM in particular) soon. Bionic-side implementation here:
https://android-review.googlesource.com/170988.
* Via a function call, as a fallback for platforms that provide
neither a fixed TLS slot, nor a reasonable TLS implementation (i.e.
not emutls).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248357
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Cong Hou [Wed, 23 Sep 2015 00:34:56 +0000 (00:34 +0000)]
Add a test case for the fix of profile update issue when lowering switch statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248356
91177308-0d34-0410-b5e6-
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Cong Hou [Wed, 23 Sep 2015 00:20:27 +0000 (00:20 +0000)]
Fixed an issue on updating profile data when lowering switch statement.
Fixed the issue that when there is an edge from the jump table to the default statement, we should check it directly instead of checking if the sibling of the jump table header is a successor of the jump table header, which may not be the default statment but a successor of it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248354
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NAKAMURA Takumi [Wed, 23 Sep 2015 00:19:20 +0000 (00:19 +0000)]
dsymutil: Fix a comment. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248353
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Adrian Prantl [Tue, 22 Sep 2015 23:42:47 +0000 (23:42 +0000)]
Add a unit test for r248341.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248348
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Adrian Prantl [Tue, 22 Sep 2015 23:21:06 +0000 (23:21 +0000)]
IR: Add a setDWOId() method to DICompileUnit.
Tested via clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248342
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Adrian Prantl [Tue, 22 Sep 2015 23:21:03 +0000 (23:21 +0000)]
IR: Fix the return value of DICompileUnit::getDWOId.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248341
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Adrian Prantl [Tue, 22 Sep 2015 23:21:00 +0000 (23:21 +0000)]
Debug Info: Emit the dwo_name only in skeleton CUs, not in DWOs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248340
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Matthias Braun [Tue, 22 Sep 2015 22:37:44 +0000 (22:37 +0000)]
LiveIntervalAnalysis: Avoid multiple connected liveness components
We may have subregister defs which are unused but not discovered and
cleaned up prior to liveness analysis. This creates multiple connected
components in the resulting live range which are forbidden in the
MachineVerifier because they would unnecesarily constrain the register
allocator. Rewrite those dead definitions to define a newly created
virtual register.
Differential Revision: http://reviews.llvm.org/D13035
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248335
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Matthias Braun [Tue, 22 Sep 2015 22:37:42 +0000 (22:37 +0000)]
LiveInterval: Distribute subregister liveranges to new intervals in ConnectedVNInfoEqClasses::Distribute()
This improves ConnectedVNInfoEqClasses::Distribute() to distribute the
segments and value numbers in the subranges instead of conservatively
clearing all subregister info.
No separate test here, just clearing the subrange instead of properly
distributing them would however break my upcoming fix regarding dead super
register definitions.
Differential Revision: http://reviews.llvm.org/D13075
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248334
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Michael Zolotukhin [Tue, 22 Sep 2015 22:27:12 +0000 (22:27 +0000)]
[Unroll] Do not crash trying to propagate a value to vector load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248333
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Adrian Prantl [Tue, 22 Sep 2015 22:20:50 +0000 (22:20 +0000)]
dsymutil: Follow references to clang modules and recursively clone the
debug info.
This does not yet resolve external type references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248331
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Michael Zolotukhin [Tue, 22 Sep 2015 21:41:29 +0000 (21:41 +0000)]
[Unroll] Follow-up for r247769: fix a bug in UnrolledInstAnalyzer::visitLoad.
Apart from checking that GlobalVariable is a constant, we should check
that it's not a weak constant, in which case we can't propagate its
value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248327
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Aaron Ballman [Tue, 22 Sep 2015 21:00:35 +0000 (21:00 +0000)]
Instead of defining the operator delete() function, it is better to delete the function so that any uses (even from within Node or its subclasses) do not accidentally call it. NFC intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248320
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Adrian Prantl [Tue, 22 Sep 2015 18:51:01 +0000 (18:51 +0000)]
dsymutil: Make -oso-prepend-path available to DwarfLinker.
NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248312
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Adrian Prantl [Tue, 22 Sep 2015 18:50:58 +0000 (18:50 +0000)]
dsymutil: Make resolveDIEReference and getUnitForOffset static functions.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248311
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Adrian Prantl [Tue, 22 Sep 2015 18:50:51 +0000 (18:50 +0000)]
dsymutil: Make DwarfLinker::reportWarning() public. (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248310
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Davide Italiano [Tue, 22 Sep 2015 17:46:10 +0000 (17:46 +0000)]
Remove macho-dump. Its functionality is now covered by llvm-readobj.
Approved by: Rafael Espindola, Eric Christopher, Jim Grosbach,
Alex Rosenberg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248302
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Ahmed Bougacha [Tue, 22 Sep 2015 17:22:58 +0000 (17:22 +0000)]
[ARM] Emit clrex in the expanded cmpxchg fail block.
ARM counterpart to r248291:
In the comparison failure block of a cmpxchg expansion, the initial
ldrex/ldxr will not be followed by a matching strex/stxr.
On ARM/AArch64, this unnecessarily ties up the execution monitor,
which might have a negative performance impact on some uarchs.
Instead, release the monitor in the failure block.
The clrex instruction was designed for this: use it.
Also see ARMARM v8-A B2.10.2:
"Exclusive access instructions and Shareable memory locations".
Differential Revision: http://reviews.llvm.org/D13033
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248294
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Ahmed Bougacha [Tue, 22 Sep 2015 17:21:44 +0000 (17:21 +0000)]
[AArch64] Emit clrex in the expanded cmpxchg fail block.
In the comparison failure block of a cmpxchg expansion, the initial
ldrex/ldxr will not be followed by a matching strex/stxr.
On ARM/AArch64, this unnecessarily ties up the execution monitor,
which might have a negative performance impact on some uarchs.
Instead, release the monitor in the failure block.
The clrex instruction was designed for this: use it.
Also see ARMARM v8-A B2.10.2:
"Exclusive access instructions and Shareable memory locations".
Differential Revision: http://reviews.llvm.org/D13033
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248291
91177308-0d34-0410-b5e6-
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Adrian Prantl [Tue, 22 Sep 2015 15:31:14 +0000 (15:31 +0000)]
Fix a typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248283
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Tue, 22 Sep 2015 14:34:57 +0000 (14:34 +0000)]
Make helper function static. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248278
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Daniel Sanders [Tue, 22 Sep 2015 13:36:28 +0000 (13:36 +0000)]
[mips][sched] Split IIBranch into specific instruction classes.
Summary:
Almost no functional change since the InstrItinData's have been duplicated.
The one functional change is to remove IIBranch from the MSA branches. The
classes will be assigned to the MSA instructions as part of implementing
the P5600 scheduler.
II_IndirectBranchPseudo and II_ReturnPseudo can probably be removed. I've
preserved the itinerary information for the corresponding pseudo
instructions to avoid making a functional change to these pseudos in
this patch.
Reviewers: vkalintiris
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D12189
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248273
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Daniel Sanders [Tue, 22 Sep 2015 12:36:28 +0000 (12:36 +0000)]
[mips][sched] Temporarily rename IIAlu to IIM16Alu. NFC.
Summary:
The only instructions left in IIAlu are MIPS16 specific. We're not
implementing a MIPS16 scheduler at this time so rename the class to make it
obvious that they are MIPS16 instructions.
Reviewers: vkalintiris
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D12188
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248267
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Stephen Canon [Tue, 22 Sep 2015 11:43:17 +0000 (11:43 +0000)]
Don't raise inexact when lowering ceil, floor, round, trunc.
The C standard has historically not specified whether or not these functions should raise the inexact flag. Traditionally on Darwin, these functions *did* raise inexact, and the llvm lowerings followed that conventions. n1778 (C bindings for IEEE-754 (2008)) clarifies that these functions should not set inexact. This patch brings the lowerings for arm64 and x86 in line with the newly specified behavior. This also lets us fold some logic into TD patterns, which is nice.
Differential Revision: http://reviews.llvm.org/D12969
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248266
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NAKAMURA Takumi [Tue, 22 Sep 2015 11:19:03 +0000 (11:19 +0000)]
Prune trailing whitespaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248265
91177308-0d34-0410-b5e6-
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NAKAMURA Takumi [Tue, 22 Sep 2015 11:15:07 +0000 (11:15 +0000)]
Untabify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248264
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NAKAMURA Takumi [Tue, 22 Sep 2015 11:14:39 +0000 (11:14 +0000)]
Reformat blank lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248263
91177308-0d34-0410-b5e6-
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NAKAMURA Takumi [Tue, 22 Sep 2015 11:14:12 +0000 (11:14 +0000)]
Reformat comment lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248262
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NAKAMURA Takumi [Tue, 22 Sep 2015 11:13:55 +0000 (11:13 +0000)]
Reformat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248261
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NAKAMURA Takumi [Tue, 22 Sep 2015 11:10:17 +0000 (11:10 +0000)]
ARMInstrInfo.cpp: Reformat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248260
91177308-0d34-0410-b5e6-
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NAKAMURA Takumi [Tue, 22 Sep 2015 11:10:08 +0000 (11:10 +0000)]
Fix utf8 chars.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248259
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Daniel Sanders [Tue, 22 Sep 2015 10:50:09 +0000 (10:50 +0000)]
[mips][ias] Implement .cpreturn directive.
Summary:
Based on a patch by David Chisnall. I've modified the original patch as follows:
* Moved the expansion to the TargetStreamers so that the directive isn't
expanded when emitting assembly.
* Fixed an operand order bug.
* Changed the move instructions from DADDu to OR to match recent changes to GAS.
Reviewers: vkalintiris
Subscribers: llvm-commits, emaste, seanbruno, theraven
Differential Revision: http://reviews.llvm.org/D13017
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248258
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Daniel Sanders [Tue, 22 Sep 2015 10:01:13 +0000 (10:01 +0000)]
[mips][sched] Added class for WSBH
Summary:
No functional change since no InstrItinData is provided.
Reviewers: vkalintiris
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D12190
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248257
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Daniel Sanders [Tue, 22 Sep 2015 09:22:53 +0000 (09:22 +0000)]
[llvm-mc-fuzzer] Support untested instruction discovery for variable length instruction sets like microMIPS.
Summary:
For fixed length instructions, we can use -max_len to limit the fuzzer to a
single instruction. This doesn't work for variable length instruction sets
since a 4-byte input could consist of one 4-byte instruction or two 2-byte
instructions.
This patch adds a --insn-limit to llvm-mc-fuzzer to limit the input in
terms of instructions processed.
Reviewers: kcc
Subscribers: kcc, llvm-commits
Differential Revision: http://reviews.llvm.org/D12960
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248253
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Simon Pilgrim [Tue, 22 Sep 2015 08:16:08 +0000 (08:16 +0000)]
[X86][SSE] Match zero/any extension shuffles that don't start from the first element
This patch generalizes the lowering of shuffles as zero extensions to allow extensions that don't start from the first element. It now recognises extensions starting anywhere in the lower 128-bits or at the start of any higher 128-bit lane.
The motivation was to reduce the number of high cost pshufb calls, but it also improves the SSE2 case as well.
Differential Revision: http://reviews.llvm.org/D12561
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248250
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Craig Topper [Tue, 22 Sep 2015 05:37:16 +0000 (05:37 +0000)]
Remove extra 'nullptr' entry from an array in tablegen register info file. It should never have been accessed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248246
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Craig Topper [Tue, 22 Sep 2015 05:37:14 +0000 (05:37 +0000)]
Fix formatting of a tablegen register info file by putting a line break in a better place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248245
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Craig Topper [Tue, 22 Sep 2015 05:37:12 +0000 (05:37 +0000)]
Use makeArrayRef and None to simplify some code in a tablegen register info file. Additionally const correct a couple static array.
Previously the code added an extra nullptr entry to a static array and then created an ArrayRef with a size one less than the static array. If there were no other entries the array would just contain the nullptr and the ArrayRef would be crated with size 0.
Instead, put the right number of entries in the array and explicitly emit 'None' if the size would be 0. This allows the static array constructor of makeArrayRef to be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248244
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Matt Arsenault [Tue, 22 Sep 2015 04:17:45 +0000 (04:17 +0000)]
AMDGPU: Remove unnecessary check
If the instruction doesn't have enough operands, it
either shouldn't be marked as isCommutable or is malformed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248242
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Matthias Braun [Tue, 22 Sep 2015 03:44:41 +0000 (03:44 +0000)]
LiveIntervalAnalysis: Factor common code into splitSeparateComponents; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248241
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Davide Italiano [Tue, 22 Sep 2015 02:14:43 +0000 (02:14 +0000)]
[llvm-readobj/MachO] Ensure we always have valid CmdName/SegmentName.
Otherwise we might end up printing garbage while dumping.
Differential Revision: http://reviews.llvm.org/D13041
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248239
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Matthias Braun [Tue, 22 Sep 2015 01:52:44 +0000 (01:52 +0000)]
Remove declarations for methods that do not exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248238
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NAKAMURA Takumi [Tue, 22 Sep 2015 01:44:21 +0000 (01:44 +0000)]
Fix r248164. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248237
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Evgeniy Stepanov [Tue, 22 Sep 2015 00:44:32 +0000 (00:44 +0000)]
Remove unused TargetTransformInfo dependency from SafeStack pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248233
91177308-0d34-0410-b5e6-
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Michael Zolotukhin [Tue, 22 Sep 2015 00:22:47 +0000 (00:22 +0000)]
[LoopUnswitch] Require DominatorTree info.
Summary:
We should either require the DT info to be available, or check if it's
available in every place we use DT (and we already miss such check in
one place, which causes failures in some cases). As other loop passes
preserve DT and it's usually available, it makes sense to just require
it here.
There is no regression test, because the bug only shows up if pass
manager decides to clean DT info right before LoopUnswitch. If
loop-unswitch is run separately, DT is available, so bug isn't exposed.
Reviewers: chandlerc, hfinkel
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D13036
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248230
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Sanjoy Das [Tue, 22 Sep 2015 00:10:57 +0000 (00:10 +0000)]
[SCEV] Use SaveAndRestore<T> instead of a hand rolled struct; NFCI.
`ClearWalkingBEDominatingCondsOnExit` is exactly `SaveAndRestore<bool>`,
so use `SaveAndRestore<bool>` instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248227
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Sanjay Patel [Mon, 21 Sep 2015 23:03:16 +0000 (23:03 +0000)]
function names should start with a lower case letter; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248224
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Sanjay Patel [Mon, 21 Sep 2015 22:47:23 +0000 (22:47 +0000)]
don't repeat function/variable names in header comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248222
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