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Olof Johansson [Sun, 23 Sep 2018 13:37:47 +0000 (06:37 -0700)]
Merge tag 'hisi-arm64-dt-for-4.20' of git://github.com/hisilicon/linux-hisi into next/dt
ARM64: DT: Hisilicon SoC DT updates for 4.20
- Add missing clocks for Hi6220
- Switch to updated coresight bindings for Hi6220
- Add DT bindings and support for Hi3670 SoC and HiKey970 board
* tag 'hisi-arm64-dt-for-4.20' of git://github.com/hisilicon/linux-hisi:
arm64: dts: Add devicetree support for HiKey970 board
dt-bindings: arm: hisilicon: Add binding for HiKey970 board
arm64: dts: Add devicetree for Hisilicon Hi3670 SoC
dt-bindings: arm: hisilicon: Add binding for Hi3670 SoC
arm64: dts: hi6220: Update coresight bindings for hardware ports
arm64: dts: hisilicon: Add missing clocks property for CPUs
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Sun, 23 Sep 2018 13:36:16 +0000 (06:36 -0700)]
Merge tag 'stm32-dt-for-v4.20-1' of git://git./linux/kernel/git/atorgue/stm32 into next/dt
STM32 DT updates for v4.20, round 1
Highlights:
----------
- MCU platforms update:
- Add missing clock node's lobel on stm32f429
- Remove cd-inverted property for sdio nodes for all mcus
- Fix stm32h7 rtc binding
- MPU STM32MP157 platform update:
- Enable display: CEC and DSI
- Fix SPI node name to match with the new DTC
* tag 'stm32-dt-for-v4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
ARM: dts: stm32: Fix SPI controller node names
ARM: dts: stm32: enable display on stm32mp157c-ev1 board
ARM: dts: stm32: update rtc st,syscfg property on stm32h743
ARM: dts: stm32: Remove cd-inverted property for stm32f746-disco
ARM: dts: stm32: Remove cd-inverted property for stm32f769-disco
ARM: dts: stm32: Remove cd-inverted property for stm32f469-disco
ARM: dts: stm32: Remove cd-inverted property for stm32429i-eval
ARM: dts: stm32: Add clk-lse node's label on stm32f429
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Sun, 23 Sep 2018 13:33:56 +0000 (06:33 -0700)]
Merge tag 'ux500-dts-arm-soc' of git://git./linux/kernel/git/linusw/linux-stericsson into next/dt
Ux500 DTS changes for the v4.20 kernel cycle.
Assorted housekeeping DTS patches.
* tag 'ux500-dts-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: dts: ux500: Mark PRCMU as syscon compatible
arm: dts: ste: Update coresight bindings for hardware port
ARM: dts: ste: Fix SPI controller node names
ARM: dts: ux500: Get rid of DTC warnings
ARM: dts: ux500: Fix LCDA clock line muxing
dt-bindings: arm: scu: Correct example SCU unit addresses
ARM: dts: ux500: Correct SCU unit address
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Sun, 23 Sep 2018 13:32:33 +0000 (06:32 -0700)]
Merge tag 'aspeed-4.20-devicetree' of git://git./linux/kernel/git/joel/aspeed into next/dt
ASPEED device tree updates for 4.20
- Two new ast2500-based machines:
* Facebook TiogaPass (x86 server)
* HXT StarDragon 4800 Reference Evaluation Platform 2 (arm64 server)
- Updates for the Quanta q71l system
- i2c device tree cleanups
* tag 'aspeed-4.20-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed:
ARM: dts: aspeed: Adding Facebook TiogaPass BMC
ARM: dts: aspeed: Add HXT StarDragon 4800 REP2 BMC
ARM: dts: aspeed: quanta-q71l: Enable adc & ibt nodes
ARM: dts: aspeed: quanta-q71l: Add four PSUs
ARM: dts: aspeed: quanta-q71l: add aliases for i2c
ARM: dts: aspeed: Fix I2C bus warnings
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Sun, 23 Sep 2018 13:31:04 +0000 (06:31 -0700)]
Merge tag 'am654-for-v4.20' of git://git./linux/kernel/git/kristo/linux into next/dt
TI AM654 support for v4.20 merge window.
This branch adds changes for the Texas Instruments AM654 SoC. Included
changes are:
- Add uart nodes
- Change address cells and size-cells of interconnect tfrom 1 to 2
- Add secure proxy instance for main domain
- Add DMSC support
* tag 'am654-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
arm64: dts: ti: k3-am6: Add Device Management Security Controller support
arm64: dts: ti: am654: Add secure proxy instance for main domain
arm64: dts: ti: am654: Add uart nodes
arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Sun, 23 Sep 2018 13:28:51 +0000 (06:28 -0700)]
Merge tag 'juno-updates-4.20' of git://git./linux/kernel/git/sudeep.holla/linux into next/dt
ARMv8 Juno/Vexpress updates for v4.20
1. Enablement of scatter gather mode for CoreSight TMC-ETR routing
2. Usage of updated coresight graph bindings that eliminates loads of
dtc warnings
* tag 'juno-updates-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: Enable coresight tmc scatter gather in ETR
arm64: dts: juno: Update entries to match latest coresight bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Sun, 23 Sep 2018 13:28:19 +0000 (06:28 -0700)]
Merge tag 'arm-soc/for-4.20/devicetree-arm64' of https://github.com/Broadcom/stblinux into next/dt
This pull request contains Broadcom ARM64-based SoCs Device Tree changes
for 4.20, please pull the following:
- Stefan provides a reference to the Compute Module IO Board V3 such
that we can reference the arm counterpart and still build it for arm64
- Rob fixes I2C and SPI bus warnings which are going to show up with his
update to DTC scheduled for 4.20
* tag 'arm-soc/for-4.20/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: broadcom: Fix I2C and SPI bus warnings
arm64: dts: broadcom: Add reference to Compute Module IO Board V3
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Sun, 23 Sep 2018 13:24:28 +0000 (06:24 -0700)]
Merge tag 'arm-soc/for-4.20/devicetree' of https://github.com/Broadcom/stblinux into next/dt
This pull request contains Broadcom ARM-based SoCs Device Tree changes
for 4.20, please pull the following:
- Rafal updates the Broadcom BCM5301x (Northstar) DTS files to use the
new style partition parser and removes the unsupported/undocumented
linux,part-probe properties that were previously introduced
- Stefan adds supports for the Raspberry Pi Compute Module 3/3Lite, he
also updates the Raspberry Pi 3B+ USB Ethernet adapter to have proper
LED configuration
- Rob fixes a bunch of SPI bus warnings in the Northstar Plus and
Hurricane 2 DTS files
- Florian documents the Broadcom roboswitch Switch Register Access Block
(SRAB) interrupts, adds the switch interrupts to the Northstar Plus
DTS include file and finally updates the BCM958625HR reference board to
have the proper SFP module definition
* tag 'arm-soc/for-4.20/devicetree' of https://github.com/Broadcom/stblinux:
ARM: dts: bcm: Fix SPI bus warnings
ARM: dts: NSP: Wire up switch interrupts
dt-bindings: net: dsa: Document B53 SRAB interrupts and registers
ARM: dts: NSP: Enable SFP on bcm958625hr
ARM: dts: bcm283x-rpi-lan7515: Enable Ethernet LEDs
ARM: dts: BCM5301X: Specify flash partitions
ARM: dts: add Raspberry Pi Compute Module 3 and IO board
dt-bindings: bcm: Add Raspberry Pi CM3 and CM3L
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Sun, 23 Sep 2018 13:21:10 +0000 (06:21 -0700)]
Merge tag 'amlogic-dt64' of https://git./linux/kernel/git/khilman/linux-amlogic into next/dt
Amlogic ARM64 DT updates for v4.20
- AXG: cleanup/reorder nodes
- AXG: add audio PDM support for s400 board
- GX: increase CMA memory size
- GX: new canvas driver
* tag 'amlogic-dt64' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
arm64: dts: meson: Switch simple-mfd and syscon order
arm64: dts: meson-axg-s400: Add chosen and memory nodes
arm64: dts: meson-axg: use the proper compatible for ethmac
arm64: dts: meson-axg: s400: add pdm to the sound card
arm64: dts: meson-axg: s400: add dmic codec
arm64: dts: meson-axg: add pdm
arm64: dts: meson-gx: add dmcbus and canvas nodes.
arm64: dts: meson: libretech: update board model
arm64: dts: meson-gx: increase default shared CMA pool size
arm64: dts: meson-axg: sort nodes consistently
arm64: dts: meson-axg: s400: add sound card
arm64: dts: meson-axg: s400: enable audio devices
arm64: dts: meson-axg: add audio fifos
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Sun, 23 Sep 2018 13:20:06 +0000 (06:20 -0700)]
Merge tag 'v4.20-rockchip-dts64-1' of git://git./linux/kernel/git/mmind/linux-rockchip into next/dt
New soc support for the px30 quad-core Cortex-A35.
New boards are the px30 eval board and roc-rk3399-pc.
The rk3328 got support for the one gpio controlled via the general
register files and the rk3399 finally got its idle-states defined.
And finally fixes and improvements for firefly-rk3399 (wifi),
roc-rk3328-cc (sdmmc-uhs, io-domains), rk3328-rock64 (gpio-regulator
pin fix) and rk3399-sapphire (gpio-regulator pin fix, pmic pin fix
and type-c port supply).
* tag 'v4.20-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Add type-c port supply on rk3399-sapphire board
arm64: dts: rockchip: fix vcc_host1_5v pin assign on rk3328-rock64
arm64: dts: rockchip: add WiFi module support for Firefly-RK3399
arm64: dts: rockchip: remove dvs2 pinctrl from pmic on rk3399-sapphire
arm64: dts: rockchip: Fix VCC5V0_HOST_EN on rk3399-sapphire
arm64: dts: rockchip: re-order vcc_sys on rk3399-sapphire
arm64: dts: rockchip: add missing vop properties for px30
arm64: dts: rockchip: Add idle-states to device tree for rk3399
arm64: dts: rockchip: add sdmmc UHS support for roc-rk3328-cc
arm64: dts: rockchip: add GRF GPIO controller to rk3328
arm64: dts: rockchip: add io-domain to roc-rk3328-cc
arm64: dts: rockchip: add PX30 evaluation board devicetree
arm64: dts: rockchip: add core dtsi file for PX30 SoCs
dt-bindings: rockchip: grf: add grf and pmugrf description for px30
arm64: dts: rockchip: add support for ROC-RK3399-PC board
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Sun, 23 Sep 2018 13:19:04 +0000 (06:19 -0700)]
Merge tag 'renesas-arm64-dt-for-v4.20' of https://git./linux/kernel/git/horms/renesas into next/dt
Renesas ARM64 Based SoC DT Updates for v4.20
* Correct whitespace around assignments
* R-Car Gen-3 SoCs:
- Enable SDR104 for SD devices
- Include R-Car product name in DTSI files to ease maintenance
* R-Car Gen-3 SoC based boards: Convert to new LVDS DT bindings
* R-Car Gen 3 Salvator-X and Salvator-XS boards:
- Override secondary addresses of ADV748x to avoid address conflicts
* R-Car Gen 3 based Salvator-XS board: Enable SATA
* R-Car M3-N (r8a77965) SoC:
- Add FDP1 device nodes
- Move arm_cc630p and timer nodes to restore sort-order of file
- Correct clock/reset for usb2_phy1
- Correct HS-USB compat string
- Add OPPs table for cpu devices enabling CPUFreq support
- Add CAN device placeholder nodes to facilitate adding
initial device tree for KF daughter board
- Attach SYS-DMAC to the IPMMU
* R-Car M3-N (r8a77965) based ULCB board:
- Initial device tree for board and KF daughter board
* R-Car E3 (r8a77990) SoC:
- Add SYS-DMAC, I2C VIN, CSI-2, MSIOF device nodes
- Add BRG support to SCIF2 which allows an increase in serial clock accuracy
- Use CPG/MSSR and SYSC binding definitions
* R-Car E3 (r8a77990) based Ebisu board: Enable PWM
* R-Car D3 (r8a77995) SoC: Attach the SYS-DMAC to the IPMMU
* R-Car D3 (r8a77995) based Draak board: Sort device nodes
* R-Car V3H (r8a77980) based V3HSK board:
- Move lvds0 node to restore sort-order of file
* R-Car V3H (r8a77980) SoC:
- Add RWDT, CSI2 and VIN, Cortex-A53 PMU nodes
- Move IPMMU and CAN clock nodes to restore sort-order of file
* R-Car V3M (r8a77970) SoC:
- Add MMC nodes
- Move CAN clock node to restore sort-order of file
* R-Car V3M (r8a77970) based V3MSK board: Add eMMC support
* R-Car V3H (r8a77980) based Condor board: Add PCIe, DU, LVDS and HDMI support
* RZ/G2M (r8a774a1) SoC:
- Initial device tree
- Add SYS-DMAC, SCIF, HSCIF, INTC-EX, EtherAVB, RWDT, pinctl, GPIO,
SDHI, I2C, IIC-DVFS, thermal, IPMMU, MSIOF, Cortex-A53 CPU core,
PWM, Audio, FCPF, FCPV, USB2.0, USB-DMAC, HSUSB and USB3.0 device nodes
* tag 'renesas-arm64-dt-for-v4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (58 commits)
arm64: dts: r8a77965: add FDP1 device nodes
arm64: dts: renesas: draak: Sort device nodes
arm64: dts: renesas: enable SDR104 on R-Car Gen3
arm64: dts: renesas: r8a77990: Add SYS-DMAC device nodes
arm64: dts: renesas: r8a77990: Add I2C device nodes
arm64: dts: renesas: r8a77990: Add VIN and CSI-2 device nodes
arm64: dts: renesas: r8a77990: Add all MSIOF nodes
arm64: dts: renesas: r8a7795: Move arm_cc630p node
arm64: dts: renesas: r8a77990: Add BRG support to SCIF2
arm64: dts: renesas: r8a77990: Use CPG/MSSR and SYSC binding definitions
arm64: dts: renesas: salvator-xs: Improve SATA switch settings comments
arm64: dts: renesas: r8a77965: Fix clock/reset for usb2_phy1
arm64: dts: renesas: r8a77965: Fix HS-USB compatible
arm64: dts: renesas: r8a77965: Move timer node
arm64: dts: renesas: v3hsk: Move lvds0 node
arm64: dts: renesas: Fix whitespace around assignments
arm64: dts: renesas: r8a77965: m3nulcb-kf: Initial device tree
arm64: dts: renesas: condor: add PCIe support
arm64: dts: renesas: r8a77980: add PCIe support
arm64: dts: renesas: r8a774a1: Add USB3.0 device nodes
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Sun, 23 Sep 2018 13:14:40 +0000 (06:14 -0700)]
Merge tag 'renesas-arm-dt-for-v4.20' of https://git./linux/kernel/git/horms/renesas into next/dt
Renesas ARM Based SoC DT Updates for v4.20
* R-Car Gen1 SoCs: Include product name in DTSI files for ease of maintenance
* R-Car Gen2 SoCs:
- Convert to new DU DT bindings
- Correct SATA device sizes to 2 MiB
* R-Car H2 (r8a7790) based Porter board: Add DA9063 OnKey PMIC node
* R-Car E2 (r8a7794) based Silk board: Add DA9063 PMIC, RTC and OnKey nodes
* R-Car M2-N (r8a7793) based Gose board: Add DA9210 node for CPU DVFS
* RZ/G1C (R8A77470) SoC:
- Add GPIO nodes
- Add PFC support
- Use r8a77470-sysc binding definitions
* RZ/G1C (r8a77470) iW-RainboW-G23S dev platform:
- Specify EtherAVB PHY IRQ
- Add pinctl support for scif1
* RZ/N1D (r9a06g032) SoC: Use r9a06g032-sysctrl binding definitions
* tag 'renesas-arm-dt-for-v4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: dts: r9a06g032: Use r9a06g032-sysctrl binding definitions
ARM: dts: Include R-Car Gen1 product name in DTSI files
ARM: dts: stout: Add DA9063 OnKey node
ARM: dts: silk: Add DA9063 RTC and OnKey node
ARM: dts: iwg23s-sbc: specify EtherAVB PHY IRQ
ARM: dts: r8a77470: Add GPIO support
ARM: dts: silk: Add DA9063 PMIC node
ARM: dts: gose: Add DA9210 node for CPU DVFS
ARM: dts: rcar-gen2: Convert to new DU DT bindings
ARM: dts: iwg23s-sbc: Add pinctl support for scif1
ARM: dts: r8a77470: Add PFC support
ARM: dts: r8a77470: Use r8a77470-sysc binding definitions
ARM: dts: rcar: Correct SATA device sizes to 2 MiB
Signed-off-by: Olof Johansson <olof@lixom.net>
Rob Herring [Fri, 21 Sep 2018 12:25:41 +0000 (14:25 +0200)]
ARM: dts: stm32: Fix SPI controller node names
SPI controller nodes should be named 'spi' rather than 'qspi'. Fixing the
name enables dtc SPI bus checks.
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Yannick Fertré [Thu, 20 Sep 2018 14:33:52 +0000 (16:33 +0200)]
ARM: dts: stm32: enable display on stm32mp157c-ev1 board
Enable panel raydium RM68200, DSI bridge & display controller.
Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Linus Walleij [Thu, 12 Jul 2018 12:52:00 +0000 (14:52 +0200)]
ARM: dts: ux500: Mark PRCMU as syscon compatible
We need to distribute out the responsibilities of the PRCMU
registers instead of having one big lump handling everything.
By making it syscon compatible, we can start grabbing the
register map elsewhere when needed.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Suzuki K Poulose [Wed, 12 Sep 2018 13:53:52 +0000 (14:53 +0100)]
arm: dts: ste: Update coresight bindings for hardware port
Switch to the new coresight bindings
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Rob Herring [Thu, 13 Sep 2018 18:12:34 +0000 (13:12 -0500)]
ARM: dts: ste: Fix SPI controller node names
SPI controller nodes should be named 'spi' rather than 'ssp'. Fixing the
name enables dtc SPI bus checks.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Tue, 3 Jul 2018 08:03:47 +0000 (10:03 +0200)]
ARM: dts: ux500: Get rid of DTC warnings
By removing the reference to skeleton.dtsi, defining chosen {}
and proper memory nodes we get warning-free device trees for
the Ux500.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Tue, 3 Jul 2018 08:30:03 +0000 (10:30 +0200)]
ARM: dts: ux500: Fix LCDA clock line muxing
The "lcdaclk_b_1" group is muxed with the function "lcd"
but needs a separate entry to be muxed in with "lcda"
rather than "lcd".
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Geert Uytterhoeven [Tue, 26 Jun 2018 07:50:10 +0000 (09:50 +0200)]
dt-bindings: arm: scu: Correct example SCU unit addresses
The unit addresses of the Cortex-A9 SCU device nodes contain too many
zeroes. Remove them.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Geert Uytterhoeven [Tue, 26 Jun 2018 07:50:09 +0000 (09:50 +0200)]
ARM: dts: ux500: Correct SCU unit address
The unit address of the Cortex-A9 SCU device node contains one zero too
many. Remove it.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Vijay Khemka [Tue, 18 Sep 2018 23:41:08 +0000 (16:41 -0700)]
ARM: dts: aspeed: Adding Facebook TiogaPass BMC
Initial introduction of Facebook TiogaPass family equipped with
Aspeed 2500 BMC SoC. TiogaPass is a x86 server development kit
with a ASPEED ast2500 BMC manufactured by Facebook.
Specifically, This adds the TiogaPass platform device tree file
including the flash layout used by the TiogaPass BMC machines.
Signed-off-by: Vijay Khemka <vijaykhemka@fb.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Yuan Yao [Thu, 13 Sep 2018 02:25:16 +0000 (10:25 +0800)]
ARM: dts: aspeed: Add HXT StarDragon 4800 REP2 BMC
The HXT StarDragon 4800 REP2 (Reference Evaluation Platform) is
an aarch64 ARMv8 server platform with an ast2520 BMC.
Signed-off-by: Yuan Yao <yao.yuan@linaro.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Amelie Delaunay [Wed, 22 Aug 2018 09:45:00 +0000 (11:45 +0200)]
ARM: dts: stm32: update rtc st,syscfg property on stm32h743
To fit with latest rtc driver updates, rtc st,syscfg property must contain
the control register offset of pwrcfg and the mask corresponding to the
DBP (Disable Backup Protection) bit.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Patrice Chotard [Thu, 26 Jul 2018 07:19:00 +0000 (09:19 +0200)]
ARM: dts: stm32: Remove cd-inverted property for stm32f746-disco
Remove cd-inverted property and update cd-gpios active level
accordingly
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Patrice Chotard [Thu, 26 Jul 2018 07:19:00 +0000 (09:19 +0200)]
ARM: dts: stm32: Remove cd-inverted property for stm32f769-disco
Remove cd-inverted property and update cd-gpios active level
accordingly
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Patrice Chotard [Thu, 26 Jul 2018 07:19:00 +0000 (09:19 +0200)]
ARM: dts: stm32: Remove cd-inverted property for stm32f469-disco
Remove cd-inverted property and update cd-gpios active level
accordingly
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Patrice Chotard [Thu, 26 Jul 2018 07:19:00 +0000 (09:19 +0200)]
ARM: dts: stm32: Remove cd-inverted property for stm32429i-eval
Remove cd-inverted property and update cd-gpios active level
accordingly
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Patrice Chotard [Thu, 19 Jul 2018 13:35:00 +0000 (15:35 +0200)]
ARM: dts: stm32: Add clk-lse node's label on stm32f429
Add missing clk_lse label for node clk-lse.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Manivannan Sadhasivam [Fri, 10 Aug 2018 17:53:39 +0000 (23:23 +0530)]
arm64: dts: Add devicetree support for HiKey970 board
Add devicetree support for HiKey970 development board which
based on Hi3670 SoC and is also one of the 96Boards Consumer
Edition and AI platform.
Only UART6 is enabled which is the default console required
by the 96Boards Consumer Edition Specification.
This patch has been tested on HiKey970 Board.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Manivannan Sadhasivam [Fri, 10 Aug 2018 17:53:38 +0000 (23:23 +0530)]
dt-bindings: arm: hisilicon: Add binding for HiKey970 board
Add devicetree binding for HiKey970 board.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Manivannan Sadhasivam [Fri, 10 Aug 2018 17:53:37 +0000 (23:23 +0530)]
arm64: dts: Add devicetree for Hisilicon Hi3670 SoC
Add initial devicetree support for Hisilicon Hi3670 SoC which
is similar to Hi3660 SoC with NPU support.
This SoC has Octal core BigLittle CPUs in two clusters(4 * A53 & 4 * A73).
Only UART6 has been added for console support which is
pre configured by the bootloader. A fixed clock is sourcing
the UART6 which will get replaced by the clock driver when available.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Manivannan Sadhasivam [Fri, 10 Aug 2018 17:53:36 +0000 (23:23 +0530)]
dt-bindings: arm: hisilicon: Add binding for Hi3670 SoC
Add devicetree binding for Hi3670 SoC.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Suzuki K Poulose [Wed, 12 Sep 2018 13:53:44 +0000 (14:53 +0100)]
arm64: dts: hi6220: Update coresight bindings for hardware ports
Switch to updated coresight bindings for hw ports.
Cc: xuwei5@hisilicon.com
Cc: lipengcheng8@huawei.com
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Tested-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Viresh Kumar [Mon, 23 Jul 2018 03:06:42 +0000 (08:36 +0530)]
arm64: dts: hisilicon: Add missing clocks property for CPUs
The clocks property should either be present for all the CPUs of a
cluster or none. If these are present only for a subset of CPUs of a
cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.
Add missing clocks property.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Nishanth Menon [Wed, 5 Sep 2018 16:20:24 +0000 (11:20 -0500)]
arm64: dts: ti: k3-am6: Add Device Management Security Controller support
Add TISCI compatible System controller for AM6 SoCs.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Nishanth Menon [Wed, 5 Sep 2018 16:20:23 +0000 (11:20 -0500)]
arm64: dts: ti: am654: Add secure proxy instance for main domain
Add secure proxy instance for Main domain
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Nishanth Menon [Wed, 5 Sep 2018 16:20:22 +0000 (11:20 -0500)]
arm64: dts: ti: am654: Add uart nodes
Add uart nodes for AM654 device tree components.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Kishon Vijay Abraham I [Wed, 5 Sep 2018 11:17:38 +0000 (16:47 +0530)]
arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2
AM65 has two PCIe controllers and each PCIe controller has '2' address
spaces one within the 4GB address space of the SoC and the other above
the 4GB address space of the SoC (cbass_main) in addition to the
register space. The size of the address space above the 4GB SoC address
space is 4GB. These address ranges will be used by CPU/DMA to access
the PCIe address space. In order to represent the address space above
the 4GB SoC address space and to represent the size of this address
space as 4GB, change address-cells and size-cells of interconnect to 2.
Since OSPI has similar need in MCU Domain Memory Map, change
address-cells and size-cells of cbass_mcu interconnect also to 2.
Fixes:
ea47eed33a3fe3d919 ("arm64: dts: ti: Add Support for AM654 SoC")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Vignesh R <vigneshr@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Patrick Venture [Tue, 4 Sep 2018 15:53:29 +0000 (08:53 -0700)]
ARM: dts: aspeed: quanta-q71l: Enable adc & ibt nodes
This machine uses the ADC and iBT devices.
Signed-off-by: Patrick Venture <venture@google.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Patrick Venture [Fri, 31 Aug 2018 20:58:55 +0000 (13:58 -0700)]
ARM: dts: aspeed: quanta-q71l: Add four PSUs
Enable the four PSUs via generic PMBUS.
Signed-off-by: Patrick Venture <venture@google.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Patrick Venture [Fri, 31 Aug 2018 20:58:39 +0000 (13:58 -0700)]
ARM: dts: aspeed: quanta-q71l: add aliases for i2c
Provide aliases to each i2c bus per labels added for
each PCIe slot, etc, that are downstream beyond a mux.
Signed-off-by: Patrick Venture <venture@google.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Rob Herring [Thu, 13 Sep 2018 18:12:27 +0000 (13:12 -0500)]
ARM: dts: aspeed: Fix I2C bus warnings
dtc has new checks for I2C buses. The ASpeed dts files have a node named
'i2c' which causes a false positive warning. As the node is a 'simple-bus',
correct the node name to be 'bus' to fix the warnings.
arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@
1e78a000: incorrect #size-cells for I2C bus
arch/arm/boot/dts/aspeed-bmc-opp-romulus.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@
1e78a000: incorrect #size-cells for I2C bus
arch/arm/boot/dts/aspeed-ast2500-evb.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@
1e78a000: incorrect #size-cells for I2C bus
arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@
1e78a000: incorrect #size-cells for I2C bus
arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@
1e78a000: incorrect #size-cells for I2C bus
arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@
1e78a000: incorrect #size-cells for I2C bus
arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@
1e78a000: incorrect #size-cells for I2C bus
arch/arm/boot/dts/aspeed-bmc-opp-zaius.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@
1e78a000: incorrect #size-cells for I2C bus
arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@
1e78a000: incorrect #size-cells for I2C bus
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@
1e78a000: incorrect #size-cells for I2C bus
Cc: Joel Stanley <joel@jms.id.au>
Cc: Andrew Jeffery <andrew@aj.id.au>
Cc: linux-aspeed@lists.ozlabs.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Rob Herring [Thu, 13 Sep 2018 18:12:30 +0000 (13:12 -0500)]
ARM: dts: bcm: Fix SPI bus warnings
dtc has new checks for SPI buses. Fix the warnings in node names.
arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dtb: Warning (spi_bus_bridge): /axi@
18000000/qspi@27200: node name for SPI buses should be 'spi'
arch/arm/boot/dts/bcm958525er.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi'
arch/arm/boot/dts/bcm958525xmc.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi'
arch/arm/boot/dts/bcm958622hr.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi'
arch/arm/boot/dts/bcm958625hr.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi'
arch/arm/boot/dts/bcm988312hr.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi'
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: Jon Mason <jonmason@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Rob Herring [Thu, 13 Sep 2018 18:12:42 +0000 (13:12 -0500)]
arm64: dts: broadcom: Fix I2C and SPI bus warnings
dtc has new checks for I2C and SPI buses. Fix the warnings in node names
and unit-addresses.
arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dtb: Warning (i2c_bus_reg): /hsls/i2c@e0000/pcf8574@20: I2C bus unit address format error, expected "27"
arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dtb: Warning (i2c_bus_reg): /hsls/i2c@e0000/pcf8574@20: I2C bus unit address format error, expected "27"
arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dtb: Warning (spi_bus_bridge): /hsls/ssp@180000: node name for SPI buses should be 'spi'
arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dtb: Warning (spi_bus_bridge): /hsls/ssp@190000: node name for SPI buses should be 'spi'
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: Jon Mason <jonmason@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Florian Fainelli [Thu, 13 Sep 2018 18:13:30 +0000 (11:13 -0700)]
Merge tag 'tags/bcm2835-dt-next-2018-09-09' into devicetree/next
This pull request brings in a board DT for the Raspberry Pi Compute
Module 3, its I/O board and enables the Ethernet LEDs for the RPi 3B+.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Florian Fainelli [Fri, 31 Aug 2018 19:20:39 +0000 (12:20 -0700)]
ARM: dts: NSP: Wire up switch interrupts
The Switch Register Access Block (SRAB) has one interrupt for link state
change on each ports (0-5, 7-8) a PHY interrupt, timestamping interrupt
and sleep timer interrupts for each management ports (5,7,8). Wire those
up so we can utilize them to speed up link resolution.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Florian Fainelli [Fri, 31 Aug 2018 19:20:38 +0000 (12:20 -0700)]
dt-bindings: net: dsa: Document B53 SRAB interrupts and registers
Document the Broadcom roboswitch Switch Register Access Block interrupt
lines and additional register base addresses for port mux configuration
and SGMII status/configuration registers.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Florian Fainelli [Fri, 31 Aug 2018 19:20:37 +0000 (12:20 -0700)]
ARM: dts: NSP: Enable SFP on bcm958625hr
Enable the SFP connected to port 5 of the switch and wire up all GPIOs
to the SFP cage. Because of a hardware limitation of the i2c controller
on the iProc SoCs which prevents large i2c (> 63 bytes) transactions to
work, we use the i2c-gpio interface instead, which does not have that
limitation. This allows us to read the SFP module EEPROM, which would
not be possible otherwise since it exceeds that size during a single
read transfer.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Neil Armstrong [Thu, 13 Sep 2018 07:12:27 +0000 (09:12 +0200)]
arm64: dts: meson: Switch simple-mfd and syscon order
The order between "syscon" and "simple-mfd" is important because in these
particular cases, the node needs to be first a "simple-mfd" to expose
it's sub-nodes, and later on a "syscon" to permit other nodes to access
this register space through the "syscon" mechanism.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Hoan Nguyen An [Fri, 24 Aug 2018 04:52:28 +0000 (13:52 +0900)]
arm64: dts: r8a77965: add FDP1 device nodes
The r8a77965 has a single FDP1 instance.
Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Thu, 6 Sep 2018 12:41:01 +0000 (14:41 +0200)]
arm64: dts: renesas: draak: Sort device nodes
- Device nodes with unit addresses are sorted by unit address,
- Device nodes without unit addresses and references are sorted
alphabetically.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Wolfram Sang [Tue, 21 Aug 2018 19:03:56 +0000 (21:03 +0200)]
arm64: dts: renesas: enable SDR104 on R-Car Gen3
Successfully tested on H3 ES1.0 and ES2.0, M3-W ES1.0, and M3-N ES1.0.
Even previously stubborn cards work fine. Transfer rates were >60MB/s.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Takeshi Kihara [Tue, 4 Sep 2018 20:22:27 +0000 (05:22 +0900)]
arm64: dts: renesas: r8a77990: Add SYS-DMAC device nodes
This patch adds SYS-DMAC{0,1,2} device nodes for the R8A77990 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Takeshi Kihara [Wed, 5 Sep 2018 15:29:44 +0000 (17:29 +0200)]
arm64: dts: renesas: r8a77990: Add I2C device nodes
Add device nodes for I2C ch[0-7] to R-Car E3 R8A77990 device tree.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Koji Matsuoka [Wed, 5 Sep 2018 15:29:43 +0000 (17:29 +0200)]
arm64: dts: renesas: r8a77990: Add VIN and CSI-2 device nodes
Add device nodes for VIN4, VIN5 and CSI40 to R-Car E3 R8A77990 device tree.
Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[simon: sorted nodes by bus address, then IP block]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Mon, 3 Sep 2018 17:30:00 +0000 (19:30 +0200)]
arm64: dts: renesas: r8a77990: Add all MSIOF nodes
Add the device nodes for all MSIOF SPI controllers, incl. clocks, power
domains, and resets properties.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Fri, 31 Aug 2018 08:54:57 +0000 (10:54 +0200)]
arm64: dts: renesas: r8a7795: Move arm_cc630p node
To preserve by-address-per-group sort order.
Fixes:
0f6d237cafda2e06 ("arm64: dts: renesas: r8a7795: add ccree to device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Takeshi Kihara [Thu, 30 Aug 2018 14:56:35 +0000 (16:56 +0200)]
arm64: dts: renesas: r8a77990: Add BRG support to SCIF2
Add the device node for the external SCIF_CLK, and describe the clock
inputs for the Baud Rate Generator for External Clock (BRG) for SCIF2,
which can increase serial clock accuracy.
The presence of the SCIF_CLK crystal and its clock frequency depend on
the actual board.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Enhance patch description]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Thu, 30 Aug 2018 14:52:20 +0000 (16:52 +0200)]
arm64: dts: renesas: r8a77990: Use CPG/MSSR and SYSC binding definitions
Use the SoC-specific CPG/MSSR include file to allow future use of
R8A77990_CLK_* symbols.
Replace the hardcoded power domain indices by R8A77990_PD_* symbols.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Thu, 30 Aug 2018 12:39:19 +0000 (14:39 +0200)]
arm64: dts: renesas: salvator-xs: Improve SATA switch settings comments
The comments describing the non-default switch settings to use SATA are
confusing: 'Off' refers to the switch position, not to the MD12 logic
value, while the parentheses suggest otherwise. Rephrase to fix this.
Fixes:
bec000784d5bb571 ("arm64: dts: renesas: salvator-xs: enable SATA")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Tue, 28 Aug 2018 14:13:27 +0000 (16:13 +0200)]
arm64: dts: renesas: r8a77965: Fix clock/reset for usb2_phy1
usb2_phy1 accidentally uses the same clock/reset as usb2_phy0.
Fixes:
b5857630a829a8d5 ("arm64: dts: renesas: r8a77965: add usb2_phy nodes")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Tue, 28 Aug 2018 13:57:02 +0000 (15:57 +0200)]
arm64: dts: renesas: r8a77965: Fix HS-USB compatible
Should be "renesas,usbhs-r8a77965", not "renesas,usbhs-r8a7796".
Fixes:
a06e8af801760a98 ("arm64: dts: renesas: r8a77965: add HS-USB node")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Tue, 28 Aug 2018 14:14:44 +0000 (16:14 +0200)]
arm64: dts: renesas: r8a77965: Move timer node
To preserve alphabetical sort order.
Fixes:
4c529600eef0a6b7 ("arm64: dts: renesas: r8a77965: Add R-Car Gen3 thermal support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Tue, 28 Aug 2018 14:15:40 +0000 (16:15 +0200)]
arm64: dts: renesas: v3hsk: Move lvds0 node
To preserve alphabetical sort order.
Fixes:
4edac426aff11a37 ("arm64: dts: renesas: condor/v3hsk: add DU/LVDS/HDMI support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Tue, 28 Aug 2018 14:10:59 +0000 (16:10 +0200)]
arm64: dts: renesas: Fix whitespace around assignments
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[simon: updated for a few new cases]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Eugeniu Rosca [Sun, 12 Aug 2018 13:31:49 +0000 (15:31 +0200)]
arm64: dts: renesas: r8a77965: m3nulcb-kf: Initial device tree
This is based on the existing KF device tree sources:
$ ls -1 arch/arm64/boot/dts/renesas/*-kf.dts
arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts
arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Sergei Shtylyov [Mon, 27 Aug 2018 18:54:35 +0000 (21:54 +0300)]
arm64: dts: renesas: condor: add PCIe support
Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor
board.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Sergei Shtylyov [Mon, 27 Aug 2018 18:53:40 +0000 (21:53 +0300)]
arm64: dts: renesas: r8a77980: add PCIe support
Describe the PCIe PHY, PCIEC, and PCIe bus clock in the R8A77980 device
tree.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Fri, 24 Aug 2018 10:43:49 +0000 (11:43 +0100)]
arm64: dts: renesas: r8a774a1: Add USB3.0 device nodes
Add usb3.0 phy, host and function device nodes on RZ/G2M SoC dtsi.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Fri, 24 Aug 2018 10:43:48 +0000 (11:43 +0100)]
arm64: dts: renesas: r8a774a1: Add USB-DMAC and HSUSB device nodes
Add usb dmac and hsusb device nodes on RZ/G2M SoC dtsi.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Fri, 24 Aug 2018 10:43:47 +0000 (11:43 +0100)]
arm64: dts: renesas: r8a774a1: Add USB2.0 phy and host(EHCI/OHCI) device nodes
Add USB2.0 phy and host (EHCI/OHCI) device nodes on RZ/G2M SoC dtsi.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fabrizio Castro [Fri, 24 Aug 2018 10:21:14 +0000 (11:21 +0100)]
arm64: dts: renesas: r8a774a1: Add FCPF and FCPV instances
Add FCPF and FCPV instances to the r8a774a1 dtsi, similarly
to what was done for the r8a7796 with commit
41dbbf0c5b4e
("arm64: dts: r8a7796: Add FCPF and FCPV instances"),
commit
69490bc9665d ("arm64: dts: renesas: r8a7796: Point
FDP1 via FCPF to IPMMU-VI0"), and commit
cef942d0bd89 ("arm64:
dts: renesas: r8a7796: Point VSPI via FCPVI to IPMMU-VC0").
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Thu, 23 Aug 2018 13:43:07 +0000 (14:43 +0100)]
arm64: dts: renesas: r8a774a1: Add audio support
Add sound support for the RZ/G2M SoC (a.k.a. R8A774A1).
This work is based on similar work done on the R8A7796 SoC
by Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fabrizio Castro [Thu, 23 Aug 2018 13:43:06 +0000 (14:43 +0100)]
arm64: dts: renesas: r8a774a1: Add PWM device nodes
This patch adds PWM[
0123456] device nodes to the RZ/G2M (a.k.a R8A774A1)
device tree.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Thu, 23 Aug 2018 13:43:05 +0000 (14:43 +0100)]
arm64: dts: renesas: r8a774a1: Add Cortex-A53 CPU cores
This patch adds definitions for L2 cache for the Cortex-A53 CPU
cores (512 KiB in size, organized as 32 KiB x 16 ways), adds
Cortex-A53 CPU cores (setting a total of 6 cores, 2 x Cortex-A57
+ 4 x Cortex-A53), and finally enables the performance monitor
unit for the Cortex-A53 cores on the R8A774A1 SoC.
Based on work done for r8a7796 SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Thu, 23 Aug 2018 13:43:04 +0000 (14:43 +0100)]
arm64: dts: renesas: r8a774a1: Add all MSIOF nodes
Add the device nodes for all MSIOF SPI controllers on RZ/G2M SoC.
Based on several similar patches of the R8A7796 device tree
by Geert Uytterhoeven <geert+renesas@glider.be>
and Simon Horman <horms+renesas@verge.net.au>.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fabrizio Castro [Thu, 23 Aug 2018 13:43:03 +0000 (14:43 +0100)]
arm64: dts: renesas: r8a774a1: Add IPMMU device nodes
Add r8a774a1 IPMMU nodes.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Thu, 23 Aug 2018 13:43:02 +0000 (14:43 +0100)]
arm64: dts: renesas: r8a774a1: Add RZ/G2M thermal support
Add thermal support for R8A774A1 (RZ/G2M) SoC.
Based on the work done for r8a7796 SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Thu, 23 Aug 2018 13:43:01 +0000 (14:43 +0100)]
arm64: dts: renesas: r8a774a1: Add I2C and IIC-DVFS support
Add the I2C[0-6] and IIC Bus Interface for DVFS (IIC for DVFS)
devices nodes to the r8a774a1 device tree.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fabrizio Castro [Thu, 23 Aug 2018 13:43:00 +0000 (14:43 +0100)]
arm64: dts: renesas: r8a774a1: Add SDHI nodes
Add SDHI nodes to the DT of the r8a774a1 SoC.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fabrizio Castro [Thu, 23 Aug 2018 14:18:18 +0000 (15:18 +0100)]
arm64: dts: renesas: r8a774a1: Add GPIO device nodes
Add GPIO device nodes to the DT of the r8a774a1 SoC.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fabrizio Castro [Thu, 23 Aug 2018 14:13:16 +0000 (15:13 +0100)]
arm64: dts: renesas: r8a774a1: Add pinctrl device node
This patch adds pinctrl device node for R8A774A1 SoC.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Thu, 23 Aug 2018 08:58:51 +0000 (09:58 +0100)]
arm64: dts: renesas: r8a774a1: Add RWDT node
Add a device node for the Watchdog Timer (RWDT) controller on the Renesas
RZ/G2M (r8a774a1) SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fabrizio Castro [Thu, 23 Aug 2018 08:58:50 +0000 (09:58 +0100)]
arm64: dts: renesas: r8a774a1: Add Ethernet AVB node
This patch adds the SoC specific part of the Ethernet AVB
device tree node.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Thu, 23 Aug 2018 08:58:49 +0000 (09:58 +0100)]
arm64: dts: renesas: r8a774a1: Add INTC-EX device node
Add support for the Interrupt Controller for External Devices
(INTC-EX) on RZ/G2M.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fabrizio Castro [Thu, 23 Aug 2018 08:58:48 +0000 (09:58 +0100)]
arm64: dts: renesas: r8a774a1: Add SCIF and HSCIF nodes
Add the device nodes for all RZ/G2M SCIF and HSCIF serial ports,
incl. clocks, power domains and DMAs.
According to the HW user manual, SCIF[015] and HSCIF[012] are
connected to both SYS-DMAC1 and SYS-DMAC2, while SCIF[34] and
HSCIF[34] are connected to SYS-DMAC0.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Thu, 23 Aug 2018 08:58:47 +0000 (09:58 +0100)]
arm64: dts: renesas: r8a774a1: Add SYS-DMAC controller nodes
Add sys-dmac[0-2] device nodes for RZ/G2M (r8a774a1) SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Sergei Shtylyov [Thu, 23 Aug 2018 16:59:20 +0000 (19:59 +0300)]
arm64: dts: renesas: condor/v3hsk: add DU/LVDS/HDMI support
Define the Condor/V3HSK board dependent parts of the DU and LVDS device
nodes. Also add the device nodes for Thine THC63LVD1024 LVDS decoder and
Analog Devices ADV7511W HDMI transmitter...
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Sergei Shtylyov [Tue, 21 Aug 2018 19:50:31 +0000 (22:50 +0300)]
arm64: dts: renesas: v3msk: add eMMC support
Add the eMMC chip support for the V3M Started Kit board.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Sergei Shtylyov [Tue, 21 Aug 2018 19:49:26 +0000 (22:49 +0300)]
arm64: dts: renesas: r8a77970: add MMC support
Define the generic R8A77970 part of the MMC0 (SDHI2) device node.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Dien Pham [Tue, 14 Aug 2018 14:12:41 +0000 (23:12 +0900)]
arm64: dts: renesas: r8a77965: Add OPPs table for cpu devices
This patch adds OPPs table for CA57{0,1} cpu devices
Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
[simon: do not give nodes unit names as they have no bus addresses]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Eugeniu Rosca [Sun, 12 Aug 2018 13:31:46 +0000 (15:31 +0200)]
arm64: dts: renesas: r8a77965: m3nulcb: Initial device tree
Allow the bare M3-N-based ULCB board to boot.
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Eugeniu Rosca [Sun, 12 Aug 2018 13:31:47 +0000 (15:31 +0200)]
arm64: dts: renesas: r8a77965: Add CAN{0,1} placeholder nodes
According to R-Car Gen3 HW manual rev1.00, R-Car M3-N has two CAN
interfaces, similar to H3, M3-W and other SoCs from the same family.
Add CAN placeholder nodes to avoid below DTC errors:
Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:19.1-6 Label or path can0 not found
Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:25.1-6 Label or path can1 not found
These errors occur *after* the addition of r8a77965-m3nulcb-kf.dts.
Fix them beforehand.
CAN support is inspired from below commits:
- v4.7 commit
308b7e4ba62e ("arm64: dts: r8a7795: Add CAN support")
- v4.11 commit
909c16252415 ("arm64: dts: r8a7796: Add CAN support")
- v4.12 commit
bec0948e810f ("arm64: dts: r8a7796: Add reset control properties")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
[simon: make placeholder minimal by only including reg property]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Mon, 20 Aug 2018 14:17:56 +0000 (23:17 +0900)]
arm64: dts: renesas: r8a77965: Attach the SYS-DMAC to the IPMMU
For R-Car M3-N hook up SYS-DMAC0, SYS-DMAC1 and SYS-DMAC2 to
IPMMU-DS0 and IPMMU-DS1 in same way as for R-Car M3-W.
This follows the R-Car Gen3 Rev.1.00 (April 2018) datasheet.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Mon, 13 Aug 2018 12:41:48 +0000 (13:41 +0100)]
arm64: dts: renesas: Initial r8a774a1 SoC device tree
Basic support for the RZ/G2M SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Kieran Bingham [Tue, 7 Aug 2018 15:59:33 +0000 (16:59 +0100)]
arm64: dts: renesas: salvator-common: adv748x: Override secondary addresses
Ensure that the ADV748x device addresses do not conflict, and group them
together (visually in i2cdetect)
Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Sergei Shtylyov [Mon, 6 Aug 2018 19:55:00 +0000 (22:55 +0300)]
arm64: dts: renesas: r8a77980: add CSI2/VIN support
Describe the CSI2 and VIN (and their interconnections) in the R8A77980
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Wolfram Sang [Mon, 30 Jul 2018 07:34:56 +0000 (09:34 +0200)]
arm64: dts: renesas: salvator-xs: enable SATA
Add the nodes to enable SATA. Note that MD12 (SW12-7) must be switched
off for that to work.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Takeshi Kihara [Mon, 30 Jul 2018 07:33:38 +0000 (09:33 +0200)]
arm64: dts: renesas: r8a77965: Add SATA controller node
This patch adds SATA controller node for the R8A77965 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[wsa: rebased to upstream base]
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>