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James Hogan [Tue, 18 Jul 2017 11:55:55 +0000 (12:55 +0100)]
target/mips: Add an MMU mode for ERL
The segmentation control feature allows a legacy memory segment to
become unmapped uncached at error level (according to CP0_Status.ERL),
and in fact the user segment is already treated in this way by QEMU.
Add a new MMU mode for this state so that QEMU's mappings don't persist
between ERL=0 and ERL=1.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
[yongbok.kim@imgtec.com:
cosmetic changes]
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
James Hogan [Tue, 18 Jul 2017 11:55:54 +0000 (12:55 +0100)]
target/mips: Abstract mmu_idx from hflags
The MIPS mmu_idx is sometimes calculated from hflags without an env
pointer available as cpu_mmu_index() requires.
Create a common hflags_mmu_index() for the purpose of this calculation
which can operate on any hflags, not just with an env pointer, and
update cpu_mmu_index() itself and gen_intermediate_code() to use it.
Also update debug_post_eret() and helper_mtc0_status() to log the MMU
mode with the status change (SM, UM, or nothing for kernel mode) based
on cpu_mmu_index() rather than directly testing hflags.
This will also allow the logic to be more easily updated when a new MMU
mode is added.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
James Hogan [Tue, 18 Jul 2017 11:55:53 +0000 (12:55 +0100)]
target/mips: Check memory permissions with mem_idx
When performing virtual to physical address translation, check the
required privilege level based on the mem_idx rather than the mode in
the hflags. This will allow EVA loads & stores to operate safely only on
user memory from kernel mode.
For the cases where the mmu_idx doesn't need to be overridden
(mips_cpu_get_phys_page_debug() and cpu_mips_translate_address()), we
calculate the required mmu_idx using cpu_mmu_index(). Note that this
only tests the MIPS_HFLAG_KSU bits rather than MIPS_HFLAG_MODE, so we
don't test the debug mode hflag MIPS_HFLAG_DM any longer. This should be
fine as get_physical_address() only compares against MIPS_HFLAG_UM and
MIPS_HFLAG_SM, neither of which should get set by compute_hflags() when
MIPS_HFLAG_DM is set.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
James Hogan [Tue, 18 Jul 2017 11:55:52 +0000 (12:55 +0100)]
target/mips: Decode microMIPS EVA load & store instructions
Implement decoding of microMIPS EVA load and store instruction groups in
the POOL31C pool. These use the same gen_ld(), gen_st(), gen_st_cond()
helpers as the MIPS32 decoding, passing the equivalent MIPS32 opcodes as
opc.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
James Hogan [Tue, 18 Jul 2017 11:55:51 +0000 (12:55 +0100)]
target/mips: Decode MIPS32 EVA load & store instructions
Implement decoding of MIPS32 EVA loads and stores. These access the user
address space from kernel mode when implemented, so for each instruction
we need to check that EVA is available from Config5.EVA & check for
sufficient COP0 privilege (with the new check_eva()), and then override
the mem_idx used for the operation.
Unfortunately some Loongson 2E instructions use overlapping encodings,
so we must be careful not to prevent those from being decoded when EVA
is absent.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
James Hogan [Tue, 18 Jul 2017 11:55:50 +0000 (12:55 +0100)]
target/mips: Prepare loads/stores for EVA
EVA load and store instructions access the user mode address map, so
they need to use mem_idx of MIPS_HFLAG_UM. Update the various utility
functions to allow mem_idx to be more easily overridden from the
decoding logic.
Specifically we add a mem_idx argument to the op_ld/st_* helpers used
for atomics, and a mem_idx local variable to gen_ld(), gen_st(), and
gen_st_cond().
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
James Hogan [Tue, 18 Jul 2017 11:55:49 +0000 (12:55 +0100)]
target/mips: Add CP0_Ebase.WG (write gate) support
Add support for the CP0_EBase.WG bit, which allows upper bits to be
written (bits 31:30 on MIPS32, or bits 63:30 on MIPS64), along with the
CP0_Config5.CV bit to control whether the exception vector for Cache
Error exceptions is forced into KSeg1.
This is necessary on MIPS32 to support Segmentation Control and Enhanced
Virtual Addressing (EVA) extensions (where KSeg1 addresses may not
represent an unmapped uncached segment).
It is also useful on MIPS64 to allow the exception base to reside in
XKPhys, and possibly out of range of KSEG0 and KSEG1.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
[yongbok.kim@imgtec.com:
minor changes]
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
James Hogan [Tue, 18 Jul 2017 11:55:48 +0000 (12:55 +0100)]
target/mips: Weaken TLB flush on UX,SX,KX,ASID changes
There is no need to invalidate any shadow TLB entries when the ASID
changes or when access to one of the 64-bit segments has been disabled,
since doing so doesn't reveal to software whether any TLB entries have
been evicted into the shadow half of the TLB.
Therefore weaken the tlb flushes in these cases to only flush the QEMU
TLB.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
James Hogan [Tue, 18 Jul 2017 11:55:47 +0000 (12:55 +0100)]
target/mips: Fix TLBWI shadow flush for EHINV,XI,RI
Writing specific TLB entries with TLBWI flushes shadow TLB entries
unless an existing entry is having its access permissions upgraded. This
is necessary as software would from then on expect the previous mapping
in that entry to no longer be in effect (even if QEMU has quietly
evicted it to the shadow TLB on a TLBWR).
However it won't do this if only EHINV, XI, or RI bits have been set,
even if that results in a reduction of permissions, so add the necessary
checks to invoke the flush when these bits are set.
Fixes:
2fb58b73746e ("target-mips: add RI and XI fields to TLB entry")
Fixes:
9456c2fbcd82 ("target-mips: add TLBINV support")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: Yongbok Kim <yongbok.kim@imgtec.com>
[yongbok.kim@imgtec.com:
cosmetic changes]
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
James Hogan [Tue, 18 Jul 2017 11:55:46 +0000 (12:55 +0100)]
target/mips: Fix MIPS64 MFC0 UserLocal on BE host
Using MFC0 to read CP0_UserLocal uses tcg_gen_ld32s_tl, however
CP0_UserLocal is a target_ulong. On a big endian host with a MIPS64
target this reads and sign extends the more significant half of the
64-bit register.
Fix this by using ld_tl to load the whole target_ulong and ext32s_tl to
sign extend it, as done for various other target_ulong COP0 registers.
Fixes:
d279279e2b5c ("target-mips: implement UserLocal Register")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Petar Jovanovic <petar.jovanovic@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Peter Maydell [Thu, 20 Jul 2017 15:40:01 +0000 (16:40 +0100)]
Merge remote-tracking branch 'remotes/kraxel/tags/ui-
20170720-pull-request' into staging
ui fixes (vnc docs, keymaps) for 2.10
# gpg: Signature made Thu 20 Jul 2017 08:54:25 BST
# gpg: using RSA key 0x4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>"
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>"
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* remotes/kraxel/tags/ui-
20170720-pull-request:
keymaps: fr-ca: more fixups
vnc: Clarify documentation of QMP command change
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Fri, 14 Jul 2017 10:45:17 +0000 (11:45 +0100)]
tests: Handle $RANDOM not being supported by the shell
In various places in our test makefiles and scripts we use the
shell $RANDOM to create a random number. This is a bash
specific extension, and doesn't work on other shells.
With dash the shell doesn't complain, it just effectively
always evaluates $RANDOM to 0:
echo $((RANDOM + 32768)) => 32768
However, on NetBSD the shell will complain:
"-sh: arith: syntax error: "RANDOM + 32768"
which means that "make check" fails.
Switch to using "${RANDOM:-0}" instead of $RANDOM,
which will portably either give us a random number or zero.
This means that on non-bash shells we don't get such
good test coverage via the MALLOC_PERTURB_ setting, but
we were already in that situation for non-bash shells.
Our only other uses of $RANDOM (in tests/qemu-iotests/check
and tests/qemu-iotests/162) are in shell scripts which use
a #!/bin/bash line so they are always run under bash.
Suggested-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Kamil Rytarowski <n54@gmx.com>
Reviewed-by: Fam Zheng <famz@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-id:
1500029117-6387-1-git-send-email-peter.maydell@linaro.org
Kamil Rytarowski [Fri, 14 Jul 2017 08:33:45 +0000 (09:33 +0100)]
configure: Don't build ivshmem tools unless CONFIG_IVSHMEM is set
Don't try to build the ivshmem-server and ivshmem-client tools unless
CONFIG_IVSHMEM is set.
This fixes in passing a build bug on NetBSD, which fails to build the
ivshmem tools because they use shm_open() and on NetBSD that requires
linking against -lrt.
Signed-off-by: Kamil Rytarowski <n54@gmx.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1500021225-4118-4-git-send-email-peter.maydell@linaro.org
[PMM: moved some code into earlier patches; minor bugfixes;
added commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Kamil Rytarowski [Fri, 14 Jul 2017 08:33:44 +0000 (09:33 +0100)]
configure: Use an explicit CONFIG_IVSHMEM rather than CONFIG_EVENTFD
Rather than relying on everywhere that cares about whether the host
supports ivshmem using CONFIG_EVENTFD, make configure set an explicit
CONFIG_IVSHMEM.
Signed-off-by: Kamil Rytarowski <n54@gmx.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1500021225-4118-3-git-send-email-peter.maydell@linaro.org
[PMM: split out from another patch, add commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Fri, 14 Jul 2017 08:33:43 +0000 (09:33 +0100)]
configure: Rename CONFIG_IVSHMEM to CONFIG_IVSHMEM_DEVICE
The current CONFIG_IVSHMEM is confusing, because it looks like it's a
flag for "do we have ivshmem support?", but actually it's a flag for
"is the ivshmem PCI device being compiled?" (and implicitly "do we
have ivshmem support?" is tested with CONFIG_EVENTFD).
Rename it to CONFIG_IVSHMEM_DEVICE to clear this confusion up;
shortly we will add a new CONFIG_IVSHMEM which really does indicate
whether the host can support ivshmem.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Message-id:
1500021225-4118-2-git-send-email-peter.maydell@linaro.org
Peter Maydell [Thu, 20 Jul 2017 11:04:05 +0000 (12:04 +0100)]
Merge remote-tracking branch 'remotes/kraxel/tags/misc-
20170720-pull-request' into staging
git orderfile and editorconfig for 2.10
# gpg: Signature made Thu 20 Jul 2017 09:00:01 BST
# gpg: using RSA key 0x4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>"
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>"
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* remotes/kraxel/tags/misc-
20170720-pull-request:
add editorconfig
add scripts/git.orderfile
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Thu, 20 Jul 2017 10:00:10 +0000 (11:00 +0100)]
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-
20170719' into staging
Queued tcg and tcg code gen related cleanups
# gpg: Signature made Thu 20 Jul 2017 00:32:00 BST
# gpg: using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg: aka "Richard Henderson <rth@redhat.com>"
# gpg: aka "Richard Henderson <rth@twiddle.net>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B
* remotes/rth/tags/pull-tcg-
20170719:
tcg: Pass generic CPUState to gen_intermediate_code()
tcg/tci: enable bswap16_i64
target/alpha: optimize gen_cvtlq() using deposit op
target/sparc: optimize gen_op_mulscc() using deposit op
target/sparc: optimize various functions using extract op
target/ppc: optimize various functions using extract op
target/m68k: optimize bcd_flags() using extract op
target/arm: optimize aarch32 rev16
target/arm: Optimize aarch64 rev16
coccinelle: add a script to optimize tcg op using tcg_gen_extract()
coccinelle: ignore ASTs pre-parsed cached C files
tcg: Expand glue macros before stringifying helper names
util/cacheinfo: Add missing include for ppc linux
tcg/mips: reserve a register for the guest_base.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Khem Raj [Wed, 28 Jun 2017 20:44:52 +0000 (13:44 -0700)]
Replace 'struct ucontext' with 'ucontext_t' type
glibc used to have:
typedef struct ucontext { ... } ucontext_t;
glibc now has:
typedef struct ucontext_t { ... } ucontext_t;
(See https://sourceware.org/bugzilla/show_bug.cgi?id=21457
for detail and rationale for the glibc change)
However, QEMU used "struct ucontext" in declarations. This is a
private name and compatibility cannot be guaranteed. Switch to
only using the standardized type name.
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Message-id:
20170628204452.41230-1-raj.khem@gmail.com
Cc: Kamil Rytarowski <kamil@netbsd.org>
Cc: Riku Voipio <riku.voipio@iki.fi>
Cc: Laurent Vivier <laurent@vivier.eu>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
[PMM: Rewrote commit message, based mostly on the one from
Nathaniel McCallum]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Gerd Hoffmann [Mon, 17 Jul 2017 10:15:47 +0000 (12:15 +0200)]
add editorconfig
Add a .editorconfig file for qemu. Specifies the indent and tab style
for various files (C code and Makefiles for starters). Most popular
editors support this either natively or via plugin.
Check http://editorconfig.org/ for details.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id:
20170717101547.22295-1-kraxel@redhat.com
Gerd Hoffmann [Mon, 17 Jul 2017 10:16:32 +0000 (12:16 +0200)]
add scripts/git.orderfile
Based on a old patch by Laszlo.
Time to get this in ...
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Message-id:
20170717101632.23247-1-kraxel@redhat.com
Gerd Hoffmann [Mon, 17 Jul 2017 13:34:44 +0000 (15:34 +0200)]
keymaps: fr-ca: more fixups
Fixes: https://bugs.launchpad.net/qemu/+bug/533613
Cc: Thomas Huth <thuth@redhat.com>
Suggested-by: Jérôme Poulin <jeromepoulin@gmail.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id:
20170717133444.16743-1-kraxel@redhat.com
Markus Armbruster [Wed, 19 Jul 2017 07:09:42 +0000 (09:09 +0200)]
vnc: Clarify documentation of QMP command change
QMP command
{ "execute": "change",
"arguments": { "device": "vnc", "target": "password", "arg": PWD } }
behaves just like
{ "execute": "change-vnc-password",
"arguments": { "password", "arg": PWD } }
Their documentation differs, however. According to
change-vnc-password's documentation, "an empty password [...] will set
the password to the empty string", while change's documentation claims
"no future logins will be allowed". The former is actually correct.
Replace the incorrect claim by a reference to change-vnc-password.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-id:
1500448182-21376-1-git-send-email-armbru@redhat.com
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Lluís Vilanova [Fri, 14 Jul 2017 08:17:35 +0000 (11:17 +0300)]
tcg: Pass generic CPUState to gen_intermediate_code()
Needed to implement a target-agnostic gen_intermediate_code()
in the future.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Alex Benneé <alex.benee@linaro.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Message-Id: <
150002025498.22386.
18051908483085660588.stgit@frigg.lan>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Philippe Mathieu-Daudé [Tue, 18 Jul 2017 04:55:40 +0000 (01:55 -0300)]
tcg/tci: enable bswap16_i64
Altough correctly implemented, bswap16_i64() never got tested/executed so the
safety TODO() statement was never removed.
Since it got now tested the TODO() can be removed.
while running Alex Bennée's image aarch64-linux-3.15rc2-buildroot.img:
Trace 0x7fa1904b0890 [0:
ffffffc00036cd04]
----------------
IN:
0xffffffc00036cd24:
5ac00694 rev16 w20, w20
OP:
----
ffffffc00036cd24 0000000000000000 0000000000000000
ext32u_i64 tmp3,x20
ext16u_i64 tmp2,tmp3
bswap16_i64 x20,tmp2
movi_i64 tmp4,$0x10
shr_i64 tmp2,tmp3,tmp4
ext16u_i64 tmp2,tmp2
bswap16_i64 tmp2,tmp2
deposit_i64 x20,x20,tmp2,$0x10,$0x10
Linking TBs 0x7fa1904b0890 [
ffffffc00036cd04] index 0 -> 0x7fa1904b0aa0 [
ffffffc00036cd24]
Trace 0x7fa1904b0aa0 [0:
ffffffc00036cd24]
TODO qemu/tci.c:1049: tcg_qemu_tb_exec()
qemu/tci.c:1049: tcg fatal error
Aborted
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Jaroslaw Pelczar <j.pelczar@samsung.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Message-Id: <
20170718045540.16322-11-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Philippe Mathieu-Daudé [Tue, 18 Jul 2017 04:55:39 +0000 (01:55 -0300)]
target/alpha: optimize gen_cvtlq() using deposit op
Suggested-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20170718045540.16322-10-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Philippe Mathieu-Daudé [Tue, 18 Jul 2017 04:55:38 +0000 (01:55 -0300)]
target/sparc: optimize gen_op_mulscc() using deposit op
Suggested-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20170718045540.16322-9-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Philippe Mathieu-Daudé [Tue, 18 Jul 2017 04:55:36 +0000 (01:55 -0300)]
target/sparc: optimize various functions using extract op
Done with the Coccinelle semantic patch
scripts/coccinelle/tcg_gen_extract.cocci.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Philippe Mathieu-Daudé [Tue, 18 Jul 2017 04:55:35 +0000 (01:55 -0300)]
target/ppc: optimize various functions using extract op
Done with the Coccinelle semantic patch
scripts/coccinelle/tcg_gen_extract.cocci.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20170718045540.16322-6-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Philippe Mathieu-Daudé [Tue, 18 Jul 2017 04:55:34 +0000 (01:55 -0300)]
target/m68k: optimize bcd_flags() using extract op
Done with the Coccinelle semantic patch
scripts/coccinelle/tcg_gen_extract.cocci.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718045540.16322-5-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Aurelien Jarno [Tue, 16 May 2017 23:01:56 +0000 (01:01 +0200)]
target/arm: optimize aarch32 rev16
Use the same mask to avoid having to load two different constants, as
suggested by Richard Henderson.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170516230159.4195-2-aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Tue, 18 Jul 2017 06:16:57 +0000 (20:16 -1000)]
target/arm: Optimize aarch64 rev16
It is much shorter to reverse all 4 half-words in parallel
than extract, reverse, and deposit each in turn.
Suggested-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Philippe Mathieu-Daudé [Tue, 18 Jul 2017 04:55:32 +0000 (01:55 -0300)]
coccinelle: add a script to optimize tcg op using tcg_gen_extract()
The following thread was helpful while writing this script:
https://github.com/coccinelle/coccinelle/issues/86
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20170718045540.16322-3-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Philippe Mathieu-Daudé [Tue, 18 Jul 2017 04:55:31 +0000 (01:55 -0300)]
coccinelle: ignore ASTs pre-parsed cached C files
files generated using coccinelle tool: 'spatch --use-cache'
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20170718045540.16322-2-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Sat, 15 Jul 2017 03:13:59 +0000 (17:13 -1000)]
tcg: Expand glue macros before stringifying helper names
Signed-off-by: Richard Henderson <rth@twiddle.net>
Philippe Mathieu-Daudé [Tue, 11 Jul 2017 01:55:24 +0000 (22:55 -0300)]
util/cacheinfo: Add missing include for ppc linux
This include was forgotten when splitting cacheinfo.c out of
tcg/ppc/tcg-target.inc.c (see commit
b255b2c8).
For a Centos7 host, the include path
<signal.h>
<bits/sigcontext.h>
<asm/sigcontext.h>
<asm/elf.h>
<asm/auxvec.h>
implicitly pulls in the desired AT_* defines.
Not so for Debian Jessie.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20170711015524.22936-1-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Jiang Biao [Mon, 10 Jul 2017 09:12:14 +0000 (17:12 +0800)]
tcg/mips: reserve a register for the guest_base.
Reserve a register for the guest_base using ppc code for reference.
By doing so, we do not have to recompute it for every memory load.
Signed-off-by: Jiang Biao <jiang.biao2@zte.com.cn>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
1499677934-2249-1-git-send-email-jiang.biao2@zte.com.cn>
Peter Maydell [Wed, 19 Jul 2017 19:45:37 +0000 (20:45 +0100)]
Merge remote-tracking branch 'remotes/berrange/tags/pull-qcrypto-2017-07-18-2' into staging
Merge qcrypto 2017/07/18 v2
# gpg: Signature made Wed 19 Jul 2017 10:11:21 BST
# gpg: using RSA key 0xBE86EBB415104FDF
# gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>"
# gpg: aka "Daniel P. Berrange <berrange@redhat.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF
* remotes/berrange/tags/pull-qcrypto-2017-07-18-2:
tests: crypto: add hmac speed benchmark support
tests: crypto: add hash speed benchmark support
tests: crypto: add cipher speed benchmark support
crypto: hmac: add af_alg-backend hmac support
crypto: hash: add afalg-backend hash support
crypto: cipher: add afalg-backend cipher support
crypto: introduce some common functions for af_alg backend
crypto: hmac: add hmac driver framework
crypto: hmac: introduce qcrypto_hmac_ctx_new for glib-backend
crypto: hmac: introduce qcrypto_hmac_ctx_new for nettle-backend
crypto: hmac: introduce qcrypto_hmac_ctx_new for gcrypt-backend
crypto: hmac: move crypto/hmac.h into include/crypto/
crypto: hash: add hash driver framework
crypto: cipher: add cipher driver framework
crypto: cipher: introduce qcrypto_cipher_ctx_new for builtin-backend
crypto: cipher: introduce qcrypto_cipher_ctx_new for nettle-backend
crypto: cipher: introduce qcrypto_cipher_ctx_new for gcrypt-backend
crypto: cipher: introduce context free function
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Wed, 19 Jul 2017 16:51:36 +0000 (17:51 +0100)]
Merge remote-tracking branch 'remotes/rth/tags/pull-axp-
20170718' into staging
Queued target/alpha patches
# gpg: Signature made Wed 19 Jul 2017 05:42:55 BST
# gpg: using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg: aka "Richard Henderson <rth@redhat.com>"
# gpg: aka "Richard Henderson <rth@twiddle.net>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B
* remotes/rth/tags/pull-axp-
20170718:
target/alpha: Log temp leaks
target/alpha: Fix temp leak in gen_fbcond
target/alpha: Fix temp leak in gen_call_pal
target/alpha: Fix temp leak in gen_mtpr
target/alpha: Fix temp leak in gen_bcond
target/alpha: Merge several flag bytes into ENV->FLAGS
target/alpha: Copy tb->flags into DisasContext
target/alpha: Remove amask from tb->flags
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Wed, 19 Jul 2017 15:31:08 +0000 (16:31 +0100)]
Merge remote-tracking branch 'remotes/sstabellini/tags/xen-
20170718-tag' into staging
Xen 2017/07/18
# gpg: Signature made Tue 18 Jul 2017 23:18:16 BST
# gpg: using RSA key 0x894F8F4870E1AE90
# gpg: Good signature from "Stefano Stabellini <stefano.stabellini@eu.citrix.com>"
# gpg: aka "Stefano Stabellini <sstabellini@kernel.org>"
# Primary key fingerprint: D04E 33AB A51F 67BA 07D3 0AEA 894F 8F48 70E1 AE90
* remotes/sstabellini/tags/xen-
20170718-tag:
xen: don't use xenstore to save/restore physmap anymore
xen/mapcache: introduce xen_replace_cache_entry()
xen/mapcache: add an ability to create dummy mappings
xen: move physmap saving into a separate function
xen-platform: separate unplugging of NVMe disks
xen_pt_msi.c: Check for xen_host_pci_get_* failures in xen_pt_msix_init()
hw/xen: Set emu_mask for igd_opregion register
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Wed, 19 Jul 2017 13:42:18 +0000 (14:42 +0100)]
Merge remote-tracking branch 'remotes/aurel/tags/pull-target-sh4-
20170718' into staging
Queued target/sh4 patches
# gpg: Signature made Tue 18 Jul 2017 22:44:25 BST
# gpg: using RSA key 0xBA9C78061DDD8C9B
# gpg: Good signature from "Aurelien Jarno <aurelien@aurel32.net>"
# gpg: aka "Aurelien Jarno <aurelien@jarno.fr>"
# gpg: aka "Aurelien Jarno <aurel32@debian.org>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7746 2642 A9EF 94FD 0F77 196D BA9C 7806 1DDD 8C9B
* remotes/aurel/tags/pull-target-sh4-
20170718: (31 commits)
target/sh4: Use tcg_gen_lookup_and_goto_ptr
target/sh4: Implement fsrra
target/sh4: Add missing FPSCR.PR == 0 checks
target/sh4: Implement fpchg
target/sh4: Introduce CHECK_SH4A
target/sh4: Introduce CHECK_FPSCR_PR_*
target/sh4: Tidy misc illegal insn checks
target/sh4: Unify code for CHECK_FPU_ENABLED
target/sh4: Unify code for CHECK_PRIVILEGED
target/sh4: Unify code for CHECK_NOT_DELAY_SLOT
target/sh4: Simplify 64-bit fp reg-reg move
target/sh4: Load/store Dr as 64-bit quantities
target/sh4: Merge DREG into fpr64 routines
target/sh4: Eliminate unused XREG macro
target/sh4: Hoist fp register bank selection
target/sh4: Pass DisasContext to fpr64 routines
target/sh4: Unify cpu_fregs into FREG
target/sh4: Hoist register bank selection
linux-user/sh4: Clean env->flags on signal boundaries
linux-user/sh4: Notice gUSA regions during signal delivery
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Wed, 19 Jul 2017 12:43:58 +0000 (13:43 +0100)]
Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging
# gpg: Signature made Tue 18 Jul 2017 17:11:07 BST
# gpg: using RSA key 0x7DEF8106AAFC390E
# gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>"
# Primary key fingerprint: FAEB 9711 A12C F475 812F 18F2 88A9 064D 1835 61EB
# Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76 CBD0 7DEF 8106 AAFC 390E
* remotes/jnsnow/tags/ide-pull-request:
tests/ahci-test: Be mean with RAM
ahci: split public and private interface
ahci: Isolate public AHCI interface
ahci: add ahci_get_num_ports
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Wed, 19 Jul 2017 11:30:41 +0000 (12:30 +0100)]
Merge remote-tracking branch 'remotes/juanquintela/tags/migration/
20170718' into staging
migration/next for
20170718
# gpg: Signature made Tue 18 Jul 2017 16:39:33 BST
# gpg: using RSA key 0xF487EF185872D723
# gpg: Good signature from "Juan Quintela <quintela@redhat.com>"
# gpg: aka "Juan Quintela <quintela@trasno.org>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723
* remotes/juanquintela/tags/migration/
20170718:
migration: check global caps for validity
migration: provide migrate_cap_add()
migration: provide migrate_caps_check()
migration: remove check against colo support
migration: check global params for validity
migration: provide migrate_params_apply()
migration: introduce migrate_params_check()
migration: export capabilities to props
migration: export parameters to props
qdev: provide DEFINE_PROP_INT64()
migration/rdma: Send error during cancelling
migration/rdma: Safely convert control types
migration/rdma: Allow cancelling while waiting for wrid
migration/rdma: fix qemu_rdma_block_for_wrid error paths
migration: Close file on failed migration load
migration/rdma: Fix race on source
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Wed, 19 Jul 2017 09:48:31 +0000 (10:48 +0100)]
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
Block layer patches
# gpg: Signature made Tue 18 Jul 2017 14:29:59 BST
# gpg: using RSA key 0x7F09B272C88F2FD6
# gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>"
# Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6
* remotes/kevin/tags/for-upstream: (21 commits)
qemu-img: Check for backing image if specified during create
blockdev: move BDRV_O_NO_BACKING option forward
block/vvfat: Fix compiler warning with gcc 7
vvfat: initialize memory after allocating it
vvfat: correctly parse non-ASCII short and long file names
vvfat: add a constant for bootsector name
vvfat: add constants for special values of name[0]
qemu-iotests: Test unplug of -device without drive
qemu-iotests: Test 'info block'
scsi-disk: bdrv_attach_dev() for empty CD-ROM
ide: bdrv_attach_dev() for empty CD-ROM
block: List anonymous device BBs in query-block
block/qapi: Use blk_all_next() for query-block
block: Make blk_all_next() public
block/qapi: Add qdev device name to query-block
block: Make blk_get_attached_dev_id() public
block/vpc.c: Handle write failures in get_image_offset()
block/vmdk: Report failures in vmdk_read_cid()
block: remove timer canceling in throttle_config()
block: add clock_type field to ThrottleGroup
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Longpeng(Mike) [Fri, 14 Jul 2017 18:04:11 +0000 (14:04 -0400)]
tests: crypto: add hmac speed benchmark support
This patch add a hmac speed benchmark, it helps us to
measure the performance by using "make check-speed" or
using "./tests/benchmark-crypto-hmac" directly.
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Longpeng(Mike) [Fri, 14 Jul 2017 18:04:10 +0000 (14:04 -0400)]
tests: crypto: add hash speed benchmark support
This patch add a hash speed benchmark, it helps us to
measure the performance by using "make check-speed" or
using "./tests/benchmark-crypto-hash" directly.
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Longpeng(Mike) [Fri, 14 Jul 2017 18:04:09 +0000 (14:04 -0400)]
tests: crypto: add cipher speed benchmark support
Now we have two qcrypto backends, libiary-backend and afalg-backend,
but which one is faster? This patch add a cipher speed benchmark, it
helps us to measure the performance by using "make check-speed" or
using "./tests/benchmark-crypto-cipher" directly.
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Longpeng(Mike) [Fri, 14 Jul 2017 18:04:08 +0000 (14:04 -0400)]
crypto: hmac: add af_alg-backend hmac support
Adds afalg-backend hmac support: introduces some private APIs
firstly, and then intergrates them into qcrypto_hmac_afalg_driver.
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Longpeng(Mike) [Fri, 14 Jul 2017 18:04:07 +0000 (14:04 -0400)]
crypto: hash: add afalg-backend hash support
Adds afalg-backend hash support: introduces some private APIs
firstly, and then intergrates them into qcrypto_hash_afalg_driver.
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Longpeng(Mike) [Fri, 14 Jul 2017 18:04:06 +0000 (14:04 -0400)]
crypto: cipher: add afalg-backend cipher support
Adds afalg-backend cipher support: introduces some private APIs
firstly, and then intergrates them into qcrypto_cipher_afalg_driver.
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Longpeng(Mike) [Fri, 14 Jul 2017 18:04:05 +0000 (14:04 -0400)]
crypto: introduce some common functions for af_alg backend
The AF_ALG socket family is the userspace interface for linux
crypto API, this patch adds af_alg family support and some common
functions for af_alg backend. It'll be used by afalg-backend crypto
latter.
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Maintainer: modified to report an error if AF_ALG is requested
but cannot be supported
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Longpeng(Mike) [Fri, 14 Jul 2017 18:04:04 +0000 (14:04 -0400)]
crypto: hmac: add hmac driver framework
1) makes the public APIs in hmac-nettle/gcrypt/glib static,
and rename them with "nettle/gcrypt/glib" prefix.
2) introduces hmac framework, including QCryptoHmacDriver
and new public APIs.
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Longpeng(Mike) [Fri, 14 Jul 2017 18:04:03 +0000 (14:04 -0400)]
crypto: hmac: introduce qcrypto_hmac_ctx_new for glib-backend
Extracts qcrypto_hmac_ctx_new() from qcrypto_hmac_new() for
glib-backend impls.
Reviewed-by: Gonglei <arei.gonglei@huawei.com>
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Longpeng(Mike) [Fri, 14 Jul 2017 18:04:02 +0000 (14:04 -0400)]
crypto: hmac: introduce qcrypto_hmac_ctx_new for nettle-backend
Extracts qcrypto_hmac_ctx_new() from qcrypto_hmac_new() for
nettle-backend impls.
Reviewed-by: Gonglei <arei.gonglei@huawei.com>
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Longpeng(Mike) [Fri, 14 Jul 2017 18:04:01 +0000 (14:04 -0400)]
crypto: hmac: introduce qcrypto_hmac_ctx_new for gcrypt-backend
1) Fix a handle-leak problem in qcrypto_hmac_new(), didn't free
ctx->handle if gcry_mac_setkey fails.
2) Extracts qcrypto_hmac_ctx_new() from qcrypto_hmac_new() for
gcrypt-backend impls.
Reviewed-by: Gonglei <arei.gonglei@huawei.com>
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Longpeng(Mike) [Fri, 14 Jul 2017 18:04:00 +0000 (14:04 -0400)]
crypto: hmac: move crypto/hmac.h into include/crypto/
Moves crypto/hmac.h into include/crypto/, likes cipher.h and hash.h
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Gonglei <arei.gonglei@huawei.com>
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Longpeng(Mike) [Fri, 14 Jul 2017 18:03:59 +0000 (14:03 -0400)]
crypto: hash: add hash driver framework
1) makes the public APIs in hash-nettle/gcrypt/glib static,
and rename them with "nettle/gcrypt/glib" prefix.
2) introduces hash framework, including QCryptoHashDriver
and new public APIs.
Reviewed-by: Gonglei <arei.gonglei@huawei.com>
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Longpeng(Mike) [Fri, 14 Jul 2017 18:03:58 +0000 (14:03 -0400)]
crypto: cipher: add cipher driver framework
1) makes the public APIs in cipher-nettle/gcrypt/builtin static,
and rename them with "nettle/gcrypt/builtin" prefix.
2) introduces cipher framework, including QCryptoCipherDriver
and new public APIs.
Reviewed-by: Gonglei <arei.gonglei@huawei.com>
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Longpeng(Mike) [Fri, 14 Jul 2017 18:03:57 +0000 (14:03 -0400)]
crypto: cipher: introduce qcrypto_cipher_ctx_new for builtin-backend
Extracts qcrypto_cipher_ctx_new() from qcrypto_cipher_new() for
builtin-backend impls.
Reviewed-by: Gonglei <arei.gonglei@huawei.com>
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Longpeng(Mike) [Fri, 14 Jul 2017 18:03:56 +0000 (14:03 -0400)]
crypto: cipher: introduce qcrypto_cipher_ctx_new for nettle-backend
Extracts qcrypto_cipher_ctx_new() from qcrypto_cipher_new() for
nettle-backend impls.
Reviewed-by: Gonglei <arei.gonglei@huawei.com>
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Longpeng(Mike) [Fri, 14 Jul 2017 18:03:55 +0000 (14:03 -0400)]
crypto: cipher: introduce qcrypto_cipher_ctx_new for gcrypt-backend
Extracts qcrypto_cipher_ctx_new() from qcrypto_cipher_new() for
gcrypt-backend impls.
Reviewed-by: Gonglei <arei.gonglei@huawei.com>
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Longpeng(Mike) [Fri, 14 Jul 2017 18:03:54 +0000 (14:03 -0400)]
crypto: cipher: introduce context free function
Refactors the qcrypto_cipher_free(), splits it into two parts. One
is gcrypt/nettle__cipher_free_ctx() to free the special context.
This makes code more clear, what's more, it would be used by the
later patch.
Reviewed-by: Gonglei <arei.gonglei@huawei.com>
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Peter Maydell [Wed, 19 Jul 2017 08:11:38 +0000 (09:11 +0100)]
Merge remote-tracking branch 'remotes/berrange/tags/pull-qio-2017-07-18-1' into staging
Merge I/O 2017/07/18 v1
# gpg: Signature made Tue 18 Jul 2017 11:31:53 BST
# gpg: using RSA key 0xBE86EBB415104FDF
# gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>"
# gpg: aka "Daniel P. Berrange <berrange@redhat.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF
* remotes/berrange/tags/pull-qio-2017-07-18-1:
io: simplify qio_channel_attach_aio_context
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Thu, 13 Jul 2017 23:55:05 +0000 (13:55 -1000)]
target/alpha: Log temp leaks
Tested-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Fri, 14 Jul 2017 00:04:00 +0000 (14:04 -1000)]
target/alpha: Fix temp leak in gen_fbcond
Tested-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Thu, 13 Jul 2017 23:32:32 +0000 (13:32 -1000)]
target/alpha: Fix temp leak in gen_call_pal
Tested-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Thu, 13 Jul 2017 23:32:09 +0000 (13:32 -1000)]
target/alpha: Fix temp leak in gen_mtpr
Tested-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Thu, 13 Jul 2017 23:22:08 +0000 (13:22 -1000)]
target/alpha: Fix temp leak in gen_bcond
Tested-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Thu, 6 Jul 2017 19:45:07 +0000 (09:45 -1000)]
target/alpha: Merge several flag bytes into ENV->FLAGS
The flags are arranged such that we can manipulate them either
a whole, or as individual bytes. The computation within
cpu_get_tb_cpu_state is now reduced to a single load and mask.
Tested-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Thu, 6 Jul 2017 19:44:56 +0000 (09:44 -1000)]
target/alpha: Copy tb->flags into DisasContext
Tested-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Thu, 6 Jul 2017 19:37:41 +0000 (09:37 -1000)]
target/alpha: Remove amask from tb->flags
This value is constant for the cpu and does not need
to be stored within the TB.
Tested-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:52 +0000 (10:02 -1000)]
target/sh4: Use tcg_gen_lookup_and_goto_ptr
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-28-rth@twiddle.net>
[aurel32: fix whitespace]
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:51 +0000 (10:02 -1000)]
target/sh4: Implement fsrra
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-27-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:50 +0000 (10:02 -1000)]
target/sh4: Add missing FPSCR.PR == 0 checks
Both frchg and fschg require PR == 0, otherwise undefined_operation.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-26-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:49 +0000 (10:02 -1000)]
target/sh4: Implement fpchg
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-25-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:48 +0000 (10:02 -1000)]
target/sh4: Introduce CHECK_SH4A
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-24-rth@twiddle.net>
[aurel32: fix conflict]
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:47 +0000 (10:02 -1000)]
target/sh4: Introduce CHECK_FPSCR_PR_*
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-23-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:46 +0000 (10:02 -1000)]
target/sh4: Tidy misc illegal insn checks
Now that we have a do_illegal label, use goto in order
to self-document the forcing of the exception.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-22-rth@twiddle.net>
[aurel32: fix whitespace issues]
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:45 +0000 (10:02 -1000)]
target/sh4: Unify code for CHECK_FPU_ENABLED
We do not need to emit N copies of raising an exception.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-21-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:44 +0000 (10:02 -1000)]
target/sh4: Unify code for CHECK_PRIVILEGED
We do not need to emit N copies of raising an exception.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-20-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:43 +0000 (10:02 -1000)]
target/sh4: Unify code for CHECK_NOT_DELAY_SLOT
We do not need to emit N copies of raising an exception.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-19-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:42 +0000 (10:02 -1000)]
target/sh4: Simplify 64-bit fp reg-reg move
We do not need to form full 64-bit quantities in order to perform
the move. This reduces code expansion on 64-bit hosts.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-18-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:41 +0000 (10:02 -1000)]
target/sh4: Load/store Dr as 64-bit quantities
This enforces proper alignment and makes the register update
more natural. Note that there is a more serious bug fix for
fmov {DX}Rn,@(R0,Rn) to use a store instead of a load.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-17-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:40 +0000 (10:02 -1000)]
target/sh4: Merge DREG into fpr64 routines
Also add a debugging assert that we did signal illegal opc
for odd double-precision registers.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-16-rth@twiddle.net>
[aurel32: fix whitespace issues]
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:39 +0000 (10:02 -1000)]
target/sh4: Eliminate unused XREG macro
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-15-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:38 +0000 (10:02 -1000)]
target/sh4: Hoist fp register bank selection
Compute which register bank to use once at the start of translation.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-14-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:37 +0000 (10:02 -1000)]
target/sh4: Pass DisasContext to fpr64 routines
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-13-rth@twiddle.net>
[aurel32: fix whitespace issues]
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:36 +0000 (10:02 -1000)]
target/sh4: Unify cpu_fregs into FREG
We were treating FREG as an index and REG as a TCGv.
Making FREG return a TCGv is both less confusing and
a step toward cleaner banking of cpu_fregs.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-12-rth@twiddle.net>
[aurel32: fix whitespace issues]
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:35 +0000 (10:02 -1000)]
target/sh4: Hoist register bank selection
Compute which register bank to use once at the start of translation.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-11-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:34 +0000 (10:02 -1000)]
linux-user/sh4: Clean env->flags on signal boundaries
If a signal is delivered during the execution of a delay slot,
or a gUSA region, clear those bits from the environment so that
the signal handler does not start in that same state.
Cleaning the bits on signal return is paranoid good sense.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-10-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:33 +0000 (10:02 -1000)]
linux-user/sh4: Notice gUSA regions during signal delivery
We translate gUSA regions atomically in a parallel context.
But in a serial context a gUSA region may be interrupted.
In that case, restart the region as the kernel would.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-9-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:32 +0000 (10:02 -1000)]
target/sh4: Recognize common gUSA sequences
For many of the sequences produced by gcc or glibc,
we can translate these as host atomic operations.
Which saves the need to acquire the exclusive lock.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-8-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:31 +0000 (10:02 -1000)]
target/sh4: Handle user-space atomics
For uniprocessors, SH4 uses optimistic restartable atomic sequences.
Upon an interrupt, a real kernel would simply notice magic values in
the registers and reset the PC to the start of the sequence.
For QEMU, we cannot do this in quite the same way. Instead, we notice
the normal start of such a sequence (mov #-x,r15), and start a new TB
that can be executed under cpu_exec_step_atomic.
Reported-by: Bruno Haible <bruno@clisp.org>
LP: https://bugs.launchpad.net/bugs/
1701971
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-7-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:30 +0000 (10:02 -1000)]
target/sh4: Adjust TB_FLAG_PENDING_MOVCA
Don't leave an unused bit after DELAY_SLOT_MASK.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-6-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:29 +0000 (10:02 -1000)]
target/sh4: Keep env->flags clean
If we mask off any out-of-band bits before we assign to the
variable, then we don't need to clean it up when reading.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-5-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:28 +0000 (10:02 -1000)]
target/sh4: Introduce TB_FLAG_ENVFLAGS_MASK
We'll be putting more things into this bitmask soon.
Let's have a name that covers all possible uses.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-4-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 18 Jul 2017 20:02:27 +0000 (10:02 -1000)]
target/sh4: Consolidate end-of-TB tests
We can fold 3 different tests within the decode loop
into a more accurate computation of max_insns to start.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170718200255.31647-3-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Sun, 2 Jul 2017 19:31:25 +0000 (21:31 +0200)]
target/sh4: return result of fcmp using TCG
Since that the T bit of the SR register is mapped using a TGC global,
it's better to return the value through TCG than writing it directly. It
allows to declare the helpers with the flag TCG_CALL_NO_WG.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <
20170702202814.27793-5-aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Sun, 2 Jul 2017 16:26:43 +0000 (18:26 +0200)]
target/sh4: do not use a helper to implement fneg
There is no need to use a helper to flip one bit, just use a TCG xor
instruction instead.
Message-Id: <
20170702202814.27793-5-aurelien@aurel32.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Sun, 2 Jul 2017 18:34:55 +0000 (20:34 +0200)]
target/sh4: fix FPSCR cause vs flag inversion
The floating-point status/control register contains cause and flag
bits. The cause bits are set to 0 before executing the instruction,
while the flag bits hold the status of the exception generated after
the field was last cleared.
Message-Id: <
20170702202814.27793-4-aurelien@aurel32.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Sun, 2 Jul 2017 19:23:56 +0000 (21:23 +0200)]
target/sh4: fix FPU unorderered compare
In case of unordered compare, the fcmp instructions should either
trigger and invalid exception (if enabled) or set T=0. The existing code
left it unchanged.
LP: https://bugs.launchpad.net/qemu/+bug/
1701821
Reported-by: Bruno Haible <bruno@clisp.org>
Message-Id: <
20170702202814.27793-3-aurelien@aurel32.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>