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David Woodhouse [Thu, 8 Feb 2018 20:06:05 +0000 (20:06 +0000)]
[X86] Support 'V' register operand modifier
This allows the register name to be printed without the leading '%'.
This can be used for emitting calls to the retpoline thunks from inline
asm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324645
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David Blaikie [Thu, 8 Feb 2018 19:57:05 +0000 (19:57 +0000)]
Fix missing field initializer warning in TableGen SubtargetEmitter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324643
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Daniel Neilson [Thu, 8 Feb 2018 19:46:12 +0000 (19:46 +0000)]
[MSan] Update uses of IRBuilder::CreateMemCpy to new API (NFC)
Summary:
This change is part of step five in the series of changes to remove alignment argument from
memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the
MemorySanitizer pass to cease using the old IRBuilder CreateMemCpy single-alignment APIs
in favour of the new API that allows setting source and destination alignments independently.
Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402, rL324626 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.
Reference
http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20151109/312083.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324642
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Simon Pilgrim [Thu, 8 Feb 2018 19:28:05 +0000 (19:28 +0000)]
Regenerate test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324639
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Simon Pilgrim [Thu, 8 Feb 2018 19:23:47 +0000 (19:23 +0000)]
[X86] Add common CHECK prefix to shift combine tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324638
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Simon Pilgrim [Thu, 8 Feb 2018 19:20:34 +0000 (19:20 +0000)]
[X86] Add shift undef, %X tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324637
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Simon Pilgrim [Thu, 8 Feb 2018 19:00:45 +0000 (19:00 +0000)]
[InstCombine] visitSRem - use m_Negative(APInt) helper. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324636
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Simon Pilgrim [Thu, 8 Feb 2018 18:58:00 +0000 (18:58 +0000)]
[InstCombine] Add vector udiv tests
Tests for X udiv C, where C >= signbit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324635
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Craig Topper [Thu, 8 Feb 2018 18:55:14 +0000 (18:55 +0000)]
[SelectionDAG] Add a helper function for creating a boolean constant based on the target's boolean content
Many in SimplifySetCC and FoldSetCC try to create true or false constants. Some of them query getBooleanContents to figure out whether to use all ones or just 1 for true. But many places do not check and just use 1 without ensuring the VT has an i1 scalar type. Note sure if those places only trigger before type legalization so they only see an i1
type?
To cleanup the inconsistency and reduce some duplicated code, this patch adds a getBoolConstant method to SelectionDAG that takes are of querying getBooleanContents and doing the right thing.
Differential Revision: https://reviews.llvm.org/D43037
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324634
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Vedant Kumar [Thu, 8 Feb 2018 18:46:49 +0000 (18:46 +0000)]
Simplify function prototypes in bugpoint, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324633
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Douglas Yung [Thu, 8 Feb 2018 18:45:16 +0000 (18:45 +0000)]
Change "UNSUPPORTED: windows" to be "UNSUPPORTED: system-windows" so that test is actually skipped on Windows.
Reviewed by Paul Robinson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324632
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Simon Pilgrim [Thu, 8 Feb 2018 18:36:01 +0000 (18:36 +0000)]
[InstCombine] Add m_Negative pattern matching
Allows us to add non-uniform constant vector support for "X urem C -> X < C ? X : X - C, where C >= signbit."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324631
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Craig Topper [Thu, 8 Feb 2018 18:34:25 +0000 (18:34 +0000)]
[X86] Add a few new test cases for shrunkblend combine
One of them shows a missed opportunity to use SimplifyDemandedBits on the condition when its used by multiple vselects.
The other is a case we shouldn't optimize because the condition has a non-vselect use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324630
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Simon Pilgrim [Thu, 8 Feb 2018 18:10:08 +0000 (18:10 +0000)]
[InstCombine] Add vector urem tests.
Improve coverage of InstCombiner::visitURem for vector types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324629
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Vedant Kumar [Thu, 8 Feb 2018 18:02:27 +0000 (18:02 +0000)]
Use ranged for loops in TypeFinder.cpp, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324628
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Simon Pilgrim [Thu, 8 Feb 2018 17:54:24 +0000 (17:54 +0000)]
[InstCombine] Regenerate vector mul tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324627
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Daniel Neilson [Thu, 8 Feb 2018 17:33:08 +0000 (17:33 +0000)]
[LoopIdiom] Be more aggressive when setting alignment in memcpy
Summary:
This change is part of step five in the series of changes to remove alignment argument from
memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the
LoopIdiom pass to cease using the old IRBuilder CreateMemCpy single-alignment APIs in
favour of the new API that allows setting source and destination alignments independently.
This allows us to be slightly more aggressive in setting the alignment of memcpy calls that
loop idiom creates.
Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.
Reference
http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20151109/312083.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324626
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Erich Keane [Thu, 8 Feb 2018 17:11:32 +0000 (17:11 +0000)]
Fix signed/unsigned compare warning I introduced
'size' of a vector is unsigned, and I accidentially compared
it to an int through GTEST. I switched it to unsigned, which
is the template parameter type anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324625
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Erich Keane [Thu, 8 Feb 2018 16:48:54 +0000 (16:48 +0000)]
[ARM] Add 'fillValidCPUArchList' to ARM targets
This is a support change for a CFE change (https://reviews.llvm.org/D42978)
that allows march and -target-cpu to list the valid targets in a note. The changes
are limited to the ARM/AArch64, since this is the only target that gets the CPU
list from LLVM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324623
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Jonas Devlieghere [Thu, 8 Feb 2018 16:31:42 +0000 (16:31 +0000)]
[dsymutil] Use llvm::sys::path to join bundle path.
When processing a dSYM bundle, use llvm::sys::path to join the different
path components instead of using a string with hard coded forward
slashes as separators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324622
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Jonas Devlieghere [Thu, 8 Feb 2018 16:31:01 +0000 (16:31 +0000)]
[dwarfdump] Normalize input path.
Before this patch, llvm-dwarfdump would reject `bundel.dSYM/` as input,
while `bundel.dSYM` was accepted. The reason is that `path::extension()`
returns an empty string for the former, leading to the argument not
being recognized as a dSYM bundle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324621
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Yaxun Liu [Thu, 8 Feb 2018 15:41:19 +0000 (15:41 +0000)]
[AMDGPU] Updae documentation about address space
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324617
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Sanjay Patel [Thu, 8 Feb 2018 15:32:28 +0000 (15:32 +0000)]
[SLPVectorizer] auto-generate complete checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324616
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Sanjay Patel [Thu, 8 Feb 2018 15:30:39 +0000 (15:30 +0000)]
[SLPVectorizer] auto-generate complete checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324615
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Sanjay Patel [Thu, 8 Feb 2018 15:28:49 +0000 (15:28 +0000)]
[SLPVectorizer] move RUN line to top-of-file; NFC
I was confused what we were checking because the RUN line was
in the middle of the file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324614
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Simon Pilgrim [Thu, 8 Feb 2018 15:19:38 +0000 (15:19 +0000)]
[InstCombine] Fix issue with X udiv (POW2_C1 << N) for non-splat constant vectors
foldUDivShl was assuming that the input was a scalar or a splat constant
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324613
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Sanjay Patel [Thu, 8 Feb 2018 15:16:26 +0000 (15:16 +0000)]
[SLPVectorizer] auto-generate complete checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324612
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Sanjay Patel [Thu, 8 Feb 2018 15:13:47 +0000 (15:13 +0000)]
[LoopVectorize] auto-generate complete checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324611
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Sanjay Patel [Thu, 8 Feb 2018 14:52:40 +0000 (14:52 +0000)]
[ValueTracking] don't crash when assumptions conflict (PR36270)
The last assume in the test says that %B12 is 0.
The first assume says that %and1 is less than %B12.
Therefore, %and1 is unsigned less than 0...does not compute.
That means this line:
Known.Zero.setHighBits(RHSKnown.countMinLeadingZeros() + 1);
...tries to set more bits than exist.
Differential Revision: https://reviews.llvm.org/D43052
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324610
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Simon Pilgrim [Thu, 8 Feb 2018 14:46:10 +0000 (14:46 +0000)]
[InstCombine] Fix issue with X udiv 2^C -> X >> C for non-splat constant vectors
foldUDivPow2Cst was assuming that the input was a scalar or a splat constant
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324608
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Oliver Stannard [Thu, 8 Feb 2018 14:31:22 +0000 (14:31 +0000)]
[ARM] Re-commit r324600 with fixed LLVMBuild.txt
ARMDisassembler now depends on the banked register tables in ARMUtils, so the
LLVMBuild.txt needed updating to reflect this.
Original commit mesage:
[ARM] Fix disassembly of invalid banked register moves
When disassembling banked register move instructions, we don't have an
assembly syntax for the unallocated register numbers, so we have to
return Fail rather than SoftFail. Previously we were returning SoftFail,
then crashing in the InstPrinter as we have no way to represent these
encodings in an assembly string.
This also switches the decoder to use the table-generated list of banked
registers, removing the duplicated list of encodings.
Differential revision: https://reviews.llvm.org/D43066
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324606
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Simon Pilgrim [Thu, 8 Feb 2018 14:24:26 +0000 (14:24 +0000)]
Fix unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324605
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Oliver Stannard [Thu, 8 Feb 2018 14:21:28 +0000 (14:21 +0000)]
Revert r324600 as it breaks a buildbot
The broken bot (clang-ppc64le-linux-multistage) is doign a shared-object build,
so I guess using lookupBankedRegByEncoding in the disassembler is a layering
violation?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324604
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Simon Pilgrim [Thu, 8 Feb 2018 14:10:01 +0000 (14:10 +0000)]
[InstCombine] Improve mul(x, pow2) -> shl combine for vector constants
Refactor getLogBase2Vector into getLogBase2 to accept all scalars/vectors. Generalize from ConstantDataVector to support all constant vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324603
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Alexander Ivchenko [Thu, 8 Feb 2018 13:16:42 +0000 (13:16 +0000)]
[x86] Add test/CodeGen/X86/vmaskmov-offset.ll. NFC.
Needed for checking current code generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324601
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Oliver Stannard [Thu, 8 Feb 2018 13:06:08 +0000 (13:06 +0000)]
[ARM] Fix disassembly of invalid banked register moves
When disassembling banked register move instructions, we don't have an
assembly syntax for the unallocated register numbers, so we have to
return Fail rather than SoftFail. Previously we were returning SoftFail,
then crashing in the InstPrinter as we have no way to represent these
encodings in an assembly string.
This also switches the decoder to use the table-generated list of banked
registers, removing the duplicated list of encodings.
Differential revision: https://reviews.llvm.org/D43066
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324600
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Jonas Devlieghere [Thu, 8 Feb 2018 11:58:16 +0000 (11:58 +0000)]
[test][dsymutil] Fix tests for Windows bots.
The UNSUPPORTED directive was not honored by the bot, presumably because
of the FIXME above it. This moves the comment down and removes the
remaining update check from basic-linking-x86.test.
This should un-break: llvm-clang-x86_64-expensive-checks-win/builds/7798/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324598
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Alexander Ivchenko [Thu, 8 Feb 2018 11:45:36 +0000 (11:45 +0000)]
Add missed PostDominatorTree analysis dependency to GVN hoist pass.
Summary:
GVN hoist pass is using PostDominatorTree analysis, therefore the analysis
should be listed in the pass initialization as a dependency.
Reviewed By: sebpop
Differential Revision: https://reviews.llvm.org/D43007
Author: ashlykov <arkady.shlykov@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324597
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Gadi Haber [Thu, 8 Feb 2018 11:16:02 +0000 (11:16 +0000)]
[X86][MC]: Adding test coverage of MC encoding for several small extensions.<NFC>
NFC.
Adding MC regressions tests to cover several small x86 extensions as follows:
CLWB, CLZERO, F16C, INVPCID, PKU, POPCNT, RTM, SGX, SHA, SVM, VMFUNC, VTX
This patch is part of a larger task to cover MC encoding of all X86 isa sets started in revision: https://reviews.llvm.org/D39952
Reviewers: RKSimon, craig.topper, zvi, AndreiGrischenko
Differential Revision: https://reviews.llvm.org/D41388
Change-Id: I254508cd17faca00b780be0fc2abf6c71b61faab
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324595
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Jonas Devlieghere [Thu, 8 Feb 2018 10:48:54 +0000 (10:48 +0000)]
Re-land [dsymutil] Upstream update feature
This commit attempts to re-land the r324480 which was reverted in
r324493 because it broke the Windows bots. For now I disabled the two
update tests on Windows until I'm able to debug this.
Differential revision: https://reviews.llvm.org/D42880
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324592
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Serguei Katkov [Thu, 8 Feb 2018 10:34:08 +0000 (10:34 +0000)]
[Loop Predication] Teach LP about reverse loops with uge and sge latch conditions
Add support of uge and sge latch condition to Loop Prediction for
reverse loops.
Reviewers: apilipenko, mkazantsev, sanjoy, anna
Reviewed By: anna
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42837
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324589
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Clement Courbet [Thu, 8 Feb 2018 09:41:50 +0000 (09:41 +0000)]
[X86] Fix compilation of r324580.
@ctopper Can you check that the fix is correct ?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324586
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Stefan Maksimovic [Thu, 8 Feb 2018 09:31:48 +0000 (09:31 +0000)]
Revert accidental changes that snuck in r324584
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324585
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Stefan Maksimovic [Thu, 8 Feb 2018 09:25:17 +0000 (09:25 +0000)]
[mips] Define certain instructions in microMIPS32r3
Instructions affected:
mthc1, mfhc1, add.d, sub.d, mul.d, div.d,
mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d
These instructions are now defined for
microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td
since they shared their encoding with those already defined
in microMIPS32r6InstrInfo.td and have been therefore
removed from the latter file.
Some instructions present in MicroMipsInstrFPU.td which
did not have both AFGR64 and FGR64 variants defined have
been altered to do so.
Differential revision: https://reviews.llvm.org/D42738
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324584
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Dylan McKay [Thu, 8 Feb 2018 09:17:11 +0000 (09:17 +0000)]
[AVR] Fix the testsuite after '%' changed to '$' in MIR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324583
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Clement Courbet [Thu, 8 Feb 2018 08:46:48 +0000 (08:46 +0000)]
[TargetSchedule] Expose sub-units of a ProcResGroup in MCProcResourceDesc.
Summary:
Right now using a ProcResource automatically counts as usage of all
super ProcResGroups. All this is done during codegen, so there is no
way for schedulers to get this information at runtime.
This adds the information of which individual ProcRes units are
contained in a ProcResGroup in MCProcResourceDesc.
Reviewers: gchatelet
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324582
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Sjoerd Meijer [Thu, 8 Feb 2018 08:39:05 +0000 (08:39 +0000)]
[AArch64] Don't materialize 0 with "fmov h0, .." when FullFP16 is not supported
We were generating "fmov h0, wzr" instructions when FullFP16 is not enabled.
I've not added any tests, because the problem was visible in:
test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll,
which I had to change: I don't think Cyclone has FullFP16 enabled
by default, so it shouldn't be using this v8.2a instruction.
I've also removed these rdar tags, please shout if there are any objections.
Differential Revision: https://reviews.llvm.org/D43020
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324581
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Craig Topper [Thu, 8 Feb 2018 08:29:43 +0000 (08:29 +0000)]
[X86] Support folding in a k-register OR when creating KORTEST from scalar compare of a bitcast from vXi1.
This should allow us to remove the kortest intrinsic from IR and use compare+bitcast+or in IR instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324580
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Craig Topper [Thu, 8 Feb 2018 07:54:16 +0000 (07:54 +0000)]
[X86] Allow KORTEST instruction to be used for testing if a mask is all ones
The KTEST instruction sets the C flag if the result of anding both operands together is all 1s. We can use this to lower (icmp eq/ne (bitcast (vXi1 X), -1)
Differential Revision: https://reviews.llvm.org/D42772
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324577
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Craig Topper [Thu, 8 Feb 2018 07:45:55 +0000 (07:45 +0000)]
[X86] Don't emit KTEST instructions unless only the Z flag is being used
Summary:
KTEST has weird flag behavior. The Z flag is set for all bits in the AND of the k-registers being 0, and the C flag is set for all bits being 1. All other flags are cleared.
We currently emit this instruction in EmitTEST and don't check the condition code. This can lead to strange things like using the S flag after a KTEST for a signed compare.
The domain reassignment pass can also transform TEST instructions into KTEST and is not protected against the flag usage either. For now I've disabled this part of the domain reassignment pass. I tried to comment out the checks in the mir test so that we could recover them later, but I couldn't figure out how to get that to work.
This patch moves the KTEST handling into LowerSETCC and now creates a ktest+x86setcc. I've chosen this approach because I'd like to add support for the C flag for all ones in a followup patch. To do that requires that I can rewrite the condition code going in the x86setcc to be different than the original SETCC condition code.
This fixes PR36182. I'll file a PR to fix domain reassignment once this goes in. Should this be merged to 6.0?
Reviewers: spatel, guyblank, RKSimon, zvi
Reviewed By: guyblank
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42770
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324576
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George Rimar [Thu, 8 Feb 2018 07:23:24 +0000 (07:23 +0000)]
Recommit r324455 "[ThinLTO] - Simplify code in ThinLTOBitcodeWriter."
With fix: reimplemented.
Original commit message:
Recently introduced convertToDeclaration is very similar
to code used in filterModule function.
Patch reuses it to reduce duplication.
Differential revision: https://reviews.llvm.org/D42971
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324574
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Serguei Katkov [Thu, 8 Feb 2018 07:16:29 +0000 (07:16 +0000)]
[SimplifyCFG] Re-apply Relax restriction for folding unconditional branches
The commit rL308422 introduces a restriction for folding unconditional
branches. Specifically if empty block with unconditional branch leads to
header of the loop then elimination of this basic block is prohibited.
However it seems this condition is redundantly strict.
If elimination of this basic block does not introduce more back edges
then we can eliminate this block.
The patch implements this relax of restriction.
The test profile/Linux/counter_promo_nest.c in compiler-rt project
is updated to meet this change.
Reviewers: efriedma, mcrosier, pacxx, hsung, davidxl
Reviewed By: pacxx
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42691
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324572
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Martell Malone [Thu, 8 Feb 2018 07:13:17 +0000 (07:13 +0000)]
CMAKE: apply -O3 for mingw clang
Differential Revision: https://reviews.llvm.org/D41596
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324570
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Craig Topper [Thu, 8 Feb 2018 06:27:18 +0000 (06:27 +0000)]
[DAGCombiner] Fix a couple mistakes from r324311 by really passing the original load to ExtendSetCCUses.
We're passing the binary op that uses the load instead of the load.
Noticed by inspection. Not sure how to test this because this just prevents the introduction of an extend that will later be truncated and will probably be combined out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324568
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Craig Topper [Thu, 8 Feb 2018 06:04:18 +0000 (06:04 +0000)]
[DAGCombiner] Don't create truncate nodes in (aext (zextload x)) -> (zextload x) and similar folds. NFCI
The truncate is being used to replace other users of of the load, but we checked that the load only has one use so there are no other uses to replace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324567
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Peter Collingbourne [Thu, 8 Feb 2018 05:28:39 +0000 (05:28 +0000)]
ARM: Remove dead code. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324565
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Francis Visoiu Mistrih [Thu, 8 Feb 2018 05:02:00 +0000 (05:02 +0000)]
[CodeGen] Print MachineBasicBlock labels using MIR syntax in -debug output
Instead of:
%bb.1: derived from LLVM BB %for.body
print:
bb.1.for.body:
Also use MIR syntax for MBB attributes like "align", "landing-pad", etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324563
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Craig Topper [Thu, 8 Feb 2018 04:38:04 +0000 (04:38 +0000)]
[DAGCombiner] Avoid creating truncate nodes in (zext (and (load)))->(and (zextload)) fold until we know for sure we're going to need it. NFCI
The truncate is only needed if the load has additional users. It used to get passed to extendSetCCUses so was created early, but that's no longer the case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324562
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Craig Topper [Thu, 8 Feb 2018 04:38:02 +0000 (04:38 +0000)]
[DAGCombiner] Rename variable to be slightly better. NFC
We were calling a load LN0 but it came from N0.getOperand(0) so its really more like LN00 if we follow the name used in other places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324561
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Yonghong Song [Thu, 8 Feb 2018 04:37:49 +0000 (04:37 +0000)]
bpf: Improve expanding logic in LowerSELECT_CC
LowerSELECT_CC is not generating optimal Select_Ri pattern at the moment. It
is not guaranteed to place ConstantNode at RHS which would miss matching
Select_Ri.
A new testcase added into the existing select_ri.ll, also there is an
existing case in cmp.ll which would be improved to use Select_Ri after this
patch, it is adjusted accordingly.
Reported-by: Alexei Starovoitov <alexei.starovoitov@gmail.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324560
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Peter Collingbourne [Thu, 8 Feb 2018 02:41:22 +0000 (02:41 +0000)]
gold-plugin: Do not set codegen opt level based on LTO opt level.
The LTO opt level should not affect the codegen opt level, and indeed
it does not affect it in lld. Ideally the codegen opt level should
be controlled by an IR-level attribute based on the compile-time opt
level, but that hasn't been implemented yet.
Differential Revision: https://reviews.llvm.org/D43040
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324557
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Matt Arsenault [Thu, 8 Feb 2018 01:56:14 +0000 (01:56 +0000)]
AMDGPU: Fix incorrect reordering when inline asm defines LDS address
Defs of operands outside of the instruction's explicit defs need
to be checked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324554
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Rafael Espindola [Thu, 8 Feb 2018 01:16:05 +0000 (01:16 +0000)]
Fix PR36268.
The issue is that clang was first creating a extern_weak hidden GV and
then changing the linkage to external.
Once we know it is not extern_weak we know it must be dso_local.
This patch refactors the code that sets the implicit dso_local to a
helper private function that is used every time we change the linkage
or visibility.
I will commit a patch to clang in a minute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324551
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Matt Arsenault [Thu, 8 Feb 2018 01:12:46 +0000 (01:12 +0000)]
AMDGPU: Don't crash when trying to fold implicit operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324550
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Justin Lebar [Thu, 8 Feb 2018 00:50:04 +0000 (00:50 +0000)]
[NVPTX] When dying due to a bad address space value, print out the value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324549
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Stanislav Mekhanoshin [Thu, 8 Feb 2018 00:18:35 +0000 (00:18 +0000)]
[AMDGPU] Fixed wait count reuse
The code reusing existing wait counts is incorrect since it keeps
adding new operands to an old instruction instead of replacing
the immediate. It was also effectively switched off by the condition
that wait count is not an AMDGPU::S_WAITCNT.
Also switched to BuildMI instead of creating instructions directly.
Differential Revision: https://reviews.llvm.org/D42997
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324547
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Chandler Carruth [Wed, 7 Feb 2018 23:59:14 +0000 (23:59 +0000)]
[x86] Fix nasty bug in the x86 backend that is essentially impossible to
hit from IR but creates a minefield for MI passes.
The x86 backend has fairly powerful logic to try and fold loads that
feed register operands to instructions into a memory operand on the
instruction. This is almost always a good thing, but there are specific
relocated loads that are only allowed to appear in specific
instructions. Notably, R_X86_64_GOTTPOFF is only allowed in `movq` and
`addq`. This patch blocks folding of memory operands using this
relocation unless the target is in fact `addq`.
The particular relocation indicates why we simply don't hit this under
normal circumstances. This relocation is only used for TLS, and it gets
used in very specific ways in conjunction with %fs-relative addressing.
The result is that loads using this relocation are essentially never
eligible for folding into an instruction's memory operands. Unless, of
course, you have an MI pass that inserts usage of such a load. I have
exactly such an MI pass and was greeted by truly mysterious miscompiles
where the linker replaced my instruction with a completely garbage byte
sequence. Go team.
This is the only such relocation I'm aware of in x86, but there may be
others that need to be similarly restricted.
Fixes PR36165.
Differential Revision: https://reviews.llvm.org/D42732
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324546
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Mircea Trofin [Wed, 7 Feb 2018 23:29:52 +0000 (23:29 +0000)]
Verify profile data confirms large loop trip counts.
Summary:
Loops with inequality comparers, such as:
// unsigned bound
for (unsigned i = 1; i < bound; ++i) {...}
have getSmallConstantMaxTripCount report a large maximum static
trip count - in this case, 0xffff fffe. However, profiling info
may show that the trip count is much smaller, and thus
counter-recommend vectorization.
This change:
- flips loop-vectorize-with-block-frequency on by default.
- validates profiled loop frequency data supports vectorization,
when static info appears to not counter-recommend it. Absence
of profile data means we rely on static data, just as we've
done so far.
Reviewers: twoh, mkuper, davidxl, tejohnson, Ayal
Reviewed By: davidxl
Subscribers: bkramer, llvm-commits
Differential Revision: https://reviews.llvm.org/D42946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324543
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Craig Topper [Wed, 7 Feb 2018 22:45:38 +0000 (22:45 +0000)]
[X86] Prune some unreachable 'return SDValue()' paths from LowerSIGN_EXTEND/LowerZERO_EXTEND/LowerANY_EXTEND.
We were doing a lot of whitelisting of what we handle in these routines, but setOperationAction constrains what we can get here. So just add some asserts and prune the unreachable paths.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324538
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Craig Topper [Wed, 7 Feb 2018 22:19:26 +0000 (22:19 +0000)]
[X86] Remove dead code from EmitTest that looked for an i1 type which should have already been type legalized away. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324536
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Craig Topper [Wed, 7 Feb 2018 21:41:50 +0000 (21:41 +0000)]
[X86] When doing callee save/restore for k-registers make sure we don't use KMOVQ on non-BWI targets
If we are saving/restoring k-registers, the default behavior of getMinimalRegisterClass will find the VK64 class with a spill size of 64 bits. This will cause the KMOVQ opcode to be used for save/restore. If we don't have have BWI instructions we need to constrain the class returned to give us VK16 with a 16-bit spill size. We can do this by passing the either v16i1 or v64i1 into getMinimalRegisterClass.
Also add asserts to make sure BWI is enabled anytime we use KMOVD/KMOVQ. These are what caught this bug.
Fixes PR36256
Differential Revision: https://reviews.llvm.org/D42989
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324533
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Craig Topper [Wed, 7 Feb 2018 21:29:30 +0000 (21:29 +0000)]
[X86] Auto-generate complete checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324530
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Momchil Velikov [Wed, 7 Feb 2018 20:28:47 +0000 (20:28 +0000)]
Revert "[DebugInfo] Improvements to representation of enumeration types (PR36168)"
Revert commit r324489, it broke LLDB tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324511
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Alexey Bataev [Wed, 7 Feb 2018 20:11:37 +0000 (20:11 +0000)]
[SLP] Add a tests for PR36280, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324510
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Zachary Turner [Wed, 7 Feb 2018 19:37:52 +0000 (19:37 +0000)]
Generate PDB files for profiling even in Release build.
This patch enables PDB generation for Release build, which has
slightly different optimize option with RelWithDebInfo on windows.
This helps to know slow part of Release build when profiling.
Patch by Takuto Ikuta
Differential Revision: https://reviews.llvm.org/D42632
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324504
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Craig Topper [Wed, 7 Feb 2018 18:32:15 +0000 (18:32 +0000)]
[X86] Regenerate test using update_mir_test_checks.py. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324497
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Rafael Espindola [Wed, 7 Feb 2018 18:09:35 +0000 (18:09 +0000)]
Revert "AMDGPU: Add 32-bit constant address space"
This reverts commit r324487.
It broke clang tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324494
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Jonas Devlieghere [Wed, 7 Feb 2018 17:35:27 +0000 (17:35 +0000)]
Revert dsymutil -update commits
Revert "[dsymutil][test] Check the updated dSYM instead of companion file."
Revert "[dsymutil] Upstream update feature."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324493
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Nirav Dave [Wed, 7 Feb 2018 17:12:34 +0000 (17:12 +0000)]
[SelectionDAG] More Aggressibly prune nodes in AddChains. NFCI.
Travel all chains paths to first non-tokenfactor node can be
exponential work. Add simple redundency check to avoid this.
Fixes PR36264.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324491
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Momchil Velikov [Wed, 7 Feb 2018 16:46:33 +0000 (16:46 +0000)]
[DebugInfo] Improvements to representation of enumeration types (PR36168)
This patch is the LLVM part of fixing the issues, described in
https://bugs.llvm.org/show_bug.cgi?id=36168
* The representation of enumerator values in the debug info metadata now
contains a boolean flag isUnsigned, which determines how the bits of
the value are interpreted.
* The DW_TAG_enumeration type DIE now always (for DWARF version >= 3)
includes a DW_AT_type attribute, which refers to the underlying
integer type, as suggested in DWARFv4 (5.7 Enumeration Type Entries).
* The debug info metadata for enumeration type contains (in flags)
indication whether this is a C++11 "fixed enum".
* For C++11 enumeration with a fixed underlying type, the DIE also
includes the DW_AT_enum_class attribute (for DWARF version >= 4).
* Encoding of enumerator constants uses DW_FORM_sdata for signed values
and DW_FORM_udata for unsigned values, as suggested by DWARFv4 (7.5.4
Attribute Encodings).
The changes should be backwards compatible:
* the isUnsigned attribute is optional and defaults to false.
* if the underlying type for the enumeration is not available, the
enumerator values are considered signed.
* the FixedEnum flag defaults to clear.
* the bitcode format for DIEnumerator stores the unsigned flag bit #1 of
the first record element, so the format does not change and the zero
previously stored there is consistent with the false default for
IsUnsigned.
Differential Revision: https://reviews.llvm.org/D42734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324489
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Marek Olsak [Wed, 7 Feb 2018 16:01:00 +0000 (16:01 +0000)]
AMDGPU: Add 32-bit constant address space
Note: This is a candidate for LLVM 6.0, because it was planned to be
in that release but was delayed due to a long review period.
Merge conflict in release_60 - resolution:
Add "-p6:32:32" into the second (non-amdgiz) string.
Only scalar loads support 32-bit pointers. An address in a VGPR will
fail to compile. That's OK because the results of loads will only be used
in places where VGPRs are forbidden.
Updated AMDGPUAliasAnalysis and used SReg_64_XEXEC.
The tests cover all uses cases we need for Mesa.
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D41651
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324487
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Marek Olsak [Wed, 7 Feb 2018 16:00:40 +0000 (16:00 +0000)]
AMDGPU: Remove the s_buffer workaround for GFX9 chips
Summary:
I checked the AMD closed source compiler and the workaround is only
needed when x3 is emulated as x4, which we don't do in LLVM.
SMEM x3 opcodes don't exist, and instead there is a possibility to use x4
with the last component being unused. If the last component is out of
buffer bounds and falls on the next 4K page, the hw hangs.
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D42756
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324486
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Simon Pilgrim [Wed, 7 Feb 2018 15:48:44 +0000 (15:48 +0000)]
[X86][AVX] Add PACKSSDW/PACKUSDW support for truncation of clamped values
SSE and shorter vector sizes will have to wait until we can add support for general SMIN/SMAX matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324485
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Jonas Devlieghere [Wed, 7 Feb 2018 15:18:21 +0000 (15:18 +0000)]
[dsymutil][test] Check the updated dSYM instead of companion file.
This patch has llvm-dwarfdump check the whole dSYM, rather than the
hard-coded path to the Mach-O companion file. This might be what's
causing the Windows bot to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324483
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Clement Courbet [Wed, 7 Feb 2018 14:26:43 +0000 (14:26 +0000)]
[SLPVectorizer][NFC] Make a loop more readable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324482
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Jonas Devlieghere [Wed, 7 Feb 2018 13:51:29 +0000 (13:51 +0000)]
[dsymutil] Upstream update feature.
Now that dsymutil can generate accelerator tables, we can upstream the
update logic that, as the name implies, updates the accelerator tables
in an existing dSYM bundle. In combination with `-minimize` this can be
used to remove redundant .debug_(inlines|pubtypes|pubnames).
Differential revision: https://reviews.llvm.org/D42880
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324480
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Simon Pilgrim [Wed, 7 Feb 2018 13:28:23 +0000 (13:28 +0000)]
[X86] Regenerate atomic i32 tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324479
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Benjamin Kramer [Wed, 7 Feb 2018 12:55:01 +0000 (12:55 +0000)]
[Orc] Pacify -pedantic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324478
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Simon Atanasyan [Wed, 7 Feb 2018 12:36:39 +0000 (12:36 +0000)]
[mips] Support 'y' operand code to print exact log2 of the operand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324477
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Simon Atanasyan [Wed, 7 Feb 2018 12:36:33 +0000 (12:36 +0000)]
[mips] Handle 'M' and 'L' operand codes for memory operands
Both operand codes now work the same way in case of register or memory
operands. It print high-order or low-order word in a double-word
register or memory location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324476
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Pavel Labath [Wed, 7 Feb 2018 11:19:29 +0000 (11:19 +0000)]
[BinaryFormat] Remove dangling declaration of DiscriminantString
The implementation of the function was deleted in r324426. This also
removes the declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324474
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Max Kazantsev [Wed, 7 Feb 2018 11:16:29 +0000 (11:16 +0000)]
Re-enable "[SCEV] Make isLoopEntryGuardedByCond a bit smarter"
The failures happened because of assert which was overconfident about
SCEV's proving capabilities and is generally not valid.
Differential Revision: https://reviews.llvm.org/D42835
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324473
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Clement Courbet [Wed, 7 Feb 2018 09:58:55 +0000 (09:58 +0000)]
[MergeICmps] Re-commit rL324317 "Enable the MergeICmps Pass by default."
With fixes from rL324341.
Original commit message:
[MergeICmps] Enable the MergeICmps Pass by default.
Summary: Now that PR33325 is fixed, this should always improve the generated code.
Reviewers: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42793
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324465
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Serguei Katkov [Wed, 7 Feb 2018 09:10:08 +0000 (09:10 +0000)]
Revert [SCEV] Make isLoopEntryGuardedByCond a bit smarter
Revert rL324453 commit which causes buildbot failures.
Differential Revision: https://reviews.llvm.org/D42835
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324462
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George Rimar [Wed, 7 Feb 2018 08:46:36 +0000 (08:46 +0000)]
Revert r324455 "[ThinLTO] - Simplify code in ThinLTOBitcodeWriter."
It broke BB:
http://lab.llvm.org:8011/builders/sanitizer-windows/builds/23721
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324458
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Sjoerd Meijer [Wed, 7 Feb 2018 08:37:17 +0000 (08:37 +0000)]
[ARM] FP16 mov imm pattern
This is a follow up of r324321, adding a match pattern for mov with a FP16
immediate (also fixing operand vfp_f16imm that wasn't even compiling).
Differential Revision: https://reviews.llvm.org/D42973
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324456
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George Rimar [Wed, 7 Feb 2018 08:32:35 +0000 (08:32 +0000)]
[ThinLTO] - Simplify code in ThinLTOBitcodeWriter.
Recently introduced convertToDeclaration is very similar
to code used in filterModule function.
Patch reuses it to reduce duplication.
Differential revision: https://reviews.llvm.org/D42971
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324455
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Max Kazantsev [Wed, 7 Feb 2018 07:56:26 +0000 (07:56 +0000)]
[SCEV] Make isLoopEntryGuardedByCond a bit smarter
Sometimes `isLoopEntryGuardedByCond` cannot prove predicate `a > b` directly.
But it is a common situation when `a >= b` is known from ranges and `a != b` is
known from a dominating condition. Thia patch teaches SCEV to sum these facts
together and prove strict comparison via non-strict one.
Differential Revision: https://reviews.llvm.org/D42835
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324453
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Michael Zolotukhin [Wed, 7 Feb 2018 06:54:11 +0000 (06:54 +0000)]
The xfailed test from r324448 passed on one of the bots: remove it entirely for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324451
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Serguei Katkov [Wed, 7 Feb 2018 06:53:37 +0000 (06:53 +0000)]
[LoopPrediction] Introduce utility function getLatchPredicateForGuard. NFC.
Factor out getting the predicate for latch condition in a guard to
utility function getLatchPredicateForGuard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324450
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