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Ville Syrjälä [Thu, 23 Oct 2014 14:41:34 +0000 (07:41 -0700)]
drm/i915: Add rotation support for cursor plane (v5)
The cursor plane also supports 180 degree rotation. Add a new
"cursor-rotation" property on the crtc which controls this.
Unlike sprites, the cursor has a fixed size, so if you have a small
cursor image with the rest of the bo filled by transparent pixels,
simply flipping the rotation property will cause the visible part
of the cursor to shift. This is something to keep in mind when
using cursor rotation.
v2: Fix gen4/vlv by offsetting the base address appropriately
v3: Removing cursor-rotation property and using rotation property on cursor
plane.
v4: Changing the author name back to Ville.
v5 (by Matt Roper): Slight tweaking to apply against latest di-nightly
codebase.
Cc: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Tested-by (IVB): Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Mon, 29 Sep 2014 13:31:26 +0000 (15:31 +0200)]
drm/i915: Correctly reject invalid flags for wait_ioctl
Not having checks for this isn't good.
I've checked igt and libdrm and they all already clear flags properly.
So we're lucky and should be able to sneak this ABI clarification in.
Testcase: igt/gem_wait/invalid-flags
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85280
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Yu Zhang [Thu, 23 Oct 2014 07:28:24 +0000 (15:28 +0800)]
drm/i915: use macros to assign mmio access functions
This is beautification prep work since vgt will add even more special
cases. With these macros it's much easier to see what's going on
really.
Signed-off-by: Yu Zhang <yu.c.zhang@linux.intel.com>
[danvet: #undef the temporary macros after the function again. And
write a commit message.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Tue, 7 Oct 2014 19:11:11 +0000 (16:11 -0300)]
drm/i915: only run hsw_power_well_post_enable when really needed
Only run it after we actually enable the power well. When we're
booting the machine there are cases where we run
hsw_power_well_post_enable without really needing, and even though
this is not causing any real bugs, it is unneeded and causes confusion
to people debugging interrupts.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Rodrigo Vivi [Fri, 17 Oct 2014 15:05:08 +0000 (08:05 -0700)]
drm/i915/chv: Use 16 and 32 for low and high drain latency precision.
Current chv spec teels we can only use either 16 or 32 bits as precision.
Although in the past VLV went from 16/32 to 32/64 and spec might not be updated,
these precision values brings stability and fixes some issues Wayne was facing.
Cc: Wayne Boyer <wayne.boyer@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Tested-by: Wayne Boyer <wayne.boyer@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Sprinkle const as requested by Ville.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Wed, 22 Oct 2014 09:06:44 +0000 (11:06 +0200)]
drm/i915: Fold in intel_mst_port_dp_detect
The indirection here seems to serve no purpose. Probably leftovers
from earlier revisions. Spotted while trying to review some mst
patches.
Cc: Dave Airlie <airlied@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Michel Thierry [Thu, 16 Oct 2014 15:13:38 +0000 (16:13 +0100)]
drm/i915: add runtime PM get/put call in i915_execlists
Otherwise we will get WARNs when we read context status registers and
the machine is suspended.
Testcase: igt/pm_rpm/debugfs-read
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Thu, 16 Oct 2014 17:52:32 +0000 (20:52 +0300)]
drm/i915: Fix chv PCS DW11 register defines
I managed to fumble the per spline PCS DW11 register defines in:
commit
570e2a747bc06cd8620662c5125ec2dc964c511b
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Mon Aug 18 14:42:46 2014 +0300
drm/i915: Clear TX FIFO reset master override bits on chv
Fortunately the bit in DW0 that was cleared due to this didn't have
any effect as long as the bit we meant to clear was already zero.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
[danvet: Fix commit ref as pointed out by Jani.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Thu, 16 Oct 2014 17:52:30 +0000 (20:52 +0300)]
drm/i915: Don't claim that we're resetting PCH ADPA register
intel_crt_reset() resets the ADPA register on all gen5+ platforms.
However the debug message claims it's touching the PCH ADPA register
which is clearly not what it does on VLV. Drop the PCH part from
the debug message.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Fri, 17 Oct 2014 21:42:03 +0000 (18:42 -0300)]
drm/i915: disable IPS while getting the pipe CRCs.
For some yet-undiscovered reason, when IPS gets enabled, the pipe CRC
changes. Since hsw_enable_ips() doesn't really guarantees to enable
IPS (it depends on package C-states), we can't really predict if IPS
is enabled or disabled while running our CRC tests, so let's just
completely disable IPS while pipe CRCs are being used.
If we find a way to make IPS not change the pipe CRC result, we may
want to fix IPS and then revert this patch. While this doesn't happen,
let's merge this patch, so every IGT test relying on the CRCs can
work on pipe A.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72864
Testcase: igt/kms_cursor_crc (and others)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Wed, 15 Oct 2014 17:15:04 +0000 (14:15 -0300)]
drm/i915: call drm_vblank_cleanup() earlier at unload
In its current place, it just segfaults while trying to access the
CRTC structures:
[ 9132.421681] Call Trace:
[ 9132.421707] [<
ffffffffa01130d8>] i915_get_crtc_scanoutpos+0x1e8/0x220 [i915]
[ 9132.421727] [<
ffffffffa001da34>] drm_calc_vbltimestamp_from_scanoutpos+0x94/0x330 [drm]
[ 9132.421744] [<
ffffffffa001d240>] ?vblank_disable_and_save+0x40/0x1e0 [drm]
[ 9132.421769] [<
ffffffffa0114328>] i915_get_vblank_timestamp+0x68/0xb0 [i915]
[ 9132.421786] [<
ffffffffa001d094>] drm_get_last_vbltimestamp+0x44/0x80 [drm]
[ 9132.421801] [<
ffffffffa001d3a6>] vblank_disable_and_save+0x1a6/0x1e0 [drm]
[ 9132.421817] [<
ffffffffa001eac1>] drm_vblank_cleanup+0x61/0xa0 [drm]
[ 9132.421849] [<
ffffffffa0177a5e>] i915_driver_unload+0xde/0x290 [i915]
[ 9132.421867] [<
ffffffffa0020264>] drm_dev_unregister+0x24/0xb0 [drm]
[ 9132.421884] [<
ffffffffa002090e>] drm_put_dev+0x1e/0x70 [drm]
[ 9132.421901] [<
ffffffffa00e01e0>] i915_pci_remove+0x10/0x20 [i915]
[ 9132.421910] [<
ffffffff81347556>] pci_device_remove+0x36/0xb0
[ 9132.421920] [<
ffffffff8140084a>] __device_release_driver+0x7a/0xf0
[ 9132.421928] [<
ffffffff81400fc8>] driver_detach+0xb8/0xc0
[ 9132.421936] [<
ffffffff8140054a>] bus_remove_driver+0x4a/0xb0
[ 9132.421944] [<
ffffffff81401717>] driver_unregister+0x27/0x50
[ 9132.421953] [<
ffffffff81346f65>] pci_unregister_driver+0x25/0x70
[ 9132.421971] [<
ffffffffa00229c8>] drm_pci_exit+0x78/0xa0 [drm]
[ 9132.422000] [<
ffffffffa017a6d2>] i915_exit+0x20/0x94e [i915]
[ 9132.422009] [<
ffffffff810fb9dc>] SyS_delete_module+0x13c/0x1f0
[ 9132.422019] [<
ffffffff8131c5fb>] ?
trace_hardirqs_on_thunk+0x3a/0x3f
[ 9132.422028] [<
ffffffff816f7792>] system_call_fastpath+0x16/0x1b
This means it has to be before intel_modeset_cleanup, which cleans the
CRTC structures. But if we move it to before intel_fbdev_fini(), we
get WARNs because intel_fbdev_fini() still tries to use the vblanks,
so the only acceptable point for drm_vblank_cleanup() seems to be this
place.
Related commit:
commit
cbb47d179fb345c579cd8cd884693903fceed26a
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Mon Sep 23 17:33:20 2013 -0300
drm/i915: Add some missing steps to i915_driver_load error path
Testsuite: igt/drv_module_reload
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77511
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83484
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jani Nikula [Fri, 10 Oct 2014 14:53:33 +0000 (17:53 +0300)]
drm/i915: spt does not have pch backlight override bit
SPT is always in the PCH override mode, and the bit MBZ. Only set
override on LPT.
v2: check for PCH version (Ville)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jesse Barnes [Thu, 9 Oct 2014 19:57:43 +0000 (12:57 -0700)]
drm/i915: preserve swizzle settings if necessary v4
Some machines (like MBAs) might use a tiled framebuffer but not enable
display swizzling at boot time. We want to preserve that configuration
if possible to prevent a boot time mode set. On IVB+ it shouldn't
affect performance anyway since the memory controller does internal
swizzling anyway.
For most other configs we'll be able to enable swizzling at boot time,
since the initial framebuffer won't be tiled, thus we won't see any
corruption when we enable it.
v2: preserve swizzling if BIOS had it set (Daniel)
v3: preserve swizzling only if we inherited a tiled framebuffer (Daniel)
check display swizzle setting in detect_bit_6_swizzle (Daniel)
use gen6 as cutoff point (Daniel)
v4: fixup swizzle preserve again, had wrong init order (Daniel)
Reported-by: Kristian Høgsberg <hoegsberg@gmail.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Imre Deak [Wed, 10 Sep 2014 15:16:54 +0000 (18:16 +0300)]
drm/i915: vlv: fix gunit HW state corruption during S4 suspend
During S4 freeze we don't call intel_suspend_complete(), which would
save the gunit HW state, but during S4 thaw/restore events we call
intel_resume_prepare() which restores it, thus ending up in a corrupted
HW state.
Fix this by calling intel_suspend_complete() from the corresponding
freeze_late event handler.
The issue was introduced in
commit
016970beb05da6285c2f3ed2bee1c676cb75972e
Author: Sagar Kamble <sagar.a.kamble@intel.com>
Date: Wed Aug 13 23:07:06 2014 +0530
CC: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Mika Kuoppala [Tue, 7 Oct 2014 14:21:27 +0000 (17:21 +0300)]
drm/i915: Check workaround status on dfs read time
As the workaround list has the value as initialization time
constant, we can do the simple checking on the go without
negleting igt.
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Mika Kuoppala [Tue, 7 Oct 2014 14:21:26 +0000 (17:21 +0300)]
drm/i915: Build workaround list in ring initialization
If we build the workaround list in ring initialization
and decouple it from the actual writing of values, we
gain the ability to decide where and how we want to apply
the values.
The advantage of this will become more clear when
we need to initialize workarounds on older gens where
it is not possible to write all the registers through ring
LRIs.
v2: rebase on newest bdw workarounds
Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
[danvet: Resolve tiny conflict in comments and ocd alignments a bit.]
[danvet2: Remove bogus force_wake_get call spotted by Paulo and QA.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jani Nikula [Tue, 21 Oct 2014 11:40:37 +0000 (14:40 +0300)]
drm/i915: remove redundant #ifdef CONFIG_COMPAT
The whole file is only built with CONFIG_COMPAT=y.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Imre Deak [Wed, 10 Sep 2014 15:16:55 +0000 (18:16 +0300)]
drm/i915: remove dead code from legacy suspend handler
The legacy DRM suspend logic (effective in UMS) doesn't handle any S4 thaw
events so we don't need to care about it either. Only S3 suspend and S4
freeze events are handled. Leave an assert behind to be sure.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ander Conselvan de Oliveira [Mon, 20 Oct 2014 10:46:45 +0000 (13:46 +0300)]
drm/i915: Make intel_pipe_has_type() and some callers take intel_crtc
For consistency, since that's the rule followed for internal functions.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ander Conselvan de Oliveira [Mon, 20 Oct 2014 10:46:44 +0000 (13:46 +0300)]
drm/i915: Make *_crtc_mode_set() take an intel_crtc insted of drm_crtc
For consistency, since that's the rule followed for internal functions.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ander Conselvan de Oliveira [Mon, 20 Oct 2014 10:46:43 +0000 (13:46 +0300)]
drm/i915: Make *_find_best_dpll() take an intel_crtc insted of drm_crtc
For consistency, since that's the rule followed for internal functions.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ander Conselvan de Oliveira [Mon, 20 Oct 2014 10:46:42 +0000 (13:46 +0300)]
drm/i915: Replace some loop through encoders with intel_pipe_has_type()
In the ironlake mode set code, there was two instances of a loop through
encoders to find out if one of them has INTEL_OUTPUT_LVDS type. Simplify
the code by deleting some lines and use intel_pipe_has_type() instead.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Thu, 16 Oct 2014 10:28:18 +0000 (12:28 +0200)]
drm/i915: Document that mmap forwarding is discouraged
Too many new drm driver writers seem to look at i915 for inspiration.
But we have two ways to do mmap, so discourage readers from the old,
ugly version. In a new driver we'd just expose two mmap offsets per
object, one for the gtt map and the other for the cpu map.
v2: Make it clear that i915 does cpu mmaps this way for past
cluelessness^W^W historical reasons. Asked for by Jani.
Cc: "Cheng, Yao" <yao.cheng@intel.com>
Cc: David Herrmann <dh.herrmann@gmail.com>
Reviewed-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Rodrigo Vivi [Thu, 9 Oct 2014 14:11:47 +0000 (07:11 -0700)]
drm/i915/bdw: Remove BDW preproduction W/As until C stepping.
Let's clean this a bit
v2: Rebase after other Mika's patch that removed some BDW production workarounds.
v3: Removed stepping info.
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Chris Wilson [Sun, 24 Aug 2014 18:35:31 +0000 (19:35 +0100)]
drm/i915: Convert a couple more INTEL_INFO-esque macros to be pointer agnostic
Just a couple more macros that assume that they were being passed a
struct drm_device when they want a struct drm_i915_private. Use our
magic macro to ease transitioning over to using drm_i915_privates
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Sonika Jindal [Sat, 4 Oct 2014 09:53:31 +0000 (10:53 +0100)]
drm/i915/skl: Add 180 degree HW rotation support
Add support for 180 degree rotation for primary and sprite planes
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Chris Wilson [Wed, 8 Oct 2014 10:25:17 +0000 (11:25 +0100)]
drm/i915: Suppress no action noise from oom shrinker
If we are not able to free anything (the shrinker leaves nothing on the
global object lists), do not log anything. This is useful when other
subsystems are being stress-tested for their oom behaviour and i915.ko
is shouting into the logs about doing nothing.
Reported-by: Dave Jones <davej@redhat.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Chris Wilson [Wed, 8 Oct 2014 10:25:16 +0000 (11:25 +0100)]
drm/i915: Report the current number of bytes freed during oom
The shrinker reports the number of pages freed, but we try to log the
number of bytes - which leads to some nonsense values being reportedly
freed during oom.
Reported-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 7 Oct 2014 14:41:20 +0000 (17:41 +0300)]
drm/i915: Add missing '\n' to cdclk debug message
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Rodrigo Vivi [Tue, 7 Oct 2014 14:06:50 +0000 (07:06 -0700)]
drm/i915: Do not export RC6p and RC6pp if they don't exist
Avoid to expose RC6 and RC6pp to the platforms that doesn't support it.
So powertop can be changed to show RC6p and RC6pp only on the platforms
they are available.
v2: Simplify by merging RC6p and RC6pp groups and respect the spec that
mentions deep and deepest RC6 on SNB and IVB although they keep disabled
by default.
v3: Remove unecessary space.
v4: RC6p and RC6pp is only for SNB and IVB; unify debug msg and use
has_rc6p() on sanitize options instead of is gen 6 and ivb.
v5: yet another fix on has_rc6p macro. final is_gen6 or is_ivb! To make sure
we are excluding hsw and baytrail.
References: https://bugs.freedesktop.org/show_bug.cgi?id=84524
Cc: Josh Triplett <josh.triplett@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Gustavo Padovan [Wed, 24 Sep 2014 17:20:25 +0000 (14:20 -0300)]
drm/i915: Fix not checking cursor and object sizes
Even if the fb is the same we should still check if the sizes are
valid to be set.
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Gustavo Padovan [Wed, 24 Sep 2014 17:20:24 +0000 (14:20 -0300)]
drm/i915: move check of intel_crtc_cursor_set_obj() out
Move check inside intel_crtc_cursor_set_obj() to
intel_check_cursor_plane(), we only use it there so move them out to
make the merge of intel_crtc_cursor_set_obj() into
intel_check_cursor_plane() easier.
This is another step toward the atomic modesetting support and unification
of plane operations such pin/unpin of fb objects on i915.
v2: take Ville's comment: move crtc_{w,h} assignment a bit down in the
code
v3: take Ville's comment: kept only the restructuring changes, the rest of
the code was moved to a separated patch since it is a bug fix (we weren't
checking sizes when the fb was the same)
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
[danvet: Fixup commit message mixup.]
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Gustavo Padovan [Wed, 24 Sep 2014 17:20:23 +0000 (14:20 -0300)]
drm/i915: remove leftover from pre-universal planes days
Now that universal planes are in place we don't need this plane unref on
failures.
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Gustavo Padovan [Wed, 24 Sep 2014 17:20:22 +0000 (14:20 -0300)]
drm/i915: Merge of visible and !visible paths for primary planes
Fold intel_pipe_set_base() in the update primary plane path merging
pieces of code that are common to both paths.
Basically the the pin/unpin procedures are the same for both paths
and some checks can also be shared (some of the were moved to the
check() stage)
v2: take Ville's comments:
- remove unnecessary plane check
- move mutex lock to inside the conditional
- make the pin fail message a debug one
- add a fixme for the fastboot hack
- call intel_frontbuffer_flip() after FBC update
v3: take more Ville's comments:
- fold update code under if (intel_crtc->active), and do the
visible/!visible split inside.
- check ret inside the same conditional we assign it
v4: don't use intel_enable_primary_hw_plane(), the primary_enabled
check inside will break page flips
v5: take more Ville's comments:
- set primary_enabled to true and add BDW hack
- unify if (old_fb) and if (old_fb != fb)
v6: take more Ville's comments:
- make was_primary bool and fix its check
- add the BDW vblank wait comment
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Wed, 1 Oct 2014 19:04:18 +0000 (20:04 +0100)]
drm/i915: Remove IS_ULT()
As stated in the few previous commits, IS_ULT/ULX() is better
per-platform as it has different consequences depending on the platform.
We now can get rid of it.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Wed, 1 Oct 2014 19:04:17 +0000 (20:04 +0100)]
drm/i915/skl: Don't check for ULT/ULX when detecting the PCH
IS_ULT() wasn't taking into account SKL so we had a warn with SPT-LP.
We don't realy need those checks here, and as we don't need to introduce
IS_SKL_ULT/ULX() at the moment, let's just drop them.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Wed, 1 Oct 2014 19:04:16 +0000 (20:04 +0100)]
drm/i915: Use IS_HSW_ULT() in HSW CDCLK clock read-out
hsw_get_cdclk_freq() is really just HSW, so we can use IS_HSW_ULT()
instead of IS_ULT() there.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Wed, 1 Oct 2014 19:04:15 +0000 (20:04 +0100)]
drm/i915: Spell out IS_HSW/BDW_ULT() in intel_crt_present()
The quality of being a ULT or ULX package doesn't tell anything across
generations and so a global IS_ULT() macro doesn't make much sense, esp.
as we're adding new products.
So, spell out which ULT/ULX SKUs we are talking about here, namely HSW
and BDW.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Wed, 1 Oct 2014 19:04:14 +0000 (20:04 +0100)]
drm/i915: Use IS_HSW_ULT() in HAS_IPS()
HAS_IPS() has a '|| IS_BROADWELL()', no need to check for IS_BDW_ULT().
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Wed, 1 Oct 2014 19:04:13 +0000 (20:04 +0100)]
drm/i915: Use IS_HSW_ULT() in a HSW specific code path
No need to add the BDW pci ULT/ULX checks inside a if (IS_HASWELL(dev))
code path.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 30 Sep 2014 08:56:50 +0000 (10:56 +0200)]
drm/i915: kerneldoc for intel_fifo_underrun.c
v2: Fix spelling fail.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Daniel Vetter [Tue, 30 Sep 2014 08:56:49 +0000 (10:56 +0200)]
drm/i915: Filter gmch fifo underruns in the shared handler
This simplifies the code in the vlv irq handler. Also this now
means that we correctly filter underruns on gen2-4.
And as the real upshot I need to document one less function for
the fifo underrun code.
v2: Shorten one long line.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 30 Sep 2014 08:56:48 +0000 (10:56 +0200)]
drm/i915: Add wrappers to handle fifo underrun interrupts
Way too much copypasta all over. And this also clarifies a bit what's
going on since it separates the "do we have an underrun irq" from the
"should we report the underrun" check.
v2: Fix excessively long lines.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Daniel Vetter [Tue, 30 Sep 2014 08:56:47 +0000 (10:56 +0200)]
drm/i915: Use dev_priv in public intel_fifo_underrun.c functions
It's the new rule!
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 30 Sep 2014 08:56:46 +0000 (10:56 +0200)]
drm/i915: Extract intel_fifo_underrun.c
Prep work for some nice documentation. Requires that we export the
display irq enable/disable functions on ilk/ibx. But we already export
them for vlv/i915. So not more inconsistency.
v2: Rebase on top of skl stage 1.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Daniel Vetter [Wed, 22 Oct 2014 09:18:51 +0000 (11:18 +0200)]
Revert "drm/i915: Enable full PPGTT on gen7"
This reverts commit
8c50f10d73b50139dcfe48bc22f2c8c7822c1983.
It's not yet solid and Dave objected to pulling the tree in its
current state.
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Dave Airlie <airlied@gmail.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
References: http://mid.mail-archive.com/CAPM=9ty2r1MLE=wzC-_vNSUzXVqAyXiGgocpSV9qOp0gzpK3xA@mail.gmail.com
References: http://lists.freedesktop.org/archives/intel-gfx/2014-October/053926.html
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Daniel Vetter [Tue, 21 Oct 2014 12:32:55 +0000 (14:32 +0200)]
Merge branch 'drm-intel-next-fixes' into drm-intel-next
So I've sent the first pull request to Dave and I expect his request
for a merge tree any second now ;-)
More seriously I have some pending patches for 3.19 that depend upon
both trees, hence backmerge. Conflicts are all trivial.
Conflicts:
drivers/gpu/drm/i915/i915_irq.c
drivers/gpu/drm/i915/intel_display.c
v2: Of course I've forgotten the fixup script for the silent conflict.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Jani Nikula [Thu, 2 Oct 2014 08:16:32 +0000 (11:16 +0300)]
drm/i915: fix short vs. long hpd detection
Fix short vs. long hpd detection for non-g4x and non-pch split
platforms.
Broken since introduction in
commit
13cf550448b58abf8f44f5d6a560f2d20871c965
Author: Dave Airlie <airlied@redhat.com>
Date: Wed Jun 18 11:29:35 2014 +1000
drm/i915: rework digital port IRQ handling (v2)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83175
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Ville Syrjälä [Thu, 9 Oct 2014 16:37:15 +0000 (19:37 +0300)]
drm/i915: Don't trust the DP_DETECT bit for eDP ports on CHV
On CHV the display DDC pins may be muxed to an alternate function if
there's no need for DDC on a specific port, which is the case for eDP
ports since there's no way to plug in a DP++ HDMI dongle.
This causes problems when trying to determine if the port is present
since the the DP_DETECTED bit is the latched state of the DDC SDA pin
at boot. If the DDC pins are muxed to an alternate function the bit
may indicate that the port isn't present.
To work around this look at the VBT as well as the DP_DETECTED bit
to determine if we should attempt registering an eDP port. Do this
only for ports B and C since port D doesn't support eDP (no PPS/BLC).
In theory someone could also wire up a normal DP port w/o DDC lines.
That would just mean that simple DP++ HDMI dongles wouldn't work
on such a port. With this change we would still fail to register
such DP ports. But let's hope no one wires their board in such a way,
and if they do we can extend the VBT checks to cover normal DP ports
as well.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84265
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Paulo Zanoni [Tue, 7 Oct 2014 21:02:52 +0000 (18:02 -0300)]
drm/i915: properly reenable gen8 pipe IRQs
We were missing the pipe B/C vblank bits! Take a look at
gen8_de_irq_postinstall for a comparison.
This should fix a bunch of IGT tests.
There are a few more things we could improve on this code, but this
should be the minimal fix to unblock us.
v2: s/extra_iir/extra_ier/ because IIR doesn't make sense (Ville)
Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=83640
Testcase: igt/*
Cc: stable@vger.kernel.org
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
U. Artie Eoff [Mon, 29 Sep 2014 22:49:33 +0000 (15:49 -0700)]
drm/i915: Move DIV_ROUND_CLOSEST_ULL macro to header
Move the duplicated DIV_ROUND_CLOSEST_ULL macro into the intel_drv.h
header file so that it can be shared between intel_display.c
and intel_panel.c.
Signed-off-by: U. Artie Eoff <ullysses.a.eoff@intel.com>
Reviewed-By: Joe Konno <joe.konno@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
U. Artie Eoff [Mon, 29 Sep 2014 22:49:32 +0000 (15:49 -0700)]
drm/i915: intel_backlight scale() math WA
Improper truncated integer division in the scale() function causes
actual_brightness != brightness. This (partial) work-around should be
sufficient for a majority of use-cases, but it is by no means a complete
solution.
TODO: Determine how best to scale "user" values to "hw" values, and
vice-versa, when the ranges are of different sizes. That would be a
buggy scenario even with this work-around.
The issue was introduced in the following (v3.17-rc1) commit:
6dda730 drm/i915: respect the VBT minimum backlight brightness
Note that for easier backporting this commit adds a duplicated macro.
A follow-up cleanup patch rectifies this for 3.18+
v2: (thanks to Chris Wilson) clarify commit message, use rounded division
macro
v3: -DIV_ROUND_CLOSEST() fails to build with CONFIG_X86_32=y. (Jani)
-Use DIV_ROUND_CLOSEST_ULL() instead. (Damien)
-v1 and v2 originally authored by Joe Konno.
Signed-off-by: U. Artie Eoff <ullysses.a.eoff@intel.com>
Cc: stable@vger.kernel.org
Reviewed-By: Joe Konno <joe.konno@intel.com>
[danvet: Add backporting note.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Fri, 3 Oct 2014 15:38:34 +0000 (17:38 +0200)]
drm/i915: Update DRIVER_DATE to
20141003
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Chris Wilson [Fri, 3 Oct 2014 09:29:51 +0000 (10:29 +0100)]
drm/i915: Remove the duplicated logic between the two shrink phases
We can use the same logic to walk the different bound/unbound lists
during shrinker (as the unbound list is a degenerate case of the bound
list), slightly compacting the code.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 30 Sep 2014 08:56:45 +0000 (10:56 +0200)]
drm/i915: kerneldoc for interrupt enable/disable functions
Just start with the basics for now.
Since there's a lot of different functionality in i915_irq.c I've
decided to split it into different sections and pull in just the
relevant functions. Splitting into different files looks like a lot
more work since the interrupt handlers do an awful lot of reuse all
over.
v2: Rebase onto changed function names.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 30 Sep 2014 08:56:44 +0000 (10:56 +0200)]
drm/i915: Use dev_priv instead of dev in irq setup functions
It's the new world order!
Not going full monty on these here and rolling this out throughout the
subsequent call chains since this is just for the kerneldoc. Later on
we can go more crazy, especially once we've embedded drm_device
correctly.
v2: Also frob the runtime_pm functions ...
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 30 Sep 2014 08:56:43 +0000 (10:56 +0200)]
drm/i915: s/pm._irqs_disabled/pm.irqs_enabled/
Double negations just parse harder. Also this allows us to ditch some
init code since clearing to 0 dtrt. Also ditch the assignment in
intel_pm_setup, that's not redundant since we do the assignement now
while setting up interrupts.
While at it do engage in a bit of OCD and wrap up the few lines of
setup/teardown code into little helper functions: intel_irq_fini for
cleanup and intel_irq_init_hw for hw setup.
v2: Use _install/_uninstall for the new wrapper function names as
Paulo suggested.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Mon, 18 Aug 2014 11:42:46 +0000 (14:42 +0300)]
drm/i915: Clear TX FIFO reset master override bits on chv
Clear the override bits to make sure the hardware manages
the TX FIFO reset master on its own.
v2: Squash with the earlier attempt at forcing the override bits
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Mon, 18 Aug 2014 11:42:45 +0000 (14:42 +0300)]
drm/i915: Make sure hardware uses the correct swing margin/deemph bits on chv
The register can house two different swing marging/deemph settings at
once. However only one gets used based on some other bits. Make sure we
set those bits correctly to make the hardware use the settings we
provided.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Rodrigo Vivi [Wed, 1 Oct 2014 14:32:37 +0000 (07:32 -0700)]
drm/i915: make sink_crc return -EIO on aux read/write failure
Even though it's unliky, we should check each aux transaction not just
the first one. Also
commit
ce31d9f4fc05964f6c0dd3a8661dc1a1d843a1e2
Author: Rodrigo Vivi <rodrigo.vivi@intel.com>
Date: Mon Sep 29 18:29:52 2014 -0400
drm/i915: preserve other DP_TEST_SINK bits.
added a new aux transaction before the one which was checked. Fix
this.
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Todd Previte <tprevite@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Thu, 2 Oct 2014 07:45:35 +0000 (09:45 +0200)]
drm/i915: Constify send buffer for intel_dp_aux_ch
Inspired by Ville constifying the send buffer for pach_aux.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Ville Syrjälä [Wed, 1 Oct 2014 13:56:56 +0000 (16:56 +0300)]
drm/i915: De-magic the PSR AUX message
Use pack_aux() to construct the PSR exit DPMS D0 AUX message,
and use the defines from dp_dp_helper.h to populate the message
contents.
v2: Use sizeof() for message size (Jani)
Use a generic loop to write EDP_PSR_AUX_DATA registers
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 30 Sep 2014 23:02:04 +0000 (01:02 +0200)]
drm/i915: Reinstate error level message for non-simulated gpu hangs
This seems to have been accidentally lost in
commit
be62acb4cce1389a28296852737e3917d9cc5b25
Author: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Date: Fri Aug 30 16:19:28 2013 +0300
drm/i915: ban badly behaving contexts
Without this real gpu hangs only log output at info level, which gets
filtered away by piglit's testrunner.
v2: Tune down to notice level. Note that we need to add drm/i915 so
that at least the automatic igt dmesg filtering still picks it up.
v3: git add and lack of coffee don't mix well.
v4: Message is in between hw and sw reset, so switch verb to
continuous form.
v5: Use i915_stop_rings_allow_warn for consistency. For Chris' case of
injecting lots of hangs I guess we need to revamp this all anyway when
merging. For now this should plug the regression for piglit testing
mesa.
v6: Make it compile (Mika).
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reported-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Daniel Vetter [Tue, 30 Sep 2014 08:56:42 +0000 (10:56 +0200)]
drm/i915: Kerneldoc for intel_runtime_pm.c
I've decided not to document the functions exported to the audio
driver since really, they shouldn't exist ...
v2: Improvements from Imre's review plus a few more spelling fixes
I've spotted.
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 30 Sep 2014 08:56:41 +0000 (10:56 +0200)]
drm/i915: Call runtime_pm_disable directly
Allows us to mark it static and so forgoe the kerneldoc for it.
Note that intel_power_domains_fini is also called from failure paths
in the driver load sequence. But the call to runtime_pm_disable for
that is harmless since by default runtime pm is already disabled.
v2: Augment the commit message as discussed with Imre on irc.
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 30 Sep 2014 08:56:40 +0000 (10:56 +0200)]
drm/i915: Move intel_display_set_init_power to intel_runtime_pm.c
I've decided to not move intel_display_port_power_domain because
that's just a hack in our design ...
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 30 Sep 2014 08:56:39 +0000 (10:56 +0200)]
drm/i915: Bikeshed rpm functions name a bit.
- fini goes with init, so call it intel_power_domains_fini. While
at it shovel some of the fini code that leaked out of it back in.
- give power_enabled functions the verb _is_ to make the meaning clearer.
Also use a __ prefix instead of _unlocked to really discourage users.
- rename runtime_pm_init/fini to enable/disable since that's what they do.
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 30 Sep 2014 08:56:38 +0000 (10:56 +0200)]
drm/i915: Extract intel_runtime_pm.c
Geez is the audio hack ugly.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
[danvet: Rebased on top of the skl patches.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 30 Sep 2014 08:56:37 +0000 (10:56 +0200)]
drm/i915: Remove intel_modeset_suspend_hw
Another layer of indirection for just an lpt-only w/a is a bit
excessive. Reduce it.
This was added in
commit
7d708ee40a6b9ca1112a322e554c887df105b025
Author: Imre Deak <imre.deak@intel.com>
Date: Wed Apr 17 14:04:50 2013 +0300
drm/i915: HSW: allow PCH clock gating for suspend
Cc: Imre Deak <imre.deak@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 30 Sep 2014 20:10:53 +0000 (22:10 +0200)]
drm/i915: spelling fixes for frontbuffer tracking kerneldoc
Oh well.
v2: Fix one more spelling fail Paulo spotted.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 30 Sep 2014 20:10:52 +0000 (22:10 +0200)]
drm/i915: Tighting frontbuffer tracking around flips
So I think I've spotted a small gap in the frontbuffer tracking
while discussing the logic with Paulo on irc:
1. Userspace schedules gpu rendering to the current frontbuffer.
This gets tracked in dev_priv->fb_tracking.busy_bits.
2. We pageflip a fully rendered buffer before the frontbuffer
rendering completes.
3. The request retiring will never clear busy_bits (since at retire
time the old frontbuffer won't have obj->frontbuffer_bits set), so
these bits now are stuck until someone again does a bit of frontbuffer
tracking.
If we clear stale busy_bits in flip_prepare this gap is closed.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Clint Taylor [Tue, 30 Sep 2014 17:30:22 +0000 (10:30 -0700)]
drm/i915: Enable pixel replicated modes on BDW and HSW.
Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition to the
DPLL_A_MD register for the pixel clock double, we also need to write
to the TRANS_MULT_n (0x6002c) register to double the pixel data. Writing
to the DPLL only double the pixel clock.
ver2: Macro name change from MULTIPLY to PIPE_MULTI. (Daniel)
ver3: Do not set pixel multiplier if transcoder is eDP (Ville)
ver4: Macro name change to PIPE_MULT and default else pixel_multiplier
Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Appease checkpatch and move one hunk back into the right
place that git am misplace!?]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 30 Sep 2014 20:36:57 +0000 (22:36 +0200)]
Merge branch 'topic/skl-stage1' into drm-intel-next-queued
SKL stage 1 patches still need polish so will likely miss the 3.18
merge window. We've decided to postpone to 3.19 so let's pull this in
to make patch merging and conflict handling easier.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Rodrigo Vivi [Mon, 29 Sep 2014 22:29:52 +0000 (18:29 -0400)]
drm/i915: preserve other DP_TEST_SINK bits.
Sink crc was implemented based on dp 1.1 spec that had all TEST_SINK bits
reserved reading all 0s. But when reviewing my latest changes on sink crc
Todd warned me that on new specs we have other valid bits on this reg that we
might want to preserve.
Cc: Todd Previte <tprevite@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Todd Previte <tprevite@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Rodrigo Vivi [Sat, 20 Sep 2014 00:16:27 +0000 (20:16 -0400)]
drm/i915/bdw: WaDisableFenceDestinationToSLM
This WA affect BDW GT3 pre-production steppings.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
[danvet: Don't mention steppings ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Rodrigo Vivi [Sat, 20 Sep 2014 00:16:26 +0000 (20:16 -0400)]
drm/i915: Add IS_BDW_GT3 macro.
It will be usefull to specify w/a that affects only BDW GT3.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Rodrigo Vivi [Tue, 16 Sep 2014 23:18:12 +0000 (19:18 -0400)]
drm/i915: Fix Sink CRC
In some cases like when PSR just got enabled the panel need more vblank
times to calculate CRC. I figured that out with the new PSR test cases
facing some cases that I had a green screen but a blank CRC. Even with
2 vblank waits on kernel + 2 vblank waits on test case.
So let's give up to 6 vblank wait time. However we now check for
TEST_CRC_COUNT that shows when panel finished to calculate CRC and
has it ready.
v2: Jani pointed out attempts decrements was wrong and should never reach
the error condition. And Daniel pointed out that EIO is more appropriated than
EGAIN. Also I realized that I have to read test_crc_count after setting
test_sink
v3: Rebase and adding error message
Cc: Todd Previte <tprevite@gmail.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Todd Previte <tprevite@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 2 Sep 2014 12:12:17 +0000 (15:12 +0300)]
drm/i915: Don't spam dmesg with rps messages on vlv/chv
If the GPU frequency isn't going to change don't spam dmesg with
debug messages about it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Tvrtko Ursulin [Fri, 26 Sep 2014 14:05:22 +0000 (15:05 +0100)]
drm/i915: Do not leak pages when freeing userptr objects
sg_alloc_table_from_pages() can build us a table with coalesced ranges which
means we need to iterate over pages and not sg table entries when releasing
page references.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: "Barbalho, Rafael" <rafael.barbalho@intel.com>
Tested-by: Rafael Barbalho <rafael.barbalho@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@vger.kernel.org
[danvet: Remove unused local variable sg.]
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Chris Wilson [Fri, 26 Sep 2014 09:31:02 +0000 (10:31 +0100)]
drm/i915: Do not store the error pointer for a failed userptr registration
If we fail to create our mmu notification, we report the error back and
currently store the error inside the i915_mm_struct. This not only causes
subsequent registerations of the same mm to fail (an issue if the first
was interrupted by a signal and needed to be restarted) but also causes
us to eventually try and free the error pointer.
[ 73.419599] BUG: unable to handle kernel NULL pointer dereference at
000000000000004c
[ 73.419831] IP: [<
ffffffff8114af33>] mmu_notifier_unregister+0x23/0x130
[ 73.420065] PGD
8650c067 PUD
870bb067 PMD 0
[ 73.420319] Oops: 0000 [#1] SMP DEBUG_PAGEALLOC
[ 73.420580] CPU: 0 PID: 42 Comm: kworker/0:1 Tainted: G W 3.17.0-rc6+ #1561
[ 73.420837] Hardware name: Intel Corporation SandyBridge Platform/LosLunas CRB, BIOS ASNBCPT1.86C.0075.P00.
1106281639 06/28/2011
[ 73.421405] Workqueue: events __i915_mm_struct_free__worker
[ 73.421724] task:
ffff880088a81220 ti:
ffff880088168000 task.ti:
ffff880088168000
[ 73.422051] RIP: 0010:[<
ffffffff8114af33>] [<
ffffffff8114af33>] mmu_notifier_unregister+0x23/0x130
[ 73.422410] RSP: 0018:
ffff88008816bd50 EFLAGS:
00010286
[ 73.422765] RAX:
0000000000000003 RBX:
ffff880086485400 RCX:
0000000000000000
[ 73.423137] RDX:
ffff88016d80ee90 RSI:
ffff880086485400 RDI:
0000000000000044
[ 73.423513] RBP:
ffff88008816bd70 R08:
0000000000000001 R09:
0000000000000000
[ 73.423895] R10:
0000000000000320 R11:
0000000000000001 R12:
0000000000000044
[ 73.424282] R13:
ffff880166e5f008 R14:
ffff88016d815200 R15:
ffff880166e5f040
[ 73.424682] FS:
0000000000000000(0000) GS:
ffff88016d800000(0000) knlGS:
0000000000000000
[ 73.425099] CS: 0010 DS: 0000 ES: 0000 CR0:
0000000080050033
[ 73.425537] CR2:
000000000000004c CR3:
0000000087f5f000 CR4:
00000000000407f0
[ 73.426157] Stack:
[ 73.426597]
ffff880088a81248 ffff880166e5f038 fffffffffffffffc ffff880166e5f008
[ 73.427096]
ffff88008816bd98 ffffffff814a75f2 ffff880166e5f038 ffff8800880f8a28
[ 73.427603]
ffff88016d812ac0 ffff88008816be00 ffffffff8106321a ffffffff810631af
[ 73.428119] Call Trace:
[ 73.428606] [<
ffffffff814a75f2>] __i915_mm_struct_free__worker+0x42/0x80
[ 73.429116] [<
ffffffff8106321a>] process_one_work+0x1ba/0x610
[ 73.429632] [<
ffffffff810631af>] ? process_one_work+0x14f/0x610
[ 73.430153] [<
ffffffff810636db>] worker_thread+0x6b/0x4a0
[ 73.430671] [<
ffffffff8108d67d>] ? trace_hardirqs_on+0xd/0x10
[ 73.431501] [<
ffffffff81063670>] ? process_one_work+0x610/0x610
[ 73.432030] [<
ffffffff8106a206>] kthread+0xf6/0x110
[ 73.432561] [<
ffffffff8106a110>] ? __kthread_parkme+0x80/0x80
[ 73.433100] [<
ffffffff8169c22c>] ret_from_fork+0x7c/0xb0
[ 73.433644] [<
ffffffff8106a110>] ? __kthread_parkme+0x80/0x80
[ 73.434194] Code: 0f 1f 84 00 00 00 00 00 66 66 66 66 90 8b 46 4c 85 c0 0f 8e 10 01 00 00 55 48 89 e5 41 55 41 54 53 48 89 f3 49 89 fc 48 83 ec 08 <48> 83 7f 08 00 0f 84 b1 00 00 00 48 c7 c7 40 e6 ac 82 e8 26 65
[ 73.435942] RIP [<
ffffffff8114af33>] mmu_notifier_unregister+0x23/0x130
[ 73.437017] RSP <
ffff88008816bd50>
[ 73.437704] CR2:
000000000000004c
Fixes regression from commit
ad46cb533d586fdb256855437af876617c6cf609
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Thu Aug 7 14:20:40 2014 +0100
drm/i915: Prevent recursive deadlock on releasing a busy userptr
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84207
Testcase: igt/gem_render_copy_redux
Testcase: igt/gem_userptr_blits/create-destroy-sync
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jacek Danecki <jacek.danecki@intel.com>
Cc: "Gong, Zhipeng" <zhipeng.gong@intel.com>
Cc: Jacek Danecki <jacek.danecki@intel.com>
Cc: "Ursulin, Tvrtko" <tvrtko.ursulin@intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Daniel Vetter [Mon, 29 Sep 2014 13:07:19 +0000 (15:07 +0200)]
Revert "drm/i915/bdw: BDW Software Turbo"
This reverts commit
c76bb61a71083b2d90504cc6d0dda2047c5d63ca.
It's apparently too broken so that Rodrigo submitted a patch to add a
config option for it. Given that the design is also ... suboptimal and
that I've only merged this to get lead engineers and managers off my
back for one second let's just revert this.
/me puts on combat gear again
It was worth a shot ...
References: http://mid.mail-archive.com/
1411686380-1953-1-git-send-email-rodrigo.vivi@intel.com
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Daisy Sun <daisy.sun@intel.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Rodrigo Vivi [Thu, 25 Sep 2014 16:28:32 +0000 (12:28 -0400)]
drm/i915: Broadwell DDI Buffer translation - more tuning
BDW display - DP buffer translation values changed to give better margin.
Further change to entry 6; set dword 0 bit 31=1.
Both changes were approved already but this one didn't landed BSpec yet
this is why it is in a separated patch. Making reviewer's life easier.
Also alowing separated tests and any future bisect that might be needed.
Reference: Predator r74080 / HSD
4394389
v2: Arthur noticed I was changing the wrong bit.
Cc: Arthur Runyan <arthur.j.runyan@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Arthur Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Rodrigo Vivi [Thu, 25 Sep 2014 00:32:43 +0000 (20:32 -0400)]
drm/i915: Broadwell DDI Buffer translation changed to give better margin.
Reference: Predator r73977 / HSD
4394389
Cc: Arthur Runyan <arthur.j.runyan@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Arthur Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Rodrigo Vivi [Wed, 24 Sep 2014 22:16:58 +0000 (18:16 -0400)]
drm/i915: Make sure PSR is ready for been re-enabled.
Let's make sure PSR is propperly disabled before to re-enabled it.
According to Spec, after disabled PSR CTL, the Idle state might occur
up to 24ms, that is one full frame time (1/refresh rate),
plus SRD exit training time (max of 6ms),
plus SRD aux channel handshake (max of 1.5ms).
So if something went wrong PSR will be disabled until next full
enable/disable setup.
v2: The 24ms above takes in account 16ms for refresh rate on 60Hz mode. However
on low frequency modes this can take longer. So let's use 50ms for safeness.
v3: Move wait out of psr.lock critical area.
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Rodrigo Vivi [Wed, 24 Sep 2014 23:50:59 +0000 (19:50 -0400)]
drm/i915: Minimize the huge amount of unecessary fbc sw cache clean.
The sw cache clean on BDW is a tempoorary workaround because we cannot
set cache clean on blt ring with risk of hungs. So we are doing the cache clean on sw.
However we are doing much more than needed. Not only when using blt ring.
So, with this extra w/a we minimize the ammount of cache cleans and call it only
on same cases that it was being called on gen7.
The traditional FBC Cache clean happens over LRI on BLT ring when there is a
frontbuffer touch happening. frontbuffer tracking set fbc_dirty variable
to let BLT flush that it must clean FBC cache.
fbc.need_sw_cache_clean works in the opposite information direction
of ring->fbc_dirty telling software on frontbuffer tracking to perform
the cache clean on sw side.
v2: Clean it a little bit and fully check for Broadwell instead of gen8.
v3: Rebase after frontbuffer organization.
v4: Wiggle confused me. So fixing v3!
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Rodrigo Vivi [Tue, 16 Sep 2014 23:19:07 +0000 (19:19 -0400)]
drm/i915: Avoid re-configure panel on every PSR re-enable.
The panel has to be reconfigured only when it really loose the power.
The traditional enable/disable sequence already take care of this so we can
minimize the time spend on every re-enable.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Thu, 27 Mar 2014 18:48:35 +0000 (00:18 +0530)]
drm/i915/skl: Move gen9 pm initialization into its own branch
Gen9 is different enough (for instance, fetching the memory latency
values is different from ILK+) to not take the HAS_PCH_SPLIT() branch,
so let's prefer a clean separation.
v2: Rebase on top of the broadwell_init_clock_gating() name change
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Thu, 27 Mar 2014 18:48:33 +0000 (00:18 +0530)]
drm/i915/skl: Introduce intel_num_planes()
It can be handy to get the number of planes for this pipe, ie including
the primary plane to loop over them. Introduce a little function to do
so.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Thu, 27 Mar 2014 18:48:32 +0000 (00:18 +0530)]
drm/i915/skl: Introduce a I915_MAX_PLANES macro
This can be useful to declare structures around pipes and planes and
don't have to go back auditing the code if the next platorm bump that
number.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Wed, 12 Mar 2014 21:05:38 +0000 (21:05 +0000)]
drm/i915/skl: Adjust assert_sprites_disabled()
Let's put to good use the new PLANE_CTL macros.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Wed, 4 Dec 2013 00:49:41 +0000 (00:49 +0000)]
drm/i915/skl: Implement drm_plane vfuncs
SKL Uses the same hardware for all planes now, so called "universal"
planes. Ie both the primary planes and sprite planes share the same
logic. This patch implements the drm_plane vfuncs for "sprites" ie
planes that aren't the primary plane.
v2: Couple of fixes:
- Actually enabled the planes and fix the plane number
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Wed, 12 Feb 2014 19:13:31 +0000 (19:13 +0000)]
drm/i915/skl: Skylake has 2 "sprite" planes per pipe
On Skylake, we use plane1 as primary plane and plane2/3 as sprite
planes.
v2: Rebase on top of the for_each_pipe() change adding dev_priv as first
argument.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Wed, 26 Mar 2014 18:18:01 +0000 (18:18 +0000)]
drm/i915/skl: Implement WaDisableDgMirrorFixInHalfSliceChicken5:skl
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Wed, 26 Mar 2014 17:42:50 +0000 (17:42 +0000)]
drm/i915/skl: Implement Wa4x4STCOptimizationDisable:skl
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Wed, 26 Mar 2014 16:55:46 +0000 (16:55 +0000)]
drm/i915/skl: Implement WaDisableSDEUnitClockGating:skl
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Satheeshakrishna M [Wed, 9 Apr 2014 05:38:57 +0000 (11:08 +0530)]
drm/i915/skl: Sunrise Point PCH detection
This patch implements detection of SPT and SPT-LP PCH devices.
v2: Added HAS_PCH_SPT macro
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Thu, 20 Mar 2014 20:45:01 +0000 (20:45 +0000)]
drm/i915/skl: Adjust the display engine interrupts
To accomodate the extra planes, the bit definitions were shuffled around
a bit.
v2: Rebase on top of the for_each_pipe() change adding dev_priv as first
argument.
v3: Rebase after yet another change int that area (done with wiggle)
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Satheeshakrishna M [Tue, 8 Apr 2014 10:16:56 +0000 (15:46 +0530)]
drm/i915/skl: Restore pipe B/C interrupts
Extending BDW implementation to gen9. Pipe B/C interrupt
restoration after exiting LPSP.
v2: Fix minor rebasing conflict.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Satheeshakrishna M [Tue, 8 Apr 2014 10:16:55 +0000 (15:46 +0530)]
drm/i915/skl: SKL backlight enabling
Extending the BDW backlight implementation to SKL.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Satheeshakrishna M [Tue, 8 Apr 2014 10:16:54 +0000 (15:46 +0530)]
drm/i915/skl: vfuncs for skl eld and global resource
Set gen 9 function pointers for eld write and global resource.
Implementation remains same as HSW.
v2: Rebase on top of Sonika's untangling of the if/else ladder (Damien)
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>