OSDN Git Service
Guozhi Wei [Thu, 14 Dec 2017 19:35:43 +0000 (19:35 +0000)]
[SLPVectorizer] Don't ignore scalar extraction instructions of aggregate value
In SLPVectorizer, the vector build instructions (insertvalue for aggregate type) is passed to BoUpSLP.buildTree, it is treated as UserIgnoreList, so later in cost estimation, the cost of these instructions are not counted.
For aggregate value, later usage are more likely to be done in scalar registers, either used as individual scalars or used as a whole for function call or return value. Ignore scalar extraction instructions may cause too aggressive vectorization for aggregate values, and slow down performance. So for vectorization of aggregate value, the scalar extraction instructions are required in cost estimation.
Differential Revision: https://reviews.llvm.org/D41139
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320736
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Thu, 14 Dec 2017 19:11:28 +0000 (19:11 +0000)]
Only use is_trivially_copyable if we know it's safe to do so.
Apparently this isn't present on older versions of libstdc++, so
it causes some builds to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320733
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Thu, 14 Dec 2017 19:05:21 +0000 (19:05 +0000)]
Add MVT::v128i1, NFC
Hexagon HVX has type v128i8, comparing two vectors of that type will
produce v128i1 types in SelectionDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320732
91177308-0d34-0410-b5e6-
96231b3b80d8
Adam Nemet [Thu, 14 Dec 2017 18:55:33 +0000 (18:55 +0000)]
[opt-viewer] Render utf-8 characters properly in the generated HTML
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320729
91177308-0d34-0410-b5e6-
96231b3b80d8
Paul Robinson [Thu, 14 Dec 2017 18:46:43 +0000 (18:46 +0000)]
[MC] Allow .file directives to be out-of-order
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320727
91177308-0d34-0410-b5e6-
96231b3b80d8
Adam Nemet [Thu, 14 Dec 2017 18:42:42 +0000 (18:42 +0000)]
[opt-viewer] Support unicode characters in function names
This is a Swift feature. The output stream for the index page and the source
HTML page is utf-8 now.
The next patch will add the HTML magic to properly render these characters in
the browser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320725
91177308-0d34-0410-b5e6-
96231b3b80d8
Shoaib Meenai [Thu, 14 Dec 2017 18:41:49 +0000 (18:41 +0000)]
[cmake] Only attempt to install MSVC system libraries on Windows
Newer versions of CMake (I'm on 3.10, but I believe 3.9 behaves the same
way) attempt to query the system for information about the VS 2017
install. Unfortunately, this query fails on non-Windows systems:
cmake_host_system_information does not recognize <key> VS_15_DIR
CMake isn't going to find these system libraries on non-Windows anyway
(and we were previously silencing the resultant warnings in our
cross-compilation toolchain), so it makes sense to just omit the
attempted installation entirely on non-Windows.
Differential Revision: https://reviews.llvm.org/D41220
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320724
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 14 Dec 2017 18:35:25 +0000 (18:35 +0000)]
[X86] Don't zero the upper bits of the k-register before extracting a single bit from a vXi1.
This doesn't match the semantics of the extract_vector_elt operation. Nothing downstream knows the bits were zeroed so they still get masked or sign extended after the extrat anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320723
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Thu, 14 Dec 2017 18:35:24 +0000 (18:35 +0000)]
[Hexagon] Remove vectors of i64 from valid HVX types
HVX does not support operations on 64-bit integers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320722
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Thu, 14 Dec 2017 18:20:23 +0000 (18:20 +0000)]
Fix error due to missing includes.
While I'm pushing cleanup changes, this also fixes a few warnings
related to extraneous semicolons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320720
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Thu, 14 Dec 2017 18:07:04 +0000 (18:07 +0000)]
[COFF] Teach LLD to use the COFF .debug$H section.
This adds the /DEBUG:GHASH option to LLD which will look for
the existence of .debug$H sections in linker inputs and use them
to accelerate type merging. The clang-cl side has already been
added, so this completes the work necessary to begin experimenting
with this feature.
Differential Revision: https://reviews.llvm.org/D40980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320719
91177308-0d34-0410-b5e6-
96231b3b80d8
Geoff Berry [Thu, 14 Dec 2017 18:06:25 +0000 (18:06 +0000)]
[ARM] Fix isRenamable flag setting on expanded VSTMDIA opcode.
Fixes expensive-check ARM buildbot failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320718
91177308-0d34-0410-b5e6-
96231b3b80d8
Gadi Haber [Thu, 14 Dec 2017 16:46:47 +0000 (16:46 +0000)]
[X86][AVX][AVX2]: Adding full coverage of MC encoding for the AVX, AVX2 isa set.<NFC>
NFC.
Adding MC regressions tests to cover the AVX and AVX2 ISA sets.
This patch is part of a larger task to cover MC encoding of all X86 ISA Sets.
See revision: https://reviews.llvm.org/D39952
Reviewers: zvi, RKSimon, aymanmus, m_zuckerman
Differential Revison: https://reviews.llvm.org/D40287
Change-Id: I304687a2b7abb473f79de99c31fc55c97b2662da
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320716
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Dardis [Thu, 14 Dec 2017 16:42:04 +0000 (16:42 +0000)]
[mips] Update some tests before posting a patch, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320715
91177308-0d34-0410-b5e6-
96231b3b80d8
Yaxun Liu [Thu, 14 Dec 2017 16:12:04 +0000 (16:12 +0000)]
Revert CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value
This commit might have caused regression on ppc64. Revert it to verify that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320712
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Thu, 14 Dec 2017 16:09:48 +0000 (16:09 +0000)]
Re-commit: [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand.
Summary:
The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand.
This is because the code will only update the diagnostic if it is more
specific than the previous diagnostic. However, when having validated
operands and 'moved on' to a next operand (for some instruction/alias for
which all previous operands are valid), if the diagnostic is InvalidOperand,
than that should be set as the diagnostic, not the more specific message
about a previous operand for some other instruction/alias candidate.
(Re-committed with an extra whitespace in SVEInstrFormats.td to trigger rebuild
of AArch64GenAsmMatcher.inc, since the llvm-clang-x86_64-expensive-checks-win
builder does not seem to rebuild AArch64GenAsmMatcher.inc with the
newly built TableGen due to a missing dependency somewhere (see:
http://lists.llvm.org/pipermail/llvm-dev/2017-December/119555.html))
Reviewers: craig.topper, olista01, rengolin, stoklund
Reviewed By: olista01
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D40011
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320711
91177308-0d34-0410-b5e6-
96231b3b80d8
Eugene Leviant [Thu, 14 Dec 2017 15:59:05 +0000 (15:59 +0000)]
[LLVMgold] Use platform dependent extension in tests
Differential revision: https://reviews.llvm.org/D41238
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320710
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Dardis [Thu, 14 Dec 2017 14:55:25 +0000 (14:55 +0000)]
[mips] Add partial support for R6 in the long branch pass
MIPSR6 introduced several new jump instructions and deprecated
the use of the 'j' instruction. For microMIPS32R6, 'j' was removed
entirely and it only has non delay slot jumps.
This patch adds support for MIPSR6 by using some R6 instructions--
'bc' instead of 'j', 'jic $reg, 0' instead of 'jalr $zero, $reg'--
and modifies the sequences not to use delay slots for R6.
Reviewers: atanasyan
Reviewed By: atanasyan
Subscribers: dschuff, arichardson, llvm-commits
Differential Revision: https://reviews.llvm.org/D40786
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320703
91177308-0d34-0410-b5e6-
96231b3b80d8
Bjorn Pettersson [Thu, 14 Dec 2017 14:47:52 +0000 (14:47 +0000)]
[ScalarEvolution] Fix base condition in isNormalAddRecPHI.
Summary:
The function is meant to recurse until it comes upon the
phi it's looking for. However, with the current condition,
it will recurse until it finds anything _but_ the phi.
The function will even fail for simple cases like:
%i = phi i32 [ %inc, %loop ], ...
...
%inc = add i32 %i, 1
because the base condition will not happen when the phi
is recursed to, and the recursion will end with a 'false'
result since the previous instruction is a phi.
Reviewers: sanjoy, atrick
Reviewed By: sanjoy
Subscribers: Ka-Ka, bjope, llvm-commits
Committing on behalf of: Bevin Hansson (bevinh)
Differential Revision: https://reviews.llvm.org/D40946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320700
91177308-0d34-0410-b5e6-
96231b3b80d8
Haicheng Wu [Thu, 14 Dec 2017 14:36:18 +0000 (14:36 +0000)]
[InlineCost] Tracking Values through PHI Nodes
This patch fix this FIXME in visitPHI()
FIXME: We should potentially be tracking values through phi nodes,
especially when they collapse to a single value due to deleted CFG edges
during inlining.
Differential Revision: https://reviews.llvm.org/D38594
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320699
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Thu, 14 Dec 2017 14:03:07 +0000 (14:03 +0000)]
Revert "[DAGCombine] Move AND nodes to multiple load leaves"
This reverts commit r320679. Causes miscompiles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320698
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrew V. Tischenko [Thu, 14 Dec 2017 12:07:11 +0000 (12:07 +0000)]
Any Target Asm comments should start from MachineInstr::TAsmComments value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320693
91177308-0d34-0410-b5e6-
96231b3b80d8
Omer Paparo Bivas [Thu, 14 Dec 2017 12:00:04 +0000 (12:00 +0000)]
Inserting several lit tests to reflect current behaviour
Change-Id: I1b8188dc3c6c7c0f455715364ece7d35ef485f2f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320692
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zuckerman [Thu, 14 Dec 2017 11:55:50 +0000 (11:55 +0000)]
[AVX512] Adding support for load truncate store of I1
store operation on a truncated memory (load) of vXi1 is poorly supported by LLVM and most of the time end with an assertion.
This patch fixes this issue.
Differential Revision: https://reviews.llvm.org/D39547
Change-Id: Ida5523dd09c1ad384acc0a27e9e59273d28cbdc9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320691
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 14 Dec 2017 11:40:54 +0000 (11:40 +0000)]
[X86] Add FMA4 schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320690
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 14 Dec 2017 11:30:01 +0000 (11:30 +0000)]
[X86] Add FMA3 schedule tests
Rewrote to use inline asm for full coverage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320689
91177308-0d34-0410-b5e6-
96231b3b80d8
Fedor Sergeev [Thu, 14 Dec 2017 10:36:31 +0000 (10:36 +0000)]
[PM][InstCombine] fixing omission of AliasAnalysis in new-pass-manager's version of InstCombine
Summary:
Passing AliasAnalysis results instead of nullptr appears to work just fine.
A couple new-pass-manager tests updated to align with new order of analyses.
Reviewers: chandlerc, spatel, craig.topper
Reviewed By: chandlerc
Subscribers: mehdi_amini, eraman, llvm-commits
Differential Revision: https://reviews.llvm.org/D41203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320687
91177308-0d34-0410-b5e6-
96231b3b80d8
Fedor Sergeev [Thu, 14 Dec 2017 10:36:20 +0000 (10:36 +0000)]
Remove redundant includes from lib/Target/AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320686
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Thu, 14 Dec 2017 10:03:23 +0000 (10:03 +0000)]
[CodeGen] Print MCSymbol operands as <mcsymbol sym> in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`<mcsymbol sym>` instead of `<MCSym=sym>`.
Only debug syntax is affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320685
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Thu, 14 Dec 2017 10:03:18 +0000 (10:03 +0000)]
[CodeGen] Move printing MO_Metadata operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320684
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Thu, 14 Dec 2017 10:03:14 +0000 (10:03 +0000)]
[CodeGen] Print live-out register lists as liveout(...) in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`liveout(...)` instead of `<regliveout>`.
Only debug syntax is affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320683
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Thu, 14 Dec 2017 10:03:09 +0000 (10:03 +0000)]
[CodeGen] Print global addresses as @foo in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`@foo` instead of `<ga:@foo>`.
Also print target flags in the MIR format since most of them are used on
global address operands.
Only debug syntax is affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320682
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Thu, 14 Dec 2017 10:02:58 +0000 (10:02 +0000)]
[CodeGen] Print external symbols as $symbol in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`$symbol` instead of `<es:symbol>`.
Only debug syntax is affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320681
91177308-0d34-0410-b5e6-
96231b3b80d8
Igor Laevsky [Thu, 14 Dec 2017 09:33:58 +0000 (09:33 +0000)]
[Verifier] Check that GEP indexes has correct types
Differential Revision: https://reviews.llvm.org/D40391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320680
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Parker [Thu, 14 Dec 2017 09:31:01 +0000 (09:31 +0000)]
[DAGCombine] Move AND nodes to multiple load leaves
Recommitting rL319773, which was reverted due to a recursive issue
causing timeouts. This happened because I failed to check whether
the discovered loads could be narrowed further. In the case of a tree
with one or more narrow loads, that could not be further narrowed, as
well as a node that would need masking, an AND could be introduced
which could then be visited and recombined again with the same load.
This could again create the masking load, with would be combined
again... We now check that the load can be narrowed so that this
process stops.
Original commit message:
Search from AND nodes to find whether they can be propagated back to
loads, so that the AND and load can be combined into a narrow load.
We search through OR, XOR and other AND nodes and all bar one of the
leaves are required to be loads or constants. The exception node then
needs to be masked off meaning that the 'and' isn't removed, but the
loads(s) are narrowed still.
Differential Revision: https://reviews.llvm.org/D41177
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320679
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 14 Dec 2017 08:26:00 +0000 (08:26 +0000)]
[X86] Make ANY_EXTEND from vXi1 Custom for more types.
We should be able to support ANY_EXTEND for any types we support ZERO_EXTEND for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320675
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 14 Dec 2017 08:25:58 +0000 (08:25 +0000)]
[SelectionDAG][X86] Improve legalization of v32i1 CONCAT_VECTORS of v16i1 for AVX512F.
A v32i1 CONCAT_VECTORS of v16i1 uses promotion to v32i8 to legalize the v32i1. This results in a bunch of extract_vector_elts and a build_vector that ultimately gets scalarized.
This patch checks to see if v16i8 is legal and inserts a any_extend to that so that we can concat v16i8 to v32i8 and avoid creating the extracts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320674
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 14 Dec 2017 08:25:53 +0000 (08:25 +0000)]
[X86] Remove redundant setOperationAction calls.
These calls already exist earlier under AVX2 feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320673
91177308-0d34-0410-b5e6-
96231b3b80d8
Dorit Nuzman [Thu, 14 Dec 2017 07:56:31 +0000 (07:56 +0000)]
[LV] Support efficient vectorization of an induction with redundant casts
D30041 extended SCEVPredicateRewriter to improve handling of Phi nodes whose
update chain involves casts; PSCEV can now build an AddRecurrence for some
forms of such phi nodes, under the proper runtime overflow test. This means
that we can identify such phi nodes as an induction, and the loop-vectorizer
can now vectorize such inductions, however inefficiently. The vectorizer
doesn't know that it can ignore the casts, and so it vectorizes them.
This patch records the casts in the InductionDescriptor, so that they could
be marked to be ignored for cost calculation (we use VecValuesToIgnore for
that) and ignored for vectorization/widening/scalarization (i.e. treated as
TriviallyDead).
In addition to marking all these casts to be ignored, we also need to make
sure that each cast is mapped to the right vector value in the vector loop body
(be it a widened, vectorized, or scalarized induction). So whenever an
induction phi is mapped to a vector value (during vectorization/widening/
scalarization), we also map the respective cast instruction (if exists) to that
vector value. (If the phi-update sequence of an induction involves more than one
cast, then the above mapping to vector value is relevant only for the last cast
of the sequence as we allow only the "last cast" to be used outside the
induction update chain itself).
This is the last step in addressing PR30654.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320672
91177308-0d34-0410-b5e6-
96231b3b80d8
Gadi Haber [Thu, 14 Dec 2017 07:26:08 +0000 (07:26 +0000)]
[X86][AES]: Adding full coverage of MC encoding for the AES and AVXAES isa sets.<NFC>
NFC.
Adding MC regressions tests to cover the AES and AVXAES ISA sets both 32 and 64 bit.
This patch is part of a larger task to cover MC encoding of all X86 ISA Sets.
started in revision: https://reviews.llvm.org/D39952
Reviewers: zvi, craig.topper, m_zuckerman, RKSimon
Differential Revision: https://reviews.llvm.org/D41154
Change-Id: I2564f9797628d0c070c4766f837f399337fb87d2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320670
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 14 Dec 2017 06:49:07 +0000 (06:49 +0000)]
[SelectionDAG] When legalizing the result type of CONCAT_VECTORS, take into account whether the input type also needs to be promoted.
If so go ahead and get the promoted input vector to extract from. Previously, we would create a bunch of any_extends of extract_vector_elts with illegal input type that needs to be promoted. The legalization of those extract_vector_elts would then potentially introduce a truncate. So now we have a bunch of any_extends of truncates. By legalizing both parts together we avoid creating these extra nodes.
The test changes seem to be because we were previously combining the build_vector with the any_extend before the any_extend got combined with the truncate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320669
91177308-0d34-0410-b5e6-
96231b3b80d8
Matthias Braun [Thu, 14 Dec 2017 03:59:24 +0000 (03:59 +0000)]
MC/AsmPrinter: Reduce code duplication.
Factor out duplicated code emitting mach-o version-min specifiers.
This should be NFC but happens to fix a bug where the code in
MCMachoStreamer didn't take the version skew between darwin and macos
versions into account.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320666
91177308-0d34-0410-b5e6-
96231b3b80d8
Matthias Braun [Thu, 14 Dec 2017 00:12:46 +0000 (00:12 +0000)]
MC: Add support for mach-o build_version
LC_BUILD_VERSION is a new load command superseding the previously used
LC_XXX_MIN_VERSION commands. This adds an assembler directive along with
encoding/streaming support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320661
91177308-0d34-0410-b5e6-
96231b3b80d8
Petr Hosek [Wed, 13 Dec 2017 23:49:51 +0000 (23:49 +0000)]
[CMake] Pass LLVM_HAVE_LINK_VERSION_SCRIPT to external projects
Some external projects depend on this LLVM CMake variable.
Differential Revision: https://reviews.llvm.org/D41205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320658
91177308-0d34-0410-b5e6-
96231b3b80d8
Shoaib Meenai [Wed, 13 Dec 2017 23:38:12 +0000 (23:38 +0000)]
[cmake] Add support for case-sensitive Windows SDKs
When the Windows SDK is hosted on a case-sensitive filesystem (e.g. when
compiling on Linux and not using ciopfs), we can automatically generate
a VFS overlay for headers and symlinks for libraries.
Differential Revision: https://reviews.llvm.org/D41156
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320657
91177308-0d34-0410-b5e6-
96231b3b80d8
Shoaib Meenai [Wed, 13 Dec 2017 23:12:38 +0000 (23:12 +0000)]
[cmake] Support host architectures other than x64
Allow building for other architectures when cross-compiling for Windows.
Differential Revision: https://reviews.llvm.org/D41158
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320656
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 13 Dec 2017 23:11:30 +0000 (23:11 +0000)]
Recommit r320461 "[X86] Use regular expressions more aggressively to reduce the number of scheduler entries needed for FMA3 instructions."
I've hopefully sidestepped the MSVC issue that caused it to be reverted. We no longer include the Sched enum from X86GenInstrInfo.inc on the X86 target. So hopefully MSVC's preprocessor will skip over it and nothing will notice the 11000 character enum name.
Original commit message:
When the scheduler tables are generated by tablegen, the instructions are divided up into groups based on their default scheduling information and how they are referenced by groups for each processor. For any set of instructions that are matched by a specific InstRW line, that group of instructions is guaranteed to not be in a group with any other instructions. So in general, the more InstRW class definitions are created, the more groups we end up with in the generated files. Particularly if a lot of the InstRW lines only match to single instructions, which is true of a large number of the Intel scheduler models.
This change alone reduces the number of instructions groups from ~6000 to ~5500. And there's lots more we could do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320655
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 13 Dec 2017 22:57:35 +0000 (22:57 +0000)]
[EarlyCSE] recognize swapped variants of abs/nabs as equivalent
Extends https://reviews.llvm.org/rL320640
Differential Revision: https://reviews.llvm.org/D41136
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320653
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 22:43:55 +0000 (22:43 +0000)]
[X86] Add missing MULX32 schedule test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320651
91177308-0d34-0410-b5e6-
96231b3b80d8
Yaxun Liu [Wed, 13 Dec 2017 22:38:09 +0000 (22:38 +0000)]
CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value
Two issues were found about machine inst scheduler when compiling ProRender
with -g for amdgcn target:
GCNScheduleDAGMILive::schedule tries to update LiveIntervals for DBG_VALUE, which it
should not since DBG_VALUE is not mapped in LiveIntervals.
when DBG_VALUE is the last instruction of MBB, ScheduleDAGInstrs::buildSchedGraph and
ScheduleDAGMILive::scheduleMI does not move RPTracker properly, which causes assertion.
This patch fixes that.
Differential Revision: https://reviews.llvm.org/D41132
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320650
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Wed, 13 Dec 2017 22:33:58 +0000 (22:33 +0000)]
[CodeView] Teach clang to emit the .debug$H COFF section.
Currently this is an LLVM extension to the COFF spec which is
experimental and intended to speed up linking. For now it is
behind a hidden cl::opt flag, but in the future we can move it
to a "real" cc1 flag and have the driver pass it through whenever
it is appropriate.
The patch to actually make use of this section in lld will come
in a followup.
Differential Revision: https://reviews.llvm.org/D40917
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320649
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 22:21:02 +0000 (22:21 +0000)]
Recover some overzealously removed includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320648
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 13 Dec 2017 22:19:40 +0000 (22:19 +0000)]
[EarlyCSE] add tests for swapped abs/nabs; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320647
91177308-0d34-0410-b5e6-
96231b3b80d8
Hans Wennborg [Wed, 13 Dec 2017 22:12:58 +0000 (22:12 +0000)]
Speculative build fix for llvm-pdbdump on Linux after Michael's #include removals
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320646
91177308-0d34-0410-b5e6-
96231b3b80d8
Hans Wennborg [Wed, 13 Dec 2017 22:12:57 +0000 (22:12 +0000)]
Speculative build fix for lld on Linux after Michael's #include removals
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320645
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 22:09:09 +0000 (22:09 +0000)]
[X86] Add CLWB schedule test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320644
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Clegg [Wed, 13 Dec 2017 22:02:25 +0000 (22:02 +0000)]
[WebAssembly] Use bitfield types in wasm YAML representation
Differential Revision: https://reviews.llvm.org/D41202
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320642
91177308-0d34-0410-b5e6-
96231b3b80d8
Brian M. Rzycki [Wed, 13 Dec 2017 22:01:17 +0000 (22:01 +0000)]
Reverting [JumpThreading] Preservation of DT and LVI across the pass
Stage 2 bootstrap failed:
http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules-2/builds/14434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320641
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 13 Dec 2017 21:58:15 +0000 (21:58 +0000)]
[EarlyCSE] recognize commuted and swapped variants of min/max as equivalent (PR35642)
As shown in:
https://bugs.llvm.org/show_bug.cgi?id=35642
...we can have different forms of min/max, so we should recognize those here in EarlyCSE
similar to how we already handle binops and compares that can commute.
Differential Revision: https://reviews.llvm.org/D41136
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320640
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Clegg [Wed, 13 Dec 2017 21:53:40 +0000 (21:53 +0000)]
[WebAssembly] Add linking metatdata test coverage for wasm2yaml
Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish
Differential Revision: https://reviews.llvm.org/D41196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320639
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 21:49:09 +0000 (21:49 +0000)]
[X86] Move ADX schedule tests out of schedule-x86_64.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320637
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:31:19 +0000 (21:31 +0000)]
Remove redundant includes from lib/Target/X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320636
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:31:17 +0000 (21:31 +0000)]
Remove redundant includes from lib/Target/ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320635
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:31:16 +0000 (21:31 +0000)]
Remove redundant includes from lib/Target/AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320634
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:31:14 +0000 (21:31 +0000)]
Remove redundant includes from lib/Target/*.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320633
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:31:13 +0000 (21:31 +0000)]
Remove redundant includes from utils/TableGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320632
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:31:10 +0000 (21:31 +0000)]
Remove redundant includes from tools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320631
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:31:05 +0000 (21:31 +0000)]
Remove redundant includes from unittests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320630
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:31:03 +0000 (21:31 +0000)]
Remove redundant includes from various places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320629
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:31:01 +0000 (21:31 +0000)]
Remove redundant includes from lib/Transforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320628
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:58 +0000 (21:30 +0000)]
Remove redundant includes from lib/Support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320627
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:57 +0000 (21:30 +0000)]
Remove redundant includes from lib/ProfileData.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320626
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:55 +0000 (21:30 +0000)]
Remove redundant includes from lib/Object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320625
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:54 +0000 (21:30 +0000)]
Remove redundant includes from lib/MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320624
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:53 +0000 (21:30 +0000)]
Remove redundant includes from lib/LTO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320623
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:52 +0000 (21:30 +0000)]
Remove redundant includes from lib/IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320622
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:50 +0000 (21:30 +0000)]
Remove redundant includes from lib/ExecutionEngine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320621
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:49 +0000 (21:30 +0000)]
Remove redundant includes from lib/DebugInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320620
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:47 +0000 (21:30 +0000)]
Remove redundant includes from lib/CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320619
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:45 +0000 (21:30 +0000)]
Remove redundant includes from lib/Bitcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320618
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:41 +0000 (21:30 +0000)]
Remove redundant includes from lib/Analysis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320617
91177308-0d34-0410-b5e6-
96231b3b80d8
Shoaib Meenai [Wed, 13 Dec 2017 21:12:37 +0000 (21:12 +0000)]
[cmake] Explicitly set VS 2017 compatibility
When cross-compiling using clang-cl 5.0 (which is currently the latest
stable release of the compiler), the default MS compatibility level is
set to VS 2013, which is too low to build LLVM. Explicitly set the
compatibility level to VS 2017 to support cross-compiling LLVM for
Windows using clang-cl 5.0. This will be a no-op when using clang-cl 6.0
and above, where the default MS compatibility level is already VS 2017.
Differential Revision: https://reviews.llvm.org/D41157
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320616
91177308-0d34-0410-b5e6-
96231b3b80d8
Shoaib Meenai [Wed, 13 Dec 2017 21:11:14 +0000 (21:11 +0000)]
[cmake] Determine MSVC host triple correctly when cross-compiling
CMAKE_CL_64 will never be set when cross-compiling with clang-cl, since
CMake relies on an actual VS environment in order to determine it.
Instead, use the size of a void pointer to determine the bit width of
the host compiler (and therefore the host triple), which works for both
native and cross compilation.
Note that, with the impending advent of Windows on AArch64, assuming
that a 64-bit host == x86_64 isn't correct either, but that's something
to be addressed in a follow-up.
Differential Revision: https://reviews.llvm.org/D41155
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320615
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 13 Dec 2017 21:07:51 +0000 (21:07 +0000)]
AMDGPU: Partially fix disassembly of MIMG instructions
Stores failed to decode at all since they didn't have a
DecoderNamespace set. Loads worked, but did not change
the register width displayed to match the numbmer of
enabled channels.
The number of printed registers for vaddr is still wrong,
but I don't think that's encoded in the instruction so
there's not much we can do about that.
Image atomics are still broken. MIMG is the same
encoding for SI/VI, but the image atomic classes
are split up into encoding specific versions unlike
every other MIMG instruction. They have isAsmParserOnly
set on them for some reason. dmask is also special for
these, so we probably should not have it as an explicit
operand as it is now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320614
91177308-0d34-0410-b5e6-
96231b3b80d8
Brian M. Rzycki [Wed, 13 Dec 2017 20:52:26 +0000 (20:52 +0000)]
[JumpThreading] Preservation of DT and LVI across the pass
Summary:
See D37528 for a previous (non-deferred) version of this
patch and its description.
Preserves dominance in a deferred manner using a new class
DeferredDominance. This reduces the performance impact of
updating the DominatorTree at every edge insertion and
deletion. A user may call DDT->flush() within JumpThreading
for an up-to-date DT. This patch currently has one flush()
at the end of runImpl() to ensure DT is preserved across
the pass.
LVI is also preserved to help subsequent passes such as
CorrelatedValuePropagation. LVI is simpler to maintain and
is done immediately (not deferred). The code to perfom the
preversation was minimally altered and was simply marked
as preserved for the PassManager to be informed.
This extends the analysis available to JumpThreading for
future enhancements. One example is loop boundary threading.
Reviewers: dberlin, kuhar, sebpop
Reviewed By: kuhar, sebpop
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D40146
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320612
91177308-0d34-0410-b5e6-
96231b3b80d8
Aditya Kumar [Wed, 13 Dec 2017 19:40:07 +0000 (19:40 +0000)]
[GVNHoist] Fix: PR35222 gvn-hoist incorrectly erases load
w.r.t. the paper
"A Practical Improvement to the Partial Redundancy Elimination in SSA Form"
(https://sites.google.com/site/jongsoopark/home/ssapre.pdf)
Proper dominance check was missing here, so having a loopinfo should not be required.
Committing this diff as this fixes the bug, if there are
further concerns, I'll be happy to work on them.
Differential Revision: https://reviews.llvm.org/D39781
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320607
91177308-0d34-0410-b5e6-
96231b3b80d8
Adrian Prantl [Wed, 13 Dec 2017 19:10:54 +0000 (19:10 +0000)]
Ignore metainstructions during the shrink wrap analysis
Shrink wrapping should ignore DBG_VALUEs referring to frame indices,
since the presence of debug information must not affect code
generation.
Differential Revision: https://reviews.llvm.org/D41187
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320606
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Wed, 13 Dec 2017 18:35:39 +0000 (18:35 +0000)]
[dsymutil][test] Fix failing test when no lipo binary available
The invocation without -no-output would try to lipo the different debug
objects together. This wouldn't work on platforms that don't provide
that utility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320605
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 18:09:45 +0000 (18:09 +0000)]
[X86] Add JCC/JECXZ/JECXZ/JRCXZ/LOOP schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320603
91177308-0d34-0410-b5e6-
96231b3b80d8
Amaury Sechet [Wed, 13 Dec 2017 18:04:57 +0000 (18:04 +0000)]
Regenerate test-shrink.ll test results. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320602
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Wed, 13 Dec 2017 18:03:04 +0000 (18:03 +0000)]
[dsymutil] Re-enable threading
Threading was disabled in r317263 because it broke a test in combination
with `-DLLVM_ENABLE_THREADS=OFF`. This was because a ThreadPool warning
was piped to llvm-dwarfdump which was expecting to read an object from
stdin.
This patch re-enables threading and fixes the offending test.
Unfortunately this required more than just moving the ThreadPool out of
the for loop because of the TempFile refactoring that took place in the
meantime.
Differential revision: https://reviews.llvm.org/D41180
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320601
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 17:50:40 +0000 (17:50 +0000)]
[X86] Add RET/RETF schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320600
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 17:42:25 +0000 (17:42 +0000)]
[X86] Add POP/PUSH schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320598
91177308-0d34-0410-b5e6-
96231b3b80d8
Brian M. Rzycki [Wed, 13 Dec 2017 16:56:18 +0000 (16:56 +0000)]
[Function] Remove trailing end-of-line whitespace. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320595
91177308-0d34-0410-b5e6-
96231b3b80d8
Nemanja Ivanovic [Wed, 13 Dec 2017 15:28:01 +0000 (15:28 +0000)]
Fix link failure on one build bot introduced by r320584.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320589
91177308-0d34-0410-b5e6-
96231b3b80d8
Galina Kistanova [Wed, 13 Dec 2017 15:26:27 +0000 (15:26 +0000)]
Reverted r320229. It broke tests on builder llvm-clang-x86_64-expensive-checks-win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320588
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 15:12:02 +0000 (15:12 +0000)]
[X86] Add PREFETCH schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320587
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 15:02:10 +0000 (15:02 +0000)]
[X86] Add XCHG schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320586
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 14:51:06 +0000 (14:51 +0000)]
[X86] Add MOVNTI schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320585
91177308-0d34-0410-b5e6-
96231b3b80d8
Nemanja Ivanovic [Wed, 13 Dec 2017 14:47:35 +0000 (14:47 +0000)]
[PowerPC] MachineSSA pass to reduce the number of CR-logical operations
The initial implementation of an MI SSA pass to reduce cr-logical operations.
Currently, the only operations handled by the pass are binary operations where
both CR-inputs come from the same block and the single use is a conditional
branch (also in the same block).
Committing this off by default to allow for a period of field testing. Will
enable it by default in a follow-up patch soon.
Differential Revision: https://reviews.llvm.org/D30431
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320584
91177308-0d34-0410-b5e6-
96231b3b80d8