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Guillaume Chatelet [Tue, 25 Sep 2018 14:48:24 +0000 (14:48 +0000)]
[llvm-exegesis] Fix missing document separator in YAML output.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52496
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342981
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Nirav Dave [Tue, 25 Sep 2018 14:43:05 +0000 (14:43 +0000)]
[DAGCombine] Don't fold dependent loads across SELECT_CC.
DAGCombine will try to fold two loads that feed a SELECT or SELECT_CC
after the select, resulting in a select of an address and a single
load after.
If either of the loads depend on the other, this is not legal as it
could introduce cycles. However, it only checked this if the opcode
was a SELECT, and not for a SELECT_CC.
Unfortunately, the only reproducer I have for this is for our
downstream target. I've tried getting it to trigger on an upstream one
but haven't been successful.
Patch thanks to Bevin Hansson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342980
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Clement Courbet [Tue, 25 Sep 2018 13:59:35 +0000 (13:59 +0000)]
[llvm-exegesis] Add lit tests (v2).
Summary: This revisits rL342953 by adding detection of host support.
Reviewers: gchatelet, lebedev.ri, alexshap
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342975
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Guillaume Chatelet [Tue, 25 Sep 2018 13:18:10 +0000 (13:18 +0000)]
[llvm-exegesis] Fix broken test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342971
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Simon Pilgrim [Tue, 25 Sep 2018 13:01:26 +0000 (13:01 +0000)]
Revert rL342916: [X86] Remove shift/rotate by CL memory (RMW) overrides
As suggested by Craig Topper - I'm going to look at cleaning up the RMW sequences instead.
The uops are slightly different to the register variant, so requires a +1uop tweak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342969
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Guillaume Chatelet [Tue, 25 Sep 2018 12:18:08 +0000 (12:18 +0000)]
[llvm-exegesis][NFC] Rewrite of the YAML serialization.
Summary: This is a NFC in preparation of exporting the initial registers as part of the YAML dump
Reviewers: courbet
Reviewed By: courbet
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342967
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Hans Wennborg [Tue, 25 Sep 2018 12:08:56 +0000 (12:08 +0000)]
Revert r342637 "[ADT] Try again to use the same version of llvm::Optional on all compilers"
and also revert follow-ups r342643 and r342723.
This caused Clang to be miscompiled by GCC 4.8.4 (Unbuntu 14.04's
default compiler) and break the Chromium build (see
https://crbug.com/888061).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342966
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David Green [Tue, 25 Sep 2018 10:08:47 +0000 (10:08 +0000)]
[LoopUnroll] Add check to Latch's terminator in UnrollRuntimeLoopRemainder
In this patch, I'm adding an extra check to the Latch's terminator in llvm::UnrollRuntimeLoopRemainder,
similar to how it is already done in the llvm::UnrollLoop.
The compiler would crash if this function is called with a malformed loop.
Patch by Rodrigo Caetano Rocha!
Differential Revision: https://reviews.llvm.org/D51486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342958
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Sameer Sahasrabuddhe [Tue, 25 Sep 2018 09:39:21 +0000 (09:39 +0000)]
[AMDGPU] restore r342722 which was reverted with r342743
[AMDGPU] lower-switch in preISel as a workaround for legacy DA
Summary:
The default target of the switch instruction may sometimes be an
"unreachable" block, when it is guaranteed that one of the cases is
always taken. The dominator tree concludes that such a switch
instruction does not have an immediate post dominator. This confuses
divergence analysis, which is unable to propagate sync dependence to
the targets of the switch instruction.
As a workaround, the AMDGPU target now invokes lower-switch as a
preISel pass. LowerSwitch is designed to handle the unreachable
default target correctly, allowing the divergence analysis to locate
the correct immediate dominator of the now-lowered switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342956
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Clement Courbet [Tue, 25 Sep 2018 09:36:44 +0000 (09:36 +0000)]
Revert rL342953 "[llvm-exegesis] Add lit tests."
We also need to make sure that we're on the right subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342955
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Clement Courbet [Tue, 25 Sep 2018 09:27:43 +0000 (09:27 +0000)]
[llvm-exegesis] Add lit tests.
Summary:
Right now we only have unit tests. This will allow testing the whole
tool. Even though We can't really check actual values, this will avoid
regressions such as PR39055.
Reviewers: gchatelet, alexshap
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52407
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342953
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Heejin Ahn [Tue, 25 Sep 2018 08:25:29 +0000 (08:25 +0000)]
[llvm-exegesis] Add MCParser to LLVM_LINK_COMPONENTS
We need this to make builds with `-DBUILD_SHARED_LIBS=ON` work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342952
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Fangrui Song [Tue, 25 Sep 2018 08:06:32 +0000 (08:06 +0000)]
Add macro LLVM_ATTRIBUTE_REINITIALIZES
Summary:
This marks legitimate use-after-move (e.g. `Found.clear()` in rC342925)
which would otherwise be caught by bugprone-use-after-move.
bugprone-use-after-move recognizes this attribute after rCTE339571.
Reviewers: aaron.ballman, rsmith, mboehme, hokein
Reviewed By: mboehme
Subscribers: kristina, llvm-commits
Differential Revision: https://reviews.llvm.org/D52451
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342949
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Clement Courbet [Tue, 25 Sep 2018 07:48:38 +0000 (07:48 +0000)]
[llvm-exegesis] Fix doc in r342947.
llvm-exegesis.rst was using invalid indentation for bullet points.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342948
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Clement Courbet [Tue, 25 Sep 2018 07:31:44 +0000 (07:31 +0000)]
[llvm-exegesis] Allow benchmarking arbitrary code snippets.
Summary:
This is a step towards fixing PR38048.
Note that right now the measurements are given per instruction. We'll
need to give measurements a per code snippet and update the analysis (PR38731).
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52041
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342947
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Stefan Maksimovic [Tue, 25 Sep 2018 06:27:49 +0000 (06:27 +0000)]
[mips] Correct MUL pattern for mips64
Guard existing pattern with a predicate, introduce a new one for revision 6.
Differential Revision: https://reviews.llvm.org/D51684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342946
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Fangrui Song [Tue, 25 Sep 2018 06:19:31 +0000 (06:19 +0000)]
Use unique_ptr to hold AsmInfo,MRI,MII,STI
Reviewers: pcc, dblaikie
Reviewed By: dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342945
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Mikael Holmen [Tue, 25 Sep 2018 06:10:04 +0000 (06:10 +0000)]
Use TRI->regsOverlap() in MachineBasicBlock::computeRegisterLiveness
Summary:
For the loop that used MCRegAliasIterator this should be NFC.
For the loop that previously used MCSubRegIterator we should
now detect more cases where the register is actually live out that
we previously missed.
Reviewers: MatzeB, arsenm
Reviewed By: MatzeB
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D52410
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342944
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Hsiangkai Wang [Tue, 25 Sep 2018 06:09:50 +0000 (06:09 +0000)]
[DebugInfo] Do not generate address info for removed debug labels.
In some senario, LLVM will remove llvm.dbg.labels in IR. For example,
when the labels are in unreachable blocks, these labels will not
be generated in LLVM IR. In the case, these debug labels will have
address zero as their address. It is not legal address for debugger to
set breakpoints or query sources. So, the patch inhibits the address info
(DW_AT_low_pc) of removed labels.
Differential Revision: https://reviews.llvm.org/D51908
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342943
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Justin Bogner [Tue, 25 Sep 2018 05:16:44 +0000 (05:16 +0000)]
[MachineCopyPropagation] Reimplement CopyTracker in terms of register units
Change the copy tracker to keep a single map of register units instead
of 3 maps of registers. This gives a very significant compile time
performance improvement to the pass. I measured a 30-40% decrease in
time spent in MCP on x86 and AArch64 and much more significant
improvements on out of tree targets with more registers.
Differential Revision: https://reviews.llvm.org/D52374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342942
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Lang Hames [Tue, 25 Sep 2018 04:54:03 +0000 (04:54 +0000)]
Revert "[ORC] Switch to asynchronous resolution in JITSymbolResolver."
This reverts commit r342939.
MSVC's promise/future implementation does not like types that are not default
constructible. Reverting while I figure out a solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342941
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Justin Bogner [Tue, 25 Sep 2018 04:45:25 +0000 (04:45 +0000)]
[MachineCopyPropagation] Rework how we manage RegMask clobbers
Instead of updating the CopyTracker's maps each time we come across a
RegMask, defer checking for this kind of interference until we're
actually trying to propagate a copy. This avoids the need to
repeatedly iterate over maps in the cases where we don't end up doing
any work.
This is a slight compile time improvement for MachineCopyPropagation
as is, but it also enables a much bigger improvement that I'll follow
up with soon.
Differential Revision: https://reviews.llvm.org/D52370
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342940
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Lang Hames [Tue, 25 Sep 2018 04:43:38 +0000 (04:43 +0000)]
[ORC] Switch to asynchronous resolution in JITSymbolResolver.
Asynchronous resolution (where the caller receives a callback once the requested
set of symbols are resolved) is a core part of the new concurrent ORC APIs. This
change extends the asynchronous resolution model down to RuntimeDyld, which is
necessary to prevent deadlocks when compiling/linking on a fixed number of
threads: If RuntimeDyld's linking process were a blocking operation, then any
complete K-graph in a program will require at least K threads to link in the
worst case, as each thread would block waiting for all the others to complete.
Using callbacks instead allows the work to be passed between dependent threads
until it is complete.
For backwards compatibility, all existing RuntimeDyld functions will continue
to operate in blocking mode as before. This change will enable the introduction
of a new async finalization process in a subsequent patch to enable asynchronous
JIT linking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342939
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Thomas Lively [Tue, 25 Sep 2018 03:39:28 +0000 (03:39 +0000)]
[WebAssembly] SIMD sqrt
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342937
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Stanislav Mekhanoshin [Tue, 25 Sep 2018 01:24:54 +0000 (01:24 +0000)]
[AMDGPU] Remove useless check from test. NFC.
The check for assignment of zero is practically useless
while the assignment moves around with different scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342935
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Craig Topper [Tue, 25 Sep 2018 00:16:57 +0000 (00:16 +0000)]
[X86] Don't create FILD ISD nodes when X87 is disabled.
The included test case previously asserted because the type legalizer tried to soften the FILD ISD node.
Fixes PR38819.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342934
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Craig Topper [Tue, 25 Sep 2018 00:16:54 +0000 (00:16 +0000)]
[X86] Remove superfluous curly braces. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342933
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Craig Topper [Tue, 25 Sep 2018 00:16:52 +0000 (00:16 +0000)]
[X86] Update comment. Use 'glued' instead of 'flagged' NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342932
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Thomas Lively [Mon, 24 Sep 2018 23:42:07 +0000 (23:42 +0000)]
[WebAssembly][NFC] Fix hardcoded stack indices in tests
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52388
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342928
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Artem Belevich [Mon, 24 Sep 2018 23:10:44 +0000 (23:10 +0000)]
[CUDA] Added basic support for compiling with CUDA-10.0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342924
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Evgeniy Stepanov [Mon, 24 Sep 2018 23:03:34 +0000 (23:03 +0000)]
[hwasan] Record and display stack history in stack-based reports.
Summary:
Display a list of recent stack frames (not a stack trace!) when
tag-mismatch is detected on a stack address.
The implementation uses alignment tricks to get both the address of
the history buffer, and the base address of the shadow with a single
8-byte load. See the comment in hwasan_thread_list.h for more
details.
Developed in collaboration with Kostya Serebryany.
Reviewers: kcc
Subscribers: srhines, kubamracek, mgorny, hiraditya, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D52249
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342923
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Evgeniy Stepanov [Mon, 24 Sep 2018 22:50:32 +0000 (22:50 +0000)]
Revert "[hwasan] Record and display stack history in stack-based reports."
This reverts commit r342921: test failures on clang-cmake-arm* bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342922
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Evgeniy Stepanov [Mon, 24 Sep 2018 21:38:42 +0000 (21:38 +0000)]
[hwasan] Record and display stack history in stack-based reports.
Summary:
Display a list of recent stack frames (not a stack trace!) when
tag-mismatch is detected on a stack address.
The implementation uses alignment tricks to get both the address of
the history buffer, and the base address of the shadow with a single
8-byte load. See the comment in hwasan_thread_list.h for more
details.
Developed in collaboration with Kostya Serebryany.
Reviewers: kcc
Subscribers: srhines, kubamracek, mgorny, hiraditya, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D52249
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342921
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Christy Lee [Mon, 24 Sep 2018 20:47:12 +0000 (20:47 +0000)]
Re-submitting changes in D51550 because it failed to patch.
Reviewers: javed.absar, trentxintong, courbet
Reviewed By: trentxintong
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342919
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Sanjay Patel [Mon, 24 Sep 2018 20:41:22 +0000 (20:41 +0000)]
[InstCombine] add bitcast+extelt helper function; NFC
We can handle patterns where the elements have different
sizes, so refactoring ahead of trying to add another blob
within these clauses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342918
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Simon Pilgrim [Mon, 24 Sep 2018 20:11:50 +0000 (20:11 +0000)]
[X86] Remove shift/rotate by CL memory (RMW) overrides
The uops are slightly different to the register variant, so requires a +1uop tweak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342916
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Craig Topper [Mon, 24 Sep 2018 18:55:41 +0000 (18:55 +0000)]
[X86] Infer 64bit feature support from the CPUID results in getHostCPUFeatures.
After r341022, we more strictly check the 64bit feature in X86Subtargets constructor when a 64-bit triple is used. If we don't infer this feature for autodetected CPUs we might incorrectly report an error if the CPU name wasn't autodetected to a CPU that supports 64-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342914
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Stefan Pintilie [Mon, 24 Sep 2018 18:14:13 +0000 (18:14 +0000)]
[Power9] [LLVM] Add __float128 exponent GET and SET builtins
Added
__builtin_vsx_scalar_extract_expq
__builtin_vsx_scalar_insert_exp_qp
Builtins should behave the same way as in GCC.
Differential Revision: https://reviews.llvm.org/D48185
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342910
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Simon Pilgrim [Mon, 24 Sep 2018 17:26:31 +0000 (17:26 +0000)]
[X86][AVX] Add truncation as shuffle test for PR31451
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342908
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Christy Lee [Mon, 24 Sep 2018 17:26:30 +0000 (17:26 +0000)]
Reland r342494 after fixing LIT checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342907
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Sanjay Patel [Mon, 24 Sep 2018 17:18:32 +0000 (17:18 +0000)]
[Analysis] add comment to generalize finding a scalar op from vector; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342906
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Sanjay Patel [Mon, 24 Sep 2018 17:17:16 +0000 (17:17 +0000)]
[InstCombine] add/move tests for extractelement; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342905
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Simon Pilgrim [Mon, 24 Sep 2018 16:58:26 +0000 (16:58 +0000)]
[X86] Remove WriteDiv/WriteIDiv schedule overrides - use classes directly. NFCI.
We're missing quite a bit of data for these instruction, removing the overrides makes this obvious - inconsistent reg/mem variants is a concern as well.
Also, we have Divider resources (HWDivider etc.) but they aren't actually used consistently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342904
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Sanjay Patel [Mon, 24 Sep 2018 16:39:03 +0000 (16:39 +0000)]
[InstCombine] improve variable name and use 'match'; NFC
'width' of a vector usually refers to the bit-width.
https://bugs.llvm.org/show_bug.cgi?id=39016
shows a case where we could extend this fold to handle
a case where the number of elements in the bitcasted
vector is not equal to the resulting value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342902
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Evandro Menezes [Mon, 24 Sep 2018 16:35:14 +0000 (16:35 +0000)]
[ARM] Adjust the cost model for Exynos
Tune `MaxInterleaveFactor` and `LdStMultipleTiming`and remove
`PartialUpdateClearance` for the Exynos processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342900
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Evandro Menezes [Mon, 24 Sep 2018 16:35:09 +0000 (16:35 +0000)]
[ARM] Adjust the feature set for Exynos
Enable crypto and literals fusion for the Exynos processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342899
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Zhaoshi Zheng [Mon, 24 Sep 2018 16:15:23 +0000 (16:15 +0000)]
[Thumb1] Any imm8 should have cost of 1
A simple MOVS rd, imm8 can materialize [-128, 127] in signed i8 type or
[0, 255] in unsigned i8 type on Thumb1.
Differential Revision: https://reviews.llvm.org/D52257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342898
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Fedor Sergeev [Mon, 24 Sep 2018 16:08:15 +0000 (16:08 +0000)]
[New PM][PassInstrumentation] IR printing support for New Pass Manager
Implementing -print-before-all/-print-after-all/-filter-print-func support
through PassInstrumentation callbacks.
- PrintIR routines implement printing callbacks.
- StandardInstrumentations class provides a central place to manage all
the "standard" in-tree pass instrumentations. Currently it registers
PrintIR callbacks.
Reviewers: chandlerc, paquette, philip.pfaffe
Differential Revision: https://reviews.llvm.org/D50923
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342896
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Simon Pilgrim [Mon, 24 Sep 2018 15:21:57 +0000 (15:21 +0000)]
[X86] Split WriteIMul into 8/16/32/64 implementations (PR36931)
Split WriteIMul by size and also by IMUL multiply-by-imm and multiply-by-reg cases.
This removes all the scheduler overrides for gpr multiplies and stops WriteMULH being ignored for BMI2 MULX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342892
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Luke Cheeseman [Mon, 24 Sep 2018 15:13:48 +0000 (15:13 +0000)]
[Arm][AsmParser] Restrict register list size for VSTM/VLDM
- The assembler accepts VSTM/VLDM with register lists (specifically double registers lists) with more than 16 registers specified
- The Arm architecture reference manual says this instruction must not contain more than 16 registers when the registers are doubleword registers
- This addresses one of the concerns in https://bugs.llvm.org/show_bug.cgi?id=38389
Differential Revision: https://reviews.llvm.org/D52082
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342891
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Sanjay Patel [Mon, 24 Sep 2018 14:47:15 +0000 (14:47 +0000)]
[DAGCombiner] use UADDO to optimize saturated unsigned add
This is a preliminary step towards solving PR14613:
https://bugs.llvm.org/show_bug.cgi?id=14613
If we have an 'add' instruction that sets flags, we can use that to eliminate an
explicit compare instruction or some other instruction (cmn) that sets flags for
use in the later select.
As shown in the unchanged tests that use 'icmp ugt %x, %a', we're effectively
reversing an IR icmp canonicalization that replaces a variable operand with a
constant:
https://rise4fun.com/Alive/V1Q
But we're not using 'uaddo' in those cases via DAG transforms. This happens in
CGP after D8889 without checking target lowering to see if the op is supported.
So AArch already shows 'uaddo' codegen for the i8/i16/i32/i64 test variants with
"using_cmp_sum" in the title. That's the pattern that CGP matches as an unsigned
saturated add and converts to uaddo without checking target capabilities.
This patch is gated by isOperationLegalOrCustom(ISD::UADDO, VT), so we see only
see AArch diffs for i32/i64 in the tests with "using_cmp_notval" in the title
(unlike x86 which sees improvements for all sizes because all sizes are 'custom').
But the AArch code (like x86) looks better when translated to 'uaddo' in all cases.
So someone that is involved with AArch may want to set i8/i16 to 'custom' for UADDO,
so this patch will fire on those tests.
Another possibility given the existing behavior: we could remove the legal-or-custom
check altogether because we're assuming that a UADDO sequence is canonical/optimal
before we ever reach here. But that seems like a bug to me. If the target doesn't
have an add-with-flags op, then it's not likely that we'll get optimal DAG combining
using a UADDO node. This is similar justification for why we don't canonicalize IR to
the overflow math intrinsic sibling (llvm.uadd.with.overflow) for UADDO in the first
place.
Differential Revision: https://reviews.llvm.org/D51929
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342886
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Petar Jovanovic [Mon, 24 Sep 2018 14:14:19 +0000 (14:14 +0000)]
[Mips][FastISel] Fix selectBranch on icmp i1
The r337288 tried to fix result of icmp i1 when its input is not sanitized
by falling back to DagISel. While it now produces the correct result for
bit 0, the other bits can still hold arbitrary value which is not supported
by MipsFastISel branch lowering. This patch fixes the issue by falling back
to DagISel in this case.
Patch by Dragan Mladjenovic.
Differential Revision: https://reviews.llvm.org/D52045
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342884
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Zaara Syeda [Mon, 24 Sep 2018 14:01:16 +0000 (14:01 +0000)]
[PowerPC] Support operand modifier 'x' in inline asm
gcc uses operand modifier 'x' in inline asm for VSX registers.
Without this modifier, instructions which use VSX numbering for their
operands are printed as VMX registers. This patch adds support for the
operand modifier 'x'.
Differential Revision: https://reviews.llvm.org/D52244
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342882
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Jonas Devlieghere [Mon, 24 Sep 2018 13:56:36 +0000 (13:56 +0000)]
[dsymutil] Set LSan blacklist whenever sanitizers are enabled.
LSan can be enabled by itself or as part of the address sanitizer.
Rather than checking the enabled sanitizers for both, just set the LSan
env options whenever a sanitizer is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342881
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Roman Lebedev [Mon, 24 Sep 2018 13:24:20 +0000 (13:24 +0000)]
[NFC][CodeGen][X86][AArch64] More tests for 'bit field extract' w/ constants
It would be best to introduce ISD::BitFieldExtract,
because clearly more than one backend faces the same problem.
But for now let's solve this in the x86-specific DAG combine.
https://bugs.llvm.org/show_bug.cgi?id=38938
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342880
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Matt Arsenault [Mon, 24 Sep 2018 13:18:15 +0000 (13:18 +0000)]
AMDGPU: Fix private handling for allowsMisalignedMemoryAccesses
If the alignment is at least 4, this should report true.
Something still seems off with how < 4-byte types are
handled here though.
Fixing this seems to change how some combines get
to where they get, but somehow isn't changing the net
result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342879
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Matt Arsenault [Mon, 24 Sep 2018 12:47:17 +0000 (12:47 +0000)]
Fix some missing opcodes in bcanalyzer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342878
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Andrea Di Biagio [Mon, 24 Sep 2018 12:45:26 +0000 (12:45 +0000)]
[llvm-mca] Improve code comments in LSUnit.{h, cpp}. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342877
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Sjoerd Meijer [Mon, 24 Sep 2018 12:02:50 +0000 (12:02 +0000)]
[ARM] Do not fuse VADD and VMUL on the Cortex-M4 and Cortex-M33
A sequence of VMUL and VADD instructions always give the same or better
performance than a fused VMLA instruction on the Cortex-M4 and Cortex-M33.
Executing the VMUL and VADD back-to-back requires the same cycles, but
having separate instructions allows scheduling to avoid the hazard between
these 2 instructions.
Differential Revision: https://reviews.llvm.org/D52289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342874
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Hans Wennborg [Mon, 24 Sep 2018 11:40:07 +0000 (11:40 +0000)]
Revert r341932 "[ARM] Enable ARMCodeGenPrepare by default"
This caused miscompilation of WebRTC for Android: PR39060.
> We've had the pass enabled downstream for a couple of weeks and it
> seems to be okay, so enable it by default.
>
> Differential Revision: https://reviews.llvm.org/D51920
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342873
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Luke Cheeseman [Mon, 24 Sep 2018 10:42:22 +0000 (10:42 +0000)]
[ARM][ARMLoadStoreOptimizer]
- The load store optimizer is currently merging multiple loads/stores into VLDM/VSTM with more than 16 doubleword registers
- This is an UNPREDICTABLE instruction and shouldn't be done
- It looks like the Limit for how many registers included in a merge got dropped at some point so I am reintroducing it in this patch
- This fixes https://bugs.llvm.org/show_bug.cgi?id=38389
Differential Revision: https://reviews.llvm.org/D52085
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342872
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Petar Jovanovic [Mon, 24 Sep 2018 10:01:24 +0000 (10:01 +0000)]
[deadargelim] Update dbg.value of 'unused' parameters
DeadArgElim pass marks unused function arguments as ‘undef’ without updating
existing dbg.values referring to it. As a consequence the debug info
metadata in the final executable was wrong.
Patch by Djordje Todorovic.
Differential Revision: https://reviews.llvm.org/D51968
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342871
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Sam Parker [Mon, 24 Sep 2018 09:34:06 +0000 (09:34 +0000)]
[ARM] bottom-top mul support ARMParallelDSP
Originally committed in rL342210 but was reverted in rL342260 because
it was causing issues in vectorized code, because I had forgotten to
ensure that we're operating on scalar values.
Original commit message:
On failing to find sequences that can be converted into dual macs,
try to find sequential 16-bit loads that are used by muls which we
can then use smultb, smulbt, smultt with a wide load.
Differential Revision: https://reviews.llvm.org/D51983
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342870
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Clement Courbet [Mon, 24 Sep 2018 08:39:48 +0000 (08:39 +0000)]
[llvm-exegesis] Fix PR39021.
Summary:
The `set` statements was incorrectly reading the value of the local variable and
setting the value of the parent variable.
Reviewers: tycho, gchatelet, john.brawn
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52343
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342865
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Hans Wennborg [Mon, 24 Sep 2018 08:34:17 +0000 (08:34 +0000)]
Fix llvm-diff anon-func.ll test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342864
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Hans Wennborg [Mon, 24 Sep 2018 08:18:47 +0000 (08:18 +0000)]
Remove debug printf leftover from r342397
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342863
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Craig Topper [Mon, 24 Sep 2018 05:46:01 +0000 (05:46 +0000)]
[X86] Add 512-bit test cases to setcc-wide-types.ll. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342860
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Dean Michael Berris [Mon, 24 Sep 2018 05:28:01 +0000 (05:28 +0000)]
[XRay] Clean up XRay build configuration
Summary:
This change spans both LLVM and compiler-rt, where we do the following:
- Add XRay to the LLVMBuild system, to allow for distributing the XRay
trace loading library along with the LLVM distributions.
- Use `llvm-config` better in the compiler-rt XRay implementation, to
depend on the potentially already-distributed LLVM XRay library.
While this is tested with the standalone compiler-rt build, it does
require that the LLVMXRay library (and LLVMSupport as well) are
available during the build. In case the static libraries are available,
the unit tests will build and work fine. We're still having issues with
attempting to use a shared library version of the LLVMXRay library since
the shared library might not be accessible from the standard shared
library lookup paths.
The larger change here is the inclusion of the LLVMXRay library in the
distribution, which allows for building tools around the XRay traces and
profiles that the XRay runtime already generates.
Reviewers: echristo, beanz
Subscribers: mgorny, hiraditya, mboerger, llvm-commits
Differential Revision: https://reviews.llvm.org/D52349
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342859
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Matt Arsenault [Mon, 24 Sep 2018 04:42:14 +0000 (04:42 +0000)]
Fix asserts when linking wrong address space declarations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342858
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Matt Arsenault [Mon, 24 Sep 2018 04:42:13 +0000 (04:42 +0000)]
llvm-diff: Fix crash on anonymous functions
Not sure what the correct behavior is for this.
Skip them and report how many there were.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342857
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Craig Topper [Mon, 24 Sep 2018 02:03:11 +0000 (02:03 +0000)]
[DAGCombiner] Remove some dead code from ConstantFoldBITCASTofBUILD_VECTOR
This code handled SCALAR_TO_VECTOR being returned by the recursion, but the code that used to return SCALAR_TO_VECTOR was removed in 2015.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342856
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Lang Hames [Sun, 23 Sep 2018 21:30:05 +0000 (21:30 +0000)]
[ORC] Add some debugging output to Core.h/Core.cpp
Core now logs when materialization units are dispatched or return to JITDylibs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342853
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Simon Pilgrim [Sun, 23 Sep 2018 21:19:15 +0000 (21:19 +0000)]
[X86] Split WriteShift/WriteRotate schedule classes by CL usage.
Variable Shifts/Rotates using the CL register have different behaviours to the immediate instructions - split accordingly to help remove yet more repeated overrides from the schedule models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342852
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Craig Topper [Sun, 23 Sep 2018 21:17:56 +0000 (21:17 +0000)]
[DAGCombiner] Clarify a comment. NFC
This comment was misleading about why we were restricting to before legalize types. The reason given would only apply to before legalize ops. But there is a before legalize types reason that should also be listed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342851
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Craig Topper [Sun, 23 Sep 2018 21:17:55 +0000 (21:17 +0000)]
[LegalizeTypes] Fix bad indentation. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342850
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Simon Pilgrim [Sun, 23 Sep 2018 19:33:58 +0000 (19:33 +0000)]
[X86] Remove unnecessary WriteRotate override. NFCI.
SNB was the last override for ROT(L|R)r(1|i) - they now all use WriteRotate correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342848
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Simon Pilgrim [Sun, 23 Sep 2018 19:16:32 +0000 (19:16 +0000)]
Fix line ending mismatches. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342847
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Simon Pilgrim [Sun, 23 Sep 2018 19:16:01 +0000 (19:16 +0000)]
[X86] ROR*mCL instruction models should match ROL*mCL etc.
Confirmed with Craig Topper - fix a typo that was missing a Port4 uop for ROR*mCL instructions on some Intel models.
Yet another step on the scheduler model cleanup marathon......
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342846
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Benjamin Kramer [Sun, 23 Sep 2018 18:43:28 +0000 (18:43 +0000)]
[Aarch64] Fix memcpy that was copying 4x too many bytes
Found by asan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342845
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Sanjay Patel [Sun, 23 Sep 2018 18:41:38 +0000 (18:41 +0000)]
[DAGCombiner][x86] extend decompose of integer multiply into shift/add with negation
This is an alternative to https://reviews.llvm.org/D37896. We can't decompose
multiplies generically without a target hook to tell us when it's profitable.
ARM and AArch64 may be able to remove some existing code that overlaps with
this transform.
This extends D52195 and may resolve PR34474:
https://bugs.llvm.org/show_bug.cgi?id=34474
(still an open question about transforming legal vector multiplies, but we
could open another bug report for those)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342844
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Simon Pilgrim [Sun, 23 Sep 2018 17:40:24 +0000 (17:40 +0000)]
[X86] Added missing RCL/RCR schedule overrides to the generic SNB model
The SandyBridge model was missing schedule values for the RCL/RCR values - instead using the (incredibly optimistic) WriteShift (now WriteRotate) defaults.
I've added overrides with more realistic (slow) values, based on a mixture of Agner/instlatx64 numbers and what later Intel models do as well.
This is necessary to allow WriteRotate to be updated to remove other rotate overrides.
It'd probably be a good idea to investigate a WriteRotateCarry class at some point but its not high priority given the unusualness of these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342842
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Simon Pilgrim [Sun, 23 Sep 2018 16:53:02 +0000 (16:53 +0000)]
[X86] Remove unnecessary WriteRotate overrides. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342841
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Simon Pilgrim [Sun, 23 Sep 2018 16:17:13 +0000 (16:17 +0000)]
[X86] Move RORX instructions back to WriteShift schedule class
Despite being rotates, these more modern instructions avoid many of the quirks of the regular x86 rotate instructions and consistently have a schedule closer to shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342839
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Sanjay Patel [Sun, 23 Sep 2018 16:07:46 +0000 (16:07 +0000)]
[x86] add tests for mul decomposition with negative constant; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342838
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Simon Pilgrim [Sun, 23 Sep 2018 15:12:10 +0000 (15:12 +0000)]
[X86] Add WriteRotate schedule class, splitting off from WriteShift.
NFCI for now, but it should make it easier to remove a lot of unnecessary overrides in a future commit.
Now that funnel shift intrinsics are coming online we need to get this cleaned up to make vectorization costs from scalar rotate patterns more straightforward.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342837
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Eugene Leviant [Sun, 23 Sep 2018 13:27:47 +0000 (13:27 +0000)]
[WholeProgramDevirt] Don't process declarations when building type id map
Differential revision: https://reviews.llvm.org/D52175
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342836
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Simon Pilgrim [Sun, 23 Sep 2018 11:28:47 +0000 (11:28 +0000)]
Build PassBuilder.cpp with /bigobj to try and appease MSVC EXPENSIVE_CHECKS buildbot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342835
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Craig Topper [Sun, 23 Sep 2018 06:49:48 +0000 (06:49 +0000)]
[X86] Add isel pattern for (v8i16 (sext (v8i1))) with DQI and no BWI.
Our lowering that tries to avoid this sign extend can be defeated by the DAG combine folding it with a truncate.
The pattern needs to extend to an v8i32 then truncate back down to v8i16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342830
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Craig Topper [Sun, 23 Sep 2018 06:49:47 +0000 (06:49 +0000)]
[X86] Fix a few typos in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342829
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Lang Hames [Sun, 23 Sep 2018 02:09:18 +0000 (02:09 +0000)]
[ORC] Update ORC C bindings to use the new llvm::Error C API.
This replaces instances of the LLVMOrcErrorCode type with LLVMErrorRef,
simplifying the implementation of the OrcCBindingsStack class and ORC
C API bindings and making it possible to return arbitrary (wrapped)
llvm::Errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342828
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Craig Topper [Sat, 22 Sep 2018 23:12:34 +0000 (23:12 +0000)]
[DAGCombiner] Simplify some code in visitBITCAST. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342826
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Tri Vo [Sat, 22 Sep 2018 22:17:50 +0000 (22:17 +0000)]
[AArch64] Support adding X[8-15,18] registers as CSRs.
Summary:
Specifying X[8-15,18] registers as callee-saved is used to support
CONFIG_ARM64_LSE_ATOMICS in Linux kernel. As part of this patch we:
- use custom CSR list/mask when user specifies custom CSRs
- update Machine Register Info's list of CSRs with additional custom CSRs in
LowerCall and LowerFormalArguments.
Reviewers: srhines, nickdesaulniers, efriedma, javed.absar
Reviewed By: nickdesaulniers
Subscribers: kristof.beyls, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D52216
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342824
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Craig Topper [Sat, 22 Sep 2018 18:03:14 +0000 (18:03 +0000)]
[DAGCombiner] Rewrite r331896 in a different way to address a FIXME. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342809
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Yonghong Song [Sat, 22 Sep 2018 17:31:01 +0000 (17:31 +0000)]
[bpf] Test case for symbol information in object file
This patch tests the change introduced in r342556.
Signed-off-by: Paul Chaignon <paul.chaignon@orange.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342807
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Sanjay Patel [Sat, 22 Sep 2018 14:43:55 +0000 (14:43 +0000)]
[InstCombine][x86] try even harder to convert blendv intrinsic to generic IR (PR38814)
Follow-up to rL342324 (D52059):
Missing optimizations with blendv are shown in:
https://bugs.llvm.org/show_bug.cgi?id=38814
This is an easier and more powerful solution than adding pattern matching for a few
special cases in the backend. The potential danger with this transform in IR is that
the condition value can get separated from the select, and the backend might not be
able to make a blendv out of it again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342806
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George Rimar [Sat, 22 Sep 2018 07:36:20 +0000 (07:36 +0000)]
[lib/MC] - Set SHF_EXCLUDE flag for .dwo sections.
DWARF5 spec says about single file split case:
"The sections that do not require relocation, however, can be written
to the relocatable object (.o) file but ignored by the
the linker or they can be written to a separate DWARF object (.dwo) file
that need not be accessed by the linker."
Nice way to make linker to ignore them is to set SHF_EXCLUDE flag.
It seems to be not harmful to always set it for .dwo sections.
That is what this patch does.
Differential revision: https://reviews.llvm.org/D52303
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342800
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Simon Atanasyan [Sat, 22 Sep 2018 06:04:32 +0000 (06:04 +0000)]
[mips] Provide more detailed description for MIPS targets. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342799
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Simon Atanasyan [Sat, 22 Sep 2018 06:04:26 +0000 (06:04 +0000)]
[mips] Remove obsoleted "experimental" tag from MIPS 64-bit targets. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342798
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Craig Topper [Sat, 22 Sep 2018 05:53:27 +0000 (05:53 +0000)]
[InstCombine] Fold (min/max ~X, Y) -> ~(max/min X, ~Y) when Y is freely invertible
Summary: This restores the combine that was reverted in r341883. The infinite loop from the failing test no longer occurs due to changes from r342163.
Reviewers: spatel, dmgreen
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52070
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342797
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 22 Sep 2018 05:16:35 +0000 (05:16 +0000)]
[X86] Fix inline expansion for memset in x32
Summary: Similar to D51893 which was for memcpy
Reviewers: efriedma
Reviewed By: efriedma
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52063
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342796
91177308-0d34-0410-b5e6-
96231b3b80d8