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Linux Build Service Account [Sat, 25 Feb 2017 09:09:26 +0000 (01:09 -0800)]
Merge "ARM: dts: msm: Enable support for LPM Errata feature on sdm660"
Linux Build Service Account [Sat, 25 Feb 2017 09:09:26 +0000 (01:09 -0800)]
Merge "ARM: dts: msm: Update LPM parameter values for sdm660"
Linux Build Service Account [Sat, 25 Feb 2017 09:09:24 +0000 (01:09 -0800)]
Merge "ARM: dts: msm: add support for msm8998 QRD HDK board"
Linux Build Service Account [Fri, 24 Feb 2017 19:52:13 +0000 (11:52 -0800)]
Merge "ath10k: fix copyright year for copy engine driver" into msm-4.4
Rakesh Pillai [Tue, 21 Feb 2017 09:13:42 +0000 (14:43 +0530)]
ath10k: fix copyright year for copy engine driver
Revert back the copyright year of third party file.
CRs-Fixed:
2009450
Change-Id: I2ca345632c70bc6b795ae6197663be68599eb0c4
Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
Linux Build Service Account [Fri, 24 Feb 2017 05:36:01 +0000 (21:36 -0800)]
Merge "smb138x: support ship mode"
Linux Build Service Account [Fri, 24 Feb 2017 05:36:00 +0000 (21:36 -0800)]
Merge "drm/msm: mdp5: Correctly return ERR_PTR for mdp5_cfg_init"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:59 +0000 (21:35 -0800)]
Merge "msm: ipa3: halt modem channels as part of SSR"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:58 +0000 (21:35 -0800)]
Merge "msm: gsi: add support for generic commands"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:58 +0000 (21:35 -0800)]
Merge "ARM: dts: msm: enable watchdog for sdm630"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:57 +0000 (21:35 -0800)]
Merge "drivers: dma-removed: page align size on free"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:56 +0000 (21:35 -0800)]
Merge "defconfig: add cti config with save-restore disable for perf of sdm660"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:55 +0000 (21:35 -0800)]
Merge "ARM: dts: msm: Add LMH DCVSh mitigation support for KTM for sdm630"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:54 +0000 (21:35 -0800)]
Merge "ARM: dts: msm: Enable LMH DCVSh driver for sdm630"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:53 +0000 (21:35 -0800)]
Merge "soc: qcom: pil: Clear elf region on authentication failure"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:53 +0000 (21:35 -0800)]
Merge "supply: qcom: battery: re-split FCC when ICL changes"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:52 +0000 (21:35 -0800)]
Merge "msm: mink: Separate out transport and client error"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:51 +0000 (21:35 -0800)]
Merge "ARM: dts: msm: enable SSC based sensors for SDM630 MTP/CDP"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:50 +0000 (21:35 -0800)]
Merge "ARM: dts: msm: Add SMB1351 device node for SDM660 QRD"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:49 +0000 (21:35 -0800)]
Merge "ARM: dts: msm: changing memlat vote for min freq on SDM660"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:49 +0000 (21:35 -0800)]
Merge "ARM: dts: msm: Add touch device node for HDK835"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:48 +0000 (21:35 -0800)]
Merge "ARM: dts: msm: Enable support for GLINK QOS feature on msm8998"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:47 +0000 (21:35 -0800)]
Merge "MMC : card: check for card status incase of timeout error"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:46 +0000 (21:35 -0800)]
Merge "ARM: dts: msm: add reg bus scale properties for sdm660 and sdm630"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:45 +0000 (21:35 -0800)]
Merge "ARM: dts: msm: Update fuse corners supported for APC0/1 CPR for sdm630"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:44 +0000 (21:35 -0800)]
Merge "ARM: dts: msm: Add support for audio over USBC for SDM630"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:44 +0000 (21:35 -0800)]
Merge "ASoC: msm: qdsp6v2: Add INT3_MI2S interface for Source tracking"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:43 +0000 (21:35 -0800)]
Merge "ASoC: codecs: Enable SSR for internal codec and WSA"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:42 +0000 (21:35 -0800)]
Merge "ARM: dts: msm: Add routing controls for sdm660 internal codec"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:37 +0000 (21:35 -0800)]
Merge "drm/msm: add support for 5V HPD pin for msm8998"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:36 +0000 (21:35 -0800)]
Merge "drm/msm: enable hpd event support for hdmi display"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:36 +0000 (21:35 -0800)]
Merge "drm/msm: add sde io util API support"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:35 +0000 (21:35 -0800)]
Merge "drm/sde: add support for customized mode"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:34 +0000 (21:35 -0800)]
Merge "ARM: dts: msm: include SDE DTSI for MSM8998"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:34 +0000 (21:35 -0800)]
Merge "ARM: dts: msm: rename mdss_mdp to sde_kms and add HDMI TX device node"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:29 +0000 (21:35 -0800)]
Merge "mhi: core: Add support for new MHI hardware channel"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:15 +0000 (21:35 -0800)]
Merge "drm/msm: Get object iova from correct address space"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:14 +0000 (21:35 -0800)]
Merge "drm/msm: Mark the microcode buffers as read-only"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:12 +0000 (21:35 -0800)]
Merge "drm/msm: Come out of secure before executing GPMU initialization"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:10 +0000 (21:35 -0800)]
Merge "drm/msm: Get and enable the IOMMU clocks"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:08 +0000 (21:35 -0800)]
Merge "drm/msm: Add hint to DRM_IOCTL_MSM_GEM_INFO to return an object IOVA"
Linux Build Service Account [Fri, 24 Feb 2017 05:35:07 +0000 (21:35 -0800)]
Merge "msm: mdss: Install sync fences after user copy"
Abhijeet Dharmapurikar [Fri, 24 Feb 2017 02:38:20 +0000 (18:38 -0800)]
smb138x: support ship mode
Provide means to set ship mode on smb138x charger. While in parallel
charger mode make the main charger set ship mode on smb138x before
calling ship mode on itself.
Change-Id: I9b96b425829520d95632aa32d2297940cca5e254
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Skylar Chang [Fri, 17 Feb 2017 19:09:50 +0000 (11:09 -0800)]
msm: ipa3: halt modem channels as part of SSR
For modem SSR, APPS needs to halt modem consumer channels after
shutdown to make sure GSI FW does not access any modem's memory.
Change-Id: I6889a2ad509e0b1104ef8c3f65f24fe39b10745d
CRs-Fixed:
2008582
Acked-by: Ady Abrahan <adya@qti.qualcomm.com>
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
Skylar Chang [Tue, 21 Feb 2017 17:46:46 +0000 (09:46 -0800)]
msm: gsi: add support for generic commands
Expose a new API from GSI driver to allow client driver to
disable channel for other Execution Environment.
This API will be used as part of SSR cleanup.
Change-Id: I3b9400643aff76ca2195a597aba9ea18aab3085e
CRs-Fixed:
2008582
Acked-by: Ady Abrahan <adya@qti.qualcomm.com>
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
Saranya Chidura [Tue, 21 Feb 2017 11:00:38 +0000 (16:30 +0530)]
ARM: dts: msm: enable watchdog for sdm630
Enable watchdog node for sdm630 which is used to detect system hang.
Change-Id: Idfb307dd991e17e0030921e03c6f8a04afb9bc1d
Signed-off-by: Saranya Chidura <schidura@codeaurora.org>
Saranya Chidura [Thu, 23 Feb 2017 05:33:03 +0000 (11:03 +0530)]
defconfig: add cti config with save-restore disable for perf of sdm660
Added CONFIG_CORESIGHT_CTI and CONFIG_CORESIGHT_CTI_SAVE_DISABLE
in perf_defconfig of SDM660 to enable cti without save-restore
functionality for CPU cores.
Change-Id: I19a2fb8a3097bac910bb5e50c9a80d84f03098d3
Signed-off-by: Saranya Chidura <schidura@codeaurora.org>
Saranya Chidura [Thu, 23 Feb 2017 07:36:30 +0000 (13:06 +0530)]
kconfig: add cti-save-disable config in coresight
Added CONFIG_CORESIGHT_CTI_SAVE_DISABLE in kconfig of
coresight to choose CTI without save-restore functionality
for CPU cores.
Change-Id: I48128fbeda293a73d78946b8c222b5d0393c7595
Signed-off-by: Saranya Chidura <schidura@codeaurora.org>
Sujeev Dias [Tue, 13 Sep 2016 23:55:01 +0000 (16:55 -0700)]
mhi: core: Add support for new MHI hardware channel
Add support for new MHI hardware channel 102 to be
use by MHI clients as ADPL channel.
CRs-Fixed:
1027069
Change-Id: Ib3c2019fc269064d097bb7f40f01d4580e63a603
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Sujeev Dias [Tue, 27 Sep 2016 18:52:29 +0000 (11:52 -0700)]
mhi: core: Do not clear transaction status
MHI transaction status stores the OVERFLOW status
received from device. MHI clients uses this
status to determine overflow buffers, do
not clear the status.
CRs-Fixed:
1042516
Change-Id: Iaaff06c1c39775d6a33ca17851f1e1579b2a2ecb
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Nicholas Troast [Fri, 17 Feb 2017 19:51:32 +0000 (11:51 -0800)]
supply: qcom: battery: re-split FCC when ICL changes
Currently the notifier does not respond to main psy changed events, so
changes in ICL will not schedule the status change work. Furthermore,
the status change work does not re-run the FCC splitting which is
dependent on the settled ICL.
First, add the main psy as one of the triggers for the status changed
work. Second, re-run the FCC and FV voteable elections to re-split the
FCC based on the new ICL.
Change-Id: I1f5f2e176ec470c9c71ff4a0787ffa0cc5828ebc
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Sujeev Dias [Tue, 30 Aug 2016 01:56:30 +0000 (18:56 -0700)]
msm: mhi: Check bb ring and transfer ring when checking for space
When checking for available spaces, check available spaces on
both bounce buffer ring and transfer ring and return min.
Change-Id: I9208b46c32821de3f5d9e3d828087d7bc29b9546
CRs-Fixed:
1055681
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Sujeev Dias [Thu, 7 Jul 2016 20:10:08 +0000 (13:10 -0700)]
mhi: core: add missing MHI state
Add missing state MHI_STATE_RESERVE to MHI states
look up table.
CRs-Fixed:
1049595
Change-Id: I9a6bd2750f81f6cabc1e7b5aff488b4a01f7897d
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Dinesh K Garg [Tue, 7 Feb 2017 23:25:10 +0000 (15:25 -0800)]
msm: mink: Separate out transport and client error
Currently, return value for SMCINVOKE_IOCTL_INVOKE_REQ IOCLT is mixed
with error generated by client. This does not seem right because client
does not understand kernel error code and vice versa.
Change-Id: I77278700c4927facf7aba92a11bfde29b1e8eb38
Signed-off-by: Dinesh K Garg <dineshg@codeaurora.org>
Sushmita Susheelendra [Mon, 13 Feb 2017 17:14:35 +0000 (10:14 -0700)]
drm/msm: Get object iova from correct address space
Get the iova for a buffer object from the context
specific address space instead of always defaulting
to the global address space.
Change-Id: Id38c2ca2d6bad334beab53d8bcf8eb5cf5b1bb99
Signed-off-by: Sushmita Susheelendra <ssusheel@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:34 +0000 (10:14 -0700)]
drm/msm: Return the current status of a fence for a timeout of 0
Return the current status of the fence (0 for retired, -EBUSY for
active) if an absolute timeout of 0 is passed to MSM_IOCTL_WAIT_FENCE.
This allows the user space to check the status of the fence without
an awkward timeout or an inadvertent kernel message.
Change-Id: Ic0dedbad66adfabed24aeb6692abb2765ee37f24
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:34 +0000 (10:14 -0700)]
drm/msm: Mark the microcode buffers as read-only
The PFP/ME and GPMU memory needs to be GPU accessible but it
does not need to be written by the GPU. Mark them as read-only
to avoid corruption.
Change-Id: Ic0dedbadc848f0a6693a4e57567077bbab38e9a5
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:33 +0000 (10:14 -0700)]
drm/msm: Come out of secure before executing GPMU initialization
There isn't any need to be in secure mode when executing the GPMU
initalization so swap out to eliminate it as a variable when
GPMU init goes broken.
Change-Id: Ic0dedbad07b8cde80e257f71999002e9cbc47c24
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:33 +0000 (10:14 -0700)]
drm/msm: Enable pm_runtime for the GPU
Enable pm_runtime for the GPU to keep power collapse from hitting
us while we expect the GPU to be powered.
Change-Id: Ic0dedbad693f1d01776a87bc7a145a65510ac3fb
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:32 +0000 (10:14 -0700)]
drm/msm: Get and enable the IOMMU clocks
If we do not enable the iommu clocks at attach time they might
be shut off automatically by other devices power collapsing which
would affect our ability to switch the pagetable dynamically.
There is little power downside to just leaving them on all the time,
or at least as long as the main device is attached (in other words,
all the time).
Change-Id: Ic0dedbad8f6d2ee2a2cb9516e062af2421d91052
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:32 +0000 (10:14 -0700)]
drm/msm: Fix the check for the command size
The overrun check for the size of submitted commands is off by one.
It should allow the offset plus the size to be equal to the
size of the memory object when the command stream is very tightly
constructed.
Change-Id: Ic0dedbadec41fb8be84d7522b4dc923dbd537ce5
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Tue, 21 Feb 2017 21:50:45 +0000 (14:50 -0700)]
drm/msm: Add support for the QTI GPU snapshot format
When a fault happens on the Adreno GPU we want to collect
a considerable amount of information to diagnose the problem
including registers, caches, and GPU memory structures (ringbuffers,
etc).
The snapshot collects all of this information following a GPU fault
and encodes it into a binary file format that can be pulled from
debugfs or extracted from a memory dump.
This may seem a duplication of other debug methods (the ->show
functions for example) and while that is true for small numbers
of registers the snapshot goes much further - it collects hundreds
(thousands) of registers in addition to memory and other structures
that would be impractical to dump as ascii. The binary format allows
for the snapshot to be easily shared and post-processed in different
ways to extract patterns.
Add the basic snapshot infrastructure and enable ringbuffer, register
and shader bank collection for A5XX targets.
Change-Id: Ic0dedbadcf0513096d05870f522ac73da74ceb31
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:31 +0000 (10:14 -0700)]
drm/msm: Allow hardware clock gating to be toggled
There are some use cases wherein we need to turn off hardware clock
gating before reading certain registers. Modify the A5XX HWCG function
to allow user to enable or disable clock gating at will.
Change-Id: Ic0dedbade1264785b3436099e638a5678a62818f
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:31 +0000 (10:14 -0700)]
drm/msm: Update the list of A5XX registers
Update the list of the A5XX register ranges that can be read on a
hang. The new list adds some registers that were previously missed,
and omits registers that are write only.
Change-Id: Ic0dedbadaf6969892c0563d9cfd8fa2869008417
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:30 +0000 (10:14 -0700)]
msm/drm: Dynamically locate the clocks from the device tree
Instead of using a fixed list of clock names, use the clock-names
list in the device tree to discover and get the list of clocks
that we need.
Change-Id: Ic0dedbad629743ff078177c301ffda3dbce88d3c
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:30 +0000 (10:14 -0700)]
drm/msm: Reference count address spaces
There are reasons for a memory object to outlive the file descriptor
that created it and so the address space that a buffer object is
attached to must also outlive the file descriptor. Reference count
the address space so that it can remain viable until all the objects
have released their addresses.
Change-Id: Ic0dedbad3769801b62152d81b37f2f43f962d308
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:29 +0000 (10:14 -0700)]
drm/msm: Support per-instance pagetables
Support per-instance pagetables for 5XX targets. Per-instance
pagetables allow each open DRM instance to have its own VM memory
space to prevent accidently or maliciously copying or overwriting
buffers from other instances. It also opens the door for SVM since
any given CPU side address can be more reliably mapped into the
instance's GPU VM space without conflict.
To support this create a new dynamic domain (pagetable) for each open
DRM file and map buffer objects for each instance into that pagetable.
Use the GPU to switch to the pagetable for the instance while doing a
submit.
Change-Id: Ic0dedbad22d157d514ed1628b83e8cded5490dec
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:29 +0000 (10:14 -0700)]
drm/msm: Support dynamic IOMMU domains
Dynamic IOMMU domains allow multiple pagetables to be attached to the
same IOMMU device. These can be used by smart devices like the GPU
that can switch the pagetable dynamically between DRM instances.
Add support for dynamic IOMMU domains if they are enabled and
supported by your friendly neighborhood IOMMU driver.
Change-Id: Ic0dedbaded3a9e57a7fbb8e745c44c183f6b4655
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:28 +0000 (10:14 -0700)]
drm/msm: Pass the MMU domain index in struct msm_file_private
Pass the index of the MMU domain in struct msm_file_private instead
of assuming gpu->id throughout the submit path.
Change-Id: Ic0dedbad3761b0f72ad6b1789f69458896214239
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:28 +0000 (10:14 -0700)]
iommu/arm-smmu: Add support for TTBR1
Allow a domain to opt into allocating and maintaining a TTBR1
pagetable. The size of the TTBR1 region will be the same as
the TTBR0 size with the sign extension bit set on the highest
bit in the region.
By example, given a TTBR0/TTBR1 virtual address range of 36
bits the memory map will look like this:
TTBR0 [0x000000000:0x7FFFFFFFF]
TTBR1 [0x800000000:0xFFFFFFFFF]
The map/unmap operations will automatically use the appropriate
pagetable for the given iova.
Change-Id: Ic0dedbad2b2c58cd9c47ce31356472e0463d4228
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:27 +0000 (10:14 -0700)]
drm/msm: a5xx: Enable 64 bit mode by default
A5XX GPUs can be run in either 32 or 64 bit mode. The GPU registers
and the microcode use 64 bit virtual addressing by default but the
upper 32 bits are ignored if the GPU is in 32 bit mode. There is no
performance disadvantage to remaining in 64 bit mode even if we are
only generating 32 bit addresses so switch over now to prepare for
possibly using addresses above 4G for those targets that support them.
Change-Id: Ic0dedbad7e527c4b1fe87878e943619c5e0ad869
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:27 +0000 (10:14 -0700)]
drm/msm: Add a struct to pass configuration to msm_gpu_init()
The amount of information that we need to pass into msm_gpu_init()
is steadily increasing, so add a new struct to stabilize the function
call and make it easier to add new configuration down the line.
Change-Id: Ic0dedbad6c62d6859c90764245437c222d61f00d
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:26 +0000 (10:14 -0700)]
drm/msm: Implement preemption for A5XX targets
Implement preemption for A5XX targets - this allows multiple
ringbuffers for different priorities with automatic preemption
of a lower priority ringbuffer if a higher one is ready.
Change-Id: Ic0dedbad428360d23768d52b585021237c6bc3d3
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:26 +0000 (10:14 -0700)]
drm/msm: Set IOMMU map attributes
Remove the IOMMU_WRITE bit from buffer objects that are
marked MSM_BO_GPU_READONLY. Add a new flag (MSM_BO_PRIVILEGED)
to pass through IOMMU_PRIV for those IOMMU targets that support
it.
Change-Id: Ic0dedbad8d9d3f461a47ea093fad3fdd90f46535
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:25 +0000 (10:14 -0700)]
drm/msm: Make the value of RB_CNTL (almost) generic
We use a global ringbuffer size and block size for all targets and
at least for 5XX preemption we need to know the value the RB_CNTL
in several locations so it makes sense to caculate it once and use
it everywhere.
The only monkey wrench is that we need to disable the RPTR shadow
for A430 targets but that only needs to be done once and doesn't
affect A5XX so we can or in the value at init time.
Change-Id: Ic0dedbadca31e835f014037ea3f9741048df3b98
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:24 +0000 (10:14 -0700)]
drm/msm: Shadow current pointer in the ring until command is complete
Add a shadow pointer to track the current command being written into
the ring. Don't commit it as 'cur' until the command is submitted.
Because 'cur' is used to construct the software copy of the wptr this
ensures that somebody peeking in on the ring doesn't assume that a
command is inflight while it is being written. This isn't a huge deal
with a single ring (though technically the hangcheck could assume
the system is prematurely busy when it isn't) but it will be rather
important for preemption where the decision to preempt is based
on a non-empty ringbuffer. Without a shadow an aggressive preemption
scheme could assume that the ringbuffer is non empty and switch to it
before the CPU is done writing the command and boom.
Even though preemption won't be supported for all targets because of
the way the code is organized it is simpler to make this generic for
all targets. The extra load for non-preemption targets should be
minimal.
Change-Id: Ic0dedbad83247c3e77de6f4f24bbb97db10e5edd
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:24 +0000 (10:14 -0700)]
drm/msm: Add support for multiple ringbuffers
Add the infrastructure for supporting multiple ringbuffers.
Change-Id: Ic0dedbada90ec5c4c8074ffce33c3fe275b0cda1
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:23 +0000 (10:14 -0700)]
drm/msm: Add a property for the GMEM base
Return the base address of GMEM in virtual address space as
a parameter.
Change-Id: Ic0dedbad3b849052313e4673efcf6c22bc81f21f
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:23 +0000 (10:14 -0700)]
drm/msm: Remove memptrs->wptr
memptrs->wptr seems to be unused. Remove it to avoid
confusing the upcoming preemption code.
Change-Id: Ic0dedbadacef5e866bd37a332019f1133f1def49
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:22 +0000 (10:14 -0700)]
drm/msm: Add hint to DRM_IOCTL_MSM_GEM_INFO to return an object IOVA
Modify the 'pad' member of struct drm_msm_gem_info to 'hint'. If the
user sets 'hint' to non-zero it means that they want a IOVA for the
GEM object instead of a mmap() offset. Return the iova in the 'offset'
member.
Change-Id: Ic0dedbad543df80fdc4b74cd1cd924e9b8534b44
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:22 +0000 (10:14 -0700)]
drm/msm: adreno: Add A540 support
Add support for the A540 GPU which is a revision of the A530 target
with somewhat more complicated power management support.
Change-Id: Ic0dedbadeca628809b6de7c1843f665ecdc427fe
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:21 +0000 (10:14 -0700)]
drm/msm: gpu: Bring in new registers for A540
Bring in a new revision of the rnndb register to fill out some A540
registers.
Change-Id: Ic0dedbad0daf9ad2301479354a83c05bdc301163
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:21 +0000 (10:14 -0700)]
drm/msm: gpu: Move DT probing and configuration to adreno_gpu
In the current code the probed configuration is pretty light and it
can be easily probed at boot time and stored in a config struct.
As more features come online the configuration becomes tougher and
more platform specific. It makes sense to do the configuration in
real time so move the majority of the config over to adreno_gpu and
probe at load.
Change-Id: Ic0dedbade871aae2d39e6b036a5e73e4347fc7ca
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:20 +0000 (10:14 -0700)]
drm/msm: gpu: Use the zap shader on 5XX if we can
The A5XX GPU powers on in "secure" mode. In secure mode the GPU can
only render to buffers that are marked as secure and inaccessible
to the kernel and user through a series of hardware protections. In
practice secure mode is used to draw things like a UI on a secure
video frame.
In order to switch out of secure mode the GPU executes a special
shader that clears out the GMEM and other sensitve registers and
then writes a register. Because the kernel can't be trusted the
shader binary is signed and verified and programmed by the
trustzone using the PIL loader to upload the binary and access
to the special register is blocked with hardware protection.
So in summary, to do secure mode correctly you need 1) a friendly
trustzone, 2) PIL loader support and 3) a verified zap shader.
For targets without secure support there is an out: if the
trustzone doesn't support secure then there are no hardware
protections and we can freely write the SECVID_TRUST register from
the CPU. Unfortunately we don't have any good way to figure out
at runtime if the trustzone is secure or not so we use a cheat.
If there is a zap shader specified in the device tree for the
target, we assume that the trustzone is secure. No zap shader
definition means that the target is not secure. The downside
of course is that if you guess wrong you trigger a XPU violation
which usually ends up in a system crash but thats a problem
that shows up immediately.
Change-Id: Ic0dedbad8738ad1fac8a7bb8d76e1988aa49f2c8
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:20 +0000 (10:14 -0700)]
drm/msm: gpu: Add support for the GPMU
Most 5XX targets have GPMU (Graphics Power Management Unit) that
handles a lot of the heavy lifting for power management including
thermal and limits management and dynamic power collapse. While
the GPMU itself is optional, it is usually nessesary to hit
aggressive power targets.
If the GPMU is to be used a filename and minimum version are
defined in the device tree. The GPMU firmware needs to be loaded
into the GPMU at init time via a shared hardware block of registers.
Using the GPU to write the microcode is more efficient than using the
CPU so at first load create an indirect buffer that can be executed
during subsequent initalization sequences.
After loading the GPMU gets initalized through a shared register
interface and then we mostly get out of its way and let it do
its thing.
Change-Id: Ic0dedbad8d899177919b71500f2e944b187e87c0
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:19 +0000 (10:14 -0700)]
drm/msm: gpu: Add A5XX target support
Add support for the A5XX family of Adreno GPUs.
Change-Id: Ic0dedbad665ef9d0f2cdb32a33eef9fe3fd7aa5c
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:19 +0000 (10:14 -0700)]
drm/msm: Make sure the GPU is valid before we use it
Verify that the GPU is valid before calling any ioctl functions
that might need the priv->gpu member. Standardize the return
code (-ENXIO).
Change-Id: Ic0dedbad015a531b792e0b94cb61e0570b691de8
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:18 +0000 (10:14 -0700)]
drm/msm: Make sure that WPTR stays in bounds
Currently the value written to CP_RB_WPTR is calculated on the fly as
(rb->next - rb->start). But as the code is designed rb->next is wrapped
before writing the commands so if a series of commands happened to
fit perfectly in the ringbuffer, rb->next would end up being equal to
rb->size / 4 and thus result in an out of bounds address to CP_RB_WPTR.
The easiest way to fix this is to mask WPTR when writing it to the
hardware; it makes the hardware happy and the rest of the ringbuffer
math appears to work and there isn't any point in messing with things.
Change-Id: Ic0dedbade543a2253b88acf46a8f8e062ae7faf9
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:18 +0000 (10:14 -0700)]
drm/msm: Make sure that MSM_SUBMIT_BO_FLAGS are set
For every submission buffer object one of MSM_SUBMIT_BO_WRITE
and MSM_SUBMIT_BO_READ must be set (and nothing else). If we
allowed zero then the buffer object would never get queued to
be unreferenced.
Change-Id: Ic0dedbad8a4543428372fe3fef9503cedd1eef6e
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:17 +0000 (10:14 -0700)]
drm/msm: Search for the SMMU device in the node sub-devices
The upstream DT model presumes that the iommu phandle is in the main
GPU device node. The downstream model defines sub-nodes for the
IOMMU devices. In order to get the right device to attach the IOMMU
domain to we need to do a bit of searching.
First, check in the top level node. If that fails, then start walking
the port list passed in the attached function - hopefully one of those
will have the right device - if found, use that to attach the domain
and breathe normally.
Change-Id: Ic0dedbad4a1852d2ff204031bd360e0b7960805a
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:17 +0000 (10:14 -0700)]
drm/msm: Use 64 bit containers for iovas
Newer Adreno GPUs are able to support 64 bit virtual addressing. To
prepare for this brave new world switch all IOVA related variables
and members to a uint64_t container. This is harmless for the
display and older targets that do not have 64 bit addressing because
a 32 bit address is just a 64 bit address with lots of zeros. To
avoid ambiguity and compiler oddness make sure to use
lower_32_bits() and upper_32_bits() everywhere the IOVA is used to
ensure that you get what you expect.
Change-Id: Ic0dedbad23322fae32509c1f4d75d9b4e2863081
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:16 +0000 (10:14 -0700)]
drm/msm: get an iova from the address space instead of an id
In the future we won't have a fixed set of addresses spaces.
Instead of going through the effort of assigning a ID for each
address space just use the address space itself as a token for
getting / putting an iova.
This forces a few changes in the gem object however: instead
of using a simple index into a list of domains, we need to
maintain a list of them. Luckily the list will be pretty small;
even with dynamic address spaces we wouldn't ever see more than
two or three.
Change-Id: Ic0dedbad4495f02a21135217f3605b93f8b8dfea
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:16 +0000 (10:14 -0700)]
drm/msm: Ask PM_QOS to set the interrupt affnity
PM_QOS will put the interrupt where it wants to and we're okay
with that.
Change-Id: Ic0dedbad5294d51a55125a0021f7dcc3b185de02
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:15 +0000 (10:14 -0700)]
drm/msm: Disable interrupts during init
Disable the interrupt during the init sequence to avoid having
interrupts fired for errors and other things that we are not
ready to handle while initializing.
Change-Id: Ic0dedbad972f25586e792478f9c96c4af7c31d17
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:15 +0000 (10:14 -0700)]
drm/msm: gpu Add new gpu register read/write functions
Add some new functions to manipulate GPU registers. gpu_read64 and
gpu_write64 can read/write a 64 bit value to two 32 bit registers.
For 4XX and older these are normally perfcounter registers, but
future targets will use 64 bit addressing so there will be many
more spots where a 64 bit read and write are needed.
gpu_rmw() does a read/modify/write on a 32 bit register given a mask
and bits to OR in.
Change-Id: Ic0dedbadb83d3ac46f7e463c9c901d4f94a7bb58
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:14 +0000 (10:14 -0700)]
drm/msm: gpu: Cut down the list of "generic" registers to the ones we use
There are very few register accesses in the common code. Cut down
the list of common registers to just those that are used. This
saves const space and saves us the effort of maintaining registers
for A3XX and A4XX that don't exist or are unused.
Change-Id: Ic0dedbadb4dccbba284e9badf2f52f3a72594581
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Jordan Crouse [Mon, 13 Feb 2017 17:14:13 +0000 (10:14 -0700)]
drm/msm: gpu: Add OUT_TYPE4 and OUT_TYPE7
Add helper functions for TYPE4 and TYPE7 ME opcodes that replace
TYPE0 and TYPE3 starting on the A5XX targets.
Change-Id: Ic0dedbad114e28bdbcba55a788c6307b48e14675
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Manaf Meethalavalappu Pallikunhi [Mon, 20 Feb 2017 16:49:26 +0000 (22:19 +0530)]
ARM: dts: msm: Add LMH DCVSh mitigation support for KTM for sdm630
Add LMH DCVSh mitigation support for kernel thermal driver for sdm630.
It enables KTM to request frequency mitigation to LMH DCVSh hardware
block.
Change-Id: Ia546f004416dff2da7c6560b8e582eac563d3f8e
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
Manaf Meethalavalappu Pallikunhi [Mon, 20 Feb 2017 16:45:01 +0000 (22:15 +0530)]
ARM: dts: msm: Enable LMH DCVSh driver for sdm630
Enable LMH DCVSh driver for sdm630. It adds information about
the interrupt generated by the LMH DCVSh block for sdm630.
Change-Id: I16a5f9f0737e64b4ed0e39e0624afb64fbf623e7
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
Maulik Shah [Mon, 6 Feb 2017 10:17:08 +0000 (15:47 +0530)]
ARM: dts: msm: Update LPM parameter values for sdm660
Update LPM parameters latency, ss power, time overhead and
energy-overhead with the values measured at minimum frequency.
Change-Id: Id5fc176a02978c54e4cb4faec4dffca83a7cbea5
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>