OSDN Git Service
Paul Robinson [Tue, 10 Jul 2018 14:41:54 +0000 (14:41 +0000)]
Support -fdebug-prefix-map in llvm-mc. This is useful to omit the
debug compilation dir when compiling assembly files with -g.
Part of PR38050.
Patch by Siddhartha Bagaria!
Differential Revision: https://reviews.llvm.org/D48988
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336680
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 10 Jul 2018 14:27:55 +0000 (14:27 +0000)]
[InstCombine] drop poison flags when shuffle mask undef propagates to constant
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336679
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Tue, 10 Jul 2018 14:05:55 +0000 (14:05 +0000)]
[AArch64][SVE] Asm: Support for predicated unary operations.
This patch adds support for the following instructions:
CLS (Count Leading Sign bits)
CLZ (Count Leading Zeros)
CNT (Count non-zero bits)
CNOT (Logically invert boolean condition in vector)
NOT (Bitwise invert vector)
FABS (Floating-point absolute value)
FNEG (Floating-point negate)
All operations are predicated and unary, e.g.
clz z0.s, p0/m, z1.s
- CLS, CLZ, CNT, CNOT and NOT have variants for 8, 16, 32
and 64 bit elements.
- FABS and FNEG have variants for 16, 32 and 64 bit elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336677
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Tue, 10 Jul 2018 14:03:41 +0000 (14:03 +0000)]
Reapply "AMDGPU: Force inlining if LDS global address is used"
This reverts commit r336623
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336675
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 10 Jul 2018 13:33:26 +0000 (13:33 +0000)]
[InstCombine] allow more shuffle-binop folds with safe constants
The case with 2 variables is more complicated than the case where
we eliminate the shuffle entirely because a shuffle with an undef
mask element creates an undef result.
I'm not aware of any current analysis/transform that recognizes that
undef propagating to a div/rem/shift, but we have to guard against
the possibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336668
91177308-0d34-0410-b5e6-
96231b3b80d8
Anastasis Grammenos [Tue, 10 Jul 2018 13:29:50 +0000 (13:29 +0000)]
[DebugInfo][LoopVectorize] Preserve DL in induction PHI and Add
Differential Revision: https://reviews.llvm.org/D48968
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336667
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 10 Jul 2018 13:18:16 +0000 (13:18 +0000)]
[DAGCombiner] visitREM - call visitSDIVLike/visitUDIVLike directly to avoid recursive combining.
As suggested by @efriedma on D48975 use the visitSDIVLike/visitUDIVLike functions introduced at rL336656.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336664
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Tue, 10 Jul 2018 12:57:49 +0000 (12:57 +0000)]
[Hexagon] Add implicit uses even when untied explicit uses are present
An explicit untied use is not sufficient to maintain liveness of a
register redefined in a predicated instruction. For example
%1 = COPY %0
...
%1 = A2_paddif %2, %1, 1
could become
$r1 = COPY $r0
...
$r1 = A2_paddif $p0, $r1, 1
and later
$r1 = COPY $r0 ;; this is not really dead!
...
$r1 = A2_paddif $p0, $r0, 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336662
91177308-0d34-0410-b5e6-
96231b3b80d8
Karl-Johan Karlsson [Tue, 10 Jul 2018 12:06:16 +0000 (12:06 +0000)]
[LowerSwitch] Fixed faulty PHI nodes
Summary:
Fixed two cases of where PHI nodes need to be updated by lowerswitch.
When lowerswitch find out that the switch default branch is not
reachable it remove the old default and replace it with the most
popular block from the cases, but it forget to update the PHI
nodes in the default block.
The PHI nodes also need to be updated when the switch is replaced
with a single branch.
Reviewers: hans, reames, arsenm
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D47203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336659
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam McCall [Tue, 10 Jul 2018 11:51:26 +0000 (11:51 +0000)]
[Support] Harded JSON against invalid UTF-8.
Parsing invalid UTF-8 input is now a parse error.
Creating JSON values from invalid UTF-8 now triggers an assertion, and
(in no-assert builds) substitutes the unicode replacement character.
Strings retrieved from json::Value are always valid UTF-8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336657
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 10 Jul 2018 11:38:00 +0000 (11:38 +0000)]
[DAGCombiner] Split SDIV/UDIV optimization expansions from the rest of the combines. NFCI.
As suggested by @efriedma on D48975, this patch separates the BuildDiv/Pow2 style optimizations from the rest of the visitSDIV/visitUDIV to make it easier to reuse the combines and will allow us to avoid some rather nasty node recursive combining in visitREM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336656
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Tue, 10 Jul 2018 10:45:46 +0000 (10:45 +0000)]
[VPlan] Add VPlanTestBase.h with helper class to build VPlan for tests.
Reviewers: dcaballe, hsaito, rengolin
Reviewed By: dcaballe
Differential Revision: https://reviews.llvm.org/D49032
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336653
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 10 Jul 2018 09:46:57 +0000 (09:46 +0000)]
Fix MSVC "signed/unsigned mismatch" warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336649
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Tue, 10 Jul 2018 08:57:04 +0000 (08:57 +0000)]
[PM/Unswitch] Fix unused variable in r336646.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336647
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Tue, 10 Jul 2018 08:36:05 +0000 (08:36 +0000)]
[PM/Unswitch] Fix a collection of closely related issues with trivial
switch unswitching.
The core problem was that the way we handled unswitching trivial exit
edges through the default successor of a switch. For some reason
I thought the right way to do this was to add a block containing
unreachable and point the default successor at this block. In
retrospect, this has an amazing number of problems.
The first issue is the one that this pass has always worked around -- we
have to *detect* such edges and avoid unswitching them again. This
seemed pretty easy really. You juts look for an edge to a block
containing unreachable. However, this pattern is woefully unsound. So
many things can break it. The amazing thing is that I found a test case
where *simple-loop-unswitch itself* breaks this! When we do
a *non-trivial* unswitch of a switch we will end up splitting this exit
edge. The result will be a default successor that is an exit and
terminates in ... a perfectly normal branch. So the first test case that
I started trying to fix is added to the nontrivial test cases. This is
a ridiculous example that did just amazing things previously. With just
unswitch, it would create 10+ copies of this stuff stamped out. But if
you combine it *just right* with a bunch of other passes (like
simplify-cfg, loop rotate, and some LICM) you can get it to do this
infinitely. Or at least, I never got it to finish. =[
This, in turn, uncovered another related issue. When we are manipulating
these switches after doing a trivial unswitch we never correctly updated
PHI nodes to reflect our edits. As soon as I started changing how these
edges were managed, it became obvious there were more issues that
I couldn't realistically leave unaddressed, so I wrote more test cases
around PHI updates here and ensured all of that works now.
And this, in turn, required some adjustment to how we collect and manage
the exit successor when it is the default successor. That showed a clear
bug where we failed to include it in our search for the outer-most loop
reached by an unswitched exit edge. This was actually already tested and
the test case didn't work. I (wrongly) thought that was due to SCEV
failing to analyze the switch. In fact, it was just a simple bug in the
code that skipped the default successor. While changing this, I handled
it correctly and have updated the test to reflect that we now get
precise SCEV analysis of trip counts for the outer loop in one of these
cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336646
91177308-0d34-0410-b5e6-
96231b3b80d8
Mikhail Dvoretckii [Tue, 10 Jul 2018 08:26:54 +0000 (08:26 +0000)]
[X86] Fast-isel tests for lowered truncation intrinsics
This patch adds fast-isel tests for the IR patterns produced for truncation
intrinsics in rC336643.
Differential Revision: https://reviews.llvm.org/D48822
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336645
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 10 Jul 2018 07:58:33 +0000 (07:58 +0000)]
[X86][SSE] Prefer BLEND(SHL(v,c1),SHL(v,c2)) over MUL(v, c3)
Now that rL336250 has landed, we should prefer 2 immediate shifts + a shuffle blend over performing a multiply. Despite the increase in instructions, this is quicker (especially for slow v4i32 multiplies), avoid loads and constant pool usage. It does mean however that we increase register pressure. The code size will go up a little but by less than what we save on the constant pool data.
This patch also adds support for v16i16 to the BLEND(SHIFT(v,c1),SHIFT(v,c2)) combine, and also prevents blending on pre-SSE41 shifts if it would introduce extra blend masks/constant pool usage.
Differential Revision: https://reviews.llvm.org/D48936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336642
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 10 Jul 2018 07:17:41 +0000 (07:17 +0000)]
[X86] Regenerate vector-shuffle-512-v8.ll so the script will merge the 32 and 64 bit checks together. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336641
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 10 Jul 2018 06:19:54 +0000 (06:19 +0000)]
[X86] Use IsProfitableToFold to block vinsertf128rm in favor of insert_subreg instead of artifically increasing pattern complexity to give priority.
This is a much more direct way to solve the issue than just giving extra priority.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336639
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 10 Jul 2018 05:31:42 +0000 (05:31 +0000)]
[X86] Remove some seemingly unnecessary patterns.
We're missing the EVEX equivalents of these patterns and seem to get along fine.
I think we end up with X86vzload for the obvious IR cases that would produce this DAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336638
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 10 Jul 2018 00:49:50 +0000 (00:49 +0000)]
[X86] Add back GCCBuiltin on mask_div_ss/sd_round.
We no longer need custom handling in clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336627
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 10 Jul 2018 00:49:49 +0000 (00:49 +0000)]
[X86] Correct vfixupimm load patterns to look for an integer load, not a floating point load bitcasted to integer.
DAG combine wouldn't let a floating point load bitcasted to integer exist. It would just be an integer load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336626
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 10 Jul 2018 00:49:47 +0000 (00:49 +0000)]
[X86] Add test cases that show failure to fold load into vfixupimm instructions due to bad isel pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336625
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 10 Jul 2018 00:49:45 +0000 (00:49 +0000)]
[X86] Remove FloatVT from X86VectorVTInfo in X86InstrAVX512.td
The only places it was used where places where VT was the same as FloatVT. So switch those uses to VT and drop it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336624
91177308-0d34-0410-b5e6-
96231b3b80d8
Vlad Tsyrklevich [Tue, 10 Jul 2018 00:46:07 +0000 (00:46 +0000)]
Revert "AMDGPU: Force inlining if LDS global address is used"
This reverts commit r336587, it was causing test failures on the
sanitizer bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336623
91177308-0d34-0410-b5e6-
96231b3b80d8
Wolfgang Pieb [Tue, 10 Jul 2018 00:10:11 +0000 (00:10 +0000)]
[DWARF][NFC] Refactor range list emission to use a static helper
This is prep for DWARF v5 range list emission. Emission of a single range list is moved
to a static helper function.
Reviewer: jdevlieghere
Differential Revision: https://reviews.llvm.org/D49098
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336621
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Mon, 9 Jul 2018 23:22:47 +0000 (23:22 +0000)]
[InstCombine] allow more shuffle folds using safe constants
getSafeVectorConstantForBinop() was calling getBinOpIdentity() assuming
that the constant we wanted was operand 1 (RHS). That's wrong, but I
don't think we could expose a bug or even a suboptimal fold from that
because the callers have other guards for any binop that would have
been affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336617
91177308-0d34-0410-b5e6-
96231b3b80d8
Heejin Ahn [Mon, 9 Jul 2018 22:30:51 +0000 (22:30 +0000)]
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336615
91177308-0d34-0410-b5e6-
96231b3b80d8
Manoj Gupta [Mon, 9 Jul 2018 22:27:23 +0000 (22:27 +0000)]
llvm: Add support for "-fno-delete-null-pointer-checks"
Summary:
Support for this option is needed for building Linux kernel.
This is a very frequently requested feature by kernel developers.
More details : https://lkml.org/lkml/2018/4/4/601
GCC option description for -fdelete-null-pointer-checks:
This Assume that programs cannot safely dereference null pointers,
and that no code or data element resides at address zero.
-fno-delete-null-pointer-checks is the inverse of this implying that
null pointer dereferencing is not undefined.
This feature is implemented in LLVM IR in this CL as the function attribute
"null-pointer-is-valid"="true" in IR (Under review at D47894).
The CL updates several passes that assumed null pointer dereferencing is
undefined to not optimize when the "null-pointer-is-valid"="true"
attribute is present.
Reviewers: t.p.northover, efriedma, jyknight, chandlerc, rnk, srhines, void, george.burgess.iv
Reviewed By: efriedma, george.burgess.iv
Subscribers: eraman, haicheng, george.burgess.iv, drinkcat, theraven, reames, sanjoy, xbolva00, llvm-commits
Differential Revision: https://reviews.llvm.org/D47895
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336613
91177308-0d34-0410-b5e6-
96231b3b80d8
Rui Ueyama [Mon, 9 Jul 2018 22:26:49 +0000 (22:26 +0000)]
Use StringRef instead of `const char *`.
I don't think there's a need to use `const char *`. In most (probably all?)
cases, we need a length of a name later, so discarding a length will
lead to a wasted effort.
Differential Revision: https://reviews.llvm.org/D49046
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336612
91177308-0d34-0410-b5e6-
96231b3b80d8
George Burgess IV [Mon, 9 Jul 2018 22:21:16 +0000 (22:21 +0000)]
Make llvm.objectsize more conservative with null
In non-zero address spaces, we were reporting that an object at `null`
always occupies zero bytes. This is incorrect in many cases, so just
return `unknown` in those cases for now.
Differential Revision: https://reviews.llvm.org/D48860
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336611
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Mon, 9 Jul 2018 20:54:36 +0000 (20:54 +0000)]
[ORC] Rename MaterializationResponsibility::delegate to replace and add a new
delegate method (and unit test).
The name 'replace' better captures what the old delegate method did: it
returned materialization responsibility for a set of symbols to the VSO.
The new delegate method delegates responsibility for a set of symbols to a new
MaterializationResponsibility instance. This can be used to split responsibility
between multiple threads, or multiple materialization methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336603
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Mon, 9 Jul 2018 20:52:07 +0000 (20:52 +0000)]
Fix line endings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336602
91177308-0d34-0410-b5e6-
96231b3b80d8
Stefan Pintilie [Mon, 9 Jul 2018 20:38:40 +0000 (20:38 +0000)]
[Power9] Add __float128 builtins for Rounding Operations
Added __float128 support for a number of rounding operations:
trunc
rint
nearbyint
round
floor
ceil
Differential Revision: https://reviews.llvm.org/D48415
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336601
91177308-0d34-0410-b5e6-
96231b3b80d8
Heejin Ahn [Mon, 9 Jul 2018 20:18:21 +0000 (20:18 +0000)]
[WebAssembly] Improve readability of load/stores and tests. NFC.
Summary:
- Changed variable/function names to be more consistent
- Improved comments in test files
- Added more tests
- Fixed a few typos
- Misc. cosmetic changes
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49087
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336598
91177308-0d34-0410-b5e6-
96231b3b80d8
Stefan Pintilie [Mon, 9 Jul 2018 20:09:22 +0000 (20:09 +0000)]
[Power9] [LLVM] Add __float128 support for trunc to double round to odd
Add support for this builtin:
double builtin_truncf128_round_to_odd(float128)
Differential Revision: https://reviews.llvm.org/D48483
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336595
91177308-0d34-0410-b5e6-
96231b3b80d8
Mark Searles [Mon, 9 Jul 2018 20:07:03 +0000 (20:07 +0000)]
RenameIndependentSubregs: Fix handling of undef tied operands
Ensure that, if updating a tied operand pair, to only update
that pair.
Differential Revision: https://reviews.llvm.org/D49052
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336593
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Mon, 9 Jul 2018 19:33:40 +0000 (19:33 +0000)]
[globalisel][irtranslator] Add support for atomicrmw and (strong) cmpxchg
Summary:
This patch adds support for the atomicrmw instructions and the strong
cmpxchg instruction to the IRTranslator.
I've left out weak cmpxchg because LangRef.rst isn't entirely clear on what
difference it makes to the backend. As far as I can tell from the code, it
only matters to AtomicExpandPass which is run at the LLVM-IR level.
Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar, volkan, javed.absar
Reviewed By: qcolombet
Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D40092
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336589
91177308-0d34-0410-b5e6-
96231b3b80d8
Mark Searles [Mon, 9 Jul 2018 19:28:14 +0000 (19:28 +0000)]
[AMDGPU][Waitcnt] fix "comparison of integers of different signs" build error
Build error on Android; reported by and fix provided by (thanks) by Mauro Rossi <issor.oruam@gmail.com>
Fixes the following building error:
external/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp:1903:61:
error: comparison of integers of different signs:
'typename iterator_traits<__wrap_iter<MachineBasicBlock **> >::difference_type'
(aka 'int') and 'unsigned int' [-Werror,-Wsign-compare]
BlockWaitcntProcessedSet.end(), &MBB) < Count)) {
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^ ~~~~~
1 error generated.
Differential Revision: https://reviews.llvm.org/D49089
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336588
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Mon, 9 Jul 2018 19:22:22 +0000 (19:22 +0000)]
AMDGPU: Force inlining if LDS global address is used
These won't work for the forseeable future. These aren't allowed
from OpenCL, but IPO optimizations can make them appear.
Also directly set the attributes on functions, regardless
of the linkage rather than cloning functions like before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336587
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Mon, 9 Jul 2018 19:06:42 +0000 (19:06 +0000)]
[X86][TLI] DAGCombine: Unfold variable bit-clearing mask to two shifts.
Summary:
This adds a reverse transform for the instcombine canonicalizations
that were added in D47980, D47981.
As discussed later, that was worse at least for the code size,
and potentially for the performance, too.
https://rise4fun.com/Alive/Zmpl
Reviewers: craig.topper, RKSimon, spatel
Reviewed By: spatel
Subscribers: reames, llvm-commits
Differential Revision: https://reviews.llvm.org/D48768
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336585
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Pfaffe [Mon, 9 Jul 2018 18:51:50 +0000 (18:51 +0000)]
[Utils] Fix gdb pretty printers to work with Python 3.
Reiterate D23202 for container printers added after the change landed.
Differential Revision: https://reviews.llvm.org/D46578
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336580
91177308-0d34-0410-b5e6-
96231b3b80d8
Stefan Pintilie [Mon, 9 Jul 2018 18:50:06 +0000 (18:50 +0000)]
[Power9] Add __float128 builtins for Round To Odd
GCC has builtins for these round to odd instructions:
__float128 __builtin_sqrtf128_round_to_odd (__float128)
__float128 __builtin_{add,sub,mul,div}f128_round_to_odd (__float128, __float128)
__float128 __builtin_fmaf128_round_to_odd (__float128, __float128, __float128)
Differential Revision: https://reviews.llvm.org/D47550
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336578
91177308-0d34-0410-b5e6-
96231b3b80d8
Maksim Panchenko [Mon, 9 Jul 2018 18:45:38 +0000 (18:45 +0000)]
[DebugInfo] Change default value of FDEPointerEncoding
Summary:
If the encoding is not specified in CIE augmentation string, then it
should be DW_EH_PE_absptr instead of DW_EH_PE_omit.
Reviewers: ruiu, MaskRay, plotfi, rafauler
Reviewed By: MaskRay
Subscribers: rafauler, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D49000
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336577
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 9 Jul 2018 18:23:55 +0000 (18:23 +0000)]
[SelectionDAG] Add VT consistency checks to the creation of ISD::FMA.
This is similar to what is done for binops. I don't know if this would have helped us catch the bug fixed in r336566 earlier or not, but I figured it couldn't hurt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336576
91177308-0d34-0410-b5e6-
96231b3b80d8
Steven Wu [Mon, 9 Jul 2018 17:57:48 +0000 (17:57 +0000)]
Add bitcode compatibility test for 6.0
Summary:
Add bitcode compatibility test for 6.0. On top of the normal disassemble
test, also runs the verifier to make sure simple 6.0 bitcode can pass
the current IR verifier.
Reviewers: vsk
Reviewed By: vsk
Subscribers: dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D49086
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336574
91177308-0d34-0410-b5e6-
96231b3b80d8
Diego Caballero [Mon, 9 Jul 2018 17:52:49 +0000 (17:52 +0000)]
[LoopInfo] Port loop exit interfaces from Loop to LoopBase
This patch ports hasDedicatedExits, getUniqueExitBlocks and
getUniqueExitBlock in Loop to LoopBase so that they can be used
from other LoopBase sub-classes.
Reviewers: chandlerc, sanjoy, hfinkel, fhahn
Reviewed By: chandlerc
Differential Revision: https://reviews.llvm.org/D48817
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336572
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Mon, 9 Jul 2018 17:48:08 +0000 (17:48 +0000)]
[InstCombine] correct test comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336570
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 9 Jul 2018 17:43:24 +0000 (17:43 +0000)]
[X86] In combineFMA, make sure we bitcast the result of isFNEG back the expected type before creating the new FMA node.
Previously, we were creating malformed SDNodes, but nothing noticed because the type constraints prevented isel from noticing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336566
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Mon, 9 Jul 2018 17:38:00 +0000 (17:38 +0000)]
[X86][AVX] Regenerate AVX1 fast-isel tests.
Let the update script merge 32/64 tests where possible
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336565
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Mon, 9 Jul 2018 17:20:20 +0000 (17:20 +0000)]
[InstCombine] avoid extra poison when moving shift above shuffle
As discussed in D49047 / D48987, shift-by-undef produces poison,
so we can't use undef vector elements in that case..
Note that we need to extend this for poison-generating flags,
and there's a proposal to create poison from FMF in D47963,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336562
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Mon, 9 Jul 2018 16:58:48 +0000 (16:58 +0000)]
[dsymutil] Add support for outputting assembly
When implementing the DWARF accelerator tables in dsymutil I ran into an
assertion in the assembler. Debugging these kind of issues is a lot
easier when looking at the assembly instead of debugging the assembler
itself. Since it's only a matter of creating an AsmStreamer instead of a
MCObjectStreamer it made sense to turn this into a (hidden) dsymutil
feature.
Differential revision: https://reviews.llvm.org/D49079
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336561
91177308-0d34-0410-b5e6-
96231b3b80d8
Steven Wu [Mon, 9 Jul 2018 16:52:05 +0000 (16:52 +0000)]
[BitcodeReader] Infer the correct runtime preemption for GlobalValue
Summary:
To allow bitcode built by old compiler to pass the current verifer,
BitcodeReader needs to auto infer the correct runtime preemption from
linkage and visibility for GlobalValues.
Since llvm-6.0 bitcode already contains the new field but can be
incorrect in some cases, the attribute needs to be recomputed all the
time in BitcodeReader. This will make all the GVs has dso_local marked
correctly if read from bitcode, and it should still allow the verifier
to catch mistakes in optimization passes.
This should fix PR38009.
Reviewers: sfertile, vsk
Reviewed By: vsk
Subscribers: dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D49039
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336560
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Mon, 9 Jul 2018 16:16:51 +0000 (16:16 +0000)]
[InstCombine] generalize safe vector constant utility
This is almost NFC, but there could be some case where the original
code had undefs in the constants (rather than just the shuffle mask),
and we'll use safe constants rather than undefs now.
The FIXME noted in foldShuffledBinop() is already visible in existing
tests, so correcting that is the next step.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336558
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 9 Jul 2018 16:03:02 +0000 (16:03 +0000)]
[X86] Remove some patterns that include a bitcast of a floating point load to an integer type.
DAG combine should have converted the type of the load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336557
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 9 Jul 2018 16:03:01 +0000 (16:03 +0000)]
[X86] Remove some patterns that seems to be unreachable.
These patterns mapped (v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))) to a MOVSD and an zeroing XOR. But the complexity of a pattern for (v2f64 (X86vzmovl (v2f64))) that selects MOVQ is artificially and hides this MOVSD pattern.
Weirder still, the SSE version of the pattern was explicitly blocked on SSE41, but yet we had copied it to AVX and AVX512.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336556
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 9 Jul 2018 16:02:59 +0000 (16:02 +0000)]
[X86] Remove some seemingly unnecessary AddedComplexity lines.
Looking at the generated tables this didn't seem to make an obvious difference in pattern priority.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336555
91177308-0d34-0410-b5e6-
96231b3b80d8
Diego Caballero [Mon, 9 Jul 2018 15:57:09 +0000 (15:57 +0000)]
[VPlan][LV] Introduce condition bit in VPBlockBase
This patch introduces a VPValue in VPBlockBase to represent the condition
bit that is used as successor selector when a block has multiple successors.
This information wasn't necessary until now, when we are about to introduce
outer loop vectorization support in VPlan code gen.
Reviewers: fhahn, rengolin, mkuper, hfinkel, mssimpso
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D48814
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336554
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Mon, 9 Jul 2018 15:22:08 +0000 (15:22 +0000)]
[AArch64][SVE] Asm: Support for CNT(B|H|W|D) and CNTP instructions.
This patch adds support for the following instructions:
CNTB CNTH - Determine the number of active elements implied by
CNTW CNTD the named predicate constant, multiplied by an
immediate, e.g.
cnth x0, vl8, #16
CNTP - Count active predicate elements, e.g.
cntp x0, p0, p1.b
counts the number of active elements in p1, predicated
by p0, and stores the result in x0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336552
91177308-0d34-0410-b5e6-
96231b3b80d8
Xin Tong [Mon, 9 Jul 2018 14:53:37 +0000 (14:53 +0000)]
[CVP] Handle calls with void return value. No need to create CVPLattice state for it.
Summary:
Tests: 10
Metric: compile_time
Program unpatch-result patch-result diff
Bullet/bullet 32.39 30.54 -5.7%
SPASS/SPASS 18.14 17.25 -4.9%
mafft/pairlocalalign 12.10 11.64 -3.8%
ClamAV/clamscan 19.21 19.63 2.2%
7zip/7zip-benchmark 49.55 48.85 -1.4%
kimwitu++/kc 15.68 15.87 1.2%
lencod/lencod 21.13 21.34 1.0%
consumer-typeset/consumer-typeset 13.65 13.62 -0.2%
tramp3d-v4/tramp3d-v4 29.88 29.92 0.1%
sqlite3/sqlite3 18.48 18.46 -0.1%
unpatch-result patch-result diff
count 10.000000 10.000000 10.000000
mean 23.022000 22.712400 -0.011671
std 11.362831 11.094183 0.027338
min 12.104000 11.640000 -0.057298
25% 16.299000 16.214000 -0.032282
50% 18.844000 19.048000 -0.001350
75% 27.689000 27.774000 0.007752
max 49.552000 48.852000 0.021861
I also tested only this pass by concatenating all the code from the
llvm/lib/Analysis/ folder and do clang -g followed by opt. I get close to 20% speedup
for the pass. I expect a majority of the gain come from skipping the dbg intrinsics.
Before patch (opt -time-passes -called-value-propagation):
============
===-------------------------------------------------------------------------===
... Pass execution timing report ...
===-------------------------------------------------------------------------===
Total Execution Time: 3.8303 seconds (3.8279 wall clock)
---User Time--- --System Time-- --User+System-- ---Wall Time--- ---
Name ---
2.0768 ( 57.3%) 0.0990 ( 48.0%) 2.1757 ( 56.8%) 2.1757 ( 56.8%) Bitcode
Writer
0.8444 ( 23.3%) 0.0600 ( 29.1%) 0.9044 ( 23.6%) 0.9044 ( 23.6%) Called
Value Propagation
0.7031 ( 19.4%) 0.0472 ( 22.9%) 0.7502 ( 19.6%) 0.7478 ( 19.5%) Module
Verifier
3.6242 (100.0%) 0.2062 (100.0%) 3.8303 (100.0%) 3.8279 (100.0%) Total
After patch (opt -time-passes -called-value-propagation):
============
===-------------------------------------------------------------------------===
... Pass execution timing report ...
===-------------------------------------------------------------------------===
Total Execution Time: 3.6605 seconds (3.6579 wall clock)
---User Time--- --System Time-- --User+System-- ---Wall Time--- ---
Name ---
2.0716 ( 59.7%) 0.0990 ( 52.5%) 2.1705 ( 59.3%) 2.1706 ( 59.3%) Bitcode
Writer
0.7144 ( 20.6%) 0.0300 ( 15.9%) 0.7444 ( 20.3%) 0.7444 ( 20.4%) Called
Value Propagation
0.6859 ( 19.8%) 0.0596 ( 31.6%) 0.7455 ( 20.4%) 0.7429 ( 20.3%) Module
Verifier
3.4719 (100.0%) 0.1886 (100.0%) 3.6605 (100.0%) 3.6579 (100.0%) Total
Reviewers: davide, mssimpso
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336551
91177308-0d34-0410-b5e6-
96231b3b80d8
Stefan Pintilie [Mon, 9 Jul 2018 13:36:14 +0000 (13:36 +0000)]
[Power9] Add __float128 support for compare operations
Added handling for the select f128.
Differential Revision: https://reviews.llvm.org/D48294
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336548
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Mon, 9 Jul 2018 13:23:41 +0000 (13:23 +0000)]
[AArch64][SVE] Asm: Support for remaining shift instructions.
This patch completes support for shifts, which include:
- LSL - Logical Shift Left
- LSLR - Logical Shift Left, Reversed form
- LSR - Logical Shift Right
- LSRR - Logical Shift Right, Reversed form
- ASR - Arithmetic Shift Right
- ASRR - Arithmetic Shift Right, Reversed form
- ASRD - Arithmetic Shift Right for Divide
In the following variants:
- Predicated shift by immediate - ASR, LSL, LSR, ASRD
e.g.
asr z0.h, p0/m, z0.h, #1
(active lanes of z0 shifted by #1)
- Unpredicated shift by immediate - ASR, LSL*, LSR*
e.g.
asr z0.h, z1.h, #1
(all lanes of z1 shifted by #1, stored in z0)
- Predicated shift by vector - ASR, LSL*, LSR*
e.g.
asr z0.h, p0/m, z0.h, z1.h
(active lanes of z0 shifted by z1, stored in z0)
- Predicated shift by vector, reversed form - ASRR, LSLR, LSRR
e.g.
lslr z0.h, p0/m, z0.h, z1.h
(active lanes of z1 shifted by z0, stored in z0)
- Predicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, p0/m, z0.h, z1.d
(active lanes of z0 shifted by wide elements of vector z1)
- Unpredicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, z1.h, z2.d
(all lanes of z1 shifted by wide elements of z2, stored in z0)
*Variants added in previous patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336547
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Mon, 9 Jul 2018 13:21:46 +0000 (13:21 +0000)]
[InstCombine] fix shuffle-of-binops transform to avoid poison/undef
As noted in D48987, there are many different ways for this transform to go wrong.
In particular, the poison potential for shifts means we have to more careful with those ops.
I added tests to make that behavior visible for all of the different cases that I could find.
This is a partial fix. To make this review easier, I did not make changes for the single binop
pattern (handled in foldSelectShuffleWith1Binop()). I also left out some potential optimizations
noted with TODO comments. I'll follow-up once we're confident that things are correct here.
The goal is to correct all marked FIXME tests to either avoid the shuffle transform or do it safely.
Note that distinguishing when the shuffle mask contains undefs and using getBinOpIdentity() allows
for some improvements to div/rem patterns, so there are wins along with the missed opportunities
and fixes.
Differential Revision: https://reviews.llvm.org/D49047
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336546
91177308-0d34-0410-b5e6-
96231b3b80d8
Stefan Maksimovic [Mon, 9 Jul 2018 13:06:44 +0000 (13:06 +0000)]
[mips] Addition of the [d]rem and [d]remu instructions
Related to http://reviews.llvm.org/D15772
Depends on http://reviews.llvm.org/D16889
Adds [D]REM[U] instructions.
Patch By: Srdjan Obucina
Contributions from: Simon Dardis
Differential Revision: https://reviews.llvm.org/D17036
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336545
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Mon, 9 Jul 2018 12:32:56 +0000 (12:32 +0000)]
[AArch64][SVE] Asm: Support for TBL instruction.
Support for SVE's TBL instruction for programmable table
lookup/permute using vector of element indices, e.g.
tbl z0.d, { z1.d }, z2.d
stores elements from z1, indexed by elements from z2, into z0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336544
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Mon, 9 Jul 2018 12:30:55 +0000 (12:30 +0000)]
[llvm-mca] report an error if the assembly sequence contains an unsupported instruction.
This is a short-term fix for PR38093.
For now, we llvm::report_fatal_error if the instruction builder finds an
unsupported instruction in the instruction stream.
We need to revisit this fix once we start addressing PR38101.
Essentially, we need a better framework for error handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336543
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam McCall [Mon, 9 Jul 2018 12:26:09 +0000 (12:26 +0000)]
[Support] Allow JSON serialization of Optional<T> for supported T.
This is ported from r333881 to JSON's new home.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336542
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam McCall [Mon, 9 Jul 2018 12:16:40 +0000 (12:16 +0000)]
[Support] Make JSON handle doubles and int64s losslessly
Summary:
This patch adds a new "integer" ValueType, and renames Number -> Double.
This allows us to preserve the full precision of int64_t when parsing integers
from the wire, or constructing from an integer.
The API is unchanged, other than giving asInteger() a clearer contract.
In addition, always output doubles with enough precision that parsing will
reconstruct the same double.
Reviewers: simon_tatham
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336541
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam McCall [Mon, 9 Jul 2018 10:43:32 +0000 (10:43 +0000)]
[Support] Fix GCC compile after r336534
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336537
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Mon, 9 Jul 2018 10:30:48 +0000 (10:30 +0000)]
[PM/Unswitch] Fix a nasty bug in the new PM's unswitch introduced in
r335553 with the non-trivial unswitching of switches.
The code correctly updated most aspects of the CFG and analyses, but
missed some crucial aspects:
1) When multiple cases have the same successor, we unswitch that
a single time and replace the switch with a direct branch. The CFG
here is correct, but the target of this direct branch may have had
a PHI node with multiple entries in it.
2) When we still have to clone a successor of the switch into an
unswitched copy of the loop, we'll delete potentially multiple edges
entering this successor, not just one.
3) We also have to delete multiple edges entering the successors in the
original loop when they have to be retained.
4) When the "retained successor" *also* occurs as a case successor, we
just assert failed everywhere. This doesn't happen very easily
because its always valid to simply drop the case -- the retained
successor for switches is always the default successor. However, it
is likely possible through some contrivance of different loop passes,
unrolling, and simplifying for this to occur in practice and
certainly there is nothing "invalid" about the IR so this pass needs
to handle it.
5) In the case of #4, we also will replace these multiple edges with
a direct branch much like in #1 and need to collapse the entries in
any PHI nodes to a single enrty.
All of this stems from the delightful fact that the same successor can
show up in multiple parts of the switch terminator, and each of these
are considered a distinct edge for the purpose of PHI nodes (and
iterating the successors and predecessors) but not for unswitching
itself, the dominator tree, or many other things. For the record,
I intensely dislike this "feature" of the IR in large part because of
the complexity it causes in passes like this. We already have a ton of
logic building sets and handling duplicates, and we just had to add
a bunch more.
I've added a complex test case that covers all five of the above failure
modes. I've also added a variation on it where #4 and #5 occur in loop
exit, adding fun where we have an LCSSA PHI node with "multiple entries"
despite have dedicated exits. There were no additional issues found by
this, but it seems a useful corner case to cover with testing.
One thing that working on all of this code has made painfully clear for
me as well is how amazingly inefficient our PHI node representation is
(in terms of the in-memory data structures and the APIs used to update
them). This code has truly marvelous complexity bounds because every
time we remove an entry from a PHI node we do a linear scan to find it
and then a linear update to the data structure to remove it. We could in
theory batch all of the PHI node updates into a single linear walk of
the operands making this much more efficient, but the APIs fight hard
against this and the fact that we have to handle duplicates in the
peculiar manner we do (removing all but one in some cases) makes even
implementing that very tedious and annoying. Anyways, none of this is
new here or specific to loop unswitching. All code in LLVM that updates
PHI node operands suffers from these problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336536
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam McCall [Mon, 9 Jul 2018 10:05:41 +0000 (10:05 +0000)]
Lift JSON library from clang-tools-extra/clangd to llvm/Support.
Summary:
This consists of four main parts:
- an type json::Expr representing JSON values of dynamic kind, which can be
composed, inspected, and modified
- a JSON parser from string -> json::Expr
- a JSON printer from json::Expr -> string, with optional pretty-printing
- a convention for mapping json::Expr <=> native types (fromJSON/toJSON)
Mapping functions are provided for primitives (e.g. int, vector) and the
ObjectMapper helper helps implement fromJSON for struct/object types.
Based on clangd's usage, a couple of places I'd appreciate review attention:
- fromJSON returns only bool. A richer error-signaling mechanism may be useful
to provide useful messages, or let recursive fromJSONs (containers/structs)
do careful error recovery.
- should json::obj be always explicitly written (like json::ary)
- there's no streaming parse API. I suspect there are some simple wins like
a callback API where the document is a long array, and each element is small.
But this can probably be bolted on easily when we see the need.
Reviewers: bkramer, labath
Subscribers: mgorny, ilya-biryukov, ioeric, MaskRay, llvm-commits
Differential Revision: https://reviews.llvm.org/D45753
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336534
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Mon, 9 Jul 2018 09:58:24 +0000 (09:58 +0000)]
[AArch64][SVE] Asm: Support for ADR instruction.
Supporting various addressing modes:
- adr z0.s, [z0.s, z0.s]
- adr z0.s, [z0.s, z0.s, lsl #<shift>]
- adr z0.d, [z0.d, z0.d]
- adr z0.d, [z0.d, z0.d, lsl #<shift>]
- adr z0.d, [z0.d, z0.d, uxtw #<shift>]
- adr z0.d, [z0.d, z0.d, sxtw #<shift>]
Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D48870
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336533
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Mon, 9 Jul 2018 09:12:17 +0000 (09:12 +0000)]
[AArch64][SVE] Asm: Support for UZP and TRN instructions.
This patch adds support for:
UZP1 Concatenate even elements from two vectors
UZP2 Concatenate odd elements from two vectors
TRN1 Interleave even elements from two vectors
TRN2 Interleave odd elements from two vectors
With variants for both data and predicate vectors, e.g.
uzp1 z0.b, z1.b, z2.b
trn2 p0.s, p1.s, p2.s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336531
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Mon, 9 Jul 2018 09:08:44 +0000 (09:08 +0000)]
[AccelTable] Provide abstraction for emitting DWARF5 accelerator tables.
When emitting the DWARF accelerator tables from dsymutil, we don't have
a DwarfDebug instance and we use a custom class to represent Dwarf
compile units. This patch adds an interface AccelTableWriterInfo to
abstract these from the Dwarf5AccelTableWriter, so we can have a custom
implementation for this in dsymutil.
Differential revision: https://reviews.llvm.org/D49031
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336529
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Mon, 9 Jul 2018 08:47:38 +0000 (08:47 +0000)]
[AccelTable] Dwarf5AccelTableEmitter -> Writer (NFC)
Renames Dwarf5AccelTableEmitter to Dwarf5AccelTableWriter as suggested
in D49031.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336525
91177308-0d34-0410-b5e6-
96231b3b80d8
Chijun Sima [Mon, 9 Jul 2018 08:07:21 +0000 (08:07 +0000)]
[PGOMemOPSize] Preserve the DominatorTree
Summary:
PGOMemOPSize only modifies CFG in a couple of places; thus we can preserve the DominatorTree with little effort.
When optimizing SQLite with -O3, this patch can decrease 3.8% of the numbers of nodes traversed by DFS and 5.7% of the times DominatorTreeBase::recalculation is called.
Reviewers: kuhar, davide, dmgreen
Reviewed By: dmgreen
Subscribers: mzolotukhin, vsk, llvm-commits
Differential Revision: https://reviews.llvm.org/D48914
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336522
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 9 Jul 2018 01:52:56 +0000 (01:52 +0000)]
[X86] Improve the message for some asserts. Remove an if that is guaranteed true by said asserts.
This replaces some asserts in lowerV2F64VectorShuffle with the similar asserts from lowerVIF64VectorShuffle which are more readable. The original asserts mentioned a blend, but there's no guarantee that it is a blend.
Also remove an if that the asserts prove is always true. Mask[0] is always less than 2 and Mask[1] is always at least 2. Therefore (Mask[0] >= 2) + (Mask[1] >= 2) == 1 must wlays be true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336517
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 8 Jul 2018 22:57:33 +0000 (22:57 +0000)]
[X86] Remove an AddedComplexity line that seems unnecessary.
It only existed on SSE and AVX version. AVX512 version didn't have it.
I checked the generated table and this didn't seem necessary to creat a match preference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336516
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Sun, 8 Jul 2018 19:01:55 +0000 (19:01 +0000)]
[X86][Nearly NFC] Split SHLD/SHRD into their own WriteShiftDouble class
Summary:
{
F6603964}
While there is still some discrepancies within that new group,
it is clearly separate from the other shifts.
And Agner's tables agree, these double shifts are clearly
different from the normal shifts/rotates.
I'm guessing `FeatureSlowSHLD` is related.
Indeed, a basic sched pair is *not* the /best/ match.
But keeping it in the WriteShift is /clearly/ not ideal either.
This can and likely will be fine-tuned later.
This is purely mechanical change, it does not change any numbers,
as the [lack of the change of] mca tests show.
Reviewers: craig.topper, RKSimon, andreadb
Reviewed By: craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49015
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336515
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 8 Jul 2018 18:04:00 +0000 (18:04 +0000)]
[X86] Enhance combineFMA to look for FNEG behind an EXTRACT_VECTOR_ELT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336514
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 8 Jul 2018 12:47:50 +0000 (12:47 +0000)]
[X86][SSE] Combine v16i8 SHL by constants to multiplies
Pre-AVX512 (which can perform a quick extend/shift/truncate), extending to 2 v8i16 for the PMULLW and then truncating is more performant than relying on the generic PBLENDVB vXi8 shift path and uses a similar amount of mask constant pool data.
Differential Revision: https://reviews.llvm.org/D48963
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336513
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 8 Jul 2018 10:32:07 +0000 (10:32 +0000)]
[X86] Set scheduler classes to unsupported. NFCI.
While looking at PR36895 I noticed how much of the atom model was still setting schedules for unsupported SSE4+ instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336512
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Sun, 8 Jul 2018 09:50:25 +0000 (09:50 +0000)]
[X86][Basically NFC] Sched: split WriteBitScan into WriteBSF/WriteBSR.
Summary:
Motivation: {
F6597954}
This only does the mechanical splitting, does not actually change
any numbers, as the tests added in previous revision show.
Reviewers: craig.topper, RKSimon, courbet
Reviewed By: craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48998
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336511
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Sun, 8 Jul 2018 09:50:14 +0000 (09:50 +0000)]
[MCA][X86][NFC] Add BSF/BSR resource tests
Reviewers: RKSimon, andreadb, courbet
Reviewed By: RKSimon
Subscribers: gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D48997
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336510
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 8 Jul 2018 01:45:47 +0000 (01:45 +0000)]
[LoopIdiomRecognize] Support for converting loops that use LSHR to CTLZ.
In the 'detectCTLZIdiom' function support for loops that use LSHR instruction instead of ASHR has been added.
This supports creating ctlz from the following code.
int lzcnt(int x) {
int count = 0;
while (x > 0) {
count++;
x = x >> 1;
}
return count;
}
Patch by Olga Moldovanova
Differential Revision: https://reviews.llvm.org/D48354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336509
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 8 Jul 2018 01:23:49 +0000 (01:23 +0000)]
[X86] Add back some intrinsic table entries lost in r336506.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336508
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 8 Jul 2018 01:10:43 +0000 (01:10 +0000)]
[X86] Add new scalar fma intrinsics with rounding mode that use f32/f64 types.
This allows us to handle masking in a very similar way to the default rounding version that uses llvm.fma.
I had to add new rounding mode CodeGenOnly instructions to support isel when we can't find a movss to grab the upper bits from to use the b_Int instruction.
Fast-isel tests have been updated to match new clang codegen.
We are currently having trouble folding fneg into the new intrinsic. I'm going to correct that in a follow up patch to keep the size of this one down.
A future patch will also remove the old intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336506
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 8 Jul 2018 00:32:56 +0000 (00:32 +0000)]
[X86] Use a rounding mode other than 4 in the scalar fma intrinsic fast-isel tests to match clang test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336505
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 7 Jul 2018 20:08:27 +0000 (20:08 +0000)]
[X86] Regenerate PR14088 test. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336496
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 7 Jul 2018 18:17:14 +0000 (18:17 +0000)]
[SelectionDAG] Split float and integer isKnownNeverZero tests
Splits off isKnownNeverZeroFloat to handle +/- 0 float cases.
This will make it easier to be more aggressive with the integer isKnownNeverZero tests (similar to ValueTracking), use computeKnownBits etc.
Differential Revision: https://reviews.llvm.org/D48969
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336492
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 7 Jul 2018 17:33:48 +0000 (17:33 +0000)]
Use const APInt& to avoid extra copy. NFCI.
As discussed on D48825.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336491
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 7 Jul 2018 17:30:06 +0000 (17:30 +0000)]
[DAGCombiner] Add EXTRACT_SUBVECTOR to SimplifyDemandedVectorElts
As discussed on PR37989, this patch adds EXTRACT_SUBVECTOR handling to TargetLowering::SimplifyDemandedVectorElts and calls it from DAGCombiner::visitEXTRACT_SUBVECTOR.
Differential Revision: https://reviews.llvm.org/D48825
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336490
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 7 Jul 2018 16:53:30 +0000 (16:53 +0000)]
[CostModel][X86] Add SREM/UREM general and constant costs (PR38056)
We penalize general SDIV/UDIV costs but don't do the same for SREM/UREM.
This patch makes general vector SREM/UREM x20 as costly as scalar, the same approach as we do for SDIV/UDIV. The patch also extends the existing SDIV/UDIV constant costs for SREM/UREM - at the moment this means the additional cost of a MUL+SUB (see D48975).
Differential Revision: https://reviews.llvm.org/D48980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336486
91177308-0d34-0410-b5e6-
96231b3b80d8
Chijun Sima [Sat, 7 Jul 2018 16:22:22 +0000 (16:22 +0000)]
Test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336485
91177308-0d34-0410-b5e6-
96231b3b80d8
Gabor Buella [Sat, 7 Jul 2018 16:09:15 +0000 (16:09 +0000)]
NFC - Typo fixes in X86 flags-copy-lowering.mir test
Differential Revision: https://reviews.llvm.org/D48934
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336484
91177308-0d34-0410-b5e6-
96231b3b80d8
Yvan Roux [Sat, 7 Jul 2018 08:42:31 +0000 (08:42 +0000)]
[MachineOutliner] Add missing liveness tracking info in MIR test.
This should bring the bots back to green state.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336482
91177308-0d34-0410-b5e6-
96231b3b80d8
Yvan Roux [Sat, 7 Jul 2018 08:02:19 +0000 (08:02 +0000)]
[MachineOutliner] Assert that Liveness tracking is accurate (NFC)
The checking is done deeper inside MachineBasicBlock, but this will
hopefully help to find issues when porting the machine outliner to a
target where Liveness tracking is broken (like ARM).
Differential Revision: https://reviews.llvm.org/D49023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336481
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Sat, 7 Jul 2018 02:46:12 +0000 (02:46 +0000)]
[Support] Clear errno before calling the function in RetryAfterSignal.
For certain APIs, the return value of the function does not distinguish
between failure (which populates errno) and other non-error conditions
(which do not set errno).
For example, `fgets` returns `NULL` both when an error has occurred, or
upon EOF. If `errno` is already `EINTR` for whatever reason, then
```
RetryAfterSignal(nullptr, fgets, ...);
```
on a stream that has reached EOF would infinite loop.
Fix this by setting `errno` to `0` before each attempt in
`RetryAfterSignal`.
Patch by Ricky Zhou!
Differential Revision: https://reviews.llvm.org/D48755
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336479
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Sat, 7 Jul 2018 01:12:56 +0000 (01:12 +0000)]
[PM/LoopUnswitch] Fix PR37889, producing the correct loop nest structure
after trivial unswitching.
This PR illustrates that a fundamental analysis update was not performed
with the new loop unswitch. This update is also somewhat fundamental to
the core idea of the new loop unswitch -- we actually *update* the CFG
based on the unswitching. In order to do that, we need to update the
loop nest in addition to the domtree.
For some reason, when writing trivial unswitching, I thought that the
loop nest structure cannot be changed by the transformation. But the PR
helps illustrate that it clearly can. I've expanded this to a number of
different test cases that try to cover the different cases of this. When
we unswitch, we move an exit edge of a loop out of the loop. If this
exit edge changes which loop reached by an exit is the innermost loop,
it changes the parent of the loop. Essentially, this transformation may
hoist the inner loop up the nest. I've added the simple logic to handle
this reliably in the trivial unswitching case. This just requires
updating LoopInfo and rebuilding LCSSA on the impacted loops. In the
trivial case, we don't even need to handle dedicated exits because we're
only hoisting the one loop and we just split its preheader.
I've also ported all of these tests to non-trivial unswitching and
verified that the logic already there correctly handles the loop nest
updates necessary.
Differential Revision: https://reviews.llvm.org/D48851
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336477
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 7 Jul 2018 01:04:22 +0000 (01:04 +0000)]
[X86] Merge INTR_TYPE_3OP_RM with INTR_TYPE_3OP. Remove unused INTR_TYPE_1OP_RM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336476
91177308-0d34-0410-b5e6-
96231b3b80d8