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Adrian Prantl [Wed, 16 Aug 2017 17:43:01 +0000 (17:43 +0000)]
Add a convenience overload of DWARFDie::dump() for debugging purposes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311026
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Xinliang David Li [Wed, 16 Aug 2017 17:33:43 +0000 (17:33 +0000)]
Add more comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311025
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Xinliang David Li [Wed, 16 Aug 2017 17:18:01 +0000 (17:18 +0000)]
[PGO] Fix ThinLTO crash
Differential Revsion: http://reviews.llvm.org/D36640
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311023
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Evgeny Mankov [Wed, 16 Aug 2017 16:47:29 +0000 (16:47 +0000)]
[AMDGPU] NFC: test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311019
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Konstantin Zhuravlyov [Wed, 16 Aug 2017 16:23:32 +0000 (16:23 +0000)]
AMDGPU/NFC: Sort files in CMakeLists.txt alphabetically
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311017
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Simon Pilgrim [Wed, 16 Aug 2017 16:22:19 +0000 (16:22 +0000)]
[X86] Regenerate immediate store merging tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311016
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Jakub Kuderski [Wed, 16 Aug 2017 16:12:52 +0000 (16:12 +0000)]
[Dominators] Introduce batch updates
Summary:
This patch introduces a way of informing the (Post)DominatorTree about multiple CFG updates that happened since the last tree update. This makes performing tree updates much easier, as it internally takes care of applying the updates in lockstep with the (virtual) updates to the CFG, which is done by reverse-applying future CFG updates.
The batch updater is able to remove redundant updates that cancel each other out. In the future, it should be also possible to reorder updates to reduce the amount of work needed to perform the updates.
Reviewers: dberlin, sanjoy, grosser, davide, brzycki
Reviewed By: brzycki
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D36167
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311015
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Hal Finkel [Wed, 16 Aug 2017 16:09:22 +0000 (16:09 +0000)]
[BDCE] Don't check demanded bits on unsized types
To clear assumptions that are potentially invalid after trivialization, we need
to walk the use/def chain. Normally, the only way to reach an instruction with
an unsized type is via an instruction that has side effects (or otherwise will
demand its input bits). That would stop the walk. However, if we have a
readnone function that returns an unsized type (e.g., void), we must avoid
asking for the demanded bits of the function call's return value. A
void-returning readnone function is always dead (and so we can stop walking the
use/def chain here), but the check is necessary to avoid asserting.
Fixes PR34211.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311014
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Davide Italiano [Wed, 16 Aug 2017 15:16:33 +0000 (15:16 +0000)]
[Verifier] Reject globals without a type associated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311012
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Dmitry Preobrazhensky [Wed, 16 Aug 2017 15:16:32 +0000 (15:16 +0000)]
[AMDGPU][MC][GFX9] Added op_sel support for v_mad_*16, v_fma_f16, v_div_fixup_f16
This change implements features postponed in https://reviews.llvm.org/D35424 because of a dependency on https://reviews.llvm.org/D36322
Reviewers: SamWot, artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D36694
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311011
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Sanjay Patel [Wed, 16 Aug 2017 14:28:23 +0000 (14:28 +0000)]
[DemandedBits] simplify call; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311009
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Balaram Makam [Wed, 16 Aug 2017 14:17:43 +0000 (14:17 +0000)]
Revert "MachineInstr: Reason locally about some memory objects before going to AA."
r310825 caused the clang-ppc64le-linux-lnt bot to go red
(http://lab.llvm.org:8011/builders/clang-ppc64le-linux-lnt/builds/5712)
because of a test-suite failure of
SingleSource/UnitTests/2003-07-09-SignedArgs
This reverts commit
0028f6a87224fb595a1c19c544cde9b003035996.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311008
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Dmitry Preobrazhensky [Wed, 16 Aug 2017 13:51:56 +0000 (13:51 +0000)]
[AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodes
See Bug 34152: https://bugs.llvm.org//show_bug.cgi?id=34152
Reviewers: SamWot, artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D36674
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311006
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Simon Pilgrim [Wed, 16 Aug 2017 13:50:20 +0000 (13:50 +0000)]
[CostModel][X86][XOP] Improve costs for XOP shuffles
VPPERM/VPERMIL2PD/VPERMIL2PS all provide more effective 2-input shuffles than regular AVX instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311005
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Davide Italiano [Wed, 16 Aug 2017 13:39:07 +0000 (13:39 +0000)]
[DI] Every DIGlobalVariable should have a type.
I'll make this a verifier check to catch other violations. This
commit fixes the tests already in tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311004
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Simon Dardis [Wed, 16 Aug 2017 12:18:04 +0000 (12:18 +0000)]
[mips] Handle variables with an explicit section and interactions with .sdata, .sbss
If a variable has an explicit section such as .sdata or .sbss, it is placed
in that section and accessed in a gp relative manner. This overrides the global
-G setting.
Otherwise if a variable has a explicit section attached to it, such as '.rodata'
or '.mysection', it is not placed in the small data section. This also overrides
the global -G setting.
Reviewers: atanasyan, nitesh.jain
Differential Revision: https://reviews.llvm.org/D36616
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311001
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Sam Parker [Wed, 16 Aug 2017 07:42:44 +0000 (07:42 +0000)]
[ARM] Improve loop unrolling for Cortex-M
- Set the default runtime unroll count to 4 and use the newly added
UnrollRemainder option.
- Create loop cost and force unroll for a cost less than 12.
- Disable unrolling on Thumb1 only targets.
Differential Revision: https://reviews.llvm.org/D36134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310997
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Igor Breger [Wed, 16 Aug 2017 07:25:51 +0000 (07:25 +0000)]
[GlobalISel][X86] Fix mir tests, use correct physical register.NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310996
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Martin Storsjo [Wed, 16 Aug 2017 05:22:49 +0000 (05:22 +0000)]
[COFF] Make the weak aliases optional
When creating an import library from lld, the cases with
Name != ExtName shouldn't end up as a weak alias, but as a real
export of the new name, which is what actually is exported from
the DLL.
This restores the behaviour of renamed exports to what it was in
4.0.
The other half of this commit, including test, goes into lld.
Differential Revision: https://reviews.llvm.org/D36633
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310991
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Martin Storsjo [Wed, 16 Aug 2017 05:18:36 +0000 (05:18 +0000)]
[llvm-dlltool] Fix creating stdcall/fastcall import libraries for i386
Hook up the -k option (that in the original GNU dlltool removes the
@n suffix from the symbol that the final executable ends up linked to).
In llvm-dlltool, make sure that functions end up with the undecorate
name type if this option is set and they are decorated. In mingw, when
creating import libraries from def files instead of creating an import
library as a side effect of linking a DLL, the symbol names in the def
contain the stdcall/fastcall decoration (but no leading underscore).
By setting the undecorate name type, a linker linking to the import
library will omit the decoration from the DLL import entry.
With this in place, mingw-w64 for i386 built with llvm-dlltool/clang
produces import libraries that actually work.
Differential Revision: https://reviews.llvm.org/D36548
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310990
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Martin Storsjo [Wed, 16 Aug 2017 05:13:16 +0000 (05:13 +0000)]
[COFF] Add SymbolName as a distinct field in COFFImportFile
The previous Name and ExtName aren't enough to convey all the nuances
between weak aliases and stdcall decorated function names.
A test for this will be added in LLD.
Differential Revision: https://reviews.llvm.org/D36544
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310988
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Stanislav Mekhanoshin [Wed, 16 Aug 2017 04:43:49 +0000 (04:43 +0000)]
[AMDGPU] Eliminate no effect instructions before s_endpgm
Differential Revision: https://reviews.llvm.org/D36585
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310987
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Dehao Chen [Wed, 16 Aug 2017 01:55:26 +0000 (01:55 +0000)]
Merge debug info when hoist then-else code to if.
Summary: When we move then-else code to if, we need to merge its debug info, otherwise the hoisted instruction may have inaccurate debug info attached.
Reviewers: aprantl, probinson, dblaikie, echristo, loladiro
Reviewed By: aprantl
Subscribers: sanjoy, llvm-commits
Differential Revision: https://reviews.llvm.org/D36778
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310985
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Derek Schuff [Wed, 16 Aug 2017 00:49:44 +0000 (00:49 +0000)]
[WebAssembly] Remove infinite loop from reg-stackify test
r310940 exposed reverse-unreachable code to some optimizers,
which caused some of the code in this test to be sunk, changing
the input to the pass and breaking the exptectations.
Since that change is irrelevant to this particular test, this change
just adds an exit node to work around the problem; the
test should really be more robust (or be an MIR test?) but this preserves
the existing test intent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310981
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Quentin Colombet [Wed, 16 Aug 2017 00:17:05 +0000 (00:17 +0000)]
[VirtRegRewriter] Properly model the register liveness on undef subreg definition
Undef subreg definition means that the content of the super register
doesn't matter at this point. While that's true for virtual registers,
this may not hold when replacing them with actual physical registers.
Indeed, some part of the physical register may be coalesced with the
related virtual register and thus, the values for those parts matter and
must be live.
The fix consists in checking whether or not subregs of the physical register
being assigned to an undef subreg definition are live through that def and
insert an implicit use if they are. Doing so, will keep them alive until
that point like they should be.
E.g., let vreg14 being assigned to R0_R1 then
%vreg14:gsub_0<def,read-undef> = COPY %R0 ; <-- R1 is still live here
%vreg14:gsub_1<def> = COPY %R1
Before this changes, the rewriter would change the code into:
%R0<def> = KILL %R0, %R0_R1<imp-def> ; <-- this tells R1 is redefined
%R1<def> = KILL %R1, %R0_R1<imp-def>, %R0_R1<imp-use> ; this value of this R1
; is believed to come
; from the previous
; instruction
Because of this invalid liveness, later pass could make wrong choices and in
particular clobber live register as it happened with the register scavenger in
llvm.org/PR34107
Now we would generate:
%R0<def> = KILL %R0, %R0_R1<imp-def>, %R0_R1<imp-use> ; This tells R1 needs to
; reach this point
%R1<def> = KILL %R1, %R0_R1<imp-def>, %R0_R1<imp-use>
The bug has been here forever, it got exposed recently because the register
scavenger got smarter.
Fixes llvm.org/PR34107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310979
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Kuba Mracek [Tue, 15 Aug 2017 23:41:34 +0000 (23:41 +0000)]
Revert archive-* tests from r310953, there were test failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310974
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Craig Topper [Tue, 15 Aug 2017 22:48:41 +0000 (22:48 +0000)]
[InstCombine] Teach canEvaluateZExtd and canEvaluateTruncated to handle vector shifts with splat shift amount
We were only allowing ConstantInt before. This patch allows splat of ConstantInt too.
Differential Revision: https://reviews.llvm.org/D36763
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310970
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Quentin Colombet [Tue, 15 Aug 2017 22:31:51 +0000 (22:31 +0000)]
Reapply "[GlobalISel] Remove the GISelAccessor API."
This reverts commit r310425, thus reapplying r310335 with a fix for link
issue of the AArch64 unittests on Linux bots when BUILD_SHARED_LIBS is ON.
Original commit message:
[GlobalISel] Remove the GISelAccessor API.
Its sole purpose was to avoid spreading around ifdefs related to
building global-isel. Since r309990, GlobalISel is not optional anymore,
thus, we can get rid of this mechanism all together.
NFC.
----
The fix for the link issue consists in adding the GlobalISel library in
the list of dependencies for the AArch64 unittests. This dependency
comes from the use of AArch64Subtarget that needs to know how
to destruct the GISel related APIs when being detroyed.
Thanks to Bill Seurer and Ahmed Bougacha for helping me reproducing and
understand the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310969
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Charles Saternos [Tue, 15 Aug 2017 22:23:44 +0000 (22:23 +0000)]
[ThinLTO] Fix ThinLTO crash while destroying context
Fix for PR32763
An assert that checks if a Ref was untracked fails during ThinLTO context cleanup. The issue is because lazy loading temporary nodes didn't properly track ValueAsMetadata nodes. This patch ensures that the temporary nodes are properly tracked when they're replaced with the value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310967
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Kuba Mracek [Tue, 15 Aug 2017 21:02:17 +0000 (21:02 +0000)]
Revert changes in r310953 for llvm-symbolizer.test. The change causes a test failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310956
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Tony Tye [Tue, 15 Aug 2017 20:47:41 +0000 (20:47 +0000)]
Update AMDGPUUsage.rst documentation:
1. Correct description of the kernel initial state for FLAT_SCRATCH_INIT.
2. Add link to GFX9 architecture documentation.
3. Update product names.
4. Rename note record from NT_AMD_AMDGPU_METADATA to NT_AMD_AMDGPU_HSA_METADATA and move description to the AMDHSA coding convention section.
5. Minor typo corrections.
Differential Revision: https://reviews.llvm.org/D36549
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310954
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Kuba Mracek [Tue, 15 Aug 2017 20:29:24 +0000 (20:29 +0000)]
[llvm] Get rid of "%T" expansions
The %T lit expansion expands to a common directory shared between all the tests in the same directory, which is unexpected and unintuitive, and more importantly, it's been a source of subtle race conditions and flaky tests. In https://reviews.llvm.org/D35396, it was agreed that it would be best to simply ban %T and only keep %t, which is unique to each test. When a test needs a temporary directory, it can just create one using mkdir %t.
This patch removes %T in llvm.
Differential Revision: https://reviews.llvm.org/D36495
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310953
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Amjad Aboud [Tue, 15 Aug 2017 19:33:14 +0000 (19:33 +0000)]
[InstCombine] Added support for (X >>s C) << C --> X & (-1 << C)
Differential Revision: https://reviews.llvm.org/D36743
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310949
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Lang Hames [Tue, 15 Aug 2017 19:20:10 +0000 (19:20 +0000)]
[ORC][Kaleidoscope] Update Chapter 1 of BuildingAJIT to incorporate recent ORC
API changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310947
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Sanjay Patel [Tue, 15 Aug 2017 18:25:52 +0000 (18:25 +0000)]
[InstCombine] sink sext after ashr
Narrow ops are better for bit-tracking, and in the case of vectors,
may enable better codegen.
As the trunc test shows, this can allow follow-on simplifications.
There's a block of code in visitTrunc that deals with shifted ops
with FIXME comments. It may be possible to remove some of that now,
but I want to make sure there are no problems with this step first.
http://rise4fun.com/Alive/Y3a
Name: hoist_ashr_ahead_of_sext_1
%s = sext i8 %x to i32
%r = ashr i32 %s, 3 ; shift value is < than source bit width
=>
%a = ashr i8 %x, 3
%r = sext i8 %a to i32
Name: hoist_ashr_ahead_of_sext_2
%s = sext i8 %x to i32
%r = ashr i32 %s, 8 ; shift value is >= than source bit width
=>
%a = ashr i8 %x, 7 ; so clamp this shift value
%r = sext i8 %a to i32
Name: junc_the_trunc
%a = sext i16 %v to i32
%s = ashr i32 %a, 18
%t = trunc i32 %s to i16
=>
%t = ashr i16 %v, 15
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310942
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Jakub Kuderski [Tue, 15 Aug 2017 18:14:57 +0000 (18:14 +0000)]
[Dominators] Include infinite loops in PostDominatorTree
Summary:
This patch teaches PostDominatorTree about infinite loops. It is built on top of D29705 by @dberlin which includes a very detailed motivation for this change.
What's new is that the patch also teaches the incremental updater how to deal with reverse-unreachable regions and how to properly maintain and verify tree roots. Before that, the incremental algorithm sometimes ended up preserving reverse-unreachable regions after updates that wouldn't appear in the tree if it was constructed from scratch on the same CFG.
This patch makes the following assumptions:
- A sequence of updates should produce the same tree as a recalculating it.
- Any sequence of the same updates should lead to the same tree.
- Siblings and roots are unordered.
The last two properties are essential to efficiently perform batch updates in the future.
When it comes to the first one, we can decide later that the consistency between freshly built tree and an updated one doesn't matter match, as there are many correct ways to pick roots in infinite loops, and to relax this assumption. That should enable us to recalculate postdominators less frequently.
This patch is pretty conservative when it comes to incremental updates on reverse-unreachable regions and ends up recalculating the whole tree in many cases. It should be possible to improve the performance in many cases, if we decide that it's important enough.
That being said, my experiments showed that reverse-unreachable are very rare in the IR emitted by clang when bootstrapping clang. Here are the statistics I collected by analyzing IR between passes and after each removePredecessor call:
```
# functions: 52283
# samples: 337609
# reverse unreachable BBs: 216022
# BBs:
247840796
Percent reverse-unreachable: 0.
08716159869015269 %
Max(PercRevUnreachable) in a function: 87.
58620689655172 %
# > 25 % samples: 471 ( 0.
1395104988314885 % samples )
... in 145 ( 0.
27733680163724345 % functions )
```
Most of the reverse-unreachable regions come from invalid IR where it wouldn't be possible to construct a PostDomTree anyway.
I would like to commit this patch in the next week in order to be able to complete the work that depends on it before the end of my internship, so please don't wait long to voice your concerns :).
Reviewers: dberlin, sanjoy, grosser, brzycki, davide, chandlerc, hfinkel
Reviewed By: dberlin
Subscribers: nhaehnle, javed.absar, kparzysz, uabelho, jlebar, hiraditya, llvm-commits, dberlin, david2050
Differential Revision: https://reviews.llvm.org/D35851
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310940
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Tom Stellard [Tue, 15 Aug 2017 18:11:56 +0000 (18:11 +0000)]
test-release.sh: Move test-suite setup to beginning of the script
Summary:
We want to catch failures early before do the full 3 stage build.
The goal here is to avoid running through the whole build process and have
it fail at the end (and not create the binary packages), just because
some prerequisites failed to install.
Reviewers: rovka, hans
Reviewed By: hans
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36422
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310939
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Lang Hames [Tue, 15 Aug 2017 18:10:19 +0000 (18:10 +0000)]
[ORC] Add case statements for AArch64 to the local stub and callback manager
creation functions.
This should allow lli to lazily execute code using OrcLazyJIT on AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310938
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Sanjay Patel [Tue, 15 Aug 2017 17:41:31 +0000 (17:41 +0000)]
[InstCombine] add tests for sext+ashr; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310935
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Rui Ueyama [Tue, 15 Aug 2017 17:39:35 +0000 (17:39 +0000)]
Fix -Wunused-lambda-capture for Release build.
`I` and `this` are used only in assert or DEBUG, so they are unused
in Release build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310934
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George Rimar [Tue, 15 Aug 2017 16:42:21 +0000 (16:42 +0000)]
[llvm-dwarfdump] - Attemp to fix BB after r310915.
Now MIPS one is unhappy:
http://lab.llvm.org:8011/builders/llvm-mips-linux/builds/2221
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310928
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Steven Wu [Tue, 15 Aug 2017 16:16:33 +0000 (16:16 +0000)]
[Doc] Update LangRef for new Module Flag Behavior
Summary:
Add the documentation for the new module flag behavior. The new
ModFlagBehavior is added in r303590.
Reviewers: tejohnson
Reviewed By: tejohnson
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36557
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310926
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George Rimar [Tue, 15 Aug 2017 15:54:43 +0000 (15:54 +0000)]
[llvm-dwarfdump] - Refactor section name/uniqueness gathering.
As was requested in D36313 thread,
with this patch section names and uniqueness calculated once,
and not every time when a range is dumped.
Differential revision: https://reviews.llvm.org/D36740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310923
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Daniel Sanders [Tue, 15 Aug 2017 15:10:31 +0000 (15:10 +0000)]
Revert r310919 - [globalisel][tablegen] Support zero-instruction emission.
As expected, this failed on the windows bots but the instrumentation showed
something interesting. The ADD8ri and INC8r rules are never directly compared
on the windows machines. That implies that the issue lies in transitivity of
the Compare predicate. I believe I've already verified that but maybe I missed
something.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310922
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Daniel Sanders [Tue, 15 Aug 2017 13:50:09 +0000 (13:50 +0000)]
Re-commit with some instrumentation: [globalisel][tablegen] Support zero-instruction emission.
Summary:
Support the case where an operand of a pattern is also the whole of the
result pattern. In this case the original result and all its uses must be
replaced by the operand. However, register class restrictions can require
a COPY. This patch handles both cases by always emitting the copy and
leaving it for the register allocator to optimize.
The previous commit failed on the windows bots and this one is likely to fail
on those same bots. However, the added instrumentation should reveal a particular
isHigherPriorityThan() evaluation which I'm expecting to expose that
these machines are weighing priority of two rules differently from the
non-windows machines.
Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar
Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D36084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310919
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George Rimar [Tue, 15 Aug 2017 13:26:12 +0000 (13:26 +0000)]
[DebugInfo] - Attemp to fix BB after r310915.
Not sure what BB does not like.
While building module 'LLVM_DebugInfo_DWARF' imported from /home/buildbot/modules-slave-2/clang-x86_64-linux-selfhost-modules-2/llvm.src/lib/DebugInfo/DWARF/DWARFAbbreviationDeclaration.cpp:10:
In file included from <module-includes>:7:
In file included from /home/buildbot/modules-slave-2/clang-x86_64-linux-selfhost-modules-2/llvm.src/include/llvm/DebugInfo/DWARF/DWARFContext.h:29:
/home/buildbot/modules-slave-2/clang-x86_64-linux-selfhost-modules-2/llvm.src/include/llvm/DebugInfo/DWARF/DWARFObject.h:30:17: error: declaration of 'object' must be imported from module 'LLVM_Object.Decompressor' before it is required
virtual const object::ObjectFile *getFile() const { return nullptr; }
^
/home/buildbot/modules-slave-2/clang-x86_64-linux-selfhost-modules-2/llvm.src/include/llvm/Object/Decompressor.h:18:11: note: previous declaration is here
namespace object {
http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules-2/builds/10766
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310918
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Alex Bradbury [Tue, 15 Aug 2017 13:08:29 +0000 (13:08 +0000)]
[RISCV] Add RISCVInstPrinter and basic MC assembler tests
With the addition of RISCVInstPrinter, it is now possible to test the basic
operation of the RISCV MC layer.
Differential Revision: https://reviews.llvm.org/D23564
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310917
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George Rimar [Tue, 15 Aug 2017 12:32:54 +0000 (12:32 +0000)]
[llvm-dwarfdump] - Print section name and index when dumping .debug_info ranges
Teaches llvm-dwarfdump to print section index and name of range
when it dumps .debug_info.
Differential revision: https://reviews.llvm.org/D36313
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310915
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Alex Bradbury [Tue, 15 Aug 2017 12:11:10 +0000 (12:11 +0000)]
[RISCV] Recognize new relocation types
This patch adds all RISC-V relocation types, as of binutils 2.29. Note that
R_RISCV32_PCREL is not currently documented in the RISC-V ELF PSABI.
Differential Revision: https://reviews.llvm.org/D36455
Patch by Chih-Mao Chen (@PkmX)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310914
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Ayal Zaks [Tue, 15 Aug 2017 08:32:59 +0000 (08:32 +0000)]
[LV] Minor savings to Sink casts to unravel first order recurrence
Two minor savings: avoid copying the SinkAfter map and avoid moving a cast if it
is not needed.
Differential Revision: https://reviews.llvm.org/D36408
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310910
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Frederich Munch [Tue, 15 Aug 2017 02:25:36 +0000 (02:25 +0000)]
Propagate error in LazyEmittingLayer::removeModule.
Summary:
Besides being the better thing to do, not doing so will triggers an assert with LLVM_ENABLE_ABI_BREAKING_CHECKS.
Reviewers: lhames
Reviewed By: lhames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36700
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310906
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Dinar Temirbulatov [Tue, 15 Aug 2017 00:31:49 +0000 (00:31 +0000)]
[SLPVectorizer] Replace VL[0] to VL0 with assert, add propagateIRFlags extra parameter VL0,
replace E->Scalars[0] to VL0, NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310904
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Petr Hosek [Mon, 14 Aug 2017 23:37:31 +0000 (23:37 +0000)]
[CMake] Add install target for LLVMFuzzer
This allows including LLVMFuzzer as distribution component.
Differential Revision: https://reviews.llvm.org/D36540
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310897
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Dehao Chen [Mon, 14 Aug 2017 23:25:21 +0000 (23:25 +0000)]
Add missing dependency in ICP. (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310896
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Jessica Paquette [Mon, 14 Aug 2017 22:57:41 +0000 (22:57 +0000)]
[MachineOutliner] Only outline candidates of length >= 2
Since we don't factor in instruction lengths into outlining calculations
right now, it's never the case that a candidate could have length < 2.
Thus, we should quit early when we see such candidates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310894
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Craig Topper [Mon, 14 Aug 2017 22:11:43 +0000 (22:11 +0000)]
[InstSimplify] Teach decomposeBitTestICmp to handle non-canonical compares
This adds support non-canonical compare predicates. InstSimplify can't rely on canonicalization to have occurred.
Differential Revision: https://reviews.llvm.org/D36646
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310893
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Reid Kleckner [Mon, 14 Aug 2017 22:10:54 +0000 (22:10 +0000)]
Remove checks for debug info intrinsics in use lists, NFC
These haven't done anything since debug info intrinsics stopped
appearing in Value use lists in 2014.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310892
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John Baldwin [Mon, 14 Aug 2017 21:49:38 +0000 (21:49 +0000)]
[MIPS] Implement support for -mstack-alignment.
Summary:
This is modeled on the implementation for x86 which stores the command line
option in a 'StackAlignOverride' field in MipsSubtarget and then uses this
to compute a 'stackAlignment' value in
MipsSubtarget::initializeSubtargetDependencies.
The stackAlignment() method in MipsSubTarget is renamed to getStackAlignment()
and returns the computed 'stackAlignment'.
Reviewers: sdardis
Reviewed By: sdardis
Subscribers: llvm-commits, arichardson
Differential Revision: https://reviews.llvm.org/D35874
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310891
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Craig Topper [Mon, 14 Aug 2017 21:39:51 +0000 (21:39 +0000)]
Recommit r310869, "[InstSimplify][InstCombine] Modify the interface of decomposeBitTestICmp and use it in the InstSimplify"
This recommits r310869, with the moved files and no extra changes.
Original commit message:
This addresses a fixme in InstSimplify about using decomposeBitTest. This also fixes InstSimplify to handle ugt and ult compares too.
I've modified the interface a little to return only the APInt version of the mask that InstSimplify needs. InstCombine now has a small wrapper routine to create a Constant out of it. I've also dropped the returning of 0 since InstSimplify doesn't need that. So InstCombine creates a zero constant itself.
I also had to make decomposeBitTest support vectors since InstSimplify needs that.
As InstSimplify can't use something from the Transforms library, I've moved the CmpInstAnalysis code to the Analysis library.
Differential Revision: https://reviews.llvm.org/D36593
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310889
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Chandler Carruth [Mon, 14 Aug 2017 21:25:00 +0000 (21:25 +0000)]
[InlineCost] Refactor the checks for different analyses to be a bit more
localized to the code that uses those analyses.
Technically, this can change behavior as we no longer require the
existence of the ProfileSummaryInfo analysis to use local profile
information via BFI. We didn't actually require the PSI to have an
interesting profile though, so this only really impacts the behavior in
non-default pass pipelines.
IMO, this makes it substantially less surprising how everything works --
before an analysis that wasn't actually used had to exist to trigger
*any* profile aware inlining. I think the new organization makes it more
obvious where various checks for profile signals happen.
Differential Revision: https://reviews.llvm.org/D36710
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310888
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Andrew Kaylor [Mon, 14 Aug 2017 21:15:13 +0000 (21:15 +0000)]
Add strictfp attribute to prevent unwanted optimizations of libm calls
Differential Revision: https://reviews.llvm.org/D34163
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310885
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Kostya Serebryany [Mon, 14 Aug 2017 20:34:35 +0000 (20:34 +0000)]
[libFuzzer] try to use less RAM while processing the initial corpus
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310881
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Kostya Serebryany [Mon, 14 Aug 2017 19:55:23 +0000 (19:55 +0000)]
[libFuzzer] explicitly use -fsanitize-coverage=trace-pc-guard in test/dump_coverage.test; mark print_coverage/dump_coverage as To-be-deprecated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310877
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Matt Arsenault [Mon, 14 Aug 2017 19:54:47 +0000 (19:54 +0000)]
IPRA: Allow target to enable IPRA by default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310876
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Matt Arsenault [Mon, 14 Aug 2017 19:54:45 +0000 (19:54 +0000)]
IPRA: Run RegUsageInfoPropagate much later
This was running immediately after isel, before
isel pseudos were even expanded which is really
unreasonable. Move this to before pre-reglloc
passes in case some other pre-regalloc pass wants to
use the updated regmask info.
Fixes one of the reasons IPRA doesn't do anything on
AMDGPU currently. Tests will be included with future
patch after a few more are fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310875
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Craig Topper [Mon, 14 Aug 2017 19:09:32 +0000 (19:09 +0000)]
Revert r310869 "[InstSimplify][InstCombine] Modify the interface of decomposeBitTestICmp and use it in the InstSimplify"
Failed to add the two files that moved. And then added an extra change I didn't mean to while trying to fix that. Reverting everything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310873
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Craig Topper [Mon, 14 Aug 2017 19:09:28 +0000 (19:09 +0000)]
Revert r310870 "[InstCombine][InstSimplify] 'git add' two files that moved in r310869."
An extra change crept in here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310872
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Craig Topper [Mon, 14 Aug 2017 19:01:32 +0000 (19:01 +0000)]
[InstCombine][InstSimplify] 'git add' two files that moved in r310869.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310870
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Craig Topper [Mon, 14 Aug 2017 18:49:42 +0000 (18:49 +0000)]
[InstSimplify][InstCombine] Modify the interface of decomposeBitTestICmp and use it in the InstSimplify
This addresses a fixme in InstSimplify about using decomposeBitTest. This also fixes InstSimplify to handle ugt and ult compares too.
I've modified the interface a little to return only the APInt version of the mask that InstSimplify needs. InstCombine now has a small wrapper routine to create a Constant out of it. I've also dropped the returning of 0 since InstSimplify doesn't need that. So InstCombine creates a zero constant itself.
I also had to make decomposeBitTest support vectors since InstSimplify needs that.
As InstSimplify can't use something from the Transforms library, I've moved the CmpInstAnalysis code to the Analysis library.
Differential Revision: https://reviews.llvm.org/D36593
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310869
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Craig Topper [Mon, 14 Aug 2017 18:49:39 +0000 (18:49 +0000)]
[InstSimplify] Add some tests cases for selects with bittests hidden in ugt/ult/uge/ule compares. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310868
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Lei Huang [Mon, 14 Aug 2017 18:09:29 +0000 (18:09 +0000)]
[PowerPC] Add codegen for VSX word extract convert to FP
Add codegen for VSX word extract conversion from signed/unsigned to single/double
precision.
For UINT_TO_FP:
Extract word unsigned and convert to float was implemented in https://reviews.llvm.org/D20239.
Here we will add the missing extract integer and conversion to double. This
utilizes the new P9 instruction xxextractuw to extracting an integer element
when the result will be converted to double thereby saving 2 direct moves
(VSR <-> GPR).
For SINT_TO_FP:
We will implement the following sequence which will also reduce the number of
instructions by saving 2 direct moves.
v4i32->f32:
xxspltw
xvcvsxwsp
xscvspdpn
v4i32->f64:
xxspltw
xvcvsxwdp
Differential Revision: https://reviews.llvm.org/D35859
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310866
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Aditya Nandakumar [Mon, 14 Aug 2017 17:25:11 +0000 (17:25 +0000)]
[GISel]: Add some helper constructors to MIRBuilder
https://reviews.llvm.org/D36636
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310860
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Hal Finkel [Mon, 14 Aug 2017 17:11:43 +0000 (17:11 +0000)]
[ValueTracking] Don't delete assumes of side-effectful instructions
ValueTracking has to strike a balance when attempting to propagate information
backwards from assumes, because if the information is trivially propagated
backwards, it can appear to LLVM that the assumption is known to be true, and
therefore can be removed.
This is sound (because an assumption has no semantic effect except for causing
UB), but prevents the assume from allowing further optimizations.
The isEphemeralValueOf check exists to try and prevent this issue by not
removing the source of an assumption. This tries to make it a little bit more
general to handle the case of side-effectful instructions, such as in
%0 = call i1 @get_val()
%1 = xor i1 %0, true
call void @llvm.assume(i1 %1)
Patch by Ariel Ben-Yehuda, thanks!
Differential Revision: https://reviews.llvm.org/D36590
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310859
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Simon Dardis [Mon, 14 Aug 2017 16:20:33 +0000 (16:20 +0000)]
Revert "Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""
This reverts r310834. It didn't pacify the buildbot, FileCheck is still
crashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310854
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Sanjay Patel [Mon, 14 Aug 2017 15:55:43 +0000 (15:55 +0000)]
[x86] fold the mask op on 8- and 16-bit rotates
Ref the post-commit thread for r310770:
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20170807/478507.html
The motivating cases as 'C' source examples can look like this:
unsigned char rotate_right_8(unsigned char v, int shift) {
// shift &= 7;
v = ( v >> shift ) | ( v << ( 8 - shift ) );
return v;
}
https://godbolt.org/g/K6rc1A
Notice that the source doesn't contain UB-safe masked shift amounts, but instcombine created those
in order to produce narrow rotate patterns. This should be the last step needed to resolve PR34046:
https://bugs.llvm.org/show_bug.cgi?id=34046
Differential Revision: https://reviews.llvm.org/D36644
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310849
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Dinar Temirbulatov [Mon, 14 Aug 2017 15:40:16 +0000 (15:40 +0000)]
[SLPVectorizer] Schedule bundle with different opcodes.
This change let us schedule a bundle with different opcodes in it, for example : [ load, add, add, add ]
Reviewers: mkuper, RKSimon, ABataev, mzolotukhin, spatel, filcab
Subscribers: llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D36518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310847
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Craig Topper [Mon, 14 Aug 2017 15:32:40 +0000 (15:32 +0000)]
[X86] Fix a place that was mishandling X86ISD::UMUL.
According to the X86ISelLowering.h, UMUL results are low, high, and flags. But this place was treating result 1 or 2 as flags.
Differential Revision: https://reviews.llvm.org/D36654
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310846
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Craig Topper [Mon, 14 Aug 2017 15:28:49 +0000 (15:28 +0000)]
[X86] Remove flag setting ISD nodes from computeKnownBitsForTargetNode
Summary:
The flag result is an i32 type. But its only really used for connectivity. I don't think anything even assumes a particular format. We don't ever do any real operations on it. So known bits don't help us optimize anything.
My main motivation is that the UMUL behavior is actually wrong. I was going to fix this in D36654, but then realized there was just no reason for it to be here.
Reviewers: RKSimon, zvi, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36657
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310845
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Craig Topper [Mon, 14 Aug 2017 15:28:48 +0000 (15:28 +0000)]
[AVX512] Make the itinerary parameter actually pass through the the AVX512_maskable_common multiclass
Summary: This looks to have been disconnected about 3 years ago in r219358.
Reviewers: gadi.haber, RKSimon, zvi
Reviewed By: gadi.haber
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310844
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Craig Topper [Mon, 14 Aug 2017 15:28:47 +0000 (15:28 +0000)]
[AVX512] Remove leftover code for when i1 was a legal type from the fast isel load/store code.
Summary:
I don't think we need this code anymore. It only existed because i1 used to be legal.
There's probably more unneeded code in fast isel still.
Reviewers: guyblank, zvi
Reviewed By: guyblank
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36652
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310843
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Sanjay Patel [Mon, 14 Aug 2017 15:13:46 +0000 (15:13 +0000)]
[BDCE] reduce scope of an assert (PR34179)
The assert was added with r310779 and is usually correct,
but as the test shows, not always. The 'volatile' on the
load is needed to expose the faulty path because without
it, DemandedBits would return that the load is just dead
rather than not demanded, and so we wouldn't hit the
bogus assert.
Also, since the lambda is just a single-line now, get rid
of it and inline the DB.isAllOnesValue() calls.
This should fix (prevent execution of a faulty assert):
https://bugs.llvm.org/show_bug.cgi?id=34179
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310842
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Simon Dardis [Mon, 14 Aug 2017 12:28:00 +0000 (12:28 +0000)]
Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."
This adjusts the tests to hopfully pacify the llvm-clang-x86_64-expensive-checks-win
buildbot.
Unlike many other instructions, these instructions have aliases which
take coprocessor registers, gpr register, accumulator (and dsp accumulator)
registers, floating point registers, floating point control registers and
coprocessor 2 data and control operands.
For the moment, these aliases are treated as pseudo instructions which are
expanded into the underlying instruction. As a result, disassembling these
instructions shows the underlying instruction and not the alias.
Reviewers: slthakur, atanasyan
Differential Revision: https://reviews.llvm.org/D35253
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310834
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Amaury Sechet [Mon, 14 Aug 2017 11:44:03 +0000 (11:44 +0000)]
[DAGCombine] Do not try to deduplicate commutative operations if both operand are the same.
Summary: It is creating useless work as the commuted nodes is the same as the node we are working on in that case.
Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D33840
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310832
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Elad Cohen [Mon, 14 Aug 2017 10:49:45 +0000 (10:49 +0000)]
[SelectionDAG] combine vextract (v1iX extract_subvector(vNiX, Idx))
into vextract(vNiX,Idx) when creating vextract with getNode().
This case appeared in AVX512 after fixing pr33349 in r310552.
Differential revision: https://reviews.llvm.org/D36571
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310828
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Sean Eveson [Mon, 14 Aug 2017 10:20:12 +0000 (10:20 +0000)]
[llvm-cov] Add an option which maps the location of source directories on another machine to your local copies
Summary:
This patch adds the -path-equivalence option (example: llvm-cov show -path-equivalence=/origin/path,/local/path) which maps the source code path from one machine to another when using `llvm-cov show`. This is similar to the -filename-equivalence option, but doesn't require you to specify all the source files on the command line.
This allows you to generate the coverage data on one machine (e.g. in a CI system), and then use llvm-cov on another machine where you have the same code base on a different path.
Reviewers: vsk
Reviewed By: vsk
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310827
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Balaram Makam [Mon, 14 Aug 2017 09:41:40 +0000 (09:41 +0000)]
MachineInstr: Reason locally about some memory objects before going to AA.
This addresses a FIXME in MachineInstr::mayAlias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310825
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Sam Parker [Mon, 14 Aug 2017 09:25:26 +0000 (09:25 +0000)]
[LoopUnroll] Enable option to peel remainder loop
On some targets, the penalty of executing runtime unrolling checks
and then not the unrolled loop can be significantly detrimental to
performance. This results in the need to be more conservative with
the unroll count, keeping a trip count of 2 reduces the overhead as
well as increasing the chance of the unrolled body being executed. But
being conservative leaves performance gains on the table.
This patch enables the unrolling of the remainder loop introduced by
runtime unrolling. This can help reduce the overhead of misunrolled
loops because the cost of non-taken branches is much less than the
cost of the backedge that would normally be executed in the remainder
loop. This allows larger unroll factors to be used without suffering
performance loses with smaller iteration counts.
Differential Revision: https://reviews.llvm.org/D36309
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310824
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Sam Parker [Mon, 14 Aug 2017 09:16:13 +0000 (09:16 +0000)]
[AArch64] Remove unused MC function
An unused function warning was raised in
https://bugs.llvm.org/show_bug.cgi?id=34178.
The offending function, in AArch64MCCodeEmitter.cpp, was committed by
me last week.
Differential Revision: https://reviews.llvm.org/D36665
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310823
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Elad Cohen [Mon, 14 Aug 2017 09:06:00 +0000 (09:06 +0000)]
Revert "[DAGCombiner] Extending pattern detection for vector shuffle (REAPPLIED)"
This reverts commit r310782.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310822
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Chandler Carruth [Mon, 14 Aug 2017 07:03:24 +0000 (07:03 +0000)]
[ValueTracking] Revert r310583 which enabled functionality that still is
causing compile time issues.
Moreover, the patch *deleted* the flag in addition to changing the
default, and links to a code review that doesn't even discuss the flag
and just has an update to a Clang test case.
I've followed up on the commit thread to ask for numbers on compile time
at this point, leaving the flag in place until things stabilize, and
pointing at specific code that seems to exhibit excessive compile time
with this patch.
Original commit message for r310583:
"""
[ValueTracking] Enabling ValueTracking patch by default (recommit). Part 2.
The original patch was an improvement to IR ValueTracking on
non-negative integers. It has been checked in to trunk (D18777,
r284022). But was disabled by default due to performance regressions.
Perf impact has improved. The patch would be enabled by default.
""""
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310816
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Craig Topper [Mon, 14 Aug 2017 05:09:34 +0000 (05:09 +0000)]
[AVX-512] Add hasSideEffects = 0 to the 8-bit and 16-bit register broadcasts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310813
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Craig Topper [Mon, 14 Aug 2017 05:09:33 +0000 (05:09 +0000)]
[X86] Remove unused argument from the vextract_for_size multiclass. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310812
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Craig Topper [Mon, 14 Aug 2017 05:09:31 +0000 (05:09 +0000)]
[AVX512] Remove comment I should have removed in r310808. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310811
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Brian Gesiak [Mon, 14 Aug 2017 04:16:43 +0000 (04:16 +0000)]
[opt-viewer] Listify `dict_items` for Py3 indexing
Summary:
In Python 2, calling `dict.items()` returns an indexable `list`, whereas
on Python 3 it returns a set-like `dict_items` object, which cannot be
indexed. Explicitly onvert the `dict_items` object so that it can be
indexed when using Python 3.
In combination with D36622, D36623, and D36624, this change allows
`opt-viewer.py` to exit successfully when run with Python 3.4.
Test Plan:
Run `opt-viewer.py` using Python 3.4 and confirm it does not encounter a
runtime error when when indexing into `dict.items()`.
Reviewers: anemet
Reviewed By: anemet
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36630
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310810
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Chandler Carruth [Mon, 14 Aug 2017 03:41:00 +0000 (03:41 +0000)]
[PowerPC] Revert r310346 (and followups r310356 & r310424) which
introduce a miscompile bug.
There appears to be a bug where the generated code to extract the sign
bit doesn't work correctly for 32-bit inputs. I've replied to the
original commit pointing out the problem. I think I see by inspection
(and reading the manual for PPC) how to fix this, but I can't be 100%
confident and I also don't know what the best way to test this is.
Currently it seems nearly impossible to get the backend to hit this code
path, but the patch autohr is likely in a better position to craft such
test cases than I am, and based on where the bug is it should be easily
done.
Original commit message for r310346:
"""
[PowerPC] Eliminate compares - add i32 sext/zext handling for SETLE/SETGE
Adds handling for SETLE/SETGE comparisons on i32 values. Furthermore, it
adds the handling for the special case where RHS == 0.
Differential Revision: https://reviews.llvm.org/D34048
"""
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310809
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Craig Topper [Mon, 14 Aug 2017 01:53:10 +0000 (01:53 +0000)]
[AVX512] Simplify the instruction defintion for VEXTRACT. NFCI
The comment about why we couldn't use avx512_maskable appears to have been incorrect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310808
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Javed Absar [Mon, 14 Aug 2017 01:38:01 +0000 (01:38 +0000)]
[ARM] Tidy-up Cortex-A15 DPR-SPR optimizer implementation
Modernise the code with range-loops etc
Reviewed by: @fhahn, @rovka
Differential Revision: https://reviews.llvm.org/D36502
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310807
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Craig Topper [Mon, 14 Aug 2017 00:04:21 +0000 (00:04 +0000)]
[InstCombine] Simplify and inline FoldOrWithConstants/FoldXorWithConstants
Summary:
These functions were overly complicated. The body of this function was rechecking for an And operation to find the constant, but we already knew we were looking at two Ands ORed together and the pieces are in variables. We already had earlier nearby code that checked for ConstantInts. So just inline the remaining parts into the earlier code.
Next step is to use m_APInt instead of ConstantInt.
Reviewers: spatel, efriedma, davide, majnemer
Reviewed By: spatel
Subscribers: zzheng, llvm-commits
Differential Revision: https://reviews.llvm.org/D36439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310806
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Simon Pilgrim [Sun, 13 Aug 2017 20:35:38 +0000 (20:35 +0000)]
[X86][BMI] Add BEXTR demanded bits test cases (PR34042)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310802
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Craig Topper [Sun, 13 Aug 2017 20:21:12 +0000 (20:21 +0000)]
[X86] Fix typo from r310794. Index = 0 should have been Index == 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310801
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