OSDN Git Service
Markus Armbruster [Thu, 26 Apr 2018 15:28:05 +0000 (17:28 +0200)]
qobject: Use qobject_to() instead of type cast
The proper way to convert from (abstract) QObject to a (concrete)
subtype is qobject_to(). Look for offenders that type cast instead:
$ git-grep '(Q[A-Z][a-z]* \*)'
hmp.c: qmp_device_add((QDict *)qdict, NULL, &err);
include/qapi/qmp/qobject.h: return (QObject *)obj;
qobject/qobject.c:static void (*qdestroy[QTYPE__MAX])(QObject *) = {
tests/check-qdict.c: dst = (QDict *)qdict_crumple(src, &error_abort);
The first two cast away const, the third isn't a type cast. Fix the
fourth.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <
20180426152805.8469-1-armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Peter Maydell [Thu, 3 May 2018 10:25:14 +0000 (11:25 +0100)]
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-
20180502' into staging
Queued TCG patches
# gpg: Signature made Wed 02 May 2018 18:43:33 BST
# gpg: using RSA key
64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-tcg-
20180502:
tcg: workaround branch instruction overflow in tcg_out_qemu_ld/st
tcg: Improve TCGv_ptr support
tcg: Allow wider vectors for cmp and mul
tcg/arm: Fix memory barrier encoding
tcg: Document INDEX_mul[us]h_*
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Thu, 3 May 2018 09:27:26 +0000 (10:27 +0100)]
Merge remote-tracking branch 'remotes/gkurz/tags/for-upstream' into staging
Just one trace
# gpg: Signature made Wed 02 May 2018 07:59:38 BST
# gpg: using RSA key
71D4D5E5822F73D6
# gpg: Good signature from "Greg Kurz <groug@kaod.org>"
# gpg: aka "Gregory Kurz <gregory.kurz@free.fr>"
# gpg: aka "[jpeg image of size 3330]"
# Primary key fingerprint: B482 8BAF 9431 40CE F2A3 4910 71D4 D5E5 822F 73D6
* remotes/gkurz/tags/for-upstream:
9p: add trace event for v9fs_setattr()
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Greg Kurz [Wed, 2 May 2018 06:59:24 +0000 (08:59 +0200)]
9p: add trace event for v9fs_setattr()
Don't print the tv_nsec part of atime and mtime, to stay below the 10
argument limit of trace events.
Signed-off-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Laurent Vivier [Sun, 29 Apr 2018 23:58:40 +0000 (01:58 +0200)]
tcg: workaround branch instruction overflow in tcg_out_qemu_ld/st
ppc64 uses a BC instruction to call the tcg_out_qemu_ld/st
slow path. BC instruction uses a relative address encoded
on 14 bits.
The slow path functions are added at the end of the generated
instructions buffer, in the reverse order of the callers.
So more we have slow path functions more the distance between
the caller (BC) and the function increases.
This patch changes the behavior to generate the functions in
the same order of the callers.
Cc: qemu-stable@nongnu.org
Fixes:
15fa08f845 ("tcg: Dynamically allocate TCGOps")
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Message-Id: <
20180429235840.16659-1-lvivier@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 23 Feb 2018 02:17:57 +0000 (18:17 -0800)]
tcg: Improve TCGv_ptr support
Drop TCGV_PTR_TO_NAT and TCGV_NAT_TO_PTR internal macros.
Add tcg_temp_local_new_ptr, tcg_gen_brcondi_ptr, tcg_gen_ext_i32_ptr,
tcg_gen_trunc_i64_ptr, tcg_gen_extu_ptr_i64, tcg_gen_trunc_ptr_i32.
Use inlines instead of macros where possible.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 17 Apr 2018 21:35:42 +0000 (11:35 -1000)]
tcg: Allow wider vectors for cmp and mul
In
db432672, we allow wide inputs for operations such as add.
However, in
212be173 and
3774030a we didn't do the same for
compare and multiply.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Henry Wertz [Tue, 17 Apr 2018 22:06:23 +0000 (12:06 -1000)]
tcg/arm: Fix memory barrier encoding
I found with qemu 2.11.x or newer that I would get an illegal instruction
error running some Intel binaries on my ARM chromebook. On investigation,
I found it was quitting on memory barriers.
qemu instruction:
mb $0x31
was translating as:
0x604050cc:
5bf07ff5 blpl #0x600250a8
After patch it gives:
0x604050cc:
f57ff05b dmb ish
In short, I found INSN_DMB_ISH (memory barrier for ARMv7) appeared to be
correct based on online docs, but due to some endian-related shenanigans it
had to be byte-swapped to suit qemu; it appears INSN_DMB_MCR (memory
barrier for ARMv6) also should be byte swapped (and this patch does so).
I have not checked for correctness of aarch64's barrier instruction.
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Henry Wertz <hwertz10@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 17 Apr 2018 17:18:01 +0000 (07:18 -1000)]
tcg: Document INDEX_mul[us]h_*
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Peter Maydell [Tue, 1 May 2018 14:26:06 +0000 (15:26 +0100)]
Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.13-pull-request' into staging
# gpg: Signature made Tue 01 May 2018 14:53:58 BST
# gpg: using RSA key
F30C38BD3F2FBE3C
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>"
# gpg: aka "Laurent Vivier <laurent@vivier.eu>"
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>"
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier/tags/m68k-for-2.13-pull-request:
hw/m68k/mcf5208: Fix trivial typo in board description
m68k: remove dead code (Coverity CID1390617)
m68k: Fix floatx80_lognp1 (Coverity CID1390587)
m68k: fix subx mem, mem instruction
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Thomas Huth [Sun, 29 Apr 2018 07:40:02 +0000 (09:40 +0200)]
hw/m68k/mcf5208: Fix trivial typo in board description
It's the MCF5208 evaluation board, not the MCF5206 eval board.
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <
20180429094002.
3293c9de@thl530.multi.box>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Laurent Vivier [Mon, 30 Apr 2018 17:01:56 +0000 (19:01 +0200)]
m68k: remove dead code (Coverity CID1390617)
floatx80_sin() and floatx80_cos() are derived from one
sincos() function. They have both unused code coming from
their common origin. Remove it.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20180430170156.1860-2-laurent@vivier.eu>
Laurent Vivier [Mon, 30 Apr 2018 17:01:55 +0000 (19:01 +0200)]
m68k: Fix floatx80_lognp1 (Coverity CID1390587)
return the result of packFloatx80() instead of
dropping it.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20180430170156.1860-1-laurent@vivier.eu>
Peter Maydell [Mon, 30 Apr 2018 15:12:00 +0000 (16:12 +0100)]
Merge remote-tracking branch 'remotes/edgar/tags/edgar/xilinx-next-2018-04-30.for-upstream' into staging
edgar/xilinx-next-2018-01.for-upstream
# gpg: Signature made Mon 30 Apr 2018 15:52:35 BST
# gpg: using RSA key
29C596780F6BCA83
# gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>"
# gpg: aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>"
# Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF 4151 29C5 9678 0F6B CA83
* remotes/edgar/tags/edgar/xilinx-next-2018-04-30.for-upstream:
target-microblaze: mmu: Make the TLBX MISS bit read-only
target-microblaze: mmu: Make TLBSX write-only
target-microblaze: Don't clobber the IMM reg for ld/st reversed
target-microblaze: Fix trap checks for FPU insns
target-microblaze: Respect MSR.PVR as read-only
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Edgar E. Iglesias [Sun, 15 Apr 2018 21:21:06 +0000 (23:21 +0200)]
target-microblaze: mmu: Make the TLBX MISS bit read-only
Make the TLBX MISS bit read-only.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Edgar E. Iglesias [Sun, 15 Apr 2018 21:05:22 +0000 (23:05 +0200)]
target-microblaze: mmu: Make TLBSX write-only
Make TLBSX write-only and guest-error log reads from it.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Edgar E. Iglesias [Fri, 13 Apr 2018 18:45:14 +0000 (20:45 +0200)]
target-microblaze: Don't clobber the IMM reg for ld/st reversed
Do not clobber the IMM register on reversed load/stores.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Edgar E. Iglesias [Sat, 14 Apr 2018 16:58:56 +0000 (18:58 +0200)]
target-microblaze: Fix trap checks for FPU insns
Fix trap checks for FPU insns when extended FPU insns are enabled.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Edgar E. Iglesias [Sat, 14 Apr 2018 16:06:34 +0000 (18:06 +0200)]
target-microblaze: Respect MSR.PVR as read-only
Respect MSR.PVR as read-only. We were wrongly overwriting the PVR bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Pavel Dovgalyuk [Wed, 18 Apr 2018 06:41:53 +0000 (09:41 +0300)]
m68k: fix subx mem, mem instruction
This patch fixes decrement of the pointers for subx mem, mem instructions.
Without the patch pointers are decremented by OS_* constant value instead of
retrieving the corresponding data size and using it as a decrement.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <
20180418064152.24606.71975.stgit@pasha-VirtualBox>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Peter Maydell [Mon, 30 Apr 2018 09:43:41 +0000 (10:43 +0100)]
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-2.13-pull-request' into staging
# gpg: Signature made Mon 30 Apr 2018 10:05:56 BST
# gpg: using RSA key
F30C38BD3F2FBE3C
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>"
# gpg: aka "Laurent Vivier <laurent@vivier.eu>"
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>"
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier2/tags/linux-user-for-2.13-pull-request: (42 commits)
linux-user: Add ARM get_tls syscall support
linux-user: move xtensa cpu loop to xtensa directory
linux-user: move hppa cpu loop to hppa directory
linux-user: move riscv cpu loop to riscv directory
linux-user: move tilegx cpu loop to tilegx directory
linux-user: move s390x cpu loop to s390x directory
linux-user: move alpha cpu loop to alpha directory
linux-user: move m68k cpu loop to m68k directory
linux-user: move microblaze cpu loop to microblaze directory
linux-user: move cris cpu loop to cris directory
linux-user: move sh4 cpu loop to sh4 directory
linux-user: move openrisc cpu loop to openrisc directory
linux-user: move nios2 cpu loop to nios2 directory
linux-user: move mips/mips64 cpu loop to mips directory
linux-user: move ppc/ppc64 cpu loop to ppc directory
linux-user: move sparc/sparc64 cpu loop to sparc directory
linux-user: move arm cpu loop to arm directory
linux-user: move aarch64 cpu loop to aarch64 directory
linux-user: move i386/x86_64 cpu loop to i386 directory
linux-user: create a dummy per arch cpu_loop.c
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Christophe Lyon [Mon, 16 Apr 2018 09:18:25 +0000 (11:18 +0200)]
linux-user: Add ARM get_tls syscall support
Co-Authored-By: Mickaël Guêné <mickael.guene@st.com>
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20180416091845.7315-1-christophe.lyon@st.com>
[lv: moved the change to linux-user/arm/cpu_loop.c]
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Laurent Vivier [Wed, 11 Apr 2018 18:56:51 +0000 (20:56 +0200)]
linux-user: move xtensa cpu loop to xtensa directory
No code change, only move code from main.c to
xtensa/cpu_loop.c.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180411185651.21351-20-laurent@vivier.eu>
Laurent Vivier [Wed, 11 Apr 2018 18:56:50 +0000 (20:56 +0200)]
linux-user: move hppa cpu loop to hppa directory
No code change, only move code from main.c to
hppa/cpu_loop.c.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20180411185651.21351-19-laurent@vivier.eu>
Laurent Vivier [Wed, 11 Apr 2018 18:56:49 +0000 (20:56 +0200)]
linux-user: move riscv cpu loop to riscv directory
No code change, only move code from main.c to
riscv/cpu_loop.c.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20180411185651.21351-18-laurent@vivier.eu>
Laurent Vivier [Wed, 11 Apr 2018 18:56:48 +0000 (20:56 +0200)]
linux-user: move tilegx cpu loop to tilegx directory
No code change, only move code from main.c to
tilegx/cpu_loop.c.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180411185651.21351-17-laurent@vivier.eu>
Laurent Vivier [Wed, 11 Apr 2018 18:56:47 +0000 (20:56 +0200)]
linux-user: move s390x cpu loop to s390x directory
No code change, only move code from main.c to
s390x/cpu_loop.c.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20180411185651.21351-16-laurent@vivier.eu>
Laurent Vivier [Wed, 11 Apr 2018 18:56:46 +0000 (20:56 +0200)]
linux-user: move alpha cpu loop to alpha directory
No code change, only move code from main.c to
alpha/cpu_loop.c.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20180411185651.21351-15-laurent@vivier.eu>
Laurent Vivier [Wed, 11 Apr 2018 18:56:45 +0000 (20:56 +0200)]
linux-user: move m68k cpu loop to m68k directory
No code change, only move code from main.c to
m68k/cpu_loop.c.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180411185651.21351-14-laurent@vivier.eu>
Laurent Vivier [Wed, 11 Apr 2018 18:56:44 +0000 (20:56 +0200)]
linux-user: move microblaze cpu loop to microblaze directory
No code change, only move code from main.c to
microblaze/cpu_loop.c.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20180411185651.21351-13-laurent@vivier.eu>
Laurent Vivier [Wed, 11 Apr 2018 18:56:43 +0000 (20:56 +0200)]
linux-user: move cris cpu loop to cris directory
No code change, only move code from main.c to
cris/cpu_loop.c.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20180411185651.21351-12-laurent@vivier.eu>
Laurent Vivier [Wed, 11 Apr 2018 18:56:42 +0000 (20:56 +0200)]
linux-user: move sh4 cpu loop to sh4 directory
No code change, only move code from main.c to
sh4/cpu_loop.c.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20180411185651.21351-11-laurent@vivier.eu>
Laurent Vivier [Wed, 11 Apr 2018 18:56:41 +0000 (20:56 +0200)]
linux-user: move openrisc cpu loop to openrisc directory
No code change, only move code from main.c to
openrisc/cpu_loop.c.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180411185651.21351-10-laurent@vivier.eu>
Laurent Vivier [Wed, 11 Apr 2018 18:56:40 +0000 (20:56 +0200)]
linux-user: move nios2 cpu loop to nios2 directory
No code change, only move code from main.c to
nios2/cpu_loop.c.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180411185651.21351-9-laurent@vivier.eu>
Laurent Vivier [Wed, 11 Apr 2018 18:56:39 +0000 (20:56 +0200)]
linux-user: move mips/mips64 cpu loop to mips directory
No code change, only move code from main.c to
mips/cpu_loop.c.
Include mips/cpu_loop.c in mips64/cpu_loop.c
to avoid to duplicate code.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20180411185651.21351-8-laurent@vivier.eu>
Laurent Vivier [Wed, 11 Apr 2018 18:56:38 +0000 (20:56 +0200)]
linux-user: move ppc/ppc64 cpu loop to ppc directory
No code change, only move code from main.c to
ppc/cpu_loop.c.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180411185651.21351-7-laurent@vivier.eu>
Laurent Vivier [Wed, 11 Apr 2018 18:56:37 +0000 (20:56 +0200)]
linux-user: move sparc/sparc64 cpu loop to sparc directory
No code change, only move code from main.c to
sparc/cpu_loop.c.
Include sparc/cpu_loop.c in sparc64/cpu_loop.c
to avoid to duplicate code.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20180411185651.21351-6-laurent@vivier.eu>
Laurent Vivier [Wed, 11 Apr 2018 18:56:36 +0000 (20:56 +0200)]
linux-user: move arm cpu loop to arm directory
No code change, only move code from main.c to
arm/cpu_loop.c and duplicate some macro
defined for both arm and aarch64.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180411185651.21351-5-laurent@vivier.eu>
Laurent Vivier [Wed, 11 Apr 2018 18:56:35 +0000 (20:56 +0200)]
linux-user: move aarch64 cpu loop to aarch64 directory
No code change, only move code from main.c to
aarch64/cpu_loop.c and duplicate some macro
defined for both arm and aarch64.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180411185651.21351-4-laurent@vivier.eu>
Laurent Vivier [Wed, 11 Apr 2018 18:56:34 +0000 (20:56 +0200)]
linux-user: move i386/x86_64 cpu loop to i386 directory
No code change, only move code from main.c to
i386/cpu_loop.c.
Include i386/cpu_loop.c in x86_64/cpu_loop.c
to avoid to duplicate code.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180411185651.21351-3-laurent@vivier.eu>
Laurent Vivier [Wed, 11 Apr 2018 18:56:33 +0000 (20:56 +0200)]
linux-user: create a dummy per arch cpu_loop.c
Create a cpu_loop-common.h for future use by
these new files and use it in the existing
main.c
Introduce target_cpu_copy_regs():
declare the function in cpu_loop-common.h
and an empty function for each target,
to move all the cpu_loop prologues to this function.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180411185651.21351-2-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:35 +0000 (21:26 +0200)]
linux-user: define TARGET_ARCH_HAS_SETUP_FRAME
Instead of calling setup_frame() conditionally to a list of known targets,
define TARGET_ARCH_HAS_SETUP_FRAME if the target provides the function
and call it only if the macro is defined.
Move declarations of setup_frame() and setup_rt_frame() to
linux-user/signal-common.h
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180424192635.6027-21-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:34 +0000 (21:26 +0200)]
linux-user: move ppc/ppc64 signal.c parts to ppc directory
No code change, only move code from signal.c to
ppc/signal.c, except adding includes and
exporting setup_frame() and setup_rt_frame().
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180424192635.6027-20-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:33 +0000 (21:26 +0200)]
linux-user: move mips/mips64 signal.c parts to mips directory
No code change, only move code from signal.c to
mips/signal.c, except adding includes and
exporting setup_frame() and setup_rt_frame().
mips64/signal.c includes mips/signal.c
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180424192635.6027-19-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:32 +0000 (21:26 +0200)]
linux-user: move sparc/sparc64 signal.c parts to sparc directory
No code change, only move code from signal.c to
sparc/signal.c, except adding includes and
exporting setup_frame() and setup_rt_frame().
sparc64/signal.c includes sparc/signal.c
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180424192635.6027-18-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:31 +0000 (21:26 +0200)]
linux-user: move i386/x86_64 signal.c parts to i386 directory
No code change, only move code from signal.c to
i386/signal.c, except adding includes and
exporting setup_frame() and setup_rt_frame().
x86_64/signal.c includes i386/signal.c
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180424192635.6027-17-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:30 +0000 (21:26 +0200)]
linux-user: move xtensa signal.c parts to xtensa directory
No code change, only move code from signal.c to
xtensa/signal.c, except adding includes and
exporting setup_rt_frame().
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180424192635.6027-16-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:29 +0000 (21:26 +0200)]
linux-user: move hppa signal.c parts to hppa directory
No code change, only move code from signal.c to
hppa/signal.c, except adding includes and
exporting setup_rt_frame().
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180424192635.6027-15-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:28 +0000 (21:26 +0200)]
linux-user: move riscv signal.c parts to riscv directory
No code change, only move code from signal.c to
riscv/signal.c, except adding includes and
exporting setup_rt_frame().
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180424192635.6027-14-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:27 +0000 (21:26 +0200)]
linux-user: move tilegx signal.c parts to tilegx directory
No code change, only move code from signal.c to
tilegx/signal.c, except adding includes and
exporting setup_rt_frame().
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20180424192635.6027-13-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:26 +0000 (21:26 +0200)]
linux-user: move alpha signal.c parts to alpha directory
No code change, only move code from signal.c to
alpha/signal.c, except adding includes and
exporting setup_frame() and setup_rt_frame().
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180424192635.6027-12-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:25 +0000 (21:26 +0200)]
linux-user: move m68k signal.c parts to m68k directory
No code change, only move code from signal.c to
m68k/signal.c, except adding includes and
exporting setup_frame() and setup_rt_frame().
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180424192635.6027-11-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:24 +0000 (21:26 +0200)]
linux-user: move s390x signal.c parts to s390x directory
No code change, only move code from signal.c to
s390x/signal.c, except adding includes and
exporting setup_frame() and setup_rt_frame().
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180424192635.6027-10-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:23 +0000 (21:26 +0200)]
linux-user: move openrisc signal.c parts to openrisc directory
No code change, only move code from signal.c to
openrisc/signal.c, except adding includes and
exporting setup_rt_frame().
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180424192635.6027-9-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:22 +0000 (21:26 +0200)]
linux-user: move nios2 signal.c parts to nios2 directory
No code change, only move code from signal.c to
nios2/signal.c, except adding includes and
exporting setup_rt_frame().
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180424192635.6027-8-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:21 +0000 (21:26 +0200)]
linux-user: move cris signal.c parts to cris directory
No code change, only move code from signal.c to
cris/signal.c, except adding includes and
exporting setup_frame() and setup_rt_frame().
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180424192635.6027-7-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:20 +0000 (21:26 +0200)]
linux-user: move microblaze signal.c parts to microblaze directory
No code change, only move code from signal.c to
microblaze/signal.c, except adding includes and
exporting setup_frame() and setup_rt_frame().
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180424192635.6027-6-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:19 +0000 (21:26 +0200)]
linux-user: move sh4 signal.c parts to sh4 directory
No code change, only move code from signal.c to
sh4/signal.c, except adding includes and
exporting setup_frame() and setup_rt_frame().
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180424192635.6027-5-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:18 +0000 (21:26 +0200)]
linux-user: move arm signal.c parts to arm directory
No code change, only move code from signal.c to
arm/signal.c, except adding includes and
exporting setup_frame() and setup_rt_frame().
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180424192635.6027-4-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:17 +0000 (21:26 +0200)]
linux-user: move aarch64 signal.c parts to aarch64 directory
No code change, only move code from signal.c to
aarch64/signal.c, except adding includes and
exporting setup_frame() and setup_rt_frame().
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180424192635.6027-3-laurent@vivier.eu>
Laurent Vivier [Tue, 24 Apr 2018 19:26:16 +0000 (21:26 +0200)]
linux-user: create a dummy per arch signal.c
Create a signal-common.h for future use by these new files
and use it in the existing signal.c
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20180424192635.6027-2-laurent@vivier.eu>
Peter Maydell [Thu, 19 Apr 2018 12:57:40 +0000 (13:57 +0100)]
linux-user: Fix getdents emulation for 64 bit guest on 32 bit host
Currently we mishandle emulation of the getdents syscall for the
case of a 64 bit guest on a 32 bit host -- it defaults into
the 'host and guest same size' codepath and generates incorrect
structures in the guest buffer.
We can't easily handle the 64-on-32 case using the host getdents
syscall, because the guest struct dirent is bigger than the
host struct dirent, and we might find the host syscall has handed
us back more records than we can fit in the guest buffer after
conversion. Instead, always emulate 64-on-32 getdents with
the host getdents64. This avoids the buffer-overrun problem
because a dirent64 struct is always the same size on any host
and always larger than any architecture's dirent struct.
Reported-by: Henry Wertz <hwertz10@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20180419125740.2695-1-peter.maydell@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Alex Bennée [Wed, 25 Apr 2018 10:02:18 +0000 (11:02 +0100)]
linux-user: set minimum uname for RISC-V
As support for RISC-V was only merged into the mainline kernel at 4.15
it is unlikely that glibc will be happy with a reported kernel version
of 3.8.0. Indeed when I testing binaries created by the current Debian
Sid compiler the tests failed with:
FATAL: kernel too old
Bump the version to the minimum a RISC-V glibc would expect:
https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/unix/sysv/linux/riscv/configure.ac
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20180425100218.24785-1-alex.bennee@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Peter Maydell [Fri, 27 Apr 2018 11:27:59 +0000 (12:27 +0100)]
Merge remote-tracking branch 'remotes/kraxel/tags/usb-
20180427-pull-request' into staging
usb: ccid bugfix, misc small improvements.
# gpg: Signature made Fri 27 Apr 2018 11:20:18 BST
# gpg: using RSA key
4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>"
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>"
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* remotes/kraxel/tags/usb-
20180427-pull-request:
ccid-card: include libcacard.h only
Fix libusb-1.0.22 deprecated libusb_set_debug with libusb_set_option
ccid: Fix dwProtocols advertisement of T=0
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Fri, 27 Apr 2018 10:39:31 +0000 (11:39 +0100)]
Merge remote-tracking branch 'remotes/kraxel/tags/ui-
20180427-pull-request' into staging
vnc: fix use-after-free.
sdl2: gles support.
vfio-display: add reset support.
# gpg: Signature made Fri 27 Apr 2018 10:54:17 BST
# gpg: using RSA key
4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>"
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>"
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* remotes/kraxel/tags/ui-
20180427-pull-request:
ui: introduce vfio_display_reset
console: introduce dpy_gfx_update_full
sdl: Allow OpenGL ES context creation
sdl: Move DisplayOptions global to sdl2_console
qapi: Parameter gl of DisplayType now accept an enum
vnc: fix use-after-free
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Fri, 27 Apr 2018 09:49:23 +0000 (10:49 +0100)]
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.13-
20180427' into staging
ppc patch queue 2018-04-27
Here's the first batch of ppc patches for 2.13. This has a lot of
stuff that's accumulated during the 2.12 freeze. Highlights are:
* Many improvements for the Uninorth PCI host bridge for Mac
machine types
* Preliminary helpers improve handling of multiple backing
pagesizes (not strictly ppc related, but have acks and aimed to
allow future ppc changes)
* Cleanups to pseries cpu initialization
* Cleanups to hash64 MMU handling
* Assorted bugfixes and improvements
# gpg: Signature made Fri 27 Apr 2018 10:20:30 BST
# gpg: using RSA key
6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>"
# gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>"
# gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>"
# gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-2.13-
20180427: (49 commits)
Clear mem_path if we fall back to anonymous RAM allocation
spapr: Set compatibility mode before the rest of spapr_cpu_reset()
target/ppc: Don't bother with MSR_EP in cpu_ppc_set_papr()
spapr: Support ibm,dynamic-memory-v2 property
ppc: e500: switch E500 based machines to full machine definition
spapr: Add ibm,max-associativity-domains property
target/ppc: Fold slb_nr into PPCHash64Options
target/ppc: Get rid of POWERPC_MMU_VER() macros
target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model
target/ppc: Fold ci_large_pages flag into PPCHash64Options
target/ppc: Move 1T segment and AMR options to PPCHash64Options
target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs
target/ppc: Split page size information into a separate allocation
target/ppc: Move page size setup to helper function
target/ppc: Remove fallback 64k pagesize information
target/ppc: Avoid taking "env" parameter to mmu-hash64 functions
target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop()
target/ppc: Simplify cpu valid check in ppc_cpu_realize
target/ppc: Standardize instance_init and realize function names
spapr: drop useless dynamic sysbus device sanity check
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tina Zhang [Fri, 27 Apr 2018 09:11:06 +0000 (17:11 +0800)]
ui: introduce vfio_display_reset
During guest OS reboot, guest framebuffer is invalid. It will cause
bugs, if the invalid guest framebuffer is still used by host.
This patch is to introduce vfio_display_reset which is invoked
during vfio display reset. This vfio_display_reset function is used
to release the invalid display resource, disable scanout mode and
replace the invalid surface with QemuConsole's DisplaySurafce.
This patch can fix the GPU hang issue caused by gd_egl_draw during
guest OS reboot.
Changes v3->v4:
- Move dma-buf based display check into the vfio_display_reset().
(Gerd)
Changes v2->v3:
- Limit vfio_display_reset to dma-buf based vfio display. (Gerd)
Changes v1->v2:
- Use dpy_gfx_update_full() update screen after reset. (Gerd)
- Remove dpy_gfx_switch_surface(). (Gerd)
Signed-off-by: Tina Zhang <tina.zhang@intel.com>
Message-id:
1524820266-27079-3-git-send-email-tina.zhang@intel.com
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Tina Zhang [Fri, 27 Apr 2018 09:11:05 +0000 (17:11 +0800)]
console: introduce dpy_gfx_update_full
dpy_gfx_update_full is used to do the whole display surface update.
This function is proposed by Gerd Hoffmann.
Signed-off-by: Tina Zhang <tina.zhang@intel.com>
Message-id:
1524820266-27079-2-git-send-email-tina.zhang@intel.com
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Elie Tournier [Fri, 13 Apr 2018 13:58:42 +0000 (14:58 +0100)]
sdl: Allow OpenGL ES context creation
Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Message-id:
20180413135842.21325-4-tournier.elie@gmail.com
[ kraxel: fix indent ]
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Michal Privoznik [Tue, 3 Apr 2018 10:34:37 +0000 (12:34 +0200)]
ccid-card: include libcacard.h only
When trying to build with latest libcacard-2.5.1, I hit the
following error:
In file included from hw/usb/ccid-card-passthru.c:12:0:
/usr/include/cacard/vscard_common.h:26:2: error: #warning "Only <libcacard.h> can be included directly" [-Werror=cpp]
#warning "Only <libcacard.h> can be included directly"
While it was fixed in libcacard upstream (so that individual
files can be included directly), it doesn't make much sense.
Let's switch to including the main libcacard.h and also require
at least libcacard-2.5.1 which introduced it. It's available
since late 2015.
Signed-off-by: Michal Privoznik <mprivozn@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-id:
3c36db1dc0702763ebb7966cc27428ed67d43804.
1522751624.git.mprivozn@redhat.com
[ kraxel: fix include path ]
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
John Thomson [Thu, 5 Apr 2018 13:20:46 +0000 (23:20 +1000)]
Fix libusb-1.0.22 deprecated libusb_set_debug with libusb_set_option
libusb-1.0.22 marked libusb_set_debug deprecated
it is replaced with
libusb_set_option(libusb_context, LIBUSB_OPTION_LOG_LEVEL, libusb_log_level);
details here: https://github.com/libusb/libusb/commit/
539f22e2fd916558d11ab9a66f10f461c5593168
Warning here:
CC hw/usb/host-libusb.o
/builds/xen/src/qemu-xen/hw/usb/host-libusb.c: In function 'usb_host_init':
/builds/xen/src/qemu-xen/hw/usb/host-libusb.c:250:5: error: 'libusb_set_debug' is deprecated: Use libusb_set_option instead [-Werror=deprecated-declarations]
libusb_set_debug(ctx, loglevel);
^~~~~~~~~~~~~~~~
In file included from /builds/xen/src/qemu-xen/hw/usb/host-libusb.c:40:0:
/usr/include/libusb-1.0/libusb.h:1300:18: note: declared here
void LIBUSB_CALL libusb_set_debug(libusb_context *ctx, int level);
^~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
make: *** [/builds/xen/src/qemu-xen/rules.mak:66: hw/usb/host-libusb.o] Error 1
make: Leaving directory '/builds/xen/src/xen/tools/qemu-xen-build'
Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au>
Message-id:
20180405132046.4968-1-git@johnthomson.fastmail.com.au
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Jason Andryuk [Fri, 20 Apr 2018 18:32:19 +0000 (14:32 -0400)]
ccid: Fix dwProtocols advertisement of T=0
Commit
d7d218ef02d87c637d20d64da8f575d434ff6f78 attempted to change
dwProtocols to only advertise support for T=0 and not T=1. The change
was incorrect as it changed 0x00000003 to 0x00010000.
lsusb -v in a linux guest shows:
"dwProtocols 65536 (Invalid values detected)", though the
smart card could still be accessed. Windows 7 does not detect inserted
smart cards and logs the the following Error in the Event Logs:
Source: Smart Card Service
Event ID: 610
Smart Card Reader 'QEMU QEMU USB CCID 0' rejected IOCTL SET_PROTOCOL:
Incorrect function. If this error persists, your smart card or reader
may not be functioning correctly
Command Header: 03 00 00 00
Setting to 0x00000001 fixes the Windows issue.
Signed-off-by: Jason Andryuk <jandryuk@gmail.com>
Message-id:
20180420183219.20722-1-jandryuk@gmail.com
Cc: qemu-stable@nongnu.org
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
David Gibson [Thu, 19 Apr 2018 07:19:11 +0000 (17:19 +1000)]
Clear mem_path if we fall back to anonymous RAM allocation
If the -mem-path option is set, we attempt to map the guest's RAM from a
file in the given path; it's usually used to back guest RAM with hugepages.
If we're unable to (e.g. not enough free hugepages) then we fall back to
allocating normal anonymous pages. This behaviour can be surprising, but a
comment in allocate_system_memory_nonnuma() suggests it's legacy behaviour
we can't change.
What really isn't ok, though, is that in this case we leave mem_path set.
That means functions which attempt to determine the pagesize of main RAM
can erroneously think it is hugepage based on the requested path, even
though it's not.
This is particular bad for the pseries machine type. KVM HV limitations
mean the guest can't use pagesizes larger than the host page size used to
back RAM. That means that such a fallback, rather than merely giving
poorer performance than expected will cause the guest to freeze up early in
boot as it attempts to use large page mappings that can't work.
This patch addresses the problem by clearing the mem_path variable when we
fall back to anonymous pages, meaning that subsequent attempts to
determine the RAM page size will get an accurate result.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
David Gibson [Thu, 5 Apr 2018 05:49:23 +0000 (15:49 +1000)]
spapr: Set compatibility mode before the rest of spapr_cpu_reset()
Although the order doesn't really matter at the moment, it's possible
other initializastions could depend on the compatiblity mode, so make sure
we set it first in spapr_cpu_reset().
While we're at it drop the test against first_cpu. Setting the compat mode
to the value it already has is redundant, but harmless, so we might as well
make a small simplification to the code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
David Gibson [Fri, 13 Apr 2018 04:54:34 +0000 (14:54 +1000)]
target/ppc: Don't bother with MSR_EP in cpu_ppc_set_papr()
cpu_ppc_set_papr() removes the EP and HV bits from the MSR mask. While
removing the HV bit makes sense (a cpu in PAPR mode should never be
emulated in hypervisor mode), the EP bit is just bizarre. Although it's
true that a papr mode guest shouldn't be able to change the exception
prefix, the MSR[EP] bit doesn't even exist on the cpus supported for PAPR
mode, so it's pointless to do anything with it here.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Bharata B Rao [Thu, 19 Apr 2018 06:47:35 +0000 (12:17 +0530)]
spapr: Support ibm,dynamic-memory-v2 property
The new property ibm,dynamic-memory-v2 allows memory to be represented
in a more compact manner in device tree.
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Igor Mammedov [Wed, 18 Apr 2018 14:28:02 +0000 (16:28 +0200)]
ppc: e500: switch E500 based machines to full machine definition
Convert PPCE500Params to PCCE500MachineClass which it essentially is,
and introduce PCCE500MachineState to keep track of E500 specific
state instead of adding global variables or extra parameters to
functions when we need to keep data beyond machine init
(i.e. make it look like typical fully defined machine).
It's pretty shallow conversion instead of currently used trivial
DEFINE_MACHINE() macro. It adds extra 60LOC of boilerplate code
of full machine definition.
The patch on top[1] will use PCCE500MachineState to keep track of
platform_bus device and add E500Plate specific machine class
to use HOTPLUG_HANDLER for explicitly initializing dynamic
sysbus devices at the time they are added instead of delaying
it to machine done time by platform_bus_init_notify() which is
being removed.
1) <
1523551221-11612-3-git-send-email-imammedo@redhat.com>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Suggested-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Serhii Popovych [Wed, 11 Apr 2018 18:41:59 +0000 (14:41 -0400)]
spapr: Add ibm,max-associativity-domains property
Now recent kernels (i.e. since linux-stable commit
a346137e9142
("powerpc/numa: Use ibm,max-associativity-domains to discover possible nodes")
support this property to mark initially memory-less NUMA nodes as "possible"
to allow further memory hot-add to them.
Advertise this property for pSeries machines to let guest kernels detect
maximum supported node configuration and benefit from kernel side change
when hot-add memory to specific, possibly empty before, NUMA node.
Signed-off-by: Serhii Popovych <spopovyc@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
David Gibson [Thu, 29 Mar 2018 07:29:38 +0000 (18:29 +1100)]
target/ppc: Fold slb_nr into PPCHash64Options
The env->slb_nr field gives the size of the SLB (Segment Lookaside Buffer).
This is another static-after-initialization parameter of the specific
version of the 64-bit hash MMU in the CPU. So, this patch folds the field
into PPCHash64Options with the other hash MMU options.
This is a bit more complicated that the things previously put in there,
because slb_nr was foolishly included in the migration stream. So we need
some of the usual dance to handle backwards compatible migration.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
David Gibson [Fri, 23 Mar 2018 05:48:43 +0000 (16:48 +1100)]
target/ppc: Get rid of POWERPC_MMU_VER() macros
These macros were introduced to deal with the fact that the mmu_model
field has bit flags mixed in with what's otherwise an enum of various mmu
types.
We've now eliminated all those flags except for one, and that one -
POWERPC_MMU_64 - is already included/compared in the MMU_VER macros. So,
we can get rid of those macros and just directly compare mmu_model values
in the places it was used.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
David Gibson [Fri, 23 Mar 2018 05:42:45 +0000 (16:42 +1100)]
target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model
The only place we test this flag is in conjunction with
ppc64_use_proc_tbl(). That checks for the LPCR_UPRT bit, which we already
ensure can't be set except on a machine with a v3 MMU (i.e. POWER9).
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
David Gibson [Fri, 23 Mar 2018 03:32:48 +0000 (14:32 +1100)]
target/ppc: Fold ci_large_pages flag into PPCHash64Options
The ci_large_pages boolean in CPUPPCState is only relevant to 64-bit hash
MMU machines, indicating whether it's possible to map large (> 4kiB) pages
as cache-inhibitied (i.e. for IO, rather than memory). Fold it as another
flag into the PPCHash64Options structure.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
David Gibson [Fri, 23 Mar 2018 03:11:07 +0000 (14:11 +1100)]
target/ppc: Move 1T segment and AMR options to PPCHash64Options
Currently env->mmu_model is a bit of an unholy mess of an enum of distinct
MMU types, with various flag bits as well. This makes which bits of the
field should be compared pretty confusing.
Make a start on cleaning that up by moving two of the flags bits -
POWERPC_MMU_1TSEG and POWERPC_MMU_AMR - which are specific to the 64-bit
hash MMU into a new flags field in PPCHash64Options structure.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
David Gibson [Fri, 23 Mar 2018 02:59:20 +0000 (13:59 +1100)]
target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs
Currently some cpus set the hash64_opts field in the class structure, with
specific details of their variant of the 64-bit hash mmu. For the
remaining cpus with that mmu, ppc_hash64_realize() fills in defaults.
But there are only a couple of cpus that use those fallbacks, so just have
them to set the has64_opts field instead, simplifying the logic.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
David Gibson [Fri, 23 Mar 2018 02:31:52 +0000 (13:31 +1100)]
target/ppc: Split page size information into a separate allocation
env->sps contains page size encoding information as an embedded structure.
Since this information is specific to 64-bit hash MMUs, split it out into
a separately allocated structure, to reduce the basic env size for other
cpus. Along the way we make a few other cleanups:
* Rename to PPCHash64Options which is more in line with qemu name
conventions, and reflects that we're going to merge some more hash64
mmu specific details in there in future. Also rename its
substructures to match qemu conventions.
* Move structure definitions to the mmu-hash64.[ch] files.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
David Gibson [Fri, 23 Mar 2018 02:07:48 +0000 (13:07 +1100)]
target/ppc: Move page size setup to helper function
Initialization of the env->sps structure at the end of instance_init is
specific to the 64-bit hash MMU, so move the code into a helper function
in mmu-hash64.c.
We also create a corresponding function to be called at finalize time -
it's empty for now, but we'll need it shortly.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
David Gibson [Fri, 23 Mar 2018 00:24:28 +0000 (11:24 +1100)]
target/ppc: Remove fallback 64k pagesize information
CPU definitions for cpus with the 64-bit hash MMU can include a table of
available pagesizes. If this isn't supplied ppc_cpu_instance_init() will
fill it in a fallback table based on the POWERPC_MMU_64K bit in mmu_model.
However, it turns out all the cpus which support 64K pages already include
an explicit table of page sizes, so there's no point to the fallback table
including 64k pages.
That removes the only place which tests POWERPC_MMU_64K, so we can remove
it. Which in turn allows some logic to be removed from
kvm_fixup_page_sizes().
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
David Gibson [Thu, 22 Mar 2018 05:49:28 +0000 (16:49 +1100)]
target/ppc: Avoid taking "env" parameter to mmu-hash64 functions
In most cases we prefer to pass a PowerPCCPU rather than the (embedded)
CPUPPCState.
For ppc_hash64_update_{rmls,vrma}() change to take "cpu" instead of "env".
For ppc_hash64_set_{dsi,isi}() remove the redundant "env" parameter.
In theory this makes more work for the functions, but since "cs", "cpu"
and "env" are related by at most constant offsets, the compiler should be
able to optimize out the difference at effectively zero cost.
helper_*() functions are left alone - since they're more closely tied to
the TCG generated code, passing "env" is still the standard there.
While we're there, fix an incorrect indentation.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
David Gibson [Thu, 22 Mar 2018 05:18:40 +0000 (16:18 +1100)]
target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop()
As a rule we prefer to pass PowerPCCPU instead of CPUPPCState, and this
change will make some things simpler later on.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
David Gibson [Fri, 23 Mar 2018 01:55:04 +0000 (12:55 +1100)]
target/ppc: Simplify cpu valid check in ppc_cpu_realize
The #if isn't necessary, because there's a suitable one inside
ppc_cpu_is_valid(). We've already filtered for suitable cpu models in the
functions that search and register them. So by the time we get to realize
having an invalid one indicates a code error, not a user error, so an
assert() is more appropriate than error_setg().
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
David Gibson [Wed, 21 Mar 2018 04:30:13 +0000 (15:30 +1100)]
target/ppc: Standardize instance_init and realize function names
Because of the various hooks called some variant on "init" - and the rather
greater number that used to exist, I'm always wondering when a function
called simply "*_init" or "*_initfn" will be called.
To make it easier on myself, and maybe others, rename the instance_init
hooks for ppc cpus to *_instance_init(). While we're at it rename the
realize time hooks to *_realize() (from *_realizefn()) which seems to be
the more common current convention.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Greg Kurz [Wed, 11 Apr 2018 15:01:20 +0000 (17:01 +0200)]
spapr: drop useless dynamic sysbus device sanity check
Since commit
7da79a167aa11, the machine class init function registers
dynamic sysbus device types it supports. Passing an unsupported device
type on the command line causes QEMU to exit with an error message
just after machine init.
It is hence not needed to do the same sanity check at machine reset.
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Serhii Popovych [Wed, 11 Apr 2018 18:42:00 +0000 (14:42 -0400)]
Revert "spapr: Don't allow memory hotplug to memory less nodes"
This reverts commit
b556854bd8524c26b8be98ab1bfdf0826831e793.
Leave change @node type from uint32_t to to int from reverted commit
because node < 0 is always false.
Note that implementing capability or some trick to detect if guest
kernel does not support hot-add to memory: this returns previous
behavour where memory added to first non-empty node.
Signed-off-by: Serhii Popovych <spopovyc@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Greg Kurz [Wed, 11 Apr 2018 17:46:06 +0000 (19:46 +0200)]
spapr: drop useless sanity check in spapr_irq_alloc*()
Both spapr_irq_alloc() and spapr_irq_alloc_block() have an errp
parameter, but they don't use it if XICS hasn't been initialized
yet.
This is doubly wrong:
- all callers do pass a non-null Error **, ie, they expect an error
to be propagated in case of failure
- XICS obviously needs to be initialized before anything starts allocating
IRQs
So this patch turns the check into an assert.
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
David Gibson [Tue, 3 Apr 2018 05:05:45 +0000 (15:05 +1000)]
Add host_memory_backend_pagesize() helper
There are a couple places (one generic, one target specific) where we need
to get the host page size associated with a particular memory backend. I
have some upcoming code which will add another place which wants this. So,
for convenience, add a helper function to calculate this.
host_memory_backend_pagesize() returns the host pagesize for a given
HostMemoryBackend object.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
David Gibson [Tue, 3 Apr 2018 04:55:11 +0000 (14:55 +1000)]
Make qemu_mempath_getpagesize() accept NULL
qemu_mempath_getpagesize() gets the effective (host side) page size for
a block of memory backed by an mmap()ed file on the host. It requires
the mem_path parameter to be non-NULL.
This ends up meaning all the callers need a different case for handling
anonymous memory (for memory-backend-ram or default memory with -mem-path
is not specified).
We can make all those callers a little simpler by having
qemu_mempath_getpagesize() accept NULL, and treat that as the anonymous
memory case.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
David Gibson [Thu, 29 Mar 2018 07:34:22 +0000 (18:34 +1100)]
spapr: Introduce pseries-2.13 machine type
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
BALATON Zoltan [Sun, 25 Mar 2018 23:54:28 +0000 (01:54 +0200)]
target/ppc: Fix reserved bit mask of dstst instruction
According to the Vector/SIMD extension documentation bit 6 that is
currently masked is valid (listed as transient bit) but bits 7 and 8
should be reserved instead. Fix the mask to match this.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Michael Matz [Fri, 23 Feb 2018 17:29:56 +0000 (17:29 +0000)]
ppc: Fix size of ppc64 xer register
The normal gdb definition of the XER registers is only 32 bit,
and that's what the current version of power64-core.xml also
says (seems copied from gdb's). But qemu's idea of the XER register
is target_ulong (in CPUPPCState, ppc_gdb_register_len and
ppc_cpu_gdb_read_register)
That mismatch leads to the following message when attaching
with gdb:
Truncated register 32 in remote 'g' packet
(and following on that qemu stops responding). The simple fix is
to say the truth in the .xml file. But the better fix is to
actually make it 32bit on the wire, as old gdbs don't support
XML files for describing registers. Also the XER state in qemu
doesn't seem to use the high 32 bits, so sending it off to gdb
doesn't seem worthwhile.
Signed-off-by: Michael Matz <matz@suse.de>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Mark Cave-Ayland [Tue, 6 Mar 2018 20:31:00 +0000 (20:31 +0000)]
uninorth: rename UNINState to UNINHostState
The existing UNINState actually represents the PCI/AGP host bridge stage so
rename it accordingly.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>