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Yiannis Tsiouris [Mon, 25 Mar 2013 13:47:46 +0000 (13:47 +0000)]
Add a GC plugin for Erlang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177867
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Duncan Sands [Mon, 25 Mar 2013 13:25:34 +0000 (13:25 +0000)]
Don't use add_llvm_definitions for adding warning flags. It makes it too hard
to have them appear in the right order. Instead append all warnings explicitly
to the language flags. This was already the case for many warnings. Fixes the
issue of -Wno-maybe-uninitialized not being effective because -Wall was being
placed after it rather than before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177866
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Joerg Sonnenberger [Mon, 25 Mar 2013 13:13:33 +0000 (13:13 +0000)]
Refine fenv.h handling: check if the desired macros exist, before using
it. NetBSD/ARM and TILE-Gx are examples for platforms that have an
unusable fenv.h and this avoids the need for a blacklist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177865
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Arnaud A. de Grandmaison [Mon, 25 Mar 2013 11:47:38 +0000 (11:47 +0000)]
Address issues found by Duncan during post-commit review of r177856.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177863
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Arnaud A. de Grandmaison [Mon, 25 Mar 2013 09:48:49 +0000 (09:48 +0000)]
InstCombine: simplify comparisons to zero of (shl %x, Cst) or (mul %x, Cst)
This simplification happens at 2 places :
- using the nsw attribute when the shl / mul is used by a sign test
- when the shl / mul is compared for (in)equality to zero
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177856
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Michael Gottesman [Mon, 25 Mar 2013 09:27:43 +0000 (09:27 +0000)]
Changed isNullOrUndef => IsNullOrUndef and isNoopInstruction => IsNoopInstruction so that all helper functions are named similarly in ObjCARC.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177855
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Jakob Stoklund Olesen [Mon, 25 Mar 2013 00:36:53 +0000 (00:36 +0000)]
Mention the new TableGen pattern format in the release notes.
Make threats about removing the old syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177848
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Justin Holewinski [Sun, 24 Mar 2013 21:17:47 +0000 (21:17 +0000)]
[NVPTX] Fix handling of vector arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177847
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Jakob Stoklund Olesen [Sun, 24 Mar 2013 19:37:04 +0000 (19:37 +0000)]
Clean up Sparc patterns.
The types of register variables no longer need to be specified in output
patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177845
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Jakob Stoklund Olesen [Sun, 24 Mar 2013 19:37:00 +0000 (19:37 +0000)]
Allow types to be omitted in output patterns.
This syntax is now preferred:
def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;
There is no reason to repeat the types in the output pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177844
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Jakob Stoklund Olesen [Sun, 24 Mar 2013 19:36:51 +0000 (19:36 +0000)]
Allow TableGen DAG arguments to be just a name.
DAG arguments can optionally be named:
(dag node, node:$name)
With this change, the node is also optional:
(dag node, node:$name, $name)
The missing node is treated as an UnsetInit, so the above is equivalent
to:
(dag node, node:$name, ?:$name)
This syntax is useful in output patterns where we currently require the
types of variables to be repeated:
def : Pat<(subc i32:$b, i32:$c), (SUBCCrr i32:$b, i32:$c)>;
This is preferable:
def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177843
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Tobias Grosser [Sun, 24 Mar 2013 15:15:19 +0000 (15:15 +0000)]
GettingStarted: Add Git clone instructions for compiler-rt and test-suite
Contributed-by: Thomas Schwinge <thomas@codesourcery.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177841
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Jakub Staszak [Sun, 24 Mar 2013 09:56:28 +0000 (09:56 +0000)]
Minor cleanups. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177837
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Jakub Staszak [Sun, 24 Mar 2013 09:25:47 +0000 (09:25 +0000)]
Use dyn_cast instead of isa && cast.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177836
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Jakob Stoklund Olesen [Sun, 24 Mar 2013 00:56:20 +0000 (00:56 +0000)]
Give Sparc instruction patterns direct types instead of register classes.
Also update the documentation since Sparc is the nicest backend, and
used as an example in WritingAnLLVMBackend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177835
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Jakob Stoklund Olesen [Sun, 24 Mar 2013 00:56:16 +0000 (00:56 +0000)]
Allow direct value types to be used in instruction 'set' patterns.
This makes it possible to define instruction patterns like this:
def LDri : F3_2<3,
0b000000,
(outs IntRegs:$dst), (ins MEMri:$addr),
"ld [$addr], $dst",
[(set i32:$dst, (load ADDRri:$addr))]>;
~~~
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177834
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Hal Finkel [Sat, 23 Mar 2013 22:06:07 +0000 (22:06 +0000)]
PPC ZERO register needs a register number of 0.
In order for the new ZERO register to be used with MC, etc. we need to specify
its register number (0).
Thanks to Kai for reporting the problem!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177833
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Hal Finkel [Sat, 23 Mar 2013 22:06:03 +0000 (22:06 +0000)]
Note in PPCFunctionInfo VRSAVE spills
In preparation for using the new register scavenger capability for providing
more than one register simultaneously, specifically note functions that have
spilled VRSAVE (currently, this can happen only in functions that use the
setjmp intrinsic). As with CR spilling, such functions will need to provide two
emergency spill slots to the scavenger.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177832
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Hal Finkel [Sat, 23 Mar 2013 20:53:15 +0000 (20:53 +0000)]
MCize the bcl instruction in PPCAsmPrinter
I recently added a BCL instruction definition as part of implementing SjLj
support. This can also be used to MCize bcl emission in the asm printer.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177830
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Jakob Stoklund Olesen [Sat, 23 Mar 2013 20:35:05 +0000 (20:35 +0000)]
Use direct types in Sparc def : Pat patterns.
The SelectionDAG graph has MVT type labels, not register classes, so
this makes it clearer what is happening.
This notation is also robust against adding more types to the IntRegs
register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177829
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Jakob Stoklund Olesen [Sat, 23 Mar 2013 20:35:01 +0000 (20:35 +0000)]
Allow direct value types in pattern definitions.
Just like register classes, value types can be used in two ways in
patterns:
(sext_inreg i32:$src, i16)
In a named leaf node like i32:$src, the value type simply provides the
type of the node directly. This simplifies type inference a lot compared
to the current practice of specifiying types indirectly with register
classes.
As an unnamed leaf node, like i16 above, the value type represents
itself as an MVT::Other immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177828
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Hal Finkel [Sat, 23 Mar 2013 19:36:47 +0000 (19:36 +0000)]
Cleanup some unused reg. scavenger parameters in PPCRegisterInfo
These spilling functions will eventually make use of the register scavenger,
however, they'll do so by taking advantage of PEI's virtual-register-based
delayed scavenging mechanism. As a result, these function parameters will not
be used, and can be removed.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177827
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Jakob Stoklund Olesen [Sat, 23 Mar 2013 18:08:44 +0000 (18:08 +0000)]
Make all unnamed RegisterClass TreePatternNodes typed MVT::i32.
A register class can appear as a leaf TreePatternNode with and without a
name:
(COPY_TO_REGCLASS GPR:$src, F8RC)
In a named leaf node like GPR:$src, the register class provides type
information for the named variable represented by the node. The TypeSet
for such a node is the set of value types that the register class can
represent.
In an unnamed leaf node like F8RC above, the register class represents
itself as a kind of immediate. Such a node has the type MVT::i32,
we'll never create a virtual register representing it.
This change makes it possible to remove the special handling of
COPY_TO_REGCLASS in CodeGenDAGPatterns.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177825
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Hal Finkel [Sat, 23 Mar 2013 17:14:27 +0000 (17:14 +0000)]
Remove dead PPC LR spilling code
The LR register is unconditionally reserved, and its spilling and restoration
is handled by the prologue/epilogue code. As a result, it is never explicitly
spilled by the register allocator.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177823
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Benjamin Kramer [Sat, 23 Mar 2013 13:56:23 +0000 (13:56 +0000)]
Plug a memory leak in FileCheck when the input file is empty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177822
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Benjamin Kramer [Sat, 23 Mar 2013 09:35:44 +0000 (09:35 +0000)]
Move X86-dependent test into the right subdirectory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177821
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Owen Anderson [Sat, 23 Mar 2013 08:26:53 +0000 (08:26 +0000)]
Remove the type legality check from the SelectionDAGBuilder when it lowers @llvm.fmuladd to ISD::FMA nodes.
Performing this check unilaterally prevented us from generating FMAs when the incoming IR contained illegal vector types which would eventually be legalized to underlying types that *did* support FMA.
For example, an @llvm.fmuladd on an OpenCL float16 should become a sequence of float4 FMAs, not float4 fmul+fadd's.
NOTE: Because we still call the target-specific profitability hook, individual targets can reinstate the old behavior, if desired, by simply performing the legality check inside their callback hook. They can also perform more sophisticated legality checks, if, for example, some illegal vector types can be productively implemented as FMAs, but not others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177820
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Michael Gottesman [Sat, 23 Mar 2013 05:46:19 +0000 (05:46 +0000)]
Change method name ClearRefCount => ClearKnownPositiveRefCount to match the name of the member that it is modifying.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177818
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Michael Gottesman [Sat, 23 Mar 2013 05:31:01 +0000 (05:31 +0000)]
Changed the method name PtrState.IsKnownIncremented() to PtrState.HasKnownPositiveRefCount().
Now said method matches namewise every other method which refers to
the member KnownPositiveRefCount of the class PtrState.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177816
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Hal Finkel [Sat, 23 Mar 2013 00:07:29 +0000 (00:07 +0000)]
Fix comparison of mixed signedness
177774 broke the lld-x86_64-darwin11 builder; error:
error: comparison of integers of different signs: 'int' and 'size_type' (aka 'unsigned long')
for (SI = 0; SI < Scavenged.size(); ++SI)
~~ ^ ~~~~~~~~~~~~~~~~
Fix this by making SI also unsigned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177780
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Sean Silva [Fri, 22 Mar 2013 23:52:38 +0000 (23:52 +0000)]
[docs] Slight reword for precision.
The new wording cannot be construed as suggesting the use of
SmallVectorImpl<T> as e.g. a class member (just because the class
happens to be in an interface).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177778
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Sean Silva [Fri, 22 Mar 2013 23:41:29 +0000 (23:41 +0000)]
[docs] Document usage of SmallVectorImpl in interfaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177775
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Hal Finkel [Fri, 22 Mar 2013 23:32:27 +0000 (23:32 +0000)]
Allow the register scavenger to spill multiple registers
This patch lets the register scavenger make use of multiple spill slots in
order to guarantee that it will be able to provide multiple registers
simultaneously.
To support this, the RS's API has changed slightly: setScavengingFrameIndex /
getScavengingFrameIndex have been replaced by addScavengingFrameIndex /
isScavengingFrameIndex / getScavengingFrameIndices.
In forthcoming commits, the PowerPC backend will use this capability in order
to implement the spilling of condition registers, and some special-purpose
registers, without relying on r0 being reserved. In some cases, spilling these
registers requires two GPRs: one for addressing and one to hold the value being
transferred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177774
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Manman Ren [Fri, 22 Mar 2013 22:34:41 +0000 (22:34 +0000)]
Support in AAEvaluator to print alias queries of loads/stores with TBAA tags.
Add "evaluate-tbaa" to print alias queries of loads/stores. Alias queries
between pointers do not include TBAA tags.
Add testing case for "placement new". TBAA currently says NoAlias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177772
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John McCall [Fri, 22 Mar 2013 21:38:36 +0000 (21:38 +0000)]
Kill every call to @clang.arc.use in the ARC contract phase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177769
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Bill Wendling [Fri, 22 Mar 2013 20:36:39 +0000 (20:36 +0000)]
Update test. There may be multiple catches, but those will be cleaned up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177758
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Bill Wendling [Fri, 22 Mar 2013 20:31:05 +0000 (20:31 +0000)]
Add all clauses when merging the landing pads. Duplicates will be handled later on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177757
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David Blaikie [Fri, 22 Mar 2013 20:18:46 +0000 (20:18 +0000)]
Swap the DIFile in DILexicalBlockFile out for the raw name/directory pair
This is the last change in transitioning all DIScopes to have a common prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177756
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David Blaikie [Fri, 22 Mar 2013 19:13:22 +0000 (19:13 +0000)]
reorder the fields in DILexicalBlockFile to match the common prefix for DIScopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177754
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Galina Kistanova [Fri, 22 Mar 2013 18:54:14 +0000 (18:54 +0000)]
Reverted r176374. In some cases the lit.site.cfg file does not get generated in tools/clang/tools/extra.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177751
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Bill Wendling [Fri, 22 Mar 2013 18:49:53 +0000 (18:49 +0000)]
Don't use the removed API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177749
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Bill Wendling [Fri, 22 Mar 2013 18:46:32 +0000 (18:46 +0000)]
Revert r177675. This is language-specific and shouldn't be in the API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177748
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Jyotsna Verma [Fri, 22 Mar 2013 18:41:34 +0000 (18:41 +0000)]
Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177747
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David Blaikie [Fri, 22 Mar 2013 17:33:20 +0000 (17:33 +0000)]
Refactor out the DIFile parameter to DILexicalBlock to refer to the raw file/directory pair
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177742
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Eli Bendersky [Fri, 22 Mar 2013 16:09:06 +0000 (16:09 +0000)]
fix small doc typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177737
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Michel Danzer [Fri, 22 Mar 2013 15:24:16 +0000 (15:24 +0000)]
R600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177736
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Ulrich Weigand [Fri, 22 Mar 2013 15:24:13 +0000 (15:24 +0000)]
Remove ABI-duplicated call instruction patterns.
We currently have a duplicated set of call instruction patterns depending
on the ABI to be followed (Darwin vs. Linux). This is a bit odd; while the
different ABIs will result in different instruction sequences, the actual
instructions themselves ought to be independent of the ABI. And in fact it
turns out that the only nontrivial difference between the two sets of
patterns is that in the PPC64 Linux ABI, the instruction used for indirect
calls is marked to take X11 as extra input register (which is indeed used
only with that ABI to hold an incoming environment pointer for nested
functions). However, this does not need to be hard-coded at the .td
pattern level; instead, the C++ code expanding calls can simply add that
use, just like it adds uses for argument registers anyway.
No change in generated code expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177735
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Ulrich Weigand [Fri, 22 Mar 2013 14:59:13 +0000 (14:59 +0000)]
Rename memrr ptrreg and offreg components.
Currently, the sub-operand of a memrr address that corresponds to what
hardware considers the base register is called "offreg", while the
sub-operand that corresponds to the offset is called "ptrreg".
To avoid confusion, this patch simply swaps the named of those two
sub-operands and updates all uses. No functional change is intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177734
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Ulrich Weigand [Fri, 22 Mar 2013 14:58:48 +0000 (14:58 +0000)]
Fix swapped BasePtr and Offset in pre-inc memory addresses.
PPCTargetLowering::getPreIndexedAddressParts currently provides
the base part of a memory address in the offset result, and the
offset part in the base result. That swap is then undone again
when an MI instruction is generated (in PPCDAGToDAGISel::Select
for loads, and using .md Pat patterns for stores).
This patch reverts this double swap, to make common code and
back-end be in sync as to which part of the address is base
and which is offset.
To avoid performance regressions in certain cases, target code
now checks whether the choice of base register would be rejected
for pre-inc accesses by common code, and attempts to swap base
and offset again in such cases. (Overall, this means that now
pre-ice accesses are generated *more* frequently than before.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177733
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Ulrich Weigand [Fri, 22 Mar 2013 14:58:17 +0000 (14:58 +0000)]
Tighten iaddroff ComplexPattern.
The iaddroff ComplexPattern is supposed to recognize displacement
expressions that have been processed by a SelectAddressRegImm,
which means it needs to accept TargetConstant and TargetGlobalAddress
nodes. Currently, it erroneously also accepts some other nodes,
in particular Constant and PPCISD::Lo.
While this problem is currently latent, it would cause wrong-code
bugs with a follow-on patch I'm about to commit, so this patch
tightens the ComplexPattern. The equivalent change is made in
PPCDAGToDAGISel::Select, where pre-inc load patterns are handled
(as opposed to store patterns, the loads are handled in C++ code
without making use of the .td ComplexPattern).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177732
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Ulrich Weigand [Fri, 22 Mar 2013 14:57:48 +0000 (14:57 +0000)]
Remove the xaddroff ComplexPattern.
The xaddroff pattern is currently (mistakenly) used to recognize
the *base* register in pre-inc store patterns. This patch replaces
those uses by ptr_rc_nor0 (as is elsewhere done to match the base
register of an address), and removes the now unused ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177731
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Michel Danzer [Fri, 22 Mar 2013 14:09:10 +0000 (14:09 +0000)]
R600: Use legacy (0 * anything = 0) MUL instructions for pow intrinsics
Fixes wrong lighting in some corner cases with r600g and radeonsi, e.g.
manifested by failure of two piglit/glean tests and intermittent black
patches in many apps.
Tested on SI and RS880.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62012 [radeonsi]
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58150 [r600g]
NOTE: This is a candidate for the Mesa stable branch.
Reviewed-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177730
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Kostya Serebryany [Fri, 22 Mar 2013 10:37:20 +0000 (10:37 +0000)]
[asan] Change the way we report the alloca frame on stack-buff-overflow.
Before: the function name was stored by the compiler as a constant string
and the run-time was printing it.
Now: the PC is stored instead and the run-time prints the full symbolized frame.
This adds a couple of instructions into every function with non-empty stack frame,
but also reduces the binary size because we store less strings (I saw 2% size reduction).
This change bumps the asan ABI version to v3.
llvm part.
Example of report (now):
==31711==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x7fffa77cf1c5 at pc 0x41feb0 bp 0x7fffa77cefb0 sp 0x7fffa77cefa8
READ of size 1 at 0x7fffa77cf1c5 thread T0
#0 0x41feaf in Frame0(int, char*, char*, char*) stack-oob-frames.cc:20
#1 0x41f7ff in Frame1(int, char*, char*) stack-oob-frames.cc:24
#2 0x41f477 in Frame2(int, char*) stack-oob-frames.cc:28
#3 0x41f194 in Frame3(int) stack-oob-frames.cc:32
#4 0x41eee0 in main stack-oob-frames.cc:38
#5 0x7f0c5566f76c (/lib/x86_64-linux-gnu/libc.so.6+0x2176c)
#6 0x41eb1c (/usr/local/google/kcc/llvm_cmake/a.out+0x41eb1c)
Address 0x7fffa77cf1c5 is located in stack of thread T0 at offset 293 in frame
#0 0x41f87f in Frame0(int, char*, char*, char*) stack-oob-frames.cc:12 <<<<<<<<<<<<<< this is new
This frame has 6 object(s):
[32, 36) 'frame.addr'
[96, 104) 'a.addr'
[160, 168) 'b.addr'
[224, 232) 'c.addr'
[288, 292) 's'
[352, 360) 'd'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177724
91177308-0d34-0410-b5e6-
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Dmitry Vyukov [Fri, 22 Mar 2013 09:04:01 +0000 (09:04 +0000)]
tsan: fix the test
Add missed file from r177717 commit that adds __tsan_vptr_read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177719
91177308-0d34-0410-b5e6-
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Dmitry Vyukov [Fri, 22 Mar 2013 08:51:22 +0000 (08:51 +0000)]
tsan: handle vptr loads specially
This is required to determine ctor/dtor vs virtual call races.
http://llvm-reviews.chandlerc.com/D566
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177717
91177308-0d34-0410-b5e6-
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Evgeniy Stepanov [Fri, 22 Mar 2013 08:43:04 +0000 (08:43 +0000)]
Fix llvm::removeUnreachableBlocks to handle unreachable loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177713
91177308-0d34-0410-b5e6-
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Arnaud A. de Grandmaison [Fri, 22 Mar 2013 08:25:01 +0000 (08:25 +0000)]
InstCombine: Improve the result bitvect type when folding (cmp pred (load (gep GV, i)) C) to a bit test.
The original code used i32, and i64 if legal. This introduced unneeded
casts when they aren't legal, or when the index variable i has another
type. In order of preference: try to use i's type; use the smallest
fitting legal type (using an added DataLayout method); default to i32.
A testcase checks that this works when the index gep operand is i16.
Patch by : Ahmed Bougacha <ahmed.bougacha@gmail.com>
Reviewed by : Duncan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177712
91177308-0d34-0410-b5e6-
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Hal Finkel [Fri, 22 Mar 2013 07:27:44 +0000 (07:27 +0000)]
Remove ScavengedRC from RegisterScavenging
ScavengedRC was a dead private variable (set, but not otherwise used). No
functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177708
91177308-0d34-0410-b5e6-
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David Blaikie [Fri, 22 Mar 2013 05:47:44 +0000 (05:47 +0000)]
Reorder the DIFile field in DILexicalBlock to become a prefix common with other DIScopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177703
91177308-0d34-0410-b5e6-
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Chandler Carruth [Fri, 22 Mar 2013 05:42:33 +0000 (05:42 +0000)]
Remove the empty directory. Silly git-svn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177702
91177308-0d34-0410-b5e6-
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Chandler Carruth [Fri, 22 Mar 2013 05:16:46 +0000 (05:16 +0000)]
Remove the ARM-specific variant of this test. It's already covered by
the ARM build bots, and it adds a weird case to the test suite where
a test uses as inputs files in the parent directory.
Talked about this with Dave on IRC and he's fine with this approach even
though it isn't optimal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177700
91177308-0d34-0410-b5e6-
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Argyrios Kyrtzidis [Fri, 22 Mar 2013 03:10:51 +0000 (03:10 +0000)]
Introduce LLVM_STATIC_ASSERT macro, which expands to C/C++'s static_assert on compilers which support it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177699
91177308-0d34-0410-b5e6-
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Chandler Carruth [Fri, 22 Mar 2013 02:20:34 +0000 (02:20 +0000)]
Revert r177543: Add timing of the IR parsing code with a new
-time-ir-parsing flag
This breaks the layering of the Support library. We can't add an
implementation side to IRReader because it refers directly to entities
only accessible as part of the IR, AsmParser, and BitcodeReader
libraries. It can only be used in a context where all of those libraries
will be available.
We'll need to find some other way to get this functionality, and
hopefully solve the long-standing layering problem of IRReader.h...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177695
91177308-0d34-0410-b5e6-
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Jack Carter [Fri, 22 Mar 2013 00:29:10 +0000 (00:29 +0000)]
Fix the invalid opcode for Mips branch instructions in the assembler
For mips a branch an 18-bit signed offset (the 16-bit
offset field shifted left 2 bits) is added to the
address of the instruction following the branch
(not the branch itself), in the branch delay slot,
to form a PC-relative effective target address.
Previously, the code generator did not perform the
shift of the immediate branch offset which resulted
in wrong instruction opcode. This patch fixes the issue.
Contributor: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177687
91177308-0d34-0410-b5e6-
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Jack Carter [Fri, 22 Mar 2013 00:05:30 +0000 (00:05 +0000)]
This patch that enables the Mips assembler to use symbols for offset for instructions
This patch uses the generated instruction info tables to
identify memory/load store instructions.
After successful matching and based on the operand type
and size, it generates additional instructions to the output.
Contributor: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177685
91177308-0d34-0410-b5e6-
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Hal Finkel [Thu, 21 Mar 2013 23:45:03 +0000 (23:45 +0000)]
Remove the G8RC_NOX0_and_GPRC_NOR0 PPC register class
As Jakob pointed out in his review of r177423, having a shared ZERO
register between the 32- and 64-bit register classes causes this
odd G8RC_NOX0_and_GPRC_NOR0 class to be created. As recommended,
this adds a ZERO8 register which differentiates the 32- and 64-bit
zeros.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177683
91177308-0d34-0410-b5e6-
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Sean Silva [Thu, 21 Mar 2013 23:40:38 +0000 (23:40 +0000)]
Add TableGen ctags(1) emitter and helper script.
To use this in conjunction with exuberant ctags to generate a single
combined tags file, run tblgen first and then
$ ctags --append [...]
Since some identifiers have corresponding definitions in C++ code,
it can be useful (if using vim) to also use cscope, and
:set cscopetagorder=1
so that
:tag X
will preferentially select the tablegen symbol, while
:cscope find g X
will always find the C++ symbol.
Patch by Kevin Schoedel!
(a couple small formatting changes courtesy of clang-format)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177682
91177308-0d34-0410-b5e6-
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Bill Wendling [Thu, 21 Mar 2013 23:30:12 +0000 (23:30 +0000)]
Always forward 'resume' instructions to the outter landing pad.
How did this ever work?
Basically, if you have a function that's inlined into the caller, it may not
have any 'call' instructions, but any 'resume' instructions it may have should
still be forwarded to the outer (caller's) landing pad. This requires that all
of the 'landingpad' instructions in the callee have their clauses merged with
the caller's outer 'landingpad' instruction (hence the bit of ugly code in the
`forwardResume' method).
Testcase in a follow commit to the test-suite repository.
<rdar://problem/
13360379> & PR15555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177680
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Hal Finkel [Thu, 21 Mar 2013 23:23:34 +0000 (23:23 +0000)]
Fix a register-class comparison bug in PPCCTRLoops
Thanks to Jakob for isolating the underlying problem from the
test case in r177423. The original commit had introduced
asymmetric copy operations, but these turned out to be a work-around
to the real problem (the use of == instead of hasSubClassEq in PPCCTRLoops).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177679
91177308-0d34-0410-b5e6-
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David Blaikie [Thu, 21 Mar 2013 23:08:34 +0000 (23:08 +0000)]
Refactor the filename/directory information in DISubprogram to refer directly to the pair rather than the DIFile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177677
91177308-0d34-0410-b5e6-
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Bill Wendling [Thu, 21 Mar 2013 23:01:03 +0000 (23:01 +0000)]
Add a query to tell if a landing pad has a catch-all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177675
91177308-0d34-0410-b5e6-
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David Blaikie [Thu, 21 Mar 2013 22:29:36 +0000 (22:29 +0000)]
Move the DIFile in DISubprogram to the beginning to be a common prefix along with other DIScopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177674
91177308-0d34-0410-b5e6-
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Douglas Gregor [Thu, 21 Mar 2013 21:46:10 +0000 (21:46 +0000)]
<rdar://problem/
13477190> On Darwin, use DARWIN_USER_TEMP_DIR or DARWIN_USER_CACHE_DIR for the system temporary directory.
The DARWIN_USER_TEMP_DIR and DARWIN_USER_CACHE_DIR configuration
settings are more idiomatic for Darwin than the TMPDIR environment
variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177669
91177308-0d34-0410-b5e6-
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Jack Carter [Thu, 21 Mar 2013 21:44:16 +0000 (21:44 +0000)]
This patch enables the Mips .set directive to define aliases
The .set directive in the Mips the assembler can be
used to set the value of a symbol to an expression.
This changes the symbol's value and type to conform
to the expression's.
Syntax: .set symbol, expression
This patch implements the parsing of the above syntax
and enables the parser to use defined symbols when
parsing operands.
Contributor: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177667
91177308-0d34-0410-b5e6-
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Hal Finkel [Thu, 21 Mar 2013 21:37:52 +0000 (21:37 +0000)]
Implement builtin_{setjmp/longjmp} on PPC
This implements SJLJ lowering on PPC, making the Clang functions
__builtin_{setjmp/longjmp} functional on PPC platforms. The implementation
strategy is similar to that on X86, with the exception that a branch-and-link
variant is used to get the right jump address. Credit goes to Bill Schmidt for
suggesting the use of the unconditional bcl form (instead of the regular bl
instruction) to limit return-address-cache pollution.
Benchmarking the speed at -O3 of:
static jmp_buf env_sigill;
void foo() {
__builtin_longjmp(env_sigill,1);
}
main() {
...
for (int i = 0; i < c; ++i) {
if (__builtin_setjmp(env_sigill)) {
goto done;
} else {
foo();
}
done:;
}
...
}
vs. the same code using the libc setjmp/longjmp functions on a P7 shows that
this builtin implementation is ~4x faster with Altivec enabled and ~7.25x
faster with Altivec disabled. This comparison is somewhat unfair because the
libc version must also save/restore the VSX registers which we don't yet
support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177666
91177308-0d34-0410-b5e6-
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Renato Golin [Thu, 21 Mar 2013 21:30:49 +0000 (21:30 +0000)]
Fix Darwin NEON FP and increase coverage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177664
91177308-0d34-0410-b5e6-
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David Blaikie [Thu, 21 Mar 2013 20:28:52 +0000 (20:28 +0000)]
Remove unused field in DISubprogram
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177661
91177308-0d34-0410-b5e6-
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Hal Finkel [Thu, 21 Mar 2013 19:03:21 +0000 (19:03 +0000)]
Add support for spilling VRSAVE on PPC
Although there is only one Altivec VRSAVE register, it is a member of
a register class, and we need the ability to spill it. Because this
register is normally callee-preserved and handled by special code this
has never before been necessary. However, this capability will be required by
a forthcoming commit adding SjLj support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177654
91177308-0d34-0410-b5e6-
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Hal Finkel [Thu, 21 Mar 2013 19:03:19 +0000 (19:03 +0000)]
Correct PPC FRAMEADDR lowering using a pseudo-register
The old code used to lower FRAMEADDR tried to replicate the logic in the real
frame-lowering code that determines whether or not the frame pointer (r31) will
be used. When it seemed as through the frame pointer would not be used, the
stack pointer (r1) was used instead. Unfortunately, because the stack size is
not yet known, this does not work. Instead, this change introduces new
always-reserved pseudo-registers (FP and FP8) that are replaced during prologue
insertion with the real frame-pointer register (either r1 or r31).
It is important that this intrinsic always return a valid frame address because
it is used by Clang to store the frame address as part of code generation for
__builtin_setjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177653
91177308-0d34-0410-b5e6-
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Renato Golin [Thu, 21 Mar 2013 18:47:47 +0000 (18:47 +0000)]
Avoid NEON SP-FP unless unsafe-math or Darwin
NEON is not IEEE 754 compliant, so we should avoid lowering single-precision
floating point operations with NEON unless unsafe-math is turned on. The
equivalent VFP instructions are IEEE 754 compliant, but in some cores they're
much slower, so some archs/OSs might still request it to be on by default,
such as Swift and Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177651
91177308-0d34-0410-b5e6-
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Bill Wendling [Thu, 21 Mar 2013 18:30:10 +0000 (18:30 +0000)]
Update some EH tests that were violating the new EH model.
The landingpad instruction needs to be the first non-PHI instruction in the
unwind destination block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177650
91177308-0d34-0410-b5e6-
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Chandler Carruth [Thu, 21 Mar 2013 09:52:22 +0000 (09:52 +0000)]
Hoist the definition of getTypeSizeInBits to be inlinable and in the
header.
This method is called in the hot path for *many* passes, SROA is what
caught my interest. A common pattern is that which branch of the switch
should be taken is known in the callsite and so it is a very good
candidate for inlining and simplification. Moving it into the header
allows the optimizer to fold a lot of boring, repeatitive code in
callers of this routine.
I'm seeing pretty significant speedups in parts of SROA and I suspect
other passes will see similar speedups if they end up working with type
sizes frequently. I've not seen any significant growth of the binaries
as a consequence, but let me know if you see anything suspicious here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177632
91177308-0d34-0410-b5e6-
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Chandler Carruth [Thu, 21 Mar 2013 09:52:18 +0000 (09:52 +0000)]
[SROA] Prefix names using a custom IRBuilder inserter.
The key part of this is ensuring that name prefixes remain in a Twine
form until we get to a point where we can nuke them under NDEBUG. This
is tricky using the old APIs as they played fast and loose with Twine,
which is prone to serious error. The inserter is much cleaner as it is
actually in the call stack leading to the setName call, and so has
a good opportunity to prepend the prefix.
This matters more than you might imagine because most runs over an
alloca find a single partition, and rewrite 3 or 4 instructions
referring to it. As a consequence doing this lazily and exclusively with
Twine allows the optimizer to delete more of it and shaves another 2% to
3% off of the release build's SROA run time for PR15412. I also think
the APIs are cleaner, and the use of Twine is more reliable, so
I consider it a win-win despite the churn required to reach this state.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177631
91177308-0d34-0410-b5e6-
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Evgeniy Stepanov [Thu, 21 Mar 2013 09:38:26 +0000 (09:38 +0000)]
[msan] Add an option to disable poisoning of shadow for undef values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177630
91177308-0d34-0410-b5e6-
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Meador Inge [Thu, 21 Mar 2013 02:44:07 +0000 (02:44 +0000)]
simplify-libcalls: Removed unused variable
The 'Modified' variable should have been removed from SimplifyLibCalls
in r177619, but was missed. This commit removes it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177622
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 21 Mar 2013 00:57:21 +0000 (00:57 +0000)]
Fix missing std::. Not sure how this compiles for anyone else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177620
91177308-0d34-0410-b5e6-
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Meador Inge [Thu, 21 Mar 2013 00:55:59 +0000 (00:55 +0000)]
Move library call prototype attribute inference to functionattrs
The simplify-libcalls pass implemented a doInitialization hook to infer
function prototype attributes for well-known functions. Given that the
simplify-libcalls pass is going away *and* that the functionattrs pass
is already in place to deduce function attributes, I am moving this logic
to the functionattrs pass. This approach was discussed during patch
review:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-
20121126/157465.html.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177619
91177308-0d34-0410-b5e6-
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David Blaikie [Thu, 21 Mar 2013 00:10:31 +0000 (00:10 +0000)]
Removing unused DISubprogram::getFile
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177614
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Thu, 21 Mar 2013 00:07:17 +0000 (00:07 +0000)]
Add a WriteMicrocoded for ancient microcoded instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177611
91177308-0d34-0410-b5e6-
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David Blaikie [Wed, 20 Mar 2013 23:58:12 +0000 (23:58 +0000)]
Debug info: refactor the first field of DICompileUnit to be a raw file/directory pair
This removes the DICompileUnit special case from DIScope.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177610
91177308-0d34-0410-b5e6-
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Jakub Staszak [Wed, 20 Mar 2013 23:56:19 +0000 (23:56 +0000)]
Use pre-inc, pre-dec when possible.
They are generally faster (at least not slower) than post-inc, post-dec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177608
91177308-0d34-0410-b5e6-
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Jakub Staszak [Wed, 20 Mar 2013 23:53:45 +0000 (23:53 +0000)]
Remove 'else' after 'return'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177607
91177308-0d34-0410-b5e6-
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Reid Kleckner [Wed, 20 Mar 2013 23:32:14 +0000 (23:32 +0000)]
[lit] Avoid CRLFs in bash scripts on Windows
Native Windows Python will do line ending translation by default, which
we don't want in bash scripts. If we're not native Windows Python, then
'b' is ignored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177602
91177308-0d34-0410-b5e6-
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Justin Holewinski [Wed, 20 Mar 2013 23:10:59 +0000 (23:10 +0000)]
Make variable name more explicit and eliminate redundant lookup in SDNodeOrdering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177600
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Wed, 20 Mar 2013 23:09:53 +0000 (23:09 +0000)]
Model prefetches and barriers as loads.
It's not yet clear if these instructions need a more careful model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177599
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Wed, 20 Mar 2013 23:09:50 +0000 (23:09 +0000)]
Add a catch-all WriteSystem SchedWrite type.
This is used for all the expensive system instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177598
91177308-0d34-0410-b5e6-
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Nadav Rotem [Wed, 20 Mar 2013 22:53:44 +0000 (22:53 +0000)]
When computing the demanded bits of Load SDNodes, make sure that we are looking at the loaded-value operand and not the ptr result (in case of pre-inc loads).
rdar://
13348420
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177596
91177308-0d34-0410-b5e6-
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David Blaikie [Wed, 20 Mar 2013 22:52:54 +0000 (22:52 +0000)]
Debug Info: Swap the 2nd and 3rd parameters to DICompileUnit to match the common DIScope prefix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177595
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Wed, 20 Mar 2013 22:37:16 +0000 (22:37 +0000)]
Annotate the remaining SSE MOV instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177592
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Wed, 20 Mar 2013 22:37:13 +0000 (22:37 +0000)]
Annotate SSE horizontal and integer instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177591
91177308-0d34-0410-b5e6-
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