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Dave Airlie [Sun, 27 Nov 2011 17:16:27 +0000 (17:16 +0000)]
image/pack: fix missing GL_BGR(A)_INTEGER support.
These codepaths were missing the cases for BGR_INTEGER/BGRA_INTEGER.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Ian Romanick [Sun, 27 Nov 2011 22:17:22 +0000 (14:17 -0800)]
docs: Add 7.11.2 release notes and news
Dave Airlie [Sat, 26 Nov 2011 16:54:29 +0000 (16:54 +0000)]
image: fix legal types for packed integer formats.
After reading ARB_texture_rgb10_a2ui it appears the packed formats
for integer types are only specified via this extension, and not via
the original ones. So condition the checks on this.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Dave Airlie [Sun, 27 Nov 2011 20:33:37 +0000 (20:33 +0000)]
r600g: add framebuffer support for 2/10/10/10 integer
Dave Airlie [Sun, 27 Nov 2011 16:24:26 +0000 (16:24 +0000)]
r600g: add int support for 2/10/10/10 format.
integer wasn't set properly for the non-uniform types.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Sun, 27 Nov 2011 16:44:03 +0000 (16:44 +0000)]
docs/gl3: these two interfaces are complete now.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Sun, 27 Nov 2011 17:15:50 +0000 (17:15 +0000)]
pack: fix indentation (trivial)
just saw this while looking for other problems.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Sun, 27 Nov 2011 16:19:39 +0000 (16:19 +0000)]
glapi: add ARB_texture_rgb10_a2ui support.
This just adds one enum.
regenerate enums.c.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Sun, 27 Nov 2011 16:18:08 +0000 (16:18 +0000)]
gallium: add B10G10R10A2_UINT format
This format is used for ARB_texture_rgb10_a2ui extension.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Chia-I Wu [Tue, 22 Nov 2011 07:05:25 +0000 (15:05 +0800)]
mesa: add MESA_FORMAT_RGBX8888 and MESA_FORMAT_RGBX8888_REV
MESA_FORMAT_RGBX8888_REV is one of the opaque pixel formats used on Android.
Thanks to texture-from-pixmap, drivers may actually see texture images with
this format on Android.
MESA_FORMAT_RGBX8888 is added only for completeness.
Reviewed-by: Brian Paul <brianp@vmware.com>
[olv: Move the new formats after MESA_FORMAT_ARGB8888_REV in gl_format. I
accidentally moved them to the wrong place when preparing the patch.]
Beren Minor [Fri, 25 Nov 2011 10:58:38 +0000 (11:58 +0100)]
egl_glx: Try first a default lookup for glXGetProcAddress before loading dynamic lib.
GLX functions are sometimes directly available in the current binary. In such
cases, we do not need any alternate library loaded using dlopen. Otherwise,
dlopen may find the wrong libGL library and get functions that conflicts with
the current loaded ones.
For example, on Debian Sid with nvidia binary drivers, using mesa's libEGL with
GLX driver leads to wrong glXGetFBConfigs symbol loaded (or loaded twice?),
which leads to "GLX: failed to create any config" error message as the
glXGetFBConfigs symbol seems to return garbage. If the binary is linked with
nvidia's libGL, the GLX symbols are already available.
Without this patch, convert_fbconfig (src/egl/drivers/glx/egl_glx.c:233) fails
for every config found, after glXGetFBConfigAttrib(... GLX_RENDER_TYPE, ...)
call, as the value returned has GLX_COLOR_INDEX_BIT and not GLX_RGBA_BIT.
[olv: initialize handle, prepend egl_glx to the commit log]
Chia-I Wu [Fri, 25 Nov 2011 12:44:12 +0000 (20:44 +0800)]
android: bring in i915_dri and i965_dri automatically
Add i915_dri and i965_dri to libGLES_mesa's LOCAL_REQUIRED_MODULES when
enabled.
Chia-I Wu [Sat, 26 Nov 2011 03:20:05 +0000 (11:20 +0800)]
android: pass -std=c99 by default
Several modules expect a C99 compiler already. It is also the default for
Makefile build.
Chia-I Wu [Sat, 26 Nov 2011 03:06:02 +0000 (11:06 +0800)]
android: move libGLES_mesa build rules to src/egl/main/.
Keep the top-level Android.mk away from building modules.
Chia-I Wu [Sat, 26 Nov 2011 02:28:13 +0000 (10:28 +0800)]
android: clean up libglapi bulid rules a bit
Make the output prettier. Make the rules reusable if we ever want to add
other modules, such as libGLESv2_mesa.
Thomas Hellstrom [Thu, 24 Nov 2011 21:23:37 +0000 (22:23 +0100)]
st/xa: Kill a couple of compilation warnings
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
Thomas Hellstrom [Thu, 24 Nov 2011 20:54:54 +0000 (21:54 +0100)]
st/xa, xa/vmwgfx: Generate exported symbol list from the st/xa symbols.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
Thomas Hellstrom [Thu, 24 Nov 2011 20:59:06 +0000 (21:59 +0100)]
st/xa, xa/vmwgfx: Use XA_EXPORT attribute to indicate global visibility
Also fix up Makefiles to use the default mesa compilation flags.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrants <jakob@vmware.com>
Thomas Hellstrom [Thu, 24 Nov 2011 21:01:54 +0000 (22:01 +0100)]
st/xa, xa/vmwgfx: Set the right version on library suffix
Also remove some unused variables in the st/xa makefile.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
Chia-I Wu [Fri, 25 Nov 2011 03:59:02 +0000 (11:59 +0800)]
android: add support for ICS
With ICS (Android 4.0), several headers and structs are renamed. Define
ANDROID_VERSION so that we can choose a different path depending on the
platform version.
I've tested only softpipe and llvmpipe. r600g is also reported to work.
Chia-I Wu [Tue, 15 Nov 2011 17:07:26 +0000 (10:07 -0700)]
vbo: fix !FEATURE_beginend build
Fix a build error in GLES-only build.
Chia-I Wu [Thu, 24 Nov 2011 09:13:15 +0000 (17:13 +0800)]
st/egl: fix a crash in Android backend
There is no buffer and android_surface_present should be a no-op when
eglSwapBuffers is called twice in a row.
Brian Paul [Wed, 23 Nov 2011 22:03:47 +0000 (15:03 -0700)]
softpipe: s/int/unsigned/ to be consistent in alpha test code
Brian Paul [Wed, 23 Nov 2011 22:02:05 +0000 (15:02 -0700)]
softpipe: remove pointless break stmt
Chad Versace [Wed, 23 Nov 2011 18:06:46 +0000 (10:06 -0800)]
i965/gen6: Fix GPU hang when using stencil buffer without depth
Enable the bit 3DSTATE_DEPTH_BUFFER.Tiled_Surface. From the Sandybridge
PRM, Volume 2, Part 1, Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27
Tiled Surface:
[DevGT+]: This field must be set to TRUE.
Fixes GPU hangs on the following Piglit tests:
hiz-stencil-test-fbo-d0-s8
hiz-stencil-read-fbo-d0-s8
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Eric Anholt [Wed, 23 Nov 2011 03:29:56 +0000 (19:29 -0800)]
i915: Fix complete texturing regression since
27505a105a
I had notes to myself to test gen3 and gen4, and then I tested gen4
and called it good. Turns out I forgot to actually call the new
function on gen3.
Eric Anholt [Tue, 22 Nov 2011 19:00:35 +0000 (11:00 -0800)]
i915: Fix build since hiz merge.
v2: Guard against rb->mt being NULL, since we may enter the draw
regions path before intel_prepare_render() has been called to set
them.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com> (v1)
Brian Paul [Wed, 23 Nov 2011 15:36:14 +0000 (08:36 -0700)]
mesa: fix incorrect error message in format_unpack.c
Vasily Khoruzhick [Wed, 23 Nov 2011 10:27:24 +0000 (13:27 +0300)]
i915g: don't set alpha to 1 for RGBX and BGRX
This patch fixes regression introduced in
1f3c5eae5c4be582e50c2d4d7950424d86059c45
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Brian Paul [Wed, 23 Nov 2011 00:07:18 +0000 (17:07 -0700)]
mesa: update comment for clear_teximage_fields()
Brian Paul [Wed, 23 Nov 2011 00:03:35 +0000 (17:03 -0700)]
gallium: remove trailing comma and unneeded comments in p_defines.h
Marek Olšák [Tue, 22 Nov 2011 20:02:08 +0000 (21:02 +0100)]
mesa: re-implement unpacking of DEPTH_COMPONENT32F
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43122
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Eric Anholt [Tue, 15 Nov 2011 23:57:39 +0000 (15:57 -0800)]
i915: Move the texture format setup for this driver out of shared code.
The i965 driver is now enabling all of these formats on its own from
the surface format table.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 15 Nov 2011 23:49:26 +0000 (15:49 -0800)]
i965: Drop intel_context.c's texture format set up for this driver.
This is a no-op change on gen6, but should result in some
actually-unsupported formats on gen4 no longer being chosen (like
RGBA_FLOAT32 now being RGBA_FLOAT16).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Wed, 16 Nov 2011 00:53:48 +0000 (16:53 -0800)]
i965: Add support for ARGB2101010 rendering.
GL 3.0 specifies GL_RGB10_A2 as a required sized format for rendering
and texturing.
This introduces two piglit regressions: one due to fbo-mipmap-copypix
hitting swrast GetRow (we want to convert swrast to MapRenderbuffer),
and one due to fbo-blending-formats being too picky while leaving
dithering on.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Wed, 16 Nov 2011 00:50:59 +0000 (16:50 -0800)]
i965: Add support for RGBA_16 unorm rendering.
GL 3.0 specifies GL_RGBA16 as a required sized format for rendering
and texturing.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Wed, 16 Nov 2011 00:26:29 +0000 (16:26 -0800)]
i965: Add support for half-float formats.
Now that all the rest of the driver is driven off of the surface
formats table, all we really need to do is add the mapping from
MESA_FORMAT to BRW_SURFACEFORMAT. However, we also add format
override for I16/L16 render targets at the same time, so that existing
users of I16 that were getting promoted to I32 and then getting the
I32->R32 override still get FBO support.
Fixes failures in piglit gl-3.0-required-sized-texture-formats, and
will prevent regressions in ARB_texture_float on gen4 when moving to
fully table-driven texture format setup.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Wed, 16 Nov 2011 00:47:25 +0000 (16:47 -0800)]
mesa: Fix unpack for MESA_FORMAT_INTENSITY_FLOAT16.
Fixes failures in i965 on fbo-blending-formats when the format is enabled.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 22 Nov 2011 21:27:54 +0000 (13:27 -0800)]
mesa: Fall back to float16 if float32 isn't supported in ChooseTexFormat.
Until GL 3.0, there isn't any requirement on the actual sizes of
channels chosen. By falling back to 16 here, we can correctly support
ARB_texture_float on original i965 hardware, which can't correctly
filter 32-bit floats.
Eric Anholt [Mon, 7 Nov 2011 02:08:36 +0000 (18:08 -0800)]
mesa: Add fallback from RGB_FLOAT16 to RGBA_FLOAT16 before RGBA_FLOAT32.
Not all i965 hardware can do RGB float16, and this will at least save
half the memory and have expected behavior in terms of precision.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Wed, 16 Nov 2011 00:16:43 +0000 (16:16 -0800)]
i965: Reorganize MESA_FORMAT -> BRW_SURFACEFORMAT table.
This should be a no-op change. The initializers are reordered to
match the ordering of the enum, since there isn't a clearly sensible
ordering, but "the order they were added to the driver, sort of" is
definitely not one.
Also, the unsupported formats are explicitly initialized to 0, so it's
more obvious what we aren't claiming to support.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 15 Nov 2011 21:15:09 +0000 (13:15 -0800)]
i965: Mark texture formats as supported using the surface formats table.
This is currently duplicated with intel_context.c's setup of the
formats table, and sets true for exactly the same set of formats on
gen6.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 15 Nov 2011 20:53:18 +0000 (12:53 -0800)]
intel: Improve debug output for begin/finish render texture.
I've never seen a use for the thread ID value, but knowing the format
being rendered is kind of a big deal.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 15 Nov 2011 20:49:25 +0000 (12:49 -0800)]
intel: Remove duplicate test for texture attachment completeness.
We are already testing this if appropriate in
intel_validate_framebuffer (FBO completeness), so no need to avoid
attaching the texture to the renderbuffer here.
This causes MESA_FORMAT_R11_G11_B10_FLOAT to now be renderable as a texture
attachment on i965.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 15 Nov 2011 20:15:37 +0000 (12:15 -0800)]
i965: Don't require spans (swrast) support to consider a format FBO complete.
We don't want to go writing GetRow/PutRow for every format required by
GL 3.0, when it's very hard to get those functions called, and in
every case we want to make swrast do direct mapping through
MapRenderbuffer anyway.
This causes MESA_FORMAT_R11_G11_B10_FLOAT to be considered complete on gen6.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 15 Nov 2011 19:44:52 +0000 (11:44 -0800)]
i965: Use the surface format table to determine render target supportedness.
This moves any chipset-dependent logic we want for render target
format choices to init time as well. There is still logic left at
state update for SRGB handling, where format choices change based on
GL state.
The brw_render_target_supported() function should now return correct
results, instead of relying on the limited results from
intel_span_supports_format() to avoid lying about FBO completeness.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 15 Nov 2011 19:43:40 +0000 (11:43 -0800)]
intel: Add the context to the render_target_supported() vtbl method.
We're going to want to provide different answers per chipset
generation.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 15 Nov 2011 00:58:57 +0000 (16:58 -0800)]
i965: Add a table of the surface format information from the PRM.
This will be used to drive chosing formats and determining framebuffer
completeness, instead of the bunch of ad-hoc checks we have had until
now.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Thu, 17 Nov 2011 21:56:30 +0000 (13:56 -0800)]
mesa: Make formats.c "datatype" values match glGetTexLevelParameter return.
The formats.c code's "datatype" value is "what does this value mean",
i.e. unorm or snorm or float, and is the return value from the
GL_TEXTURE_RED_TYPE class of queries. The depth formats were marked
as GL_UNSIGNED_INT, which is what we use for integer, and not what we
should be returning from the glGetTexLevelParameter.
In texstore, we were inappropriately using it as an argument to
_mesa_unpack_depth_span() that was expecting a value like
GL_UNSIGNED_INT or GL_UNSIGNED_SHORT. Just hardcode
_mesa_unpack_depth_span()'s arguments for now, though it looks like
the consumers of that interface would be happier with using
MESA_FORMAT.
Reviewed-by: Brian Paul <brianp@vmware.com>
Eric Anholt [Fri, 4 Nov 2011 22:28:58 +0000 (15:28 -0700)]
mesa: Don't report types for 0-sized components of textures.
The GL_TEXTURE_WHATEVER_SIZE entrypoints were checking if the
specified base type of the texture allowed that channel to be present
before reporting the size of the channel, so that GL_RGB didn't end up
with an alpha size if the hardware driver had to store it that way.
The GL_TEXTURE_WHATEVER_TYPE entrypoints weren't checking it, so you
would end up with strange responses from the GL involving 0-bit
floating-point alpha components in GL_RGB32F, even though it says
GL_NONE as expected for other 0-sized channels.
Make _TYPE check _BaseFormat the same as _SIZE, which results in
fixing most of the GL_RGB* testcases of gl-3.0-required-sized-formats
pass on i965.
v2: Add a default case with a warning (suggestion by Brian Paul)
Reviewed-by: Brian Paul <brianp@vmware.com> (v1)
Marek Olšák [Tue, 22 Nov 2011 19:48:23 +0000 (20:48 +0100)]
r600g: handle all remaining CAPs
Marek Olšák [Tue, 22 Nov 2011 19:44:14 +0000 (20:44 +0100)]
r600g: remove default case statements in get_param
This will throw a compile warning if there's an unhandled CAP.
Marek Olšák [Tue, 22 Nov 2011 19:47:14 +0000 (20:47 +0100)]
r300g: re-order shaders CAPs
Marek Olšák [Tue, 22 Nov 2011 19:46:43 +0000 (20:46 +0100)]
r300g: handle SHADER_CAP_OUTPUT_READ
Marek Olšák [Tue, 22 Nov 2011 19:44:14 +0000 (20:44 +0100)]
r300g: remove default case statements in get_param
This will throw a compile warning if there's an unhandled CAP.
Marek Olšák [Tue, 22 Nov 2011 19:43:21 +0000 (20:43 +0100)]
u_vbuf_mgr: rename to u_vbuf
Marek Olšák [Sun, 20 Nov 2011 19:45:57 +0000 (20:45 +0100)]
u_vbuf_mgr: better way to find a free VB slot + check errors early
Marek Olšák [Tue, 22 Nov 2011 19:04:40 +0000 (20:04 +0100)]
u_vbuf_mgr: remove a useless variable
Marek Olšák [Sun, 20 Nov 2011 19:36:35 +0000 (20:36 +0100)]
u_vbuf_mgr: remove redundant memset
Marek Olšák [Sun, 20 Nov 2011 19:34:12 +0000 (20:34 +0100)]
u_vbuf_mgr: don't reference non-native vertex buffers as native
also don't mark them as 'user', because they will be uploaded through
the translate fallback anyway.
Marek Olšák [Sun, 20 Nov 2011 19:33:31 +0000 (20:33 +0100)]
u_vbuf_mgr: rename translate_vb_slot -> fallback_vb_slot
Marek Olšák [Sat, 19 Nov 2011 21:38:22 +0000 (22:38 +0100)]
gallium: separate out floating-point CAPs into its own enum
The motivation behind this is to add some self-documentation in the code
about how each CAP can be used.
The idea is:
- enum pipe_cap is only valid in get_param
- enum pipe_capf is only valid in get_paramf
Which CAPs are floating-point have been determined based on how everybody
except svga implemented the functions. svga have been modified to match all
the other drivers.
Besides that, the floating-point CAPs are now prefixed with PIPE_CAPF_.
Marek Olšák [Fri, 18 Nov 2011 14:51:47 +0000 (15:51 +0100)]
gallium: remove PIPE_CAP_GLSL and enable GLSL unconditionally
Only i965g does not enable GLSL, but that driver has been unmaintained and
bitrotting for quite a while anyway.
Marek Olšák [Sat, 19 Nov 2011 15:45:46 +0000 (16:45 +0100)]
glsl: convervative_depth is not allowed in the vertex shader
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Marek Olšák [Sat, 19 Nov 2011 15:41:08 +0000 (16:41 +0100)]
glsl: finish up ARB_conservative_depth (v2)
v2: updated an error message
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Marek Olšák [Sat, 19 Nov 2011 15:27:50 +0000 (16:27 +0100)]
mesa: rename the AMD_conservative_depth extension flag to ARB
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Marek Olšák [Sun, 20 Nov 2011 14:08:56 +0000 (15:08 +0100)]
st/mesa: quick fix of CopyPixels with GL_DEPTH_STENCIL
This fixes:
- depthstencil-default_fb-copypixels
- fbo-depthstencil-GL_DEPTH24_STENCIL8-copypixels
Reviewed-by: Brian Paul <brianp@vmware.com>
Ian Romanick [Mon, 21 Nov 2011 19:42:37 +0000 (11:42 -0800)]
linker: Remove erroneous multiply by 4 in uniform usage calculation
The old count_uniform_size::num_shader_uniforms was actually
calculating the number of components used. Multiplying by 4 when
setting gl_shader::num_uniform_components caused us to count 4x as
many uniform components as were actually used.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42930
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42966
Acked-by: Marek Olšák <maraeo@gmail.com>
Tested-by: Vinson Lee <vlee@vmware.com>
Tested-by: Pavel Ondračka <pavel.ondracka@email.cz>
Reviewed-and-tested-by: Kenneth Graunke <kenneth@whitecape.org>
Chad Versace [Tue, 22 Nov 2011 18:52:29 +0000 (10:52 -0800)]
Merge branch 'hiz' of ssh://people.freedesktop.org/~chadversary/mesa
Chad Versace [Thu, 17 Nov 2011 16:53:39 +0000 (08:53 -0800)]
i965/gen6: Enable HiZ by default
Regresses one Piglit test: bugs/fdo10370.
I'm not enabling HiZ for gen7 yet because it causes a mysterious
performance regression.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Thu, 17 Nov 2011 16:50:05 +0000 (08:50 -0800)]
intel: Use separate stencil whenever possible
For depthstencil renderbuffers, we were using separate stencil only if the
hardware required it. Since the performance gains from HiZ is so high, we
should always use separate stencil if the hardware supports it.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Kenneth Graunke [Mon, 7 Nov 2011 23:58:43 +0000 (15:58 -0800)]
i965: Implement the actual tables for texture alignment units [v2]
I implemented functions for horizontal/vertical alignment units separately
because I find it easier to read that way...especially with all the
corner-cases.
[chad] Corrected the vertical alignment calculation by checking for
depthstencil formats.
v2:
- Fix typos in intel_horizontal_texture_alignment_unit():
s/height/width/ and s/VALIGN/HALIGN.
- Remove special case for compressed formats in
intel_get_texture_alignment unit(). Compressed formats are already
handled in the halign and valign functions.
- Replace check ``_mesa_is_depth_format(...) ||
_mesa_is_depthstencil_format(...)`` with explcitit checks against
GL_DEPTH_COMPONENT and GL_DEPTH_STENCIL.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Thu, 17 Nov 2011 17:09:56 +0000 (09:09 -0800)]
i965/gen6: Set vertical alignment in SURFACE_STATE batch
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Thu, 17 Nov 2011 16:30:30 +0000 (08:30 -0800)]
intel: Store miptree alignment units in the miptree
This allows us to replace all the calls to
intel_get_texture_alignment_unit() with a single call at miptree creation.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Wed, 16 Nov 2011 06:51:35 +0000 (22:51 -0800)]
intel: Enable HiZ for texture renderbuffers
When a depth texture is first attached to framebuffer, allocate a HiZ
miptree for it.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Wed, 16 Nov 2011 02:25:39 +0000 (18:25 -0800)]
intel: Resolve buffers in intel_map_renderbuffer()
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Wed, 16 Nov 2011 02:21:12 +0000 (18:21 -0800)]
intel: Resolve buffers in intel_map_texture_image()
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Wed, 16 Nov 2011 02:21:09 +0000 (18:21 -0800)]
intel: Mark needed resolves when first enabling HiZ on a miptree
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Wed, 16 Nov 2011 02:20:43 +0000 (18:20 -0800)]
i965: Mark that depth buffer needs depth resolve after drawing
After brw_try_draw_prims() emits a batch, mark that the depth buffer needs
a depth resolve if the buffer was written to and if it has an accompanying
HiZ buffer.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Wed, 16 Nov 2011 02:21:05 +0000 (18:21 -0800)]
intel: Resolve buffers in intelSpanRenderStart
Resolve all buffers that will be mapped by intelSpanRenderStart. This
comprises resolving the depth buffer of each enabled texture and of the
read and draw buffers.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Wed, 16 Nov 2011 02:20:57 +0000 (18:20 -0800)]
intel: Refactor intelSpanRenderStart
Factor the mapping loops from intelSpanRenderStart() into
intel_span_map_buffers(). This in preparation for the next commit,
which resolves the buffers before mapping.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Wed, 16 Nov 2011 02:20:39 +0000 (18:20 -0800)]
i965: Resolve buffers before drawing [v2]
Before emitting primitives in brw_try_draw_prims(), resolve the depth
buffer's HiZ buffer and resolve the depth buffer of each enabled depth
texture.
v2: [anholt] The driver no longer validates drm bo's, so update a comment
to reflect that.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Wed, 16 Nov 2011 02:20:34 +0000 (18:20 -0800)]
i965: Prevent recursive calls to FLUSH_VERTICES [v2]
To do so, we must resolve all buffers on entering a glBegin/glEnd block.
For the detailed explanation, see the Doxygen comments in this patch.
v2:
- Fix typo: s/enusure/ensure/.
- In brwPrepareExecBegin(), do the same resolves as done by
brw_predraw_resolve_buffers().
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Wed, 16 Nov 2011 02:20:31 +0000 (18:20 -0800)]
i965/gen6: Manipulate state batches for HiZ meta-ops [v4]
A lot of the state manipulation is handled by the meta-op state setup.
However, some batches need manual intervention.
v2:
Do not special-case the 3DSTATE_DEPTH_STENCIL.Depth_Test_Enable bit
for HiZ in gen6_upload_depth_stencil(). The HiZ meta-op sets
ctx->Depth.Test, just read the value from that.
v3:
Add a new dirty flag, BRW_STATE_HIZ, for brw_tracked_state. Flag it
immediately before and after executing the HiZ operation in
gen6_resolve_slice(). Add the flag to the the dirty bits for the
following state packets:
gen6_clip_state
gen6_depth_stencil_state
gen6_sf_state
gen6_wm_state
v4:
- Add BRW_NEW_STATE_HIZ to the dirty bit table in brw_state_upload.c.
This is needed for INTEL_DEBUG=state.
- Align brw dirty bit for gen6_depth_stencil_state.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Thu, 17 Nov 2011 16:10:57 +0000 (08:10 -0800)]
i965/gen6: Complete stubs for HiZ buffer resolves
Some state batches also need to be manipulated. That's done in the next
commit.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Wed, 16 Nov 2011 02:20:20 +0000 (18:20 -0800)]
i965: Add HiZ operation state to brw_context
brw_context::hiz contains state needed to perform HiZ meta-ops and
indicates if a HiZ operation is currently in progress.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Thu, 17 Nov 2011 16:03:48 +0000 (08:03 -0800)]
intel: Add resolve functions for renderbuffers
Add the following functions:
intel_renderbuffer_resolve_hiz
intel_renderbuffer_resolve_depth
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Wed, 16 Nov 2011 02:20:02 +0000 (18:20 -0800)]
intel: Add resolve functions for miptrees
Add functions that
- set a miptree slice as needing a resolve
- resolve a single slice of a miptree
- resolve all slices of a miptree
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Thu, 17 Nov 2011 15:42:21 +0000 (07:42 -0800)]
intel: Add field intel_mipmap_tree::hiz_map
This is a map of miptree slices to needed resolves.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Thu, 17 Nov 2011 07:43:56 +0000 (23:43 -0800)]
intel: Define struct intel_resolve_map [v2]
This is a map of miptree slices to needed resolves, implemented as
a linked list. A future commit will embed such a list in
intel_mipmap_tree.
If you think I'm crazy to put a list in a miptree, read the Doxygen in
this patch for intel_resolve_map.
v2: [anholt] Move Doxygen from functin prototypes to definitions.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Thu, 17 Nov 2011 07:23:30 +0000 (23:23 -0800)]
intel: Change signature of HiZ resolve functions
Now that intel_renderbuffer::region has been replaced with a miptree, the
HiZ functions region parameter must be replaced with a miptree parameter.
Change the return type from bool to void.
Rename the 'depth' parameter to 'layer', because it will correspond to
irb->mt_layer.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Thu, 17 Nov 2011 07:10:48 +0000 (23:10 -0800)]
intel: Remove unused HiZ functions
Remove the following functions:
i830_hiz_resolve_noop
i915_hiz_resolve_noop
brw_hiz_resolve_noop
My original strategy for how intel->vtbl.resolve_*buffer was used has
substantially changed. The above functions are no longer called in the
current strategy.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Thu, 17 Nov 2011 07:14:39 +0000 (23:14 -0800)]
intel: Replace intel_mipmap_tree::hiz_region with a miptree [v2]
This is required to correctly implement HiZ for mipmapped and
multi-layered textures.
v2: Accomodate refcount fixes in intel_process_dri2_buffer_*() that were
introduced in v2 of commit
intel: Replace intel_renderbuffer::region with a miptree [v2]
Reviewed-by: Eric Anholt <eric@anholt>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Wed, 16 Nov 2011 06:17:34 +0000 (22:17 -0800)]
intel: Replace intel_texture_image::stencil_irb with intel_mipmap_tree::stencil_mt [v3]
For depthstencil textures using separate stencil, we embedded a stencil
buffer in intel_texture_image. The intention was that the embedded stencil
buffer would be the golden copy of the texture's stencil bits. When
necessary, we scattered/gathered the stencil bits between the texture
miptree and the embedded stencil buffer.
This approach had a serious deficiency for mipmapped or multi-layer
textures. Any given moment the embedded stencil buffer was consistent with
exactly one miptree slice, the most recent one to be scattered. This
permitted tests of type A to pass, but broke tests of type B.
Test A:
1. Create a depthstencil texture.
2. Upload data into (level=x1,layer=y1).
3. Read and test stencil data at (level=x1, layer=y1).
4. Upload data into (level=x2,layer=y2).
5. Read and test stencil data at (level=x2, layer=y2).
Test B:
1. Create a depthstencil texture.
2. Upload data into (level=x1,layer=y1).
3. Upload data into (level=x2,layer=y2).
4. Read and test stencil data at (level=x1, layer=y1).
5. Read and test stencil data at (level=x2, layer=y2).
v2:
Only allocate stencil miptree if intel->must_use_separate_stencil,
because we don't make the conversion from must_use_separate_stencil to
has_separate_stencil until commit
intel: Use separate stencil whenever possible
v3:
Don't call ChooseNewTexture in intel_renderbuffer_wrap_miptree() in
order to determine the renderbuffer format. Instead, pass the format as
a param to that function.
CC: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Wed, 16 Nov 2011 06:11:33 +0000 (22:11 -0800)]
intel: Refactor intel_render_texture() [v2]
This is in preparation for properly implementing glFramebufferTexture*()
for mipmapped depthstencil textures. The FIXME comments deleted by this
patch give a rough explanation of what was broken.
This refactor does the following:
- In intel_update_wrapper() and intel_wrap_texture(), change the
parameters to prepare to remove functions' dependency on
gl_texture_image.
- Move the call to intel_renderbuffer_set_draw_offsets() from
intel_render_texture() into intel_udpate_wrapper().
Each time I encounter those functions, I dislike their vague names.
(Update which wrapper? What is wrapped? What is the wrapper?). So, while
I was mucking around, I also renamed the functions.
v2:
In addition to the ``GLenum internal_format`` parameter to
intel_wrap_miptree(), add a ``gl_format format`` parameter. This
removes the need to recalculate for the true format from
internal_format with ChooseNewTextureFormat, which was just weird.
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Thu, 17 Nov 2011 06:42:44 +0000 (22:42 -0800)]
intel: Define intel_miptree_check_level_layer()
This is a small helper function that asserts that a given level and layer
are valid for a miptree. I will be extensively using it in the future
miptree HiZ functions.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Tue, 15 Nov 2011 18:22:14 +0000 (10:22 -0800)]
intel: Remove unneeded params from intel_renderbuffer_set_draw_offset()
Since the renderbuffer tracks the miptree level and layer that it wraps,
the 'tex_image' and 'zoffset' params are no longer needed to calculate the draw
offsets.
Not only are they no longer needed, but their presence would prevent
calculating the renderbuffer draw offsets in situations where there were
no texture image. Such situations will occur during the HiZ meta-op and
during scatter/gather of separate stencil textures.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Tue, 15 Nov 2011 18:05:21 +0000 (10:05 -0800)]
intel: Track the miptree layer wrapped by a renderbuffer [v2]
TODO: Make v2 for kwg.
Add two fields to intel_renderbuffer:
mt_level
mt_layer
Multiple renderbuffers may simultaneously wrap a single texture and each
provide a different view into that texture. [Consider
glFramebufferTextureLayer()]. The new fields indicate which slice of the
miptree is wrapped by the renderbuffer.
The buffer resolve operations, to be introduced in the future, require
these fields in order to resolve the correct slice in the miptree.
To add the fields, it was necessary to replace the type of some function
parameters from gl_texture_image to gl_renderbuffer_attachment.
v2: [kwg] Replace confusing condition `CubeMapFace > 0` with the more
sensible `Target == GL_TEXTURE_CUBE_MAP`.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Tue, 15 Nov 2011 17:55:40 +0000 (09:55 -0800)]
intel: Kill intel_mipmap_level::nr_images [v4]
For all texture targets except GL_TEXTURE_CUBE_MAP, the 'nr_images' and
'depth' fields of intel_mipmap_level were identical. In the exceptional
case, nr_images == 6 and depth == 1.
It is simple to determine if a texture is a cube or not, so the presence
of two fields here was not helpful. Worse, it was confusing. When we
eventually implement GL_ARB_texture_cube_map_array, this mess would have
become even more confusing.
This patch removes 'nr_images' and assigns to 'depth' a consistent
meaning: depth is the number of 2D slices at each miplevel. The exact
semantics of depth varies according to the texture target:
- For GL_TEXTURE_CUBE_MAP, depth is 6.
- For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
identical for all miplevels in the texture.
- For GL_TEXTURE_3D, it is the texture's depth at each miplevel. Its
value, like width and height, varies with miplevel.
- For other texture types, depth is 1.
As a consequence, parameters were removed from the following function
signatures:
intel_miptree_set_level_info
Remove 'nr_images'.
i945_miptree_layout
brw_miptree_layout_texture
brw_miptree_layout_texture_array
Remove 'slices'.
v2:
- Replace "It's" with "Its".
- Remove all hunks in intel_fbo.c. The hunks were spurious and sneaked
in during a rebase.
- Remove unneeded hunk in intel_tex_map_image_for_swrast(). It was
a little refactor of the for-loop's upper bound.
v4:
In intel_miptree_get_image_offset(), document the conditions under
which different if-branches are taken.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Vasily Khoruzhick [Tue, 22 Nov 2011 16:04:04 +0000 (19:04 +0300)]
i915g: implement RGBX and BGRX render targets
They're not supported by hw directly, but it's easy to emulate
them with a shader swizzling fixup.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[danvet: The important thing is to write a 1 to the unused alpha
channel, the ddx is relying on this for render accel.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>