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Matt Arsenault [Mon, 15 Jul 2019 21:41:44 +0000 (21:41 +0000)]
AMDGPU: Use standalone MUBUF load patterns
We already do this for the flat and DS instructions, although it is
certainly uglier and more verbose.
This will allow using separate pattern definitions for extload and
zextload. Currently we get away with using a single PatFrag with
custom predicate code to check if the extension type is a zextload or
anyextload. The generic mechanism the global isel emitter understands
treats these as mutually exclusive. I was considering making the
pattern emitter accept zextload or sextload extensions for anyextload
patterns, but in global isel, the different extending loads have
distinct opcodes, and there is currently no mechanism for an opcode
matcher to try multiple (and there probably is very little need for
one beyond this case).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366132
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Nick Desaulniers [Mon, 15 Jul 2019 21:16:29 +0000 (21:16 +0000)]
[LoopUnroll+LoopUnswitch] do not transform loops containing callbr
Summary:
There is currently a correctness issue when unrolling loops containing
callbr's where their indirect targets are being updated correctly to the
newly created labels, but their operands are not. This manifests in
unrolled loops where the second and subsequent copies of callbr
instructions have blockaddresses of the label from the first instance of
the unrolled loop, which would result in nonsensical runtime control
flow.
For now, conservatively do not unroll the loop. In the future, I think
we can pursue unrolling such loops provided we transform the cloned
callbr's operands correctly.
Such a transform and its legalities are being discussed in:
https://reviews.llvm.org/D64101
Link: https://bugs.llvm.org/show_bug.cgi?id=42489
Link: https://groups.google.com/forum/#!topic/clang-built-linux/z-hRWP9KqPI
Reviewers: fhahn, hfinkel, efriedma
Reviewed By: fhahn, hfinkel, efriedma
Subscribers: efriedma, hiraditya, zzheng, dmgreen, llvm-commits, pirama, kees, nathanchance, E5ten, craig.topper, chandlerc, glider, void, srhines
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64368
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366130
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Matt Arsenault [Mon, 15 Jul 2019 21:15:20 +0000 (21:15 +0000)]
TableGen/GlobalISel: Fix handling of truncstore patterns
This was failing to import the AMDGPU truncstore patterns. The
truncating stores from 32-bit to 8/16 were then somehow being
incorrectly selected to a 4-byte store.
A separate check is emitted for the LLT size in comparison to the
specific memory VT, which looks strange to me but makes sense based on
the hierarchy of PatFrags used for the default truncstore PatFrags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366129
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Matt Arsenault [Mon, 15 Jul 2019 20:59:42 +0000 (20:59 +0000)]
TableGen: Add address space to matchers
Currently AMDGPU uses a CodePatPred to check address spaces from the
MachineMemOperand. Introduce a new first class property so that the
existing patterns can be easily modified to uses the new generated
predicate, which will also be handled for GlobalISel.
I would prefer these to match against the pointer type of the
instruction, but that would be difficult to get working with
SelectionDAG compatbility. This is much easier for now and will avoid
a painful tablegen rewrite for all the loads and stores.
I'm also not sure if there's a better way to encode multiple address
spaces in the table, rather than putting the number to expect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366128
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Matt Arsenault [Mon, 15 Jul 2019 20:20:18 +0000 (20:20 +0000)]
AMDGPU/GlobalISel: Allow scalar s1 and/or/xor
If a 1-bit value is in a 32-bit VGPR, the scalar opcodes set SCC to
whether the result is 0. If the inputs are SCC, these can be copied to
a 32-bit SGPR to produce an SCC result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366125
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Evgeniy Stepanov [Mon, 15 Jul 2019 20:02:23 +0000 (20:02 +0000)]
ARM MTE stack sanitizer.
Add "memtag" sanitizer that detects and mitigates stack memory issues
using armv8.5 Memory Tagging Extension.
It is similar in principle to HWASan, which is a software implementation
of the same idea, but there are enough differencies to warrant a new
sanitizer type IMHO. It is also expected to have very different
performance properties.
The new sanitizer does not have a runtime library (it may grow one
later, along with a "debugging" mode). Similar to SafeStack and
StackProtector, the instrumentation pass (in a follow up change) will be
inserted in all cases, but will only affect functions marked with the
new sanitize_memtag attribute.
Reviewers: pcc, hctim, vitalybuka, ostannard
Subscribers: srhines, mehdi_amini, javed.absar, kristof.beyls, hiraditya, cryptoad, steven_wu, dexonsmith, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D64169
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366123
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Matt Arsenault [Mon, 15 Jul 2019 19:50:07 +0000 (19:50 +0000)]
AMDGPU/GlobalISel: Select G_AND/G_OR/G_XOR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366121
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Matt Arsenault [Mon, 15 Jul 2019 19:48:36 +0000 (19:48 +0000)]
AMDGPU/GlobalISel: Don't constrain source register of VCC copies
This is a hack until I come up with a better way of dealing with the
pseudo-register banks used for boolean values. If the use instruction
constrains the register, the selector for the def instruction won't
see that the bank was VCC. A 1-bit SReg_32 is could ambiguously have
been SCCRegBank or VCCRegBank in wave32.
This is necessary to successfully select branches with and and/or/xor
condition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366120
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Matt Arsenault [Mon, 15 Jul 2019 19:46:48 +0000 (19:46 +0000)]
AMDGPU/GlobalISel: Fix selecting vcc->vcc bank copies
The extra test change is correct, although how it arrives there is a
bug that needs work. With wave32, the test for isVCC ambiguously
reports true for an SCC or VCC source. A new allocatable pseudo
register class for SCC may be necesssary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366119
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Matt Arsenault [Mon, 15 Jul 2019 19:45:49 +0000 (19:45 +0000)]
AMDGPU/GlobalISel: Fix not constraining result reg of copies to VCC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366118
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Matt Arsenault [Mon, 15 Jul 2019 19:44:07 +0000 (19:44 +0000)]
AMDGPU/GlobalISel: Fix handling of sgpr (not scc bank) s1 to VCC
This was emitting a copy from a 32-bit register to a 64-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366117
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Matt Arsenault [Mon, 15 Jul 2019 19:43:04 +0000 (19:43 +0000)]
AMDGPU/GlobalISel: Custom legalize G_INSERT_VECTOR_ELT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366116
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Matt Arsenault [Mon, 15 Jul 2019 19:40:59 +0000 (19:40 +0000)]
AMDGPU/GlobalISel: Custom legalize G_EXTRACT_VECTOR_ELT
Turn the constant cases into G_EXTRACTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366115
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Matt Arsenault [Mon, 15 Jul 2019 19:39:31 +0000 (19:39 +0000)]
AMDGPU/GlobalISel: Fix G_ICMP for wave32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366114
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Matt Arsenault [Mon, 15 Jul 2019 19:37:34 +0000 (19:37 +0000)]
GlobalISel: Implement narrowScalar for vector extract/insert indexes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366113
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Matt Arsenault [Mon, 15 Jul 2019 19:12:00 +0000 (19:12 +0000)]
AMDGPU: Fix missing immarg from interp intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366110
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Thomas Preud'homme [Mon, 15 Jul 2019 19:04:56 +0000 (19:04 +0000)]
[FileCheck] Store line numbers as optional values
Summary:
Processing of command-line definition of variable and logic around
implicit not directives both reuse parsing code that expects a line
number to be defined. So far, a special line number of 0 was used for
those users of the parsing code where a line number does not make sense.
This commit instead represents line numbers as Optional values so that
they can be None for those cases.
Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk
Subscribers: JonChesterfield, rogfer01, hfinkel, kristina, rnk, tra, arichardson, grimar, dblaikie, probinson, llvm-commits, hiraditya
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64639
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366109
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Keno Fischer [Mon, 15 Jul 2019 19:04:04 +0000 (19:04 +0000)]
[cmake] Don't set install rules for tblgen if building utils is disabled
Summary:
This is a follow up to D64032. Afterwards if building utils is disabled
and cross compilation is attempted, CMake will complain that adding
`install()` directives to targets with EXCLUDE_FROM_ALL set is "undefined".
Indeed, it appears depending on the CMake version and the selected
Generator, the install rule will error because the underlying target isn't
built. Fix that by not adding the install rule if building utils is not
requested. Note that this doesn't prevent building tblgen as a
dependency in not cross-build, even if building tools is disabled.
Reviewed By: smeenai
Differential Revision: https://reviews.llvm.org/D64225
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366108
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Nico Weber [Mon, 15 Jul 2019 18:56:56 +0000 (18:56 +0000)]
Expand comment about how StringsToBuckets was computed, and add more entries
The construction was explained in
https://reviews.llvm.org/D44810?id=139526#inline-391999 but reading the code
shouldn't require hunting down old reviews to understand it.
The precomputed list was missing an entry for the empty list case, and
one entry at the very end. (The current last entry is the last one where
3 * BucketCount fits in a signed int, but the reference implementation
uses unsigneds as far as I can tell, so there's room for one more entry.)
No behavior change for inputs seen in practice.
Differential Revision: https://reviews.llvm.org/D64738
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366107
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David Green [Mon, 15 Jul 2019 18:42:54 +0000 (18:42 +0000)]
[ARM] MVE vector for 64bit types
We need to make sure that we are sensibly dealing with vectors of types v2i64
and v2f64, even if most of the time we cannot generate native operations for
them. This mostly adds a lot of testing, plus fixes up a couple of the issues
found. And, or and xor can be legal for v2i64, and shifts combining needs a
slight fixup.
Differential Revision: https://reviews.llvm.org/D64316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366106
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Wouter van Oortmerssen [Mon, 15 Jul 2019 18:36:07 +0000 (18:36 +0000)]
[WebAssembly] Assembler: recognize .init_array as data section.
Reviewers: sbc100
Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64602
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366104
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Matt Arsenault [Mon, 15 Jul 2019 18:31:10 +0000 (18:31 +0000)]
AMDGPU/GlobalISel: Widen vector extracts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366103
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Matt Arsenault [Mon, 15 Jul 2019 18:25:24 +0000 (18:25 +0000)]
AMDGPU/GlobalISel: Handle llvm.amdgcn.if.break
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366102
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Konstantin Zhuravlyov [Mon, 15 Jul 2019 18:22:06 +0000 (18:22 +0000)]
AMDGPU: Remove reserved value accidentally left in for gfx908
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366101
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Matt Arsenault [Mon, 15 Jul 2019 18:18:46 +0000 (18:18 +0000)]
AMDGPU/GlobalISel: Select llvm.amdgcn.end.cf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366099
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Sanjay Patel [Mon, 15 Jul 2019 18:17:23 +0000 (18:17 +0000)]
[x86] try to keep FP casted+truncated+extracted vector element out of GPRs
inttofp (trunc (extelt X, 0)) --> inttofp (extelt (bitcast X), 0)
We have pseudo-vectorization of scalar int to FP casts, so this tries to
make that more likely by replacing a truncate with a bitcast. I didn't see
any test diffs starting from 'uitofp', so I left that as a TODO. We can't
only match the shorter trunc+extract pattern because there's an opposing
transform somewhere, so we infinite loop. Waiting to try this during
lowering is another possibility.
A motivating case is shown in PR39975 and included in the test diffs here:
https://bugs.llvm.org/show_bug.cgi?id=39975
Differential Revision: https://reviews.llvm.org/D64710
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366098
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Stella Stamenova [Mon, 15 Jul 2019 18:15:12 +0000 (18:15 +0000)]
[llvm-lib] Add a dependency to intrinsics_gen to the LLVMLibDriver build
Summary:
Occasionally the build of LLVMLibDriver will fail because Attributes.inc has not been generated yet. Add an explicit dependency, so that we can guarantee that the file has been generated before LLVMLibDriver is build.
##[error]llvm\include\llvm\IR\Attributes.h(73,0): Error C1083: Cannot open include file: 'llvm/IR/Attributes.inc': No such file or directory
llvm\include\llvm/IR/Attributes.h(73): fatal error C1083: Cannot open include file: 'llvm/IR/Attributes.inc': No such file or directory [LLVMLibDriver.vcxproj]
Reviewers: asmith
Subscribers: mgorny, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64357
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366097
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Craig Topper [Mon, 15 Jul 2019 17:56:57 +0000 (17:56 +0000)]
[X86] Return UNDEF from LowerScalarImmediateShift when the shift amount is out of range.
I think we only turn out of range shiftss to undef when
all elements are out of range or the shift amount is a splat out
of range. I'm not sure which, I didn't check.
During lowering we can split a shift where some elements
are out of range into multiple shifts. This can create a
new shift with a splat shift amount that is out of range.
This patch returns undef for this case.
Fixes PR42615.
Differential Revision: https://reviews.llvm.org/D64699
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366096
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Matt Arsenault [Mon, 15 Jul 2019 17:50:31 +0000 (17:50 +0000)]
AMDGPU: Add 24-bit mul intrinsics
Insert these during codegenprepare.
This works around a DAG issue where generic combines eliminate the and
asserting the high bits are zero, which then exposes an unknown read
source to the mul combine. It doesn't worth the hassle of trying to
insert an AssertZext or something to try to deal with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366094
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Matt Arsenault [Mon, 15 Jul 2019 17:50:28 +0000 (17:50 +0000)]
Add some release notes for 9.0 release
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366093
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Stanislav Mekhanoshin [Mon, 15 Jul 2019 17:49:25 +0000 (17:49 +0000)]
[AMDGPU] Copy missing predicate from pseudo to real
NFC at the momemnt, needed for future commit.
Differential Revision: https://reviews.llvm.org/D64761
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366092
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Johannes Doerfert [Mon, 15 Jul 2019 17:31:26 +0000 (17:31 +0000)]
[FunctionAttrs] Remove readonly and writeonly assertion
There are scenarios where mutually recursive functions may cause the SCC
to contain both read only and write only functions. This removes an
assertion when adding read attributes which caused a crash with a the
provided test case, and instead just doesn't add the attributes.
Patch by Luke Lau <luke.lau@intel.com>
Differential Revision: https://reviews.llvm.org/D60761
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366090
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David Green [Mon, 15 Jul 2019 17:29:06 +0000 (17:29 +0000)]
[ARM] Minor formatting in ARMInstrMVE.td. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366089
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Matt Arsenault [Mon, 15 Jul 2019 17:26:43 +0000 (17:26 +0000)]
AMDGPU/GlobalISel: Select easy cases for G_BUILD_VECTOR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366087
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Matt Arsenault [Mon, 15 Jul 2019 17:20:40 +0000 (17:20 +0000)]
AMDGPU/GlobalISel: RegBankSelect for G_CONCAT_VECTORS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366086
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Sanjay Patel [Mon, 15 Jul 2019 16:59:38 +0000 (16:59 +0000)]
[x86] add tests for reductions that might be better with more horizontal ops; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366082
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Ilya Biryukov [Mon, 15 Jul 2019 16:43:36 +0000 (16:43 +0000)]
Revert "r366069: [PatternMatch] Implement matching code for LibFunc"
Reason: the change introduced a layering violation by adding a
dependency on IR to Analysis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366081
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James Henderson [Mon, 15 Jul 2019 16:40:34 +0000 (16:40 +0000)]
[docs][llvm-nm] Fix inconsistent grammar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366080
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Simon Pilgrim [Mon, 15 Jul 2019 16:23:42 +0000 (16:23 +0000)]
[X86][SSE] Regenerated packss.ll test file.
Not sure what went wrong in rL366077....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366079
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Simon Pilgrim [Mon, 15 Jul 2019 15:43:04 +0000 (15:43 +0000)]
[X86][SSE] Add PACKSS with zero shuffle masks.
This is an example of expansion due to D61129 - it should combine back to a PACKSS with a zero operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366077
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Lang Hames [Mon, 15 Jul 2019 15:36:37 +0000 (15:36 +0000)]
[ORC] Start adding ORCv1 to ORCv2 transition tips to the ORCv2 doc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366075
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Stanislav Mekhanoshin [Mon, 15 Jul 2019 15:34:05 +0000 (15:34 +0000)]
[AMDGPU] fixed scheduler crash in gfx908
For some reason scheduler can send down an SUnit without an
instruction.
Differential Revision: https://reviews.llvm.org/D64709
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366074
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Nico Weber [Mon, 15 Jul 2019 15:14:09 +0000 (15:14 +0000)]
gn build: Add a note on how to locally tell git to ignore build dir
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366072
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Dmitry Preobrazhensky [Mon, 15 Jul 2019 15:12:16 +0000 (15:12 +0000)]
[AMDGPU][MC][GFX9][GFX10] Added support of GET_DOORBELL message
Reviewers: artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D64729
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366071
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Dmitry Venikov [Mon, 15 Jul 2019 14:47:45 +0000 (14:47 +0000)]
[PatternMatch] Implement matching code for LibFunc
Summary: Provides m_LibFunc pattern that can be used to match LibFuncs.
Reviewers: spatel, hfinkel, efriedma, lebedev.ri
Reviewed By: lebedev.ri
Subscribers: lebedev.ri, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D42047
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366069
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Dmitry Preobrazhensky [Mon, 15 Jul 2019 14:37:57 +0000 (14:37 +0000)]
[AMDGPU][MC] Corrected encoding of src0 for DS_GWS_* instructions
See bug 42599: https://bugs.llvm.org/show_bug.cgi?id=42599
Reviewers: artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D64716
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366067
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Simon Pilgrim [Mon, 15 Jul 2019 14:29:14 +0000 (14:29 +0000)]
[X86] isTargetShuffleEquivalent - assert the expected mask is correctly formed. NFCI.
While we don't make any assumptions about the actual mask, assert that the expected mask only contains valid mask element values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366066
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David Zarzycki [Mon, 15 Jul 2019 14:12:35 +0000 (14:12 +0000)]
[Testing] Add missing "REQUIRES: asserts"
This broke after r366048 / https://reviews.llvm.org/D63923
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366065
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Simon Atanasyan [Mon, 15 Jul 2019 13:12:36 +0000 (13:12 +0000)]
[mips] Remove "else-after-return". NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366064
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Nico Weber [Mon, 15 Jul 2019 12:10:02 +0000 (12:10 +0000)]
PDB HashTable: Make iterator key type const
Having the hash table key change during iteration is bad, so make it
impossible. Nothing relied on the key type not being const.
(This is also necessary to be able to call the const version of
iterator_facade_base::operator->(). Nothing calls this, and nothing
will, but I tried using it locally during development and it took me a
while to understand what was going wrong.)
Also rename the iterator typedef to const_iterator.
No behavior change.
Differential Revision: https://reviews.llvm.org/D64641
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366060
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George Rimar [Mon, 15 Jul 2019 11:53:39 +0000 (11:53 +0000)]
Recommit r366052 "[obj2yaml] - Rework tool's error reporting logic for ELF target."
No changes, LLD code was updated in r366057.
Original commit message:
ELF.h contains two getSymbol methods
which seems to be used only from obj2yaml.
One of these methods calls another, which in turn
contains untested error message which doesn't
provide enough information.
Problem is that after improving only just that message,
obj2yaml will not show it,
("Error reading file: yaml: Invalid data was
encountered while parsing the file" message will be shown instead),
because internal errors handling of tool is based on ErrorOr<> class which
stores a error code and as a result can only show a predefined error string, what
actually isn't very useful.
In this patch, I rework obj2yaml's error reporting system
for ELF targets to use Error Expected<> classes.
Also, I improve the error message produced
by getSymbol for demonstration of the new functionality.
Differential revision: https://reviews.llvm.org/D64631
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366058
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David Green [Mon, 15 Jul 2019 11:35:39 +0000 (11:35 +0000)]
[ARM] MVE Vector Shifts
This adds basic lowering for MVE shifts. There are many shifts in MVE, but the
instructions handled here are:
VSHL (imm)
VSHRu (imm)
VSHRs (imm)
VSHL (vector)
VSHL (register)
MVE, like NEON before it, doesn't have shift right by a vector (or register).
We instead have to negate the amount and shift in the opposite direction. This
means we have to convert any SHR's into a form of SHL (that is still signed or
unsigned) with a negated condition and selecting from there. MVE still does
have shifting by an immediate for SHL, ASR and LSR.
This adds lowering for these and for register forms, which work well for shift
lefts but may require an extra fold of neg(vdup(x)) -> vdup(neg(x)) to potentially
work optimally for right shifts.
Differential Revision: https://reviews.llvm.org/D64212
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366056
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David Green [Mon, 15 Jul 2019 11:22:05 +0000 (11:22 +0000)]
[ARM] Move Shifts after Bits. NFC
This just moves the shift instruction definitions further down the
ARMInstrMVE.td file, to make positioning patterns slightly more natural.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366054
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George Rimar [Mon, 15 Jul 2019 11:00:42 +0000 (11:00 +0000)]
Revert r366052 "[obj2yaml] - Rework tool's error reporting logic for ELF target."
Seems it broke LLD:
http://lab.llvm.org:8011/builders/sanitizer-windows/builds/48434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366053
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George Rimar [Mon, 15 Jul 2019 10:50:03 +0000 (10:50 +0000)]
[obj2yaml] - Rework tool's error reporting logic for ELF target.
ELF.h contains two getSymbol methods
which seems to be used only from obj2yaml.
One of these methods calls another, which in turn
contains untested error message which doesn't
provide enough information.
Problem is that after improving only just that message,
obj2yaml will not show it,
("Error reading file: yaml: Invalid data was
encountered while parsing the file" message will be shown instead),
because internal errors handling of tool is based on ErrorOr<> class which
stores a error code and as a result can only show a predefined error string, what
actually isn't very useful.
In this patch, I rework obj2yaml's error reporting system
for ELF targets to use Error Expected<> classes.
Also, I improve the error message produced
by getSymbol for demonstration of the new functionality.
Differential revision: https://reviews.llvm.org/D64631
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366052
91177308-0d34-0410-b5e6-
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David Green [Mon, 15 Jul 2019 10:44:50 +0000 (10:44 +0000)]
[ARM] Adjust how NEON shifts are lowered
This adjusts the way that we lower NEON shifts to use a DAG target node, not
via a neon intrinsic. This is useful for handling MVE shifts operations in the
same the way. It also renames some of the immediate shift nodes for
consistency, and moves some of the processing of immediate shifts into
LowerShift allowing it to capture more cases.
Differential Revision: https://reviews.llvm.org/D64426
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366051
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Serguei Katkov [Mon, 15 Jul 2019 09:13:11 +0000 (09:13 +0000)]
[Loop Peeling] Fix the bug with IDom setting for exit loops
It is possible that loop exit has two predecessors in a loop body.
In this case after the peeling the iDom of the exit should be a clone of
iDom of original exit but no a clone of a block coming to this exit.
Reviewers: reames, fhahn
Reviewed By: reames
Subscribers: hiraditya, zzheng, llvm-commits
Differential Revision: https://reviews.llvm.org/D64618
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366050
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Florian Hahn [Mon, 15 Jul 2019 08:48:47 +0000 (08:48 +0000)]
[LoopVectorize] Pass unfiltered list of arguments to getIntrinsicInstCost.
We do not compute the scalarization overhead in getVectorIntrinsicCost
and TTI::getIntrinsicInstrCost requires the full arguments list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366049
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Serguei Katkov [Mon, 15 Jul 2019 08:26:45 +0000 (08:26 +0000)]
[Loop Peeling] Enable peeling for loops with multiple exits
This CL enables peeling of the loop with multiple exits where
one exit should be from latch and others are basic blocks with
call to deopt.
The peeling is enabled under the flag which is false by default.
Reviewers: reames, mkuper, iajbar, fhahn
Reviewed By: reames
Subscribers: xbolva00, hiraditya, zzheng, llvm-commits
Differential Revision: https://reviews.llvm.org/D63923
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366048
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Richard Sandiford [Mon, 15 Jul 2019 08:09:21 +0000 (08:09 +0000)]
DeveloperPolicy: fix a typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366046
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Hideto Ueno [Mon, 15 Jul 2019 06:49:04 +0000 (06:49 +0000)]
[Attributor] Deduce "nonnull" attribute
Summary:
Porting nonnull attribute to attributor.
Reviewers: jdoerfert, sstefan1
Reviewed By: jdoerfert
Subscribers: xbolva00, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63604
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366043
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Serguei Katkov [Mon, 15 Jul 2019 06:42:39 +0000 (06:42 +0000)]
[LoopUtils] Extend the scope of getLoopEstimatedTripCount
With this patch the getLoopEstimatedTripCount function will
accept also the loops where there are more than one exit but
all exits except latch block should ends up with a call to deopt.
This side exits should not impact the estimated trip count.
Reviewers: reames, mkuper, danielcdh
Reviewed By: reames
Subscribers: fhahn, lebedev.ri, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D64553
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366042
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Bill Wendling [Mon, 15 Jul 2019 06:35:28 +0000 (06:35 +0000)]
Remove set but unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366041
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Serguei Katkov [Mon, 15 Jul 2019 05:51:10 +0000 (05:51 +0000)]
[LoopInfo] Introduce getUniqueNonLatchExitBlocks utility function
Extract the code from LoopUnrollRuntime into utility function to
re-use it in D63923.
Reviewers: reames, mkuper
Reviewed By: reames
Subscribers: fhahn, hiraditya, zzheng, dmgreen, llvm-commits
Differential Revision: https://reviews.llvm.org/D64548
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366040
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Fangrui Song [Mon, 15 Jul 2019 05:02:32 +0000 (05:02 +0000)]
[PowerPC] Support fp128 libcalls
On PowerPC, IEEE 754 quadruple-precision libcall names use "kf" instead of "tf".
In libgcc, libgcc/config/rs6000/float128-sed converts TF names to KF
names. This patch implements its 24 substitution rules.
Reviewed By: hfinkel
Differential Revision: https://reviews.llvm.org/D64282
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366039
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Yonghong Song [Mon, 15 Jul 2019 04:51:34 +0000 (04:51 +0000)]
[BPF] add unit tests for preserve_{array,union,struct}_access_index intrinsics
This is a followup patch for https://reviews.llvm.org/D61810/new/,
which adds new intrinsics preserve_{array,union,struct}_access_index.
Currently, only BPF backend utilizes preserve_{array,union,struct}_access_index
intrinsics, so all tests are compiled with BPF target.
https://reviews.llvm.org/D61524 already added some tests for these
intrinsics, but some of them pretty complex.
This patch added a few unit test cases focusing on individual intrinsic
functions.
Also made a few clarification on language reference for these intrinsics.
Differential Revision: https://reviews.llvm.org/D64606
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366038
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Kang Zhang [Mon, 15 Jul 2019 03:55:10 +0000 (03:55 +0000)]
[NFC][PowerPC] Add the test block-placement.mir
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366037
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Johannes Doerfert [Mon, 15 Jul 2019 03:24:35 +0000 (03:24 +0000)]
[ValueTracking] Look through constant Int2Ptr/Ptr2Int expressions
Summary:
This is analogous to the int2ptr/ptr2int instruction handling introduced
in D54956.
Reviewers: fhahn, efriedma, spatel, nlopes, sanjoy, lebedev.ri
Subscribers: hiraditya, bollu, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64708
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366036
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Craig Topper [Mon, 15 Jul 2019 02:02:31 +0000 (02:02 +0000)]
[X86] Separate the memory size of vzext_load/vextract_store from the element size of the result type. Use them improve the codegen of v2f32 loads/stores with sse1 only.
Summary:
SSE1 only supports v4f32. But does have instructions like movlps/movhps that load/store 64-bits of memory.
This patch breaks the connection between the node VT of the vzext_load/vextract_store patterns and the memory VT. Enabling a v4f32 node with a 64-bit memory VT. I've used i64 as the memory VT here. I've written the PatFrag predicate to just check the store size not the specific VT. I think the VT will only matter for CSE purposes. We could use v2f32, but if we want to start using these operations in more places a simple integer type might make the most sense.
I'd like to maybe use this same thing for SSE2 and later as well, but that will need more work to be supported by EltsFromConsecutiveLoads to avoid regressing lit tests. I'd maybe also like to combine bitcasts with these load/stores nodes now that the types are disconnected. And I'd also like to consider canonicalizing (scalar_to_vector + load) to vzext_load.
If you want I can split the mechanical tablegen stuff where I added the 32/64 off from the sse1 change.
Reviewers: spatel, RKSimon
Reviewed By: RKSimon
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64528
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366034
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Alexandros Lamprineas [Sun, 14 Jul 2019 20:31:15 +0000 (20:31 +0000)]
[TargetParser][ARM] Account dependencies when processing target features
Teaches ARM::appendArchExtFeatures to account dependencies when processing
target features: i.e. when you say -march=armv8.1-m.main+mve.fp+nofp it
means mve.fp should get discarded too. (Split from D63936)
Differential Revision: https://reviews.llvm.org/D64048
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366031
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Florian Hahn [Sun, 14 Jul 2019 20:12:36 +0000 (20:12 +0000)]
[LV] Exclude loop-invariant inputs from scalar cost computation.
Loop invariant operands do not need to be scalarized, as we are using
the values outside the loop. We should ignore them when computing the
scalarization overhead.
Fixes PR41294
Reviewers: hsaito, rengolin, dcaballe, Ayal
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D59995
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366030
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Alexandros Lamprineas [Sun, 14 Jul 2019 18:32:42 +0000 (18:32 +0000)]
[clang][Driver][ARM] Favor -mfpu over default CPU features
When processing the command line options march, mcpu and mfpu, we store
the implied target features on a vector. The change D62998 introduced a
temporary vector, where the processed features get accumulated. When
calling DecodeARMFeaturesFromCPU, which sets the default features for
the specified CPU, we certainly don't want to override the features
that have been explicitly specified on the command line. Therefore, the
default features should appear first in the final vector. This problem
became evident once I added the missing (unhandled) target features in
ARM::getExtensionFeatures.
Differential Revision: https://reviews.llvm.org/D63936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366027
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Johannes Doerfert [Sun, 14 Jul 2019 18:24:19 +0000 (18:24 +0000)]
[GitSVN][NFC] Mark dry-run commits as such in the log output
Summary: This helps to avoid worries about the "dry run flag" while testing.
Reviewers: jyknight, rnk, mehdi_amini
Subscribers: bollu, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366023
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Nikita Popov [Sun, 14 Jul 2019 15:55:32 +0000 (15:55 +0000)]
[InstCombine] Add assume context test; NFC
Baseline test for D37215.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366021
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Simon Pilgrim [Sun, 14 Jul 2019 15:05:05 +0000 (15:05 +0000)]
[Hashing] hash_1to3_bytes - avoid trunc(v + zext(x)) NFCI.
MSVC complains about the extension to uint64_t for an addition followed by truncation back to uint32_t - add an explicit uint32_t cast to avoid this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366020
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Sanjay Patel [Sun, 14 Jul 2019 14:08:39 +0000 (14:08 +0000)]
[x86] add test for sub-with-flags opportunity (PR40483); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366019
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Florian Hahn [Sun, 14 Jul 2019 14:06:25 +0000 (14:06 +0000)]
Recommit "[BitcodeReader] Validate OpNum, before accessing Record array."
This recommits r365750 (git commit
8b222ecf2769ee133691f208f6166ce118c4a164)
Original message:
Currently invalid bitcode files can cause a crash, when OpNum exceeds
the number of elements in Record, like in the attached bitcode file.
The test case was generated by clusterfuzz: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=15698
Reviewers: t.p.northover, thegameg, jfb
Reviewed By: jfb
Differential Revision: https://reviews.llvm.org/D64507
llvm-svn: 365750jkkkk
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366018
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Florian Hahn [Sun, 14 Jul 2019 12:35:50 +0000 (12:35 +0000)]
[BitcodeReader] Use tighter upper bound to validate forward references.
At the moment, bitcode files with invalid forward reference can easily
cause the bitcode reader to run out of memory, by creating a forward
reference with a very high index.
We can use the size of the bitcode file as an upper bound, because a
valid bitcode file can never contain more records. This should be
sufficient to fail early in most cases. The only exception is large
files with invalid forward references close to the file size.
There are a couple of clusterfuzz runs that fail with out-of-memory
because of very high forward references and they should be fixed by this
patch.
A concrete example for this is D64507, which causes out-of-memory on
systems with low memory, like the hexagon upstream bots.
Reviewers: t.p.northover, thegameg, jfb, efriedma, hfinkel
Reviewed By: jfb
Differential Revision: https://reviews.llvm.org/D64577
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366017
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Simon Pilgrim [Sun, 14 Jul 2019 11:47:36 +0000 (11:47 +0000)]
VirtRegMap - add missing initializers. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366016
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Simon Pilgrim [Sun, 14 Jul 2019 11:41:52 +0000 (11:41 +0000)]
SlotIndexes - add missing initializer. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366015
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Simon Pilgrim [Sun, 14 Jul 2019 11:10:04 +0000 (11:10 +0000)]
[MachineOutliner] Add missing initializers for OutlinedFunction. NFCI.
Appeases MSVC/cppcheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366014
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Craig Topper [Sun, 14 Jul 2019 04:13:33 +0000 (04:13 +0000)]
[X86] Remove offset of 8 from the call to FuseInst for UNPCKLPDrr folding added in r365287.
This was copy/pasted from above and I forgot to change it. We just
need the default offset of 0 here.
Fixes PR42616.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366011
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Johannes Doerfert [Sat, 13 Jul 2019 17:01:00 +0000 (17:01 +0000)]
[Attributor][Fix] Never override given argument numbers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366009
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David Green [Sat, 13 Jul 2019 15:43:00 +0000 (15:43 +0000)]
[ARM] Add sign and zero extend patterns for MVE
The vmovlb instructions can be uses to sign or zero extend vector registers
between types. This adds some patterns for them and relevant testing. The
VBICIMM generation is also put behind a hasNEON check (as is already done for
VORRIMM).
Code originally by David Sherwood.
Differential Revision: https://reviews.llvm.org/D64069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366008
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David Green [Sat, 13 Jul 2019 15:26:51 +0000 (15:26 +0000)]
[ARM] MVE VNEG instruction patterns
This selects integer VNEG instructions, which can be especially useful with shifts.
Differential Revision: https://reviews.llvm.org/D64204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366006
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David Green [Sat, 13 Jul 2019 14:58:32 +0000 (14:58 +0000)]
[ARM] MVE integer abs
Similar to floating point abs, we also have instructions for integers.
Differential Revision: https://reviews.llvm.org/D64027
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366005
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David Green [Sat, 13 Jul 2019 14:48:54 +0000 (14:48 +0000)]
[ARM] MVE integer min and max
This simply makes the MVE integer min and max instructions legal and adds the
relevant patterns for them.
Differential Revision: https://reviews.llvm.org/D64026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366004
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David Green [Sat, 13 Jul 2019 14:38:53 +0000 (14:38 +0000)]
[ARM] MVE VRINT support
This adds support for the floor/ceil/trunc/... series of instructions,
converting to various forms of VRINT. They use the same suffixes as their
floating point counterparts. There is not VTINTR, so nearbyint is expanded.
Also added a copysign test, to show it is expanded.
Differential Revision: https://reviews.llvm.org/D63985
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366003
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David Green [Sat, 13 Jul 2019 14:29:02 +0000 (14:29 +0000)]
[ARM] MVE minnm and maxnm instructions
This adds the patterns for minnm and maxnm from the fminnum and fmaxnum nodes,
similar to scalar types.
Original patch by Simon Tatham
Differential Revision: https://reviews.llvm.org/D63870
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366002
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Thomas Preud'homme [Sat, 13 Jul 2019 13:24:30 +0000 (13:24 +0000)]
FileCheck [7/12]: Arbitrary long numeric expressions
Summary:
This patch is part of a patch series to add support for FileCheck
numeric expressions. This specific patch extend numeric expression to
support an arbitrary number of operands, either variable or literals.
Copyright:
- Linaro (changes up to diff 183612 of revision D55940)
- GraphCore (changes in later versions of revision D55940 and
in new revision created off D55940)
Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk
Subscribers: hiraditya, llvm-commits, probinson, dblaikie, grimar, arichardson, tra, rnk, kristina, hfinkel, rogfer01, JonChesterfield
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366001
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Sanjay Patel [Sat, 13 Jul 2019 13:16:46 +0000 (13:16 +0000)]
Revert "[InstCombine] add tests for umin/umax via usub.sat; NFC"
This reverts commit rL365999 /
0f6148df23edcd3081f5e761de19edd4f823f16d.
The tests already exist in this file, and the hoped-for transform
(mentioned in D62871) is invalid because of undef as discussed in
D63060.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366000
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Sanjay Patel [Sat, 13 Jul 2019 12:54:48 +0000 (12:54 +0000)]
[InstCombine] add tests for umin/umax via usub.sat; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365999
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Sanjay Patel [Sat, 13 Jul 2019 12:04:52 +0000 (12:04 +0000)]
[x86] simplify cmov with same true/false operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365998
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Fangrui Song [Sat, 13 Jul 2019 09:28:33 +0000 (09:28 +0000)]
[Object] isNotObjectErrorInvalidFileType: simplify
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365997
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Fangrui Song [Sat, 13 Jul 2019 09:23:35 +0000 (09:23 +0000)]
[Object] isNotObjectErrorInvalidFileType: fix use-after-move
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365996
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Johannes Doerfert [Sat, 13 Jul 2019 01:09:27 +0000 (01:09 +0000)]
[Attributor][NFC] Run clang-format on the attributor files (.h/.cpp)
The Attributor files are kept formatted with clang-format, we should try
to keep this state.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365984
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Johannes Doerfert [Sat, 13 Jul 2019 01:09:21 +0000 (01:09 +0000)]
[Attributor] Only return attributes with a valid state
Attributor::getAAFor will now only return AbstractAttributes with a
valid AbstractState. This simplifies call sites as they only need to
check if the returned pointer is non-null. It also reduces the potential
for accidental misuse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365983
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Evgeniy Stepanov [Sat, 13 Jul 2019 00:29:03 +0000 (00:29 +0000)]
Extend function attributes bitset size from 64 to 96.
Summary: We are going to add a function attribute number 64.
Reviewers: pcc, jdoerfert, lebedev.ri
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365980
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Johannes Doerfert [Sat, 13 Jul 2019 00:09:27 +0000 (00:09 +0000)]
[Attributor][FIX] Lookup of (call site) argument attributes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365977
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Nico Weber [Fri, 12 Jul 2019 23:30:55 +0000 (23:30 +0000)]
PDB HashTable: Move TraitsT from class parameter to the methods that need it
The traits object is only used by a few methods. Deserializing a hash
table and walking it is possible without the traits object, so it
shouldn't be required to build a dummy object for that use case.
The TraitsT object used to be a function template parameter before
r327647, this restores it to that state.
This makes it clear that the traits object isn't needed at all in 1 of
the current 3 uses of HashTable (and I am going to add another use that
doesn't need it), and that the default PdbHashTraits isn't used outside
of tests.
While here, also re-enable 3 checks in the test that were commented out
(which requires making HashTableInternals templated and giving FooBar
an operator==).
No intended behavior change.
Differential Revision: https://reviews.llvm.org/D64640
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365974
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