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Adrian Prantl [Mon, 23 Apr 2018 16:08:01 +0000 (16:08 +0000)]
Fix computeSymbolSizes SEGFAULT on invalid file
We use llvm-symbolizer in some production systems, and we run it
against all possibly related files, including some that are not
ELF. We noticed that for some of those invalid files, llvm-symbolizer
would crash with SEGFAULT. Here is an example of such a file.
It is due to that in computeSymbolSizes, a loop uses condition
for (unsigned I = 0, N = Addresses.size() - 1; I < N; ++I) {
where if Addresses.size() is 0, N would overflow and causing the loop
to access invalid memory.
Instead of patching the loop conditions, the commit makes so that the
function returns early if Addresses is empty.
Validated by checking that llvm-symbolizer no longer crashes.
Patch by Teng Qin!
Differential Revision: https://reviews.llvm.org/D44285
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330610
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Matt Arsenault [Mon, 23 Apr 2018 15:51:26 +0000 (15:51 +0000)]
AMDGPU: Assign enum name to stack ID
Also assert that it is correct for SGPRs. There is currently a bug
where stack slot coloring replaces SGPR spill FIs with one with
the default ID, which results in a more confusing assert later
about a dead object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330607
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Matt Arsenault [Mon, 23 Apr 2018 15:51:21 +0000 (15:51 +0000)]
StackSlotColoring: Fix missing skipFunction check
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330606
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Daniel Neilson [Mon, 23 Apr 2018 15:40:37 +0000 (15:40 +0000)]
[SelectionDAG] Refactor lowering of atomic memory intrinsics.
Summary:
This just refactors the lowering of the atomic memory intrinsics to more
closely match the code patterns used in the lowering of the non-atomic
memory intrinsics. Specifically, we encapsulate the lowering in
SelectionDAG::getAtomicMem*() functions rather than embedding
the code directly in the SelectionDAGBuilder code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330603
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Robert Widmann [Mon, 23 Apr 2018 14:29:33 +0000 (14:29 +0000)]
[LLVM-C] DIBuilderBindings for Subrange and Arrays
Summary: Move Go bindings for subranges and DINode arrays.
Reviewers: harlanhaskins, whitequark, deadalnix
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45933
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330594
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Nico Weber [Mon, 23 Apr 2018 14:28:49 +0000 (14:28 +0000)]
Sort a target list a bit better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330593
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Alexey Bataev [Mon, 23 Apr 2018 14:00:53 +0000 (14:00 +0000)]
[DEBUGINFO, NVPTX] Add the test for the debug info of the local
variables, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330592
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Robert Widmann [Mon, 23 Apr 2018 13:51:43 +0000 (13:51 +0000)]
[LLVM-C] Finish Up Scope Bindings
Summary: Adds bindings for Module and NameSpace scopes and LLVMDIBuilderCreateForwardDecl, a counterpart to LLVMDIBuilderCreateReplaceableCompositeType.
Reviewers: harlanhaskins, whitequark, deadalnix
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45934
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330591
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Marianne Mailhot-Sarrasin [Mon, 23 Apr 2018 13:45:28 +0000 (13:45 +0000)]
[doc] Removed obsolete -count-aa from AliasAnalysis documentation
Summary:
This patch removes references to AliasAnalysisCounter pass from the AliasAnalysis documentation. That pass have been eliminated in 2015, at revision trunk@247167.
Reviewed By: hfinkel
Differential Revision: https://reviews.llvm.org/D45876
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330590
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Simon Pilgrim [Mon, 23 Apr 2018 13:24:17 +0000 (13:24 +0000)]
[X86] Remove instregex matching from CLAC/STAC.
Note - noticed this as the STAC case as it was unintentionally matching against *STACK* pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330588
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Nico Weber [Mon, 23 Apr 2018 13:11:51 +0000 (13:11 +0000)]
List cpp file only once (was added in 147117 and 147117 as build fix each).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330587
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Nicolai Haehnle [Mon, 23 Apr 2018 13:06:03 +0000 (13:06 +0000)]
AMDGPU: Fix SDWA peephole for V_AND_B32
Summary:
Found by inspection. We care about the operand that *doesn't*
contain the immediate.
I believe this is currently not hit because we fold 0xff / 0xffff
immediates only later.
Change-Id: Ic3cf8538bc7da5eff3200d96eccf9d339e6345a7
Reviewers: arsenm, rampitec
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45886
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330586
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Nicolai Haehnle [Mon, 23 Apr 2018 13:05:50 +0000 (13:05 +0000)]
AMDGPU: Fix a corner case crash in SIOptimizeExecMasking
Summary:
See the new test case; this is really unlikely to happen with real code,
but I ran into this while attempting to bugpoint-reduce a different issue.
Change-Id: I9ade1dc1aa8fd9c4d9fc83661d7b80e310b5c4a6
Reviewers: arsenm, rampitec
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45885
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330585
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Nico Weber [Mon, 23 Apr 2018 12:49:34 +0000 (12:49 +0000)]
Consistently sort add_subdirectory calls in lib/Target/*/CMakeLists.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330584
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Sander de Smalen [Mon, 23 Apr 2018 12:43:19 +0000 (12:43 +0000)]
[AArch64][SVE] Asm: Support for contiguous, non-faulting LDNF1 (scalar+imm) load instructions
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330583
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Max Kazantsev [Mon, 23 Apr 2018 12:33:31 +0000 (12:33 +0000)]
[LoopRotate] Fix incorrect SCEV invalidation in loop rotation
LoopRotate only invalidates innermost loops while the changes that it makes may
also affert any of this parents. With patch rL329047, SCEV becomes much smarter
about calculation of exit counts for outer loops, so we cannot assume that they are
not affected.
Differential Revision: https://reviews.llvm.org/D45945
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330582
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Simon Pilgrim [Mon, 23 Apr 2018 11:57:15 +0000 (11:57 +0000)]
[X86] Remove unnecessary MMX reg-mem InstRW scheduler overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330581
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Max Kazantsev [Mon, 23 Apr 2018 10:39:38 +0000 (10:39 +0000)]
[LoopUnroll] Fix potentially incorrect SCEV invalidation in UnrollRuntime
Current runtime unrolling invalidates parent loop saying that it might have changed
after the inner loop has changed, but it doesn't bother to do the same to its parents.
With patch rL329047, SCEV becomes much smarter about calculation of exit counts for
outer loops. We might need to invalidate not only the immediate parent, but also
any of its parents as well.
There is no clear evidence that there is some miscompile happening because of this
(at least I don't have such test), but the common sense says that the current code
is wrong.
Differential Revision: https://reviews.llvm.org/D45940
Reviewed By: chandlerc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330577
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Max Kazantsev [Mon, 23 Apr 2018 10:32:37 +0000 (10:32 +0000)]
[LoopSimplify] Fix incorrect SCEV invalidation
In the function `simplifyOneLoop` we optimistically assume that changes in the
inner loop only affect this very loop and have no impact on its parents. In fact,
after rL329047 has been merged, we can now calculate exit counts for outer
loops which may depend on inner loops. Thus, we need to invalidate all parents
when we do something to a loop.
There is an evidence of incorrect behavior of `simplifyOneLoop`: when we insert
`SE->verify()` check in the end of this funciton, it fails on a bunch of existing
test, in particular:
LLVM :: Transforms/LoopUnroll/peel-loop-not-forced.ll
LLVM :: Transforms/LoopUnroll/peel-loop-pgo.ll
LLVM :: Transforms/LoopUnroll/peel-loop.ll
LLVM :: Transforms/LoopUnroll/peel-loop2.ll
Note that previously we have fixed issues of this variety, see rL328483.
This patch makes this function invalidate the outermost loop properly.
Differential Revision: https://reviews.llvm.org/D45937
Reviewed By: chandlerc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330576
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Simon Tatham [Mon, 23 Apr 2018 09:15:47 +0000 (09:15 +0000)]
Fix BNF nits in TableGen language reference.
Summary:
In the course of writing an experimental ANTLR grammar based on this
document, I found three errors in the documented BNF:
SimpleValues of dag type are allowed to have no operands at all after
the initial DagArg specifying the operator. For example, the value
(outs) is extremely common in backends; an example in the test suite
is test/TableGen/AsmVariant.td line 30. But the BNF doesn't allow
DagArgList to expand to the empty string (it must contain at least one
DagArg), and therefore the DagArgList specifying the operands in the
dag-shaped production for SimpleValue should be optional.
In the production for BodyItem with a 'let' and an optional RangeList,
the RangeList should have braces around it if it's present, matching
code such as "let E{7-0} = ..." on test/TableGen/BitsInit.td line 42.
Those braces aren't included in the RangeList nonterminal itself, so
instead they need to be part of the optional segment of the BodyItem
production.
Finally, the identifier after 'defm' should be optional. Again, this
is very common in the real back end .td files; an example in the test
suite is in test/TableGen/defmclass.td line 49.
Reviewers: rengolin, nhaehnle, stoklund
Reviewed By: nhaehnle
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45818
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330570
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Simon Tatham [Mon, 23 Apr 2018 08:41:53 +0000 (08:41 +0000)]
Test commit access.
Should be a harmless trimming of trailing whitespace from a
documentation file.
(There are other instances of trailing whitespace in this file alone.
I've only fixed one of them, on the basis that that way the rest are
still available for other people's commit-access tests :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330567
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Sander de Smalen [Mon, 23 Apr 2018 07:50:35 +0000 (07:50 +0000)]
[AArch64][SVE] Asm: Support for structured ST2, ST3 and ST4 (scalar+imm) store instructions.
Reviewers: fhahn, rengolin, javed.absar, SjoerdMeijer, t.p.northover, echristo, evandro, huntergr
Reviewed By: rengolin
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45681
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330565
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Chandler Carruth [Mon, 23 Apr 2018 06:58:36 +0000 (06:58 +0000)]
[PM/LoopUnswitch] Remove a buggy assert in the new loop unswitch.
The condition this was asserting doesn't actually hold. I've added
comments to explain why, removed the assert, and added a fun test case
reduced out of 403.gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330564
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Craig Topper [Mon, 23 Apr 2018 04:50:01 +0000 (04:50 +0000)]
[X86] Add VEX_WIG to VEX encoded version of VCMPPSY/VCMPPDY.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330563
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Chandler Carruth [Mon, 23 Apr 2018 00:48:42 +0000 (00:48 +0000)]
[PM/LoopUnswitch] Fix comment typo. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330560
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Simon Pilgrim [Sun, 22 Apr 2018 21:37:08 +0000 (21:37 +0000)]
[X86][Znver1] Remove unnecessary BMI1 ANDN InstRW overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330558
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Simon Pilgrim [Sun, 22 Apr 2018 20:42:24 +0000 (20:42 +0000)]
[llvm-mca][X86] Add BMI/LZCNT/POPCNT resource tests to all relevant models
The SandyBridge BMI tests are actually run on IvyBridge as that's the first lowest CPU that actually support the ISAs (but still use the SandyBridge model).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330556
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Robert Widmann [Sun, 22 Apr 2018 19:24:44 +0000 (19:24 +0000)]
[LLVM-C] Add DIBuilder Bindings For Variable Creation
Summary: Wrap LLVMDIBuilderCreateAutoVariable, LLVMDIBuilderCreateParameterVariable, LLVMDIBuilderCreateExpression, and move and correct LLVMDIBuilderInsertDeclareBefore and LLVMDIBuilderInsertDeclareAtEnd from the Go bindings to the C bindings.
Reviewers: harlanhaskins, whitequark, deadalnix
Reviewed By: harlanhaskins, whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45928
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330555
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Simon Pilgrim [Sun, 22 Apr 2018 18:35:53 +0000 (18:35 +0000)]
[X86] Remove unnecessary WriteFBlend/WriteBlend InstRW overrides.
Fixed a lot of the default classes which were being completely overridden.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330554
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Simon Pilgrim [Sun, 22 Apr 2018 18:09:50 +0000 (18:09 +0000)]
[X86] Remove unnecessary WriteFMul/WriteFRcp/WriteFRsqrt InstRW overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330553
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Simon Pilgrim [Sun, 22 Apr 2018 17:54:58 +0000 (17:54 +0000)]
[X86] Remove unnecessary CVT instrw overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330552
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Andres Freund [Sun, 22 Apr 2018 17:53:34 +0000 (17:53 +0000)]
Test commit access.
Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330551
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Sanjay Patel [Sun, 22 Apr 2018 17:07:44 +0000 (17:07 +0000)]
[PatternMatch] allow undef elements when matching a vector zero
This is the last step in getting constant pattern matchers to allow
undef elements in constant vectors.
I'm adding a dedicated m_ZeroInt() function and building m_Zero() from
that. In most cases, calling code can be updated to use m_ZeroInt()
directly when there's no need to match pointers, but I'm leaving that
efficiency optimization as a follow-up step because it's not always
clear when that's ok.
There are just enough icmp folds in InstSimplify that can be used for
integer or pointer types, that we probably still want a generic m_Zero()
for those cases. Otherwise, we could eliminate it (and possibly add a
m_NullPtr() as an alias for isa<ConstantPointerNull>()).
We're conservatively returning a full zero vector (zeroinitializer) in
InstSimplify/InstCombine on some of these folds (see diffs in InstSimplify),
but I'm not sure if that's actually necessary in all cases. We may be
able to propagate an undef lane instead. One test where this happens is
marked with 'TODO'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330550
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Simon Pilgrim [Sun, 22 Apr 2018 16:51:12 +0000 (16:51 +0000)]
[X86][SkylakeServer] Remove unnecessary PMULLD instrw overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330549
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Simon Pilgrim [Sun, 22 Apr 2018 16:49:35 +0000 (16:49 +0000)]
[X86][Atom] Remove unnecessary scalar/vector load/move instrw overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330548
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Sanjay Patel [Sun, 22 Apr 2018 15:59:14 +0000 (15:59 +0000)]
[InstCombine] add vector test with undef elts; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330547
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Simon Pilgrim [Sun, 22 Apr 2018 15:25:59 +0000 (15:25 +0000)]
[X86] Fix (completely overridden) WriteFHAdd/WritePHAdd classes to allow us to remove unnecessary instrw overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330546
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Simon Pilgrim [Sun, 22 Apr 2018 15:02:23 +0000 (15:02 +0000)]
[X86][MMX][SSE] Tag missed PHADD/PHSUB instructions with WritePHAdd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330545
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Simon Pilgrim [Sun, 22 Apr 2018 14:43:12 +0000 (14:43 +0000)]
[X86] Remove unnecessary WriteFVarBlend/WriteVarBlend InstRW overrides.
This also fixes some of the ReadAfterLd issues due to InstRW.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330544
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Sanjay Patel [Sun, 22 Apr 2018 14:19:37 +0000 (14:19 +0000)]
[InstSimplify, InstCombine] add vector tests with undef elts; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330543
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Simon Pilgrim [Sun, 22 Apr 2018 10:39:16 +0000 (10:39 +0000)]
[X86] Fix WriteMPSAD/WritePSADBW values to allow us to remove unnecessary instrw overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330542
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Simon Pilgrim [Sun, 22 Apr 2018 10:03:52 +0000 (10:03 +0000)]
[X86][SandyBridge] Remove unnecessary WritePOPCNTLd overrides by fixing load latency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330541
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Simon Pilgrim [Sun, 22 Apr 2018 09:58:00 +0000 (09:58 +0000)]
[llvm-mca][X86] Add POPCNT resource test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330540
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Jonas Devlieghere [Sun, 22 Apr 2018 08:46:27 +0000 (08:46 +0000)]
[test] Fix MC/ELF/nocompression.s
Unbreak the linux build bots:
http://lab.llvm.org:8011/builders/clang-lld-x86_64-2stage/builds/5165/
http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/28775
http://lab.llvm.org:8011/builders/clang-with-lto-ubuntu/builds/8227
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330539
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Jonas Devlieghere [Sun, 22 Apr 2018 08:35:00 +0000 (08:35 +0000)]
[lli] Fix syntax error: missing ';'
Fixes build issue on the windows bots:
error C2143: syntax error: missing ';'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330538
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Jonas Devlieghere [Sun, 22 Apr 2018 08:02:11 +0000 (08:02 +0000)]
[lli] Make error handling more consistent.
Makes error handling more consistent by using the helpers in support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330537
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Jonas Devlieghere [Sun, 22 Apr 2018 08:01:35 +0000 (08:01 +0000)]
[llvm-mc] Make error handling more consistent.
Makes error handling more consistent by using the helpers in support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330536
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Jonas Devlieghere [Sun, 22 Apr 2018 08:01:01 +0000 (08:01 +0000)]
[Support] Fix prefix logic in WithColor.
When a prefix is passed, we need to print a colon a space after it, not
just the prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330535
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Craig Topper [Sun, 22 Apr 2018 06:40:37 +0000 (06:40 +0000)]
[X86] Remove an unnecessary HANDLE_OPTIONAL line from the disassembler operand processing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330534
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Craig Topper [Sun, 22 Apr 2018 03:15:02 +0000 (03:15 +0000)]
[X86] Change TB to PS on LFENCE instruction.
This matches the other FENCE instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330533
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Craig Topper [Sun, 22 Apr 2018 01:24:58 +0000 (01:24 +0000)]
[X86] Remove OpSizeIgnore, it's not implemented any differently than OpSizeFixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330532
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Craig Topper [Sun, 22 Apr 2018 00:52:02 +0000 (00:52 +0000)]
[X86] Remove DATA32_PREFIX. Hack the printing for DATA16_PREFIX to print 'data32' in 16-bit mode. Hack the asm parser to convert 'data32' to 'data16' in 16-bit mode.
Improve the error messages to match GNU assembler.
This also allows us to remove the hack from the disassembler table building.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330531
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Brian Gesiak [Sat, 21 Apr 2018 23:52:04 +0000 (23:52 +0000)]
[bcanalyzer] Recognize more stream types
Summary:
`llvm-bcanalyzer` prints out the stream type of the file it is
analyzing. If the file begins with the LLVM IR magic number, it reports
a stream type of "LLVM IR". However, any other bitstream format is
reported as "unknown".
Add some checks for two other common bitstream formats: Clang AST
files, which begin with 'CPCH', and Clang serialized diagnostics, which
begin with 'DIAG'.
Test Plan: `check-llvm`
Reviewers: pcc, aprantl, mehdi_amini, davide, george.karpenkov, JDevlieghere
Reviewed By: JDevlieghere
Subscribers: JDevlieghere, bruno, davide, llvm-commits
Differential Revision: https://reviews.llvm.org/D41979
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330529
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Simon Pilgrim [Sat, 21 Apr 2018 21:59:36 +0000 (21:59 +0000)]
[X86] Strip unnecessary prefetch + vector move/load instrw overrides from scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330527
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Jonas Devlieghere [Sat, 21 Apr 2018 21:36:11 +0000 (21:36 +0000)]
[Support] Add optional prefix to convenience helpers in WithColor.
Several tools prefix the error/warning/note output with the name of the
tool. One such tool is LLD for example. This commit adds as an optional
'Prefix' argument to the convenience helpers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330526
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Simon Pilgrim [Sat, 21 Apr 2018 21:16:44 +0000 (21:16 +0000)]
[X86] Strip unnecessary WriteCvtF2I instrw overrides from scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330525
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Jonas Devlieghere [Sat, 21 Apr 2018 21:11:59 +0000 (21:11 +0000)]
[tools] Use WithColor for printing errors.
Use convenience helpers in WithColor to print errors, warnings and notes
in a few more tools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330524
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Simon Pilgrim [Sat, 21 Apr 2018 20:45:12 +0000 (20:45 +0000)]
[X86] Strip unnecessary broadcast/shuffle256 instrw overrides from scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330523
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Simon Pilgrim [Sat, 21 Apr 2018 20:04:24 +0000 (20:04 +0000)]
[X86][AVX] VPERM2F128/VINSERTF128 should be a shuffle256 schedule like VPERM2I128/VINSERTI128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330522
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Simon Pilgrim [Sat, 21 Apr 2018 19:11:55 +0000 (19:11 +0000)]
[X86] Strip unnecessary vector integer math, shift-imm, extend, shuffle, pack/unpack instruction instrw overrides from scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330521
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Craig Topper [Sat, 21 Apr 2018 18:39:21 +0000 (18:39 +0000)]
[X86] Add DAG combine to turn (trunc (srl (mul ext, ext), 16) into PMULHW/PMULHUW.
Ultimately I want to use this to remove the intrinsics for these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330520
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Craig Topper [Sat, 21 Apr 2018 18:39:20 +0000 (18:39 +0000)]
[X86] Add test cases that show the current codegen for (trunc (srl (mul ext, ext), 16)). NFC
A future patch will turn this into MULHU/MULHS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330519
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Craig Topper [Sat, 21 Apr 2018 18:07:36 +0000 (18:07 +0000)]
[X86] Add SchedWrites for LDMXCSR/STMXCSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330517
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Sanjay Patel [Sat, 21 Apr 2018 16:58:00 +0000 (16:58 +0000)]
[InstSimplify] move tests for shifts; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330516
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Sanjay Patel [Sat, 21 Apr 2018 16:23:47 +0000 (16:23 +0000)]
[InstSimplify] move/add/regenerate checks for tests; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330515
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Simon Pilgrim [Sat, 21 Apr 2018 16:20:28 +0000 (16:20 +0000)]
[X86][Haswell] Strip unnecessary WriteFAdd/WriteFHAdd instruction instrw overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330514
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Simon Pilgrim [Sat, 21 Apr 2018 16:17:47 +0000 (16:17 +0000)]
[X86][Broadwell] Remove unnecessary VORPD/VORPS instrw override - missed in D45629
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330513
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Simon Pilgrim [Sat, 21 Apr 2018 16:12:42 +0000 (16:12 +0000)]
[llvm-mca][X86] Add AVX2 resource tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330512
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Simon Pilgrim [Sat, 21 Apr 2018 15:16:59 +0000 (15:16 +0000)]
[X86] Strip unnecessary WriteFRcp/WriteFRsqrt instruction instrw overrides from scheduler models.
The required the default skylake schedules to be updated - these were being completely overriden by the InstRW and the existing values not used at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330510
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Simon Pilgrim [Sat, 21 Apr 2018 14:56:56 +0000 (14:56 +0000)]
[X86] Strip unnecessary WriteFShuffle instruction instrw overrides from scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330508
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Simon Pilgrim [Sat, 21 Apr 2018 14:16:57 +0000 (14:16 +0000)]
[llvm-mca][X86] Add SSE resource tests to all models
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330506
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Simon Pilgrim [Sat, 21 Apr 2018 14:03:40 +0000 (14:03 +0000)]
[X86][SandyBridge] Strip unnecessary MOVQ/CVT instruction instrw overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330505
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Simon Pilgrim [Sat, 21 Apr 2018 12:15:42 +0000 (12:15 +0000)]
[X86] Strip unnecessary MMX instruction instrw overrides from scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330503
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Simon Pilgrim [Sat, 21 Apr 2018 11:28:59 +0000 (11:28 +0000)]
[llvm-mca][X86] Add MMX resource tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330502
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Simon Pilgrim [Sat, 21 Apr 2018 11:25:02 +0000 (11:25 +0000)]
[X86] Strip unnecessary x87 instruction instrw overrides from scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330501
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Simon Pilgrim [Sat, 21 Apr 2018 10:36:19 +0000 (10:36 +0000)]
[llvm-mca][X86] Add X87 resource tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330499
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Simon Pilgrim [Sat, 21 Apr 2018 10:35:04 +0000 (10:35 +0000)]
[X86][X87] Add missing fldlg2 schedule test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330498
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Hiroshi Inoue [Sat, 21 Apr 2018 09:32:17 +0000 (09:32 +0000)]
[PowerPC] fix incorrect vectorization of abs() on POWER9
Vectorized loops with abs() returns incorrect results on POWER9. This patch fixes it.
For example the following code returns negative result if input values are negative though it sums up the absolute value of the inputs.
int vpx_satd_c(const int16_t *coeff, int length) {
int satd = 0;
for (int i = 0; i < length; ++i) satd += abs(coeff[i]);
return satd;
}
This problem causes test failures for libvpx.
For vector absolute and vector absolute difference on POWER9, LLVM generates VABSDUW (Vector Absolute Difference Unsigned Word) instruction or variants.
Since these instructions are for unsigned integers, we need adjustment for signed integers.
For abs(sub(a, b)), we generate VABSDUW(a+0x80000000, b+0x80000000). Otherwise, abs(sub(-1, 0)) returns 0xFFFFFFFF(=-1) instead of 1. For abs(a), we generate VABSDUW(a+0x80000000, 0x80000000).
Differential Revision: https://reviews.llvm.org/D45522
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330497
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Eli Friedman [Sat, 21 Apr 2018 00:07:46 +0000 (00:07 +0000)]
[AArch64] Don't crash trying to resolve __stack_chk_guard.
In certain cases, the compiler might try to merge __stack_chk_guard with
another global variable. (Or someone could theoretically define
__stack_chk_guard as an alias.) In that case, make sure we don't crash.
Differential Revision: https://reviews.llvm.org/D45746
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330495
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Jessica Paquette [Fri, 20 Apr 2018 23:37:48 +0000 (23:37 +0000)]
Fix typo in test (verify-machine-instrs -> verify-machineinstrs)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330494
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Jessica Paquette [Fri, 20 Apr 2018 23:35:54 +0000 (23:35 +0000)]
[MachineOutliner] XFAIL machine-outliner-noredzone.ll
The verifier began complaining about an undefined physical register in this
test. XFAILing for the purposes of getting a bot up while I look into it.
Failure:
http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-expensive/11385/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330493
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Shoaib Meenai [Fri, 20 Apr 2018 22:14:45 +0000 (22:14 +0000)]
[ObjCARC] Take BlockColors by const reference. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330489
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Shoaib Meenai [Fri, 20 Apr 2018 22:11:03 +0000 (22:11 +0000)]
[ObjCARC] Account for funclet token in storeStrong transform
When creating a call to storeStrong in ObjCARCContract, ensure the call
gets the correct funclet token, otherwise WinEHPrepare will turn the
call (and all subsequent instructions) into unreachable.
We already have logic to do this for the ARC autorelease elision marker;
factor that out into a common function that's used for both. These are
the only two places in this transform that create call instructions.
Differential Revision: https://reviews.llvm.org/D45857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330487
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Simon Pilgrim [Fri, 20 Apr 2018 22:04:11 +0000 (22:04 +0000)]
[llvm-mca][X86] Add MMX/SSE/AES/CLMUL resource SandyBridge tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330486
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Simon Pilgrim [Fri, 20 Apr 2018 21:16:05 +0000 (21:16 +0000)]
[X86] Add WriteFSign/WriteFLogic scheduler classes
Split the fp and integer vector logical instruction scheduler classes - older CPUs especially often handled these on different pipes.
This unearthed a couple of things that are also handled in this patch:
(1) We were tagging avx512 fp logic ops as WriteFAdd, probably because of the lack of WriteFLogic
(2) SandyBridge had integer logic ops only using Port5, when afaict they can use Ports015.
(3) Cleaned up x86 FCHS/FABS scheduling as they are typically treated as fp logic ops.
Differential Revision: https://reviews.llvm.org/D45629
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330480
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Alexander Shaposhnikov [Fri, 20 Apr 2018 20:46:04 +0000 (20:46 +0000)]
[llvm-objcopy] Fix sh_link
This diff fixes sh_link for various types of sections
(i.e. for SHT_ARM_EXIDX, SHT_HASH). In particular, this change enables us
to use llvm-objcopy with clang -gsplit-dwarf for the target android-arm.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D45851
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330478
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Alex Shlyapnikov [Fri, 20 Apr 2018 20:04:04 +0000 (20:04 +0000)]
[HWASan] Introduce non-zero based and dynamic shadow memory (LLVM).
Summary:
Support the dynamic shadow memory offset (the default case for user
space now) and static non-zero shadow memory offset
(-hwasan-mapping-offset option). Keeping the the latter case around
for functionality and performance comparison tests (and mostly for
-hwasan-mapping-offset=0 case).
The implementation is stripped down ASan one, picking only the relevant
parts in the following assumptions: shadow scale is fixed, the shadow
memory is dynamic, it is accessed via ifunc global, shadow memory address
rematerialization is suppressed.
Keep zero-based shadow memory for kernel (-hwasan-kernel option) and
calls instreumented case (-hwasan-instrument-with-calls option), which
essentially means that the generated code is not changed in these cases.
Reviewers: eugenis
Subscribers: srhines, llvm-commits
Differential Revision: https://reviews.llvm.org/D45840
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330475
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Sean Fertile [Fri, 20 Apr 2018 19:56:26 +0000 (19:56 +0000)]
[PartialInlining] Fix Crash from holding a reference to a destructed ORE.
The callback used to create an ORE for the legacy PI pass caches the allocated
object in a unique_ptr in the runOnModule function, and returns a reference to
that object. Under certian circumstances we can end up holding onto that
reference after the OREs destruction. Rather then allowing the new and legacy
passes to create ORE object in diffrent ways, create the ORE at the point of
use.
Differential Revision: https://reviews.llvm.org/D43219
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330473
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Krzysztof Parzyszek [Fri, 20 Apr 2018 19:45:49 +0000 (19:45 +0000)]
[Hexagon] hexagon-autohvx was left on again
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330472
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Krzysztof Parzyszek [Fri, 20 Apr 2018 19:38:37 +0000 (19:38 +0000)]
[Hexagon] Improve HVX instruction selection (bitcast, vsplat)
There was some unfortunate interaction between VSPLAT and BITCAST
related to the selection of constant vectors (coming from selecting
shuffles). Introduce VSPLATW that always splats a 32-bit word, and
can have arbitrary result type (to avoid BITCASTs of VSPLAT).
Clean up the previous selection of BITCAST/VSPLAT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330471
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Eric Christopher [Fri, 20 Apr 2018 19:07:57 +0000 (19:07 +0000)]
Remove unused argument from emitModuleMetadata.
NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330470
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Krzysztof Parzyszek [Fri, 20 Apr 2018 19:06:46 +0000 (19:06 +0000)]
[Hexagon] Skip fixed-stack indexes in HexagonConstExtenders
Fixed slots have negative values, and TRI::stackSlot2Index and
TRI::index2StackSlot do not handle negative numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330468
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Craig Topper [Fri, 20 Apr 2018 18:55:40 +0000 (18:55 +0000)]
[X86][SandyBridge] Remove duplciate InstRWs from Sandy Brige scheduler model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330465
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Gabor Buella [Fri, 20 Apr 2018 18:42:47 +0000 (18:42 +0000)]
[X86] WaitPKG instructions
Three new instructions:
umonitor - Sets up a linear address range to be
monitored by hardware and activates the monitor.
The address range should be a writeback memory
caching type.
umwait - A hint that allows the processor to
stop instruction execution and enter an
implementation-dependent optimized state
until occurrence of a class of events.
tpause - Directs the processor to enter an
implementation-dependent optimized state
until the TSC reaches the value in EDX:EAX.
Also modifying the description of the mfence
instruction, as the rep prefix (0xF3) was allowed
before, which would conflict with umonitor during
disassembly.
Before:
$ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble
.text
mfence
After:
$ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble
.text
umonitor %rax
Reviewers: craig.topper, zvi
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D45253
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330462
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Jessica Paquette [Fri, 20 Apr 2018 18:03:21 +0000 (18:03 +0000)]
[MachineOutliner] Change B instruction for tail calls to TCRETURNdi
First off, this is more correct than having the B. Second off, this was making
a bot upset. This fixes that.
Update the test to include -verify-machineinstrs as well to prevent stuff like
this slipping by non debug/assert builds in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330459
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Zachary Turner [Fri, 20 Apr 2018 18:00:46 +0000 (18:00 +0000)]
[LLD/PDB] Emit first section contribution for DBI Module Descriptor.
Part of the DBI stream is a list of variable length structures
describing each module that contributes to the final executable.
One member of this structure is a section contribution entry that
describes the first section contribution in the output file for
the given module.
We have been leaving this structure unpopulated until now, so with
this patch it is now filled out correctly.
Differential Revision: https://reviews.llvm.org/D45832
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330457
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Nico Weber [Fri, 20 Apr 2018 17:21:10 +0000 (17:21 +0000)]
Remove llvm-build's --configure-target-def-file.
It was added 6.5 years ago in r144345, but was never hooked up and has been
unused since. If _you_ do use this, feel free to revert, but add a comment
on where it's used.
https://reviews.llvm.org/D45262
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330455
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Sanjay Patel [Fri, 20 Apr 2018 17:16:23 +0000 (17:16 +0000)]
[utils] improve AArch64 asm parser
If we don't mark the cfi line as optional, the script won't
work with 'nounwind' code. Without that attr, there may be
extra noise in the asm body that we don't want to see.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330453
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Nicholas Wilson [Fri, 20 Apr 2018 17:07:24 +0000 (17:07 +0000)]
[WebAssembly] Distinguish debug/symbol names in the Wasm structs. NFC
Differential Revision: https://reviews.llvm.org/D45021
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330448
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Michael Zolotukhin [Fri, 20 Apr 2018 16:57:10 +0000 (16:57 +0000)]
Revert r330431.
There are still stage3/stage4 miscompares :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330446
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