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Andreas Gampe [Sat, 11 Apr 2015 02:57:29 +0000 (19:57 -0700)]
ART: Ignore result for exception-case JNIEndWithReference
The value may not contain a valid jobject, so ignore and use null
directly.
Refactor a bit to have one common function for both synchronized
and non-synchronized case.
Add a test to the JNI compiler tests.
Bug:
18135031
Change-Id: If2f004a112f36f4ff68172a946dec67ce561ae4d
Andreas Gampe [Fri, 10 Apr 2015 22:35:34 +0000 (22:35 +0000)]
Merge "ART: Add Array.createObjectArray to unstarted runtime"
Andreas Gampe [Fri, 10 Apr 2015 21:57:10 +0000 (14:57 -0700)]
ART: Add Array.createObjectArray to unstarted runtime
Necessary for compile-time initialization of android.text.Layout.
Bug:
19542228
Change-Id: I4220c65fcc3a8aaa2765b6f07f1f81c330484244
Nicolas Geoffray [Fri, 10 Apr 2015 21:40:59 +0000 (21:40 +0000)]
Merge "Revert "[optimizing] Improve x86 shifts""
Mathieu Chartier [Fri, 10 Apr 2015 21:22:55 +0000 (21:22 +0000)]
Merge "Move ArtField to native"
Andreas Gampe [Fri, 10 Apr 2015 20:14:01 +0000 (20:14 +0000)]
Merge "ART: Fix failure-log script"
Andreas Gampe [Fri, 10 Apr 2015 20:06:22 +0000 (13:06 -0700)]
ART: Fix failure-log script
The transaction error class has been changed, update the script.
Change-Id: Ibc4dfb8cdca01eb9dc9e868c18d36bf6badb0521
Mathieu Chartier [Fri, 27 Mar 2015 21:35:38 +0000 (14:35 -0700)]
Move ArtField to native
Add linear alloc. Moved ArtField to be native object. Changed image
writer to put ArtFields after the mirror section.
Savings:
2MB on low ram devices
4MB on normal devices
Total PSS measurements before (normal N5, 95s after shell start):
Image size:
7729152 bytes
23112 kB: .NonMoving
23212 kB: .NonMoving
22868 kB: .NonMoving
23072 kB: .NonMoving
22836 kB: .NonMoving
19618 kB: .Zygote
19850 kB: .Zygote
19623 kB: .Zygote
19924 kB: .Zygote
19612 kB: .Zygote
Avg: 42745.4 kB
After:
Image size:
7462912 bytes
17440 kB: .NonMoving
16776 kB: .NonMoving
16804 kB: .NonMoving
17812 kB: .NonMoving
16820 kB: .NonMoving
18788 kB: .Zygote
18856 kB: .Zygote
19064 kB: .Zygote
18841 kB: .Zygote
18629 kB: .Zygote
3499 kB: .LinearAlloc
3408 kB: .LinearAlloc
3424 kB: .LinearAlloc
3600 kB: .LinearAlloc
3436 kB: .LinearAlloc
Avg: 39439.4 kB
No reflection performance changes.
Bug:
19264997
Bug:
17643507
Change-Id: I10c73a37913332080aeb978c7c94713bdfe4fe1c
Andreas Gampe [Fri, 10 Apr 2015 19:14:24 +0000 (19:14 +0000)]
Merge "ART: Refactor CompileOptimized"
Vladimir Marko [Fri, 10 Apr 2015 18:22:10 +0000 (18:22 +0000)]
Merge "Avoid using dex cache array pointers in libart."
Roland Levillain [Fri, 10 Apr 2015 18:12:48 +0000 (18:12 +0000)]
Revert "[optimizing] Improve x86 shifts"
This reverts commit
222fcf96c9b73bbb739012575e7e413caf9348ec.
Reverting this CL as it is breaking a few tests (see http://build.chromium.org/p/client.art/builders/host-x86/builds/3251/steps/test%20optimizing/logs/stdio). Will investigate ASAP.
Change-Id: Iddd8363e83a24aa49fbdf0f0c9dc12e63b4848de
Andreas Gampe [Fri, 10 Apr 2015 17:49:32 +0000 (10:49 -0700)]
ART: Refactor CompileOptimized
Factor out register allocation. Both Clang and GCC inline the
function, but it changes how Clang stack-allocates enough so
that the resulting frame size is below our limit.
Bug:
20139216
Change-Id: I2cf393aed70f2ce0556252b61ae639aacab6f3a7
Vladimir Marko [Thu, 9 Apr 2015 13:13:13 +0000 (14:13 +0100)]
Avoid using dex cache array pointers in libart.
In preparation for making dex cache arrays native, avoid
using them in Java code.
This causes a performance regression for our reflection
benchmarks. Class_getDeclaredMethod and Class_getMethod
take an up to 30% hit, measured using the Quick compiler.
We accept this hit at this stage and we will tune the
performance after we're done with the larger effort.
Companion libcore/ change:
https://android-review.googlesource.com/146069
Bug:
20134538
Change-Id: Ibbef3b50043a1311cd40723ed42e1f1c609b8fc1
Andreas Gampe [Fri, 10 Apr 2015 16:47:48 +0000 (16:47 +0000)]
Merge "ART: Remove WriteElf from Compiler"
Andreas Gampe [Fri, 10 Apr 2015 16:28:22 +0000 (09:28 -0700)]
ART: Remove WriteElf from Compiler
As Portable is gone, we only have one elf_writer left. It also
allows to put the decision for 32b vs 64b ELF into a central
point.
Change-Id: Iae67d06df85268b3f0ee5725abc65edd23eb2499
Roland Levillain [Fri, 10 Apr 2015 16:20:23 +0000 (16:20 +0000)]
Merge "Opt compiler: Instruction simplification for HAdd, HNeg, HNot, HSub."
Alexandre Rames [Thu, 9 Apr 2015 17:30:21 +0000 (18:30 +0100)]
Opt compiler: Instruction simplification for HAdd, HNeg, HNot, HSub.
Under assumptions for the 'cost' of each IR (eg. neither HAdd nor HSub
are faster than the other), transformations are only applied if they
(locally) cannot degrade the quality of the graph. The code could be
extended to look at uses of the IRs and detect more opportunities for
optimisations. The optimisations in this patch do not look at other
uses for their inputs.
Change-Id: Ib60dab007af30f43421ef5bb55db2ec32fb8fc0c
Calin Juravle [Fri, 10 Apr 2015 16:15:07 +0000 (16:15 +0000)]
Merge "Follow up of "div/rem on x86 and x86_64", to tidy up the code a little."
Calin Juravle [Fri, 10 Apr 2015 16:12:12 +0000 (16:12 +0000)]
Merge "[optimizing] Improve x86 parallel moves/swaps"
Mark Mendell [Wed, 1 Apr 2015 16:51:05 +0000 (12:51 -0400)]
[optimizing] Improve x86 parallel moves/swaps
Add a new constructor to ScratchRegisterScope that will supply a
register if there is a free one, but not spill to force one. Use this
to generated alternate code that doesn't use a temporary, as the
spill/restore of a register generates extra instructions that aren't
necessary on x86.
Here is the benefit for a 32 bit memory-to-memory exchange with no
free registers:
< 50 push eax
< 53 push ebx
<
8B44244C mov eax, [esp + 76]
<
8B5C246C mov ebx, [esp + 108]
<
8944246C mov [esp + 108], eax
<
895C244C mov [esp + 76], ebx
< 5B pop ebx
< 58 pop eax
---
>
FF742444 push [esp + 68]
>
FF742468 push [esp + 104]
>
8F44244C pop [esp + 72]
>
8F442468 pop [esp + 100]
Avoid using xchg instruction, as it is slow on smaller processors.
Change-Id: Id29ee3abd998577baaee552d55d23e60ae0c7871
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
Roland Levillain [Fri, 10 Apr 2015 15:39:15 +0000 (15:39 +0000)]
Merge "[optimizing] Improve x86 shifts"
Roland Levillain [Fri, 10 Apr 2015 14:15:37 +0000 (14:15 +0000)]
Merge "Optimizing x86: Fix VisitArraySet for FP value"
Roland Levillain [Fri, 10 Apr 2015 13:46:09 +0000 (13:46 +0000)]
Merge "[optimizing] Address x86_64 RIP patch comments"
Mark Mendell [Mon, 30 Mar 2015 18:13:30 +0000 (14:13 -0400)]
[optimizing] Improve x86 shifts
Support memory operands for integer shifts. Generate better code for
long shifts by constants.
Change-Id: Icc92fa1b59cc280d4894af6f054e19b01977d5ce
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
Mark Mendell [Fri, 10 Apr 2015 00:42:42 +0000 (20:42 -0400)]
[optimizing] Address x86_64 RIP patch comments
Nicolas had some comments after the patch
https://android-review.googlesource.com/#/c/144100 had merged. Fix the
problems that he found.
Change-Id: I40e8a4273997860db7511dc8f1986281b72bead2
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
Roland Levillain [Fri, 10 Apr 2015 11:07:18 +0000 (11:07 +0000)]
Merge "Fix checker tests in 458-checker-instruction-simplification."
Alexandre Rames [Thu, 9 Apr 2015 14:21:41 +0000 (15:21 +0100)]
Fix checker tests in 458-checker-instruction-simplification.
Change-Id: I9931e1692117360b8396c0dd8d171c822f0aba3b
Guillaume Sanchez [Thu, 9 Apr 2015 20:12:15 +0000 (21:12 +0100)]
Follow up of "div/rem on x86 and x86_64", to tidy up the code a little.
Change-Id: Ibf39cbc8ac1d773599d70be2cb1e941674b60f1d
Serguei Katkov [Wed, 8 Apr 2015 07:26:09 +0000 (13:26 +0600)]
Optimizing x86: Fix VisitArraySet for FP value
Instruction generator expects to see FP value in XMM register,
so update location builder to follow this.
Change-Id: Idca4bb5cdb59249c77fcc6f76cdfcaba47222b3d
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Vladimir Marko [Fri, 10 Apr 2015 08:46:20 +0000 (08:46 +0000)]
Merge "Refine erratum 843419 check for linker workaround."
David Srbecky [Fri, 10 Apr 2015 08:38:25 +0000 (08:38 +0000)]
Merge "Move DWARF related code in ElfWriter to its own file."
David Srbecky [Fri, 10 Apr 2015 08:37:00 +0000 (08:37 +0000)]
Merge "Extend the DWARF library to support .debug_info section."
David Srbecky [Thu, 9 Apr 2015 23:22:14 +0000 (00:22 +0100)]
Move DWARF related code in ElfWriter to its own file.
This is purely for organisation. The DWARF related code
is becoming more complex and I do not want to keep mixing
it with the ElfWriter. The ElfWriter probably should not
be dealing with the fine details of DWARF generation.
I intend to do much more work on DWARF in the future so
this situatuion would only get worse as the code grows.
The code could also use some refactoring and splitting.
However, I have mostly just moved it in this CL.
Change-Id: I6e3401a2b745ddf991b440ad7899ad7d4b921be6
Andreas Gampe [Thu, 9 Apr 2015 23:33:24 +0000 (23:33 +0000)]
Merge "[MIPS] Refactoring code for disassembler"
Andreas Gampe [Thu, 9 Apr 2015 23:07:00 +0000 (23:07 +0000)]
Merge "ART: Use canonical location in dex2oat"
Mathieu Chartier [Thu, 9 Apr 2015 23:03:45 +0000 (23:03 +0000)]
Merge "Add support for nested method verifiers"
David Srbecky [Wed, 8 Apr 2015 18:37:39 +0000 (19:37 +0100)]
Extend the DWARF library to support .debug_info section.
Change-Id: I9916abd8db227e7a73a3311294e675be5222a709
David Srbecky [Thu, 9 Apr 2015 22:39:32 +0000 (22:39 +0000)]
Merge "Remove duplicate of DexFile::DecodeDebugInfo."
David Srbecky [Thu, 9 Apr 2015 22:39:20 +0000 (22:39 +0000)]
Merge "Fix memory leaks in the CFI tests."
David Srbecky [Thu, 9 Apr 2015 21:51:56 +0000 (22:51 +0100)]
Fix memory leaks in the CFI tests.
Change-Id: Icb98e4995731c7ac5f99d1be20b447161ea4c4bd
Andreas Gampe [Thu, 9 Apr 2015 22:33:11 +0000 (22:33 +0000)]
Merge "ART: Fix indent in Mips backend"
Andreas Gampe [Thu, 9 Apr 2015 22:30:51 +0000 (15:30 -0700)]
ART: Fix indent in Mips backend
Change-Id: Ib8bc6f6bf36079e0b6e4b65ceab8af7dedc60efc
David Srbecky [Tue, 7 Apr 2015 18:02:58 +0000 (19:02 +0100)]
Remove duplicate of DexFile::DecodeDebugInfo.
Call DexFile::DecodeDebugInfo instead of having a local copy.
Change-Id: I4f94fd56a81fea1a2d10d5a26b9650d6d7ff9448
Mathieu Chartier [Tue, 31 Mar 2015 21:59:59 +0000 (14:59 -0700)]
Add support for nested method verifiers
Can occur in the following scenario:
MethodVerifier::Verify -> MethodVerifier::GetStaticField ->
ResolveFieldJLS -> ThrowNoSuchFieldError -> EnsureInitialized ->
VerifyClass
Also fixed another case where we can be requested to dump for ANR
while we are suspended in one of the AllowSuspension points.
Bug:
20140397
Change-Id: Ib17f6b98954caa5d1ea1c1dcde66091cc6d11c25
Andreas Gampe [Thu, 9 Apr 2015 22:09:29 +0000 (22:09 +0000)]
Merge "Fix GenDivRemLit() for Mips."
Andreas Gampe [Thu, 9 Apr 2015 21:46:31 +0000 (14:46 -0700)]
ART: Use canonical location in dex2oat
To filter class-path dex files, use the canonical location, not
the location. That will correctly resolve relative vs absolute
paths.
Bug:
20133593
Change-Id: I894656cb6bef75cdaffb188987af0a3647c74ad6
David Srbecky [Thu, 9 Apr 2015 20:13:22 +0000 (20:13 +0000)]
Merge "Fix build - the stack frame is too large."
David Srbecky [Thu, 9 Apr 2015 20:00:58 +0000 (21:00 +0100)]
Fix build - the stack frame is too large.
Change-Id: Icabad2e3ccbaa4783df6c18c60a206357398edc5
David Srbecky [Thu, 9 Apr 2015 19:00:44 +0000 (19:00 +0000)]
Merge "Fix Mac compile error in debug_frame_writer.h"
Matteo Franchin [Thu, 2 Apr 2015 14:49:06 +0000 (15:49 +0100)]
Refine erratum 843419 check for linker workaround.
The check is extended to avoid patching sequences where the adrp
is followed by a load which can easily be proved to be aligned.
Change-Id: Ia5741e3d73bc143c29bf0e301f767012d7598171
Vladimir Marko [Thu, 9 Apr 2015 18:40:37 +0000 (18:40 +0000)]
Merge "Quick: PC-relative loads from dex cache arrays on x86."
David Srbecky [Thu, 9 Apr 2015 18:39:53 +0000 (19:39 +0100)]
Fix Mac compile error in debug_frame_writer.h
Change-Id: I1c5723348011570425cbe5cc1627cd9872020beb
David Srbecky [Thu, 9 Apr 2015 17:27:31 +0000 (17:27 +0000)]
Merge "Implement CFI for Optimizing."
Roland Levillain [Thu, 9 Apr 2015 17:25:02 +0000 (17:25 +0000)]
Merge "[optimizing] Add RIP support for x86_64"
Andreas Gampe [Thu, 9 Apr 2015 17:15:22 +0000 (17:15 +0000)]
Merge "ART: IRT refactor"
David Srbecky [Thu, 9 Apr 2015 16:47:14 +0000 (16:47 +0000)]
Merge "Implement CFI for JNI."
Andreas Gampe [Thu, 9 Apr 2015 16:41:55 +0000 (16:41 +0000)]
Merge "x86_64: Fix the rex prefix for movzxb, movsxb, movb"
Andreas Gampe [Thu, 9 Apr 2015 16:40:40 +0000 (16:40 +0000)]
Merge "Fix for incorrect parse of PEXTRW instruction"
Andreas Gampe [Wed, 8 Apr 2015 17:26:16 +0000 (10:26 -0700)]
ART: IRT refactor
IRT creation might fail. Add a path that allows to bypass the aborts
and instead signal validity. Hide this path with a private constructor,
rewrite users to use a static Create method.
Bug:
20110201
Change-Id: I440499c3372cd7557eb970b70ce2c4543da520e4
Andreas Gampe [Thu, 9 Apr 2015 16:04:55 +0000 (16:04 +0000)]
Merge "Add test cases to make sure GenDivRemLit() handles 16-bit constants correctly."
Douglas Leung [Wed, 8 Apr 2015 22:53:58 +0000 (15:53 -0700)]
Add test cases to make sure GenDivRemLit() handles 16-bit
constants correctly.
Change-Id: Idb4aee8b98dc908cb28887e96254f8c254ad7d4d
Richard Uhler [Thu, 9 Apr 2015 15:59:02 +0000 (15:59 +0000)]
Merge "Test DexOptStatus enum values match DexFile values."
Richard Uhler [Wed, 8 Apr 2015 20:17:29 +0000 (13:17 -0700)]
Test DexOptStatus enum values match DexFile values.
Change-Id: Id480fa3f273ff0ce3ec806749f26bfb5a995bc4a
David Srbecky [Thu, 9 Apr 2015 15:52:20 +0000 (15:52 +0000)]
Merge "Implement CFI for Quick."
David Srbecky [Tue, 7 Apr 2015 19:32:43 +0000 (20:32 +0100)]
Implement CFI for Optimizing.
CFI is necessary for stack unwinding in gdb, lldb, and libunwind.
Change-Id: I1a3480e3a4a99f48bf7e6e63c4e83a80cfee40a2
Mark Mendell [Fri, 27 Mar 2015 01:07:46 +0000 (21:07 -0400)]
[optimizing] Add RIP support for x86_64
Support a constant area addressed using RIP on x86_64. Use it for FP
operations to avoid loading constants into a CPU register and moving
to a XMM register.
Change-Id: I58421759ef2a8475538876c20e696ec787015a72
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
Richard Uhler [Thu, 9 Apr 2015 14:13:29 +0000 (14:13 +0000)]
Merge "Rename isDexOptNeededInternal and add kSelfPatchOatNeeded"
Calin Juravle [Thu, 9 Apr 2015 12:46:58 +0000 (12:46 +0000)]
Merge "Speedup div/rem by constants on x86 and x86_64"
Guillaume Sanchez [Mon, 30 Mar 2015 16:55:45 +0000 (17:55 +0100)]
Speedup div/rem by constants on x86 and x86_64
This is done using the algorithms in Hacker's Delight chapter 10.
Change-Id: I7bacefe10067569769ed31a1f7834f796fb41119
Roland Levillain [Thu, 9 Apr 2015 11:14:45 +0000 (11:14 +0000)]
Merge "Opt compiler: ARM64: Use TBZ and TBNZ in VisitIf."
Roland Levillain [Thu, 9 Apr 2015 10:59:36 +0000 (10:59 +0000)]
Merge "Exercise art::arm::Thumb2Assembler::StoreToOffset for word pairs."
Vladimir Marko [Wed, 8 Apr 2015 19:51:48 +0000 (20:51 +0100)]
Quick: PC-relative loads from dex cache arrays on x86.
Rewrite all PC-relative addressing on x86 and implement
PC-relative loads from dex cache arrays. Don't adjust the
base to point to the start of the method, let it point to
the anchor, i.e. the target of the "call +0" insn.
Change-Id: Ic22544a8bc0c5e49eb00a75154dc8f3ead816989
Goran Jakovljevic [Wed, 8 Apr 2015 14:26:05 +0000 (16:26 +0200)]
[MIPS] Refactoring code for disassembler
Code for mips64 is merged with code for mips.
Change-Id: I2e3f2118c69a189787ae8e7f09adb4ee5c0d00d9
Chao-ying Fu [Tue, 7 Apr 2015 23:03:04 +0000 (16:03 -0700)]
x86_64: Fix the rex prefix for movzxb, movsxb, movb
This patch sets the rex prefix for the source byte register of
movzxb, movsxb, and movb that has the destination memory operand,
when the register is SPL, BPL, SIL, DIL.
This patch adds tests for movzxb and movsxb via Repeatrb(),
and adds the tertiary and quaternary register views for word and
byte registers on x86_64.
TODO: Support tests with memory operands.
Change-Id: I0c5c727f3dd4a75af039b87f7e57d0741e689038
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Vladimir Marko [Wed, 8 Apr 2015 17:08:04 +0000 (17:08 +0000)]
Merge "Quick: Clean up temp use counting."
Sebastien Hertz [Wed, 8 Apr 2015 16:42:38 +0000 (16:42 +0000)]
Merge "Fix JDWP race at runtime shutdown"
Andreas Gampe [Wed, 8 Apr 2015 16:07:41 +0000 (16:07 +0000)]
Merge "[optimizing] Implement more x86/x86_64 intrinsics"
David Srbecky [Tue, 7 Apr 2015 19:29:48 +0000 (20:29 +0100)]
Implement CFI for JNI.
CFI is necessary for stack unwinding in gdb, lldb, and libunwind.
Change-Id: I37eb7973f99a6975034cf0e699e138c3a9aba10f
Vladimir Marko [Wed, 8 Apr 2015 09:01:01 +0000 (10:01 +0100)]
Quick: Clean up temp use counting.
For the boot image on arm64 and x86-64 we're using true
PC-relative addressing, so pc_rel_temp_ is nullptr and
CanUsePcRelDexCacheArrayLoad() returns true, but we're not
actually using the ArtMethod* so fix the AnalyzeMIR() to
take it into account.
Also don't count intrinsic invokes towards ArtMethod* uses.
To avoid repeated method inliner inquiries about whether a
method is intrinsic or special (requiring lock acquisition),
cache that information in MirMethodLoweringInfo. As part of
that cleanup, take quickened invokes into account for
suspend check elimination.
Change-Id: I5b4ec124221c0db1314c8e72675976c110ebe7ca
David Srbecky [Tue, 7 Apr 2015 19:21:06 +0000 (20:21 +0100)]
Implement CFI for Quick.
CFI is necessary for stack unwinding in gdb, lldb, and libunwind.
Change-Id: Ic3b84c9dc91c4bae80e27cda02190f3274e95ae8
David Srbecky [Wed, 8 Apr 2015 12:30:18 +0000 (12:30 +0000)]
Merge "Remove the old CFI infrastructure."
Alexandre Rames [Tue, 3 Feb 2015 10:28:33 +0000 (10:28 +0000)]
Opt compiler: ARM64: Use TBZ and TBNZ in VisitIf.
TBZ and TBNZ have a short range. Now that VIXL supports
veneers, we can use them safely without the danger of
running out of range.
Change-Id: Iaf77a441ccf86282c1793a2213a69a2091ca829a
Roland Levillain [Wed, 8 Apr 2015 08:50:47 +0000 (08:50 +0000)]
Merge "Exercise art::arm::Thumb2Assembler::StoreToOffset for words."
Sebastien Hertz [Wed, 8 Apr 2015 08:49:19 +0000 (08:49 +0000)]
Merge "Ignore not yet loaded classes during hprof"
Andreas Gampe [Wed, 8 Apr 2015 03:06:26 +0000 (03:06 +0000)]
Merge "ART: Remove LLVM cruft"
Andreas Gampe [Wed, 8 Apr 2015 02:58:03 +0000 (19:58 -0700)]
ART: Remove LLVM cruft
Change-Id: I133ebed6101bf12a0642ed71e13f332c0c4f14e7
Douglas Leung [Tue, 7 Apr 2015 20:25:56 +0000 (13:25 -0700)]
Fix GenDivRemLit() for Mips.
This bug was reported by Ingenic where the result is incorrect if
we divide a number by an unsigned 16-bit constant with its
MSB bit (bit 15) set.
Change-Id: I53d2599918cc47b1a9809160310716dca67ef243
Andreas Gampe [Wed, 8 Apr 2015 00:37:23 +0000 (00:37 +0000)]
Merge "ART: Fix 64-bit ELF file support"
Andreas Gampe [Tue, 7 Apr 2015 23:09:30 +0000 (16:09 -0700)]
ART: Fix 64-bit ELF file support
The API wasn't cross-compile-safe, 32-bit patchoat would fail for
negative delta applied to a 64-bit ELF file.
Add 64-bit ELF file output to the compilers, behind a flag, currently
off by default (preserving current behavior).
Bug:
20095017
Change-Id: I2cde7b4c7cc83413c76692d7b745868d644a604c
Vladimir Marko [Tue, 7 Apr 2015 19:34:39 +0000 (19:34 +0000)]
Merge "Promote pointer to dex cache arrays on arm."
Vladimir Marko [Tue, 7 Apr 2015 19:34:01 +0000 (19:34 +0000)]
Merge "PC-relative loads from dex cache arrays for arm."
David Srbecky [Tue, 7 Apr 2015 18:46:22 +0000 (19:46 +0100)]
Remove the old CFI infrastructure.
Change-Id: I12a17a8a1c39ffccaa499c328ebac36e4d74dc4e
Vladimir Marko [Tue, 7 Apr 2015 19:01:32 +0000 (19:01 +0000)]
Merge "Quick: Use PC-relative dex cache array loads for SGET/SPUT."
Mathieu Chartier [Tue, 7 Apr 2015 18:24:13 +0000 (18:24 +0000)]
Merge "Fix CC root visiting bug"
Vladimir Marko [Tue, 7 Apr 2015 08:36:09 +0000 (09:36 +0100)]
Promote pointer to dex cache arrays on arm.
Do the use-count analysis on temps (ArtMethod* and the new
PC-relative temp) in Mir2Lir, rather than MIRGraph. MIRGraph
isn't really supposed to know how the ArtMethod* is used by
the backend.
Change-Id: Iaf56a46ae203eca86281b02b54f39a80fe5cc2dd
Vladimir Marko [Mon, 6 Apr 2015 11:10:19 +0000 (12:10 +0100)]
PC-relative loads from dex cache arrays for arm.
Change-Id: Ic25df4b51a901ff1d2ca356b5eec71d4acc5d9b7
Vladimir Marko [Tue, 7 Apr 2015 08:56:48 +0000 (09:56 +0100)]
Quick: Use PC-relative dex cache array loads for SGET/SPUT.
Change-Id: I890284b73f69120ada5cf9b9ef4a717af3273cd2
Mathieu Chartier [Tue, 7 Apr 2015 17:39:04 +0000 (10:39 -0700)]
Fix CC root visiting bug
Also some cleanup.
Change-Id: Ia3de8f2d409770be3619ec116e8b06ecd82338fe
David Brazdil [Tue, 7 Apr 2015 17:33:43 +0000 (17:33 +0000)]
Merge "ART: Print C1vis header only if visualizer enabled"
Andreas Gampe [Tue, 7 Apr 2015 17:29:21 +0000 (17:29 +0000)]
Merge "ART: Remove unused variables."