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George Burgess IV [Tue, 2 Aug 2016 22:17:25 +0000 (22:17 +0000)]
[CFLAA] Be more conservative with values we haven't seen.
There were issues with simply reporting AttrUnknown on
previously-unknown values in CFLAnders. So, we now act *entirely*
conservatively for values we haven't seen before. As in the prior patch
(r277362), writing a lit test for this isn't exactly trivial. If someone
wants a test badly, I'm willing to try to write one.
Patch by Jia Chen.
Differential Revision: https://reviews.llvm.org/D23077
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277533
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Daniel Berlin [Tue, 2 Aug 2016 21:57:52 +0000 (21:57 +0000)]
Move to having a single real instructionClobbersQuery
Summary: We really want to move towards MemoryLocOrCall (or fix AA) everywhere, but for now, this lets us have a single instructionClobbersQuery.
Reviewers: george.burgess.iv
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277530
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Rui Ueyama [Tue, 2 Aug 2016 21:56:37 +0000 (21:56 +0000)]
PDB: Mark extended file pages as free by default.
BitVector::extend initializes extended bits as true by default.
That is not desirable because new pages should be initially free.
Differential Revision: https://reviews.llvm.org/D23048
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277529
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Krzysztof Parzyszek [Tue, 2 Aug 2016 21:49:20 +0000 (21:49 +0000)]
[Hexagon] Recognize vcombine in copy propagation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277528
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Michael Zolotukhin [Tue, 2 Aug 2016 21:43:25 +0000 (21:43 +0000)]
[LoopUnroll] Fix a PowerPC test broken by r277524.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277527
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Michael Zolotukhin [Tue, 2 Aug 2016 21:24:14 +0000 (21:24 +0000)]
[LoopUnroll] Switch the default value of -unroll-runtime-epilog back to its original value.
As agreed in post-commit review of r265388, I'm switching the flag to
its original value until the 90% runtime performance regression on
SingleSource/Benchmarks/Stanford/Bubblesort is addressed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277524
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Lang Hames [Tue, 2 Aug 2016 21:00:40 +0000 (21:00 +0000)]
[lli] Add the ability for OrcLazyJIT to accept multiple input modules.
LLI already supported passing multiple input modules to MCJIT via the
-extra-module option. This patch adds the plumbing to pass these modules to
the OrcLazy JIT too.
This functionality will be used in an upcoming test case for weak symbol
handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277521
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Artem Belevich [Tue, 2 Aug 2016 20:58:24 +0000 (20:58 +0000)]
[NVPTX] remove unnecessary named metadata update that happens to break debug info.
Also added test case to verify IR changes done by NVPTXGenericToNVVM pass.
Differential Revision: https://reviews.llvm.org/D22837
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277520
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Wei Mi [Tue, 2 Aug 2016 20:27:49 +0000 (20:27 +0000)]
[LoopVectorize] Change comment for isOutOfScope in collectLoopUniforms, NFC
Update comment for isOutOfScope and add a testcase for uniform value being used
out of scope.
Differential Revision: https://reviews.llvm.org/D23073
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277515
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Tim Northover [Tue, 2 Aug 2016 20:22:36 +0000 (20:22 +0000)]
AArch64: properly calculate cmpxchg status in FastISel.
We were relying on the misleadingly-names $status result to actually be the
status. Actually it's just a scratch register that may or may not be valid (and
is the inverse of the real ststus anyway). Success can be determined by
comparing the value loaded against the one we wanted to see for "cmpxchg
strong" loops like this.
Should fix PR28819.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277513
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Daniel Berlin [Tue, 2 Aug 2016 20:02:21 +0000 (20:02 +0000)]
Fixes for post-commit review comments on r277480
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277510
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Sanjoy Das [Tue, 2 Aug 2016 19:32:01 +0000 (19:32 +0000)]
[IRCE] Rename variable; NFC
There is nothing "Original" about "OriginalLoopInfo".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277506
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Sanjoy Das [Tue, 2 Aug 2016 19:31:54 +0000 (19:31 +0000)]
[IRCE] Preserve DomTree and LCSSA
This changes IRCE to "preserve" LCSSA and DomTree by recomputing them.
It still does not preserve LoopSimplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277505
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Nicolai Haehnle [Tue, 2 Aug 2016 19:31:14 +0000 (19:31 +0000)]
AMDGPU: Stay in WQM for non-intrinsic stores
Summary:
Two types of stores are possible in pixel shaders: stores to memory that are
explicitly requested at the API level, and stores that are an implementation
detail of register spilling or lowering of arrays.
For the first kind of store, we must ensure that helper pixels have no effect
and hence WQM must be disabled. The second kind of store must always be
executed, because the written value may be loaded again in a way that is
relevant for helper pixels as well -- and there are no externally visible
effects anyway.
This is a candidate for the 3.9 release branch.
Reviewers: arsenm, tstellarAMD, mareko
Subscribers: arsenm, kzhuravl, llvm-commits
Differential Revision: https://reviews.llvm.org/D22675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277504
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Albert Gutowski [Tue, 2 Aug 2016 19:25:17 +0000 (19:25 +0000)]
test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277503
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Michael Zolotukhin [Tue, 2 Aug 2016 19:19:31 +0000 (19:19 +0000)]
[LoopUnroll] Ensure we create prolog loops in simplified form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277502
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Nirav Dave [Tue, 2 Aug 2016 19:17:54 +0000 (19:17 +0000)]
Fix handling of end-of-line preprocessor comments Attempt 2
Attempt 2: Retryign after Tsan.mman test fix.
Attempt 1: Recommitting after fixing test.
When parsing assembly where the line comment syntax is not hash, the
lexer cannot distinguish between hash's that start a hash line comment
and one that is part of an assembly statement and must be distinguished
during parsing. Previously, this was incompletely handled by not checking
for EndOfStatement at the end of statements and interpreting hash
prefixed statements as comments.
Change EndOfStatement Parsing to check for Hash comments and reintroduce
Hash statement parsing to catch previously handled cases.
Reviewers: rnk, majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23017
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277501
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Nicolai Haehnle [Tue, 2 Aug 2016 19:17:37 +0000 (19:17 +0000)]
AMDGPU: Track physical registers in SIWholeQuadMode
Summary:
There are cases where uniform branch conditions are computed in VGPRs, and
we didn't correctly mark those as WQM.
The stray change in basic-branch.ll is because invoking the LiveIntervals
analysis leads to the detection of a dead register that would otherwise not
be seen at -O0.
This is a candidate for the 3.9 branch, as it fixes a possible hang.
Reviewers: arsenm, tstellarAMD, mareko
Subscribers: arsenm, llvm-commits, kzhuravl
Differential Revision: https://reviews.llvm.org/D22673
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277500
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Ahmed Bougacha [Tue, 2 Aug 2016 19:04:29 +0000 (19:04 +0000)]
[AArch64][GlobalISel] Replace test REQUIRES with lit.local.cfg. NFC.
I forgot the REQUIRES once (see r277486).
Let's prevent it from happening again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277499
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Ahmed Bougacha [Tue, 2 Aug 2016 19:04:25 +0000 (19:04 +0000)]
[AArch64] Remove useless 'import re' from CodeGen lit.local.cfg. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277498
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Krzysztof Parzyszek [Tue, 2 Aug 2016 18:50:05 +0000 (18:50 +0000)]
[Hexagon] Prefer _io over _rr for 64-bit store with constant offset
Identify patterns where the address is aligned to an 8-byte boundary,
but both the base address and the constant offset are both proper
multiples of 4. In such cases, extract Base+4 into a separate instruc-
tion, and use S2_storerd_io, instead of using S4_storerd_rr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277497
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Krzysztof Parzyszek [Tue, 2 Aug 2016 18:39:32 +0000 (18:39 +0000)]
[Hexagon] Remove unused option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277496
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Krzysztof Parzyszek [Tue, 2 Aug 2016 18:34:31 +0000 (18:34 +0000)]
[Hexagon] Improvements to address mode checks in TargetLowering
- Implement getOptimalMemOpType.
- Check BaseOffset in isLegalAddressingMode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277494
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Nirav Dave [Tue, 2 Aug 2016 17:56:03 +0000 (17:56 +0000)]
[MC] Fix Intel Operand assembly parsing for .set ids
Recommitting after fixing overaggressive fastpath return in parsing.
Fix intel syntax special case identifier operands that refer to a constant
(e.g. .set <ID> n) to be interpreted as immediate not memory in parsing.
Associated commit to fix clang test commited shortly.
Reviewers: rnk
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D22585
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277489
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Ahmed Bougacha [Tue, 2 Aug 2016 17:19:35 +0000 (17:19 +0000)]
[AArch64][GlobalISel] Add REQUIRES: global-isel to verifier tests.
I thought the directory had a lit.local.cfg, but it doesn't.
I'll add one, but for now, add the REQUIRES line. While there,
move the triple into the IR and add a datalayout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277486
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Daniel Berlin [Tue, 2 Aug 2016 16:59:51 +0000 (16:59 +0000)]
MSVC 2013 does not implement C++11 unions properly, so remove the anoymous union for now,
and leave a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277485
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Ahmed Bougacha [Tue, 2 Aug 2016 16:49:25 +0000 (16:49 +0000)]
[GlobalISel] Set the Selected MF property.
None of GlobalISel requires the property, but this lets us use the
verifier instead of rolling our own "all instructions selected" check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277484
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Ahmed Bougacha [Tue, 2 Aug 2016 16:49:22 +0000 (16:49 +0000)]
[GlobalISel] Verify Selected MF property.
After instruction selection, there should be no pre-isel generic
instructions remaining, nor should generic virtual registers be
used. Verify that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277483
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Ahmed Bougacha [Tue, 2 Aug 2016 16:49:19 +0000 (16:49 +0000)]
[GlobalISel] Add Selected MachineFunction property.
Selected: the InstructionSelect pass ran and all pre-isel generic
instructions have been eliminated; i.e., all instructions are now
target-specific or non-pre-isel generic instructions (e.g., COPY).
Since only pre-isel generic instructions can have generic virtual register
operands, this also means that all generic virtual registers have been
constrained to virtual registers (assigned to register classes) and that
all sizes attached to them have been eliminated.
This lets us enforce certain invariants across passes.
This property is GlobalISel-specific, but is always available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277482
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Daniel Berlin [Tue, 2 Aug 2016 16:24:03 +0000 (16:24 +0000)]
Rewrite the use optimizer to be less memory intensive and 50% faster.
Fixes PR28670
Summary:
Rewrite the use optimizer to be less memory intensive and 50% faster.
Fixes PR28670
The new use optimizer works like a standard SSA renaming pass, storing
all possible versions a MemorySSA use could get in a stack, and just
tracking indexes into the stack.
This uses much less memory than caching N^2 alias query results.
It's also a lot faster.
The current version defers phi node walking to the normal walker.
Reviewers: george.burgess.iv
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23032
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277480
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Artur Pilipenko [Tue, 2 Aug 2016 16:20:48 +0000 (16:20 +0000)]
[LVI] NFC. Sink a condition type check from the caller down to getValueFromCondition
This is a preparatory refactoring to support conditions other than ICmpInst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277479
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Ahmed Bougacha [Tue, 2 Aug 2016 16:17:18 +0000 (16:17 +0000)]
[GlobalISel] Set and require RegBankSelected MF property.
The InstructionSelect pass assumes that RegBankSelect ran; set the
property on all tests (thereby verifying the test inputs) and require
it in the pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277477
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Ahmed Bougacha [Tue, 2 Aug 2016 16:17:15 +0000 (16:17 +0000)]
[GlobalISel] Verify RegBankSelected MF property.
RegBankSelected functions shouldn't have any generic virtual
register not assigned to a bank. Verify that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277476
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Ahmed Bougacha [Tue, 2 Aug 2016 16:17:10 +0000 (16:17 +0000)]
[GlobalISel] Add RegBankSelected MachineFunction property.
RegBankSelected: the RegBankSelect pass ran and all generic virtual
registers have been assigned to a register bank.
This lets us enforce certain invariants across passes.
This property is GlobalISel-specific, but is always available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277475
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Matthew Simpson [Tue, 2 Aug 2016 15:25:16 +0000 (15:25 +0000)]
[LV] Generate both scalar and vector integer induction variables
This patch enables the vectorizer to generate both scalar and vector versions
of an integer induction variable for a given loop. Previously, we only
generated a scalar induction variable if we knew all its users were going to be
scalar. Otherwise, we generated a vector induction variable. In the case of a
loop with both scalar and vector users of the induction variable, we would
generate the vector induction variable and extract scalar values from it for
the scalar users. With this patch, we now generate both versions of the
induction variable when there are both scalar and vector users and select which
version to use based on whether the user is scalar or vector.
Differential Revision: https://reviews.llvm.org/D22869
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277474
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Ahmed Bougacha [Tue, 2 Aug 2016 15:10:32 +0000 (15:10 +0000)]
[GlobalISel] Set, require, and verify Legalized MF property.
RegBankSelect and InstructionSelect run after the legalizer and
require a Legalized function: check that all instructions are legal.
Note that this should be in the MachineVerifier, but it can't use the
MachineLegalizer as it's currently in the separate GlobalISel library.
Note that the RegBankSelect verifier checks have the same layering
problem, but we only use inline methods so end up not needing to link
against the GlobalISel library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277472
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Ahmed Bougacha [Tue, 2 Aug 2016 15:10:28 +0000 (15:10 +0000)]
[AArch64][GlobalISel] Mark basic binops/memops as legal.
We currently use and test these, and select most of them. Mark them
as legal even though we don't go through the full ir->asm flow yet.
This doesn't currently have standalone tests, but the verifier will
soon learn to check that the regbankselect/select tests are legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277471
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Ahmed Bougacha [Tue, 2 Aug 2016 15:10:25 +0000 (15:10 +0000)]
[GlobalISel] Add Legalized MachineFunction property.
Legalized: The MachineLegalizer ran; all pre-isel generic instructions
have been legalized, i.e., all instructions are now one of:
- generic and always legal (e.g., COPY)
- target-specific
- legal pre-isel generic instructions.
This lets us enforce certain invariants across passes.
This property is GlobalISel-specific, but is always available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277470
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Nirav Dave [Tue, 2 Aug 2016 15:08:52 +0000 (15:08 +0000)]
Revert "[MC] Fix handling of end-of-line preprocessor comments"
Causes TSan failure on PPC64
This reverts commit r277459.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277468
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Dan Gohman [Tue, 2 Aug 2016 14:53:44 +0000 (14:53 +0000)]
[WebAssembly] Remove a README.txt entry that is now implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277467
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Artur Pilipenko [Tue, 2 Aug 2016 14:44:32 +0000 (14:44 +0000)]
[LVI] NFC. Fix a typo getValueFromFromCondition -> getValueFromCondition
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277466
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Ahmed Bougacha [Tue, 2 Aug 2016 14:42:57 +0000 (14:42 +0000)]
[CodeGen] Generalize MachineFunctionProperties::print comma handling.
This is only used for debug prints, but the previous hardcoded ", "
caused it to be printed unnecessarily when OnlySet, and is annoying
when adding new properties.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277465
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Ahmed Bougacha [Tue, 2 Aug 2016 14:42:55 +0000 (14:42 +0000)]
[GlobalISel] Require isSSA in GISel passes.
The GISel passes don't make sense on non-SSA functions.
All GISel tests already set isSSA. Enforce that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277464
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Matthew Simpson [Tue, 2 Aug 2016 14:29:41 +0000 (14:29 +0000)]
[LV] Untangle the concepts of uniform and scalar
This patch refactors the logic in collectLoopUniforms and
collectValuesToIgnore, untangling the concepts of "uniform" and "scalar". It
adds isScalarAfterVectorization along side isUniformAfterVectorization to
distinguish the two. Known scalar values include those that are uniform,
getelementptr instructions that won't be vectorized, and induction variables
and induction variable update instructions whose users are all known to be
scalar.
This patch includes the following functional changes:
- In collectLoopUniforms, we mark uniform the pointer operands of interleaved
accesses. Although non-consecutive, these pointers are treated like
consecutive pointers during vectorization.
- In collectValuesToIgnore, we insert a value into VecValuesToIgnore if it
isScalarAfterVectorization rather than isUniformAfterVectorization. This
differs from the previous functionaly in that we now add getelementptr
instructions that will not be vectorized into VecValuesToIgnore.
This patch also removes the ValuesNotWidened set used for induction variable
scalarization since, after the above changes, it is now equivalent to
isScalarAfterVectorization.
Differential Revision: https://reviews.llvm.org/D22867
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277460
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Nirav Dave [Tue, 2 Aug 2016 14:25:49 +0000 (14:25 +0000)]
[MC] Fix handling of end-of-line preprocessor comments
Recommitting after fixing test.
When parsing assembly where the line comment syntax is not hash, the
lexer cannot distinguish between hash's that start a hash line comment
and one that is part of an assembly statement and must be distinguished
during parsing. Previously, this was incompletely handled by not checking
for EndOfStatement at the end of statements and interpreting hash
prefixed statements as comments.
Change EndOfStatement Parsing to check for Hash comments and reintroduce
Hash statement parsing to catch previously handled cases.
Reviewers: rnk, majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23017
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277459
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David Callahan [Tue, 2 Aug 2016 13:26:07 +0000 (13:26 +0000)]
Revert rL277454
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277455
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David Callahan [Tue, 2 Aug 2016 13:19:12 +0000 (13:19 +0000)]
test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277454
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Sam Parker [Tue, 2 Aug 2016 12:44:27 +0000 (12:44 +0000)]
[ARM] Improve smul* and smla* isel for Thumb2
Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to
simplify some pattern matching. This has allowed several patterns
for smul* and smla* to be removed as well as making it easier to add
the matching for the corresponding instructions for Thumb2 targets.
Also added two Pat classes that are predicated on Thumb2 with the
hasDSP flag and UseMulOps flags. Updated the smul codegen test with
the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets.
Differential Revision: https://reviews.llvm.org/D22908
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277450
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NAKAMURA Takumi [Tue, 2 Aug 2016 11:59:16 +0000 (11:59 +0000)]
HexagonVectorPrint.cpp: Fix r277370. Don't use getInstrVecReg() in the expression of assert(). It has side effects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277448
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Ahmed Bougacha [Tue, 2 Aug 2016 11:41:16 +0000 (11:41 +0000)]
[GlobalISel] Don't RegBankSelect target-specific instructions.
They don't have types and should be using register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277447
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Ahmed Bougacha [Tue, 2 Aug 2016 11:41:09 +0000 (11:41 +0000)]
[GlobalISel] Don't legalize non-generic instructions.
They don't have types and should be legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277446
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Ahmed Bougacha [Tue, 2 Aug 2016 11:41:03 +0000 (11:41 +0000)]
[GlobalISel] Const-ify MachineInstrs passed to MachineLegalizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277445
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Simon Dardis [Tue, 2 Aug 2016 10:32:00 +0000 (10:32 +0000)]
[mips] Update the P5600 scheduler for isComplete = 1
These changes update the schedule model for the P5600 and includes the
rest of the MSA and MIPS32R5 instruction sets.
Reviewers: dsanders, vkalintris
Differential Revision: https://reviews.llvm.org/D21835
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277441
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Bernard Ogden [Tue, 2 Aug 2016 10:04:03 +0000 (10:04 +0000)]
[ARM] Some saturation instructions not DSP-only
Summary:
Commit 276701 requires that targets have the DSP extensions to use
certain saturating instructions. This requires some corrections.
For ARM ISA the instructions in question are available in all v6*
architectures.
For Thumb2, the instructions in question are available from v6T2.
SSAT and USAT are part of the base architecture while SSAT16 and
USAT16 require the DSP extensions.
Reviewers: rengolin
Subscribers: aemerson, rengolin, samparker, llvm-commits
Differential Revision: https://reviews.llvm.org/D23010
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277439
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Benjamin Kramer [Tue, 2 Aug 2016 09:35:17 +0000 (09:35 +0000)]
[LoadStoreVectorizer] Don't use a linear walk for an existence check in a SmallPtrSet
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277436
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Igor Breger [Tue, 2 Aug 2016 09:15:28 +0000 (09:15 +0000)]
[AVX512] Don't use i128 masked gather/scatter/load/store. Do more accurately dataWidth check.
Differential Revision: http://reviews.llvm.org/D23055
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277435
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Matt Arsenault [Tue, 2 Aug 2016 08:56:52 +0000 (08:56 +0000)]
AArch64: Assert on branch displacement bits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277434
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Matt Arsenault [Tue, 2 Aug 2016 08:30:06 +0000 (08:30 +0000)]
AArch64: Consolidate branch inversion logic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277431
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Matt Arsenault [Tue, 2 Aug 2016 08:06:17 +0000 (08:06 +0000)]
AArch64: BranchRelaxtion cleanups
Move some logic into TII.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277430
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Matt Arsenault [Tue, 2 Aug 2016 07:41:05 +0000 (07:41 +0000)]
AArch64: Add missing branch relaxation tests
The branch relaxation pass has the worst test coverage
of any pass in AArch64. Add a few tests that hit some
large pieces of code in the pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277428
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Matt Arsenault [Tue, 2 Aug 2016 07:20:09 +0000 (07:20 +0000)]
AArch64: Fix end iterator dereference
Not all blocks have terminators. I'm not sure how this wasn't
crashing before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277427
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Craig Topper [Tue, 2 Aug 2016 06:16:53 +0000 (06:16 +0000)]
[AVX-512] Mark VADDPS/PD and VMULPS/PD as commutable. This necessitated adding itineraries to all of the instructions that use the avx512_fp_binop_p class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277422
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Craig Topper [Tue, 2 Aug 2016 06:16:51 +0000 (06:16 +0000)]
[AVX-512] Use SSE_MUL_ITINS_S/SSE_DIV_ITINS_S for the scalar FMUL/FDIV instructions to match SSE/AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277421
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Chandler Carruth [Tue, 2 Aug 2016 05:49:32 +0000 (05:49 +0000)]
[Inliner] Clean up doxygen comments to match modern style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277417
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Craig Topper [Tue, 2 Aug 2016 05:11:15 +0000 (05:11 +0000)]
[AVX-512] Correct ExeDomain for many AVX-512 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277416
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Junmo Park [Tue, 2 Aug 2016 04:38:27 +0000 (04:38 +0000)]
Minor code cleanups. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277415
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Sanjoy Das [Tue, 2 Aug 2016 03:23:22 +0000 (03:23 +0000)]
[Verifier] Improve test coverage for rL277413
As suggest via post-commit review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277414
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Sanjoy Das [Tue, 2 Aug 2016 02:55:57 +0000 (02:55 +0000)]
[Verifier] Disallow illegal ptr<->int casts in ConstantExprs
This should have been a part of rL277085, but I hadn't considered this
case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277413
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Bruno Cardoso Lopes [Tue, 2 Aug 2016 02:53:59 +0000 (02:53 +0000)]
Revert r277408 and r277407
Revert r277408 "Fix test from rL277407."
Revert r277407 "[MC] Fix handling of end-of-line preprocessor comments"
This is currently breaking:
http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_check/20731
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277412
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Sean Silva [Tue, 2 Aug 2016 02:15:45 +0000 (02:15 +0000)]
CodeExtractor : Add ability to preserve profile data.
Added ability to estimate the entry count of the extracted function and
the branch probabilities of the exit branches.
Patch by River Riddle!
Differential Revision: https://reviews.llvm.org/D22744
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277411
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Sanjoy Das [Tue, 2 Aug 2016 01:34:50 +0000 (01:34 +0000)]
Tie the Verifier class to a Module; NFCI
Summary:
This commit changes the Verifier class to accept a Module via the
constructor to make it obvious that a specific instance of the class is
only intended to work with a specific module. The `updateModule` setter
(despite being private) was making this fact less transparent.
There are fields in the `Verifier` class like `DeoptimizeDeclarations`
and `GlobalValueVisited` which are module specific, so a given
Verifier instance will not in fact work across multiple modules today.
This change just makes that more obvious.
The motivation is to make it easy to get to the datalayout of the
module unambiguously. That is required to verify that `inttoptr` and
`ptrtoint` constant expressions are well typed in the face of
non-integral pointer types.
Reviewers: dexonsmith, bkramer, majnemer, chandlerc
Subscribers: mehdi_amini, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D23040
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277409
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Nirav Dave [Tue, 2 Aug 2016 01:27:09 +0000 (01:27 +0000)]
Fix test from rL277407.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277408
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Nirav Dave [Tue, 2 Aug 2016 01:05:29 +0000 (01:05 +0000)]
[MC] Fix handling of end-of-line preprocessor comments
Summary:
When parsing assembly where the line comment syntax is not hash, the
lexer cannot distinguish between hash's that start a hash line comment
and one that is part of an assembly statement and must be distinguished
during parsing. Previously, this was incompletely handled by not checking
for EndOfStatement at the end of statements and interpreting hash
prefixed statements as comments.
Change EndOfStatement Parsing to check for Hash comments and reintroduce
Hash statement parsing to catch previously handled cases.
Reviewers: rnk, majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23017
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277407
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Hans Wennborg [Mon, 1 Aug 2016 23:00:01 +0000 (23:00 +0000)]
Revert r276895 "[MC][X86] Fix Intel Operand assembly parsing for .set ids"
This caused PR28805. Adding a regression test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277402
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Tim Shen [Mon, 1 Aug 2016 22:32:20 +0000 (22:32 +0000)]
[ADT] NFC: Generalize GraphTraits requirement of "NodeType *" in interfaces to "NodeRef", and migrate SCCIterator.h to use NodeRef
Summary: By generalize the interface, users are able to inject more flexible Node token into the algorithm, for example, a pair of vector<Node>* and index integer. Currently I only migrated SCCIterator to use NodeRef, but more is coming. It's a NFC.
Reviewers: dblaikie, chandlerc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D22937
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277399
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Derek Schuff [Mon, 1 Aug 2016 22:25:02 +0000 (22:25 +0000)]
[WebAssembly] Support CFI for WebAssembly target
Summary: This patch implements CFI for WebAssembly. It modifies the
LowerTypeTest pass to pre-assign table indexes to functions that are
called indirectly, and lowers type checks to test against the
appropriate table indexes. It also modifies the WebAssembly backend to
support a special ".indidx" assembly directive that propagates the table
index assignments out to the linker.
Patch by Dominic Chen
Differential Revision: https://reviews.llvm.org/D21768
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277398
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Lang Hames [Mon, 1 Aug 2016 22:23:24 +0000 (22:23 +0000)]
[Orc] Fix common symbol support in ORC.
Common symbol support in ORC was broken in r270716 when the symbol resolution
rules in RuntimeDyld were changed. With the switch to lazily materialized
symbols in r277386, common symbols can be supported by having
RuntimeDyld::emitCommonSymbols search for (but not materialize!) definitions
elsewhere in the logical dylib.
This patch adds the 'Common' flag to JITSymbolFlags, and the necessary check
to RuntimeDyld::emitCommonSymbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277397
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David Blaikie [Mon, 1 Aug 2016 21:50:43 +0000 (21:50 +0000)]
Simplify some code found when it was moved in r277177
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277394
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Michael Kuperstein [Mon, 1 Aug 2016 21:48:33 +0000 (21:48 +0000)]
[PM] Port SpeculativeExecution to the new PM
Differential Revision: https://reviews.llvm.org/D23033
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277393
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Derek Schuff [Mon, 1 Aug 2016 21:34:04 +0000 (21:34 +0000)]
[WebAssembly] Add asm.js-style exception handling support
Summary: This patch includes asm.js-style exception handling support for
WebAssembly. The WebAssembly MVP does not have any support for
unwinding or non-local control flow. In order to support C++ exceptions,
emscripten currently uses JavaScript exceptions along with some support
code (written in JavaScript) that is bundled by emscripten with the
generated code.
This scheme lowers exception-related instructions for wasm such that
wasm modules can be compatible with emscripten's existing scheme and
share the support code.
Patch by Heejin Ahn
Differential Revision: https://reviews.llvm.org/D22958
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277391
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Sumanth Gundapaneni [Mon, 1 Aug 2016 21:28:03 +0000 (21:28 +0000)]
Build llvm with ccache if package is present
This patch has the following changes
The CMake variable LLVM_CCACHE_BUILD is set to OFF by default.
Set this to ON for a ccache enabled build
CCACHE_CPP2 is required to compile the source file directly instead
of compiling the preprocessed file. This will help WERROR is turned ON
for a host clang compiler
The below two options makes more sense in the context of a buildbot
CCACHE_HASHDIR is required to maintain the separate cached data across
builders. This will also help the debuggers to point to the correct source
location
CCACHE_SIZE is important in the perspective of buildbot to increase the
limit on the amount of data to hold in cache for faster compilation
CCACHE_DIR is used to save the cached data to a specific directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277389
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Zachary Turner [Mon, 1 Aug 2016 21:19:45 +0000 (21:19 +0000)]
[msf] Teach LLVM to parse a split Fpm.
The FPM is split at regular intervals across the MSF file, as the MS code
suggests. It turns out that the value of the interval is precisely the
block size. If the block size is 4096, then there are two Fpm pages every
4096 blocks.
So here we teach the PDBFile class to parse a split FPM, and also add more
options when dumping the FPM to display some additional information such
as orphaned pages (pages which the FPM says are allocated, but which
nothing appears to use), use after free pages (pages which the FPM says
are not allocated, but which are referenced by a stream), and multiple use
pages (pages which the FPM says are allocated but are used more than
once).
Reviewed By: ruiu
Differential Revision: https://reviews.llvm.org/D23022
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277388
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Lang Hames [Mon, 1 Aug 2016 20:49:11 +0000 (20:49 +0000)]
[ExecutionEngine][MCJIT][Orc] Replace RuntimeDyld::SymbolInfo with JITSymbol.
This patch replaces RuntimeDyld::SymbolInfo with JITSymbol: A symbol class
that is capable of lazy materialization (i.e. the symbol definition needn't be
emitted until the address is requested). This can be used to support common
and weak symbols in the JIT (though this is not implemented in this patch).
For consistency, RuntimeDyld::SymbolResolver is renamed to JITSymbolResolver.
For space efficiency a new class, JITEvaluatedSymbol, is introduced that
behaves like the old RuntimeDyld::SymbolInfo - i.e. it is just a pair of an
address and symbol flags. Instances of JITEvaluatedSymbol can be used in
symbol-tables to avoid paying the space cost of the materializer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277386
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Krzysztof Parzyszek [Mon, 1 Aug 2016 20:31:50 +0000 (20:31 +0000)]
[Hexagon] Tidy up some code, NFC: reapply r277372 with a fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277383
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Xinliang David Li [Mon, 1 Aug 2016 20:25:06 +0000 (20:25 +0000)]
[Profile] IR profiling minor cleanup /nfc
Differential Revision: http://reviews.llvm.org/D22995
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277379
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Matthew Simpson [Mon, 1 Aug 2016 20:11:25 +0000 (20:11 +0000)]
[LV] Move isGatherOrScatterLegal into LoopVectorizationLegality (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277376
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Matthew Simpson [Mon, 1 Aug 2016 20:08:09 +0000 (20:08 +0000)]
[LV] Use getPointerOperand helper where appropriate (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277375
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Krzysztof Parzyszek [Mon, 1 Aug 2016 20:00:33 +0000 (20:00 +0000)]
Revert r277372, it is causing buildbot failures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277374
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Krzysztof Parzyszek [Mon, 1 Aug 2016 19:46:21 +0000 (19:46 +0000)]
[Hexagon] Tidy up some code, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277372
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Michael Kuperstein [Mon, 1 Aug 2016 19:39:49 +0000 (19:39 +0000)]
[DAGCombine] Make sext(setcc) combine respect getBooleanContents
We used to combine "sext(setcc x, y, cc) -> (select (setcc x, y, cc), -1, 0)"
Instead, we should combine to (select (setcc x, y, cc), T, 0) where the value
of T is 1 or -1, depending on the type of the setcc, and getBooleanContents()
for the type if it is not i1.
This fixes PR28504.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277371
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Ron Lieberman [Mon, 1 Aug 2016 19:36:39 +0000 (19:36 +0000)]
[Hexagon] Generate vector printing instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277370
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George Burgess IV [Mon, 1 Aug 2016 18:47:28 +0000 (18:47 +0000)]
[CFLAA] Remove modref queries from CFLAA.
As it turns out, modref queries are broken with CFLAA. Specifically,
the data source we were using for determining modref behaviors
explicitly ignores operations on non-pointer values. So, it wouldn't
note e.g. storing an i32 to an i32* (or loading an i64 from an i64*).
It also ignores external function calls, rather than acting
conservatively for them.
(N.B. These operations, where necessary, *are* tracked by CFLAA; we just
use a different mechanism to do so. Said mechanism is relatively
imprecise, so it's unlikely that we can provide reasonably good modref
answers with it as implemented.)
Patch by Jia Chen.
Differential Revision: https://reviews.llvm.org/D22978
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277366
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Evandro Menezes [Mon, 1 Aug 2016 18:39:45 +0000 (18:39 +0000)]
[AArch64] Add support for Samsung Exynos M2 (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277364
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George Burgess IV [Mon, 1 Aug 2016 18:27:33 +0000 (18:27 +0000)]
[CFLAA] Make CFLAnders more conservative with new Values.
Currently, CFLAnders assumes that values it hasn't seen don't alias
anything. This patch fixes that. Given that the only way for this to
happen is to query AA, rely on specific transformations happening, then
query AA again (looking for a specific set of queries), lit testing is a
bit difficult. If someone really wants a test, I'm happy to add one.
Patch by Jia Chen.
Differential Revision: https://reviews.llvm.org/D22981
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277362
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David Majnemer [Mon, 1 Aug 2016 18:07:19 +0000 (18:07 +0000)]
Included test for r277360.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277361
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David Majnemer [Mon, 1 Aug 2016 18:06:34 +0000 (18:06 +0000)]
[Verifier] Resume instructions can only be in functions w/ a personality
This fixes PR28799.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277360
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Krzysztof Parzyszek [Mon, 1 Aug 2016 17:55:48 +0000 (17:55 +0000)]
Replace MachineInstr* with MachineInstr& in TargetInstrInfo, NFC
There were a few cases introduced with the modulo scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277358
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Krzysztof Parzyszek [Mon, 1 Aug 2016 17:15:30 +0000 (17:15 +0000)]
[Hexagon] Check for offset overflow when reserving scavenging slots
Scavenging slots were only reserved when pseudo-instruction expansion in
frame lowering created new virtual registers. It is possible to still
need a scavenging slot even if no virtual registers were created, in cases
where the stack is large enough to overflow instruction offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277355
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Nirav Dave [Mon, 1 Aug 2016 15:36:10 +0000 (15:36 +0000)]
Add removed inline-assembly-comment test from r277146
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277349
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Daniel Sanders [Mon, 1 Aug 2016 15:32:51 +0000 (15:32 +0000)]
[mips][fastisel] Correct argument lowering for (f64, f64, i32) and similar.
Summary:
Allocating an AFGR64 shadows two GPR32's instead of just one.
This fixes an LNT regression detected by our internal buildbots.
Reviewers: sdardis
Subscribers: dsanders, sdardis, llvm-commits
Differential Revision: https://reviews.llvm.org/D23012
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277348
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