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Peter Maydell [Thu, 29 May 2014 10:59:26 +0000 (11:59 +0100)]
slirp: Remove unused zero_ethaddr[] variable
The zero_ethaddr[] array is never used; delete it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Sergey Fedorov [Tue, 27 May 2014 12:15:20 +0000 (16:15 +0400)]
qtest: fix hex2nib for capital characters
Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Peter Crosthwaite [Mon, 26 May 2014 08:39:29 +0000 (01:39 -0700)]
net: cadence_gem: Remove &desc[0] usages
Just use desc instead.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Peter Crosthwaite [Mon, 26 May 2014 08:38:55 +0000 (01:38 -0700)]
net: cadence_gem: Comment spelling sweep
Fix some typos in comments.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Peter Crosthwaite [Mon, 26 May 2014 08:38:21 +0000 (01:38 -0700)]
net: cadence_gem: Add Tx descriptor fetch printf
Add a debug printf for TX descriptor fetching. This is helpful to anyone
needing to debug TX ring buffer traversal. It is also now consistent with
the RX code which has a similar printf.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Peter Crosthwaite [Mon, 26 May 2014 08:37:47 +0000 (01:37 -0700)]
net: cadence_gem: Fix Tx descriptor update
The local variable "desc" was being used to read-modify-write the
first descriptor (of a multi-desc packet) upon packet completion.
desc however continues to be used by the code as the current
descriptor. Give this first desc RMW it's own local variable to
avoid trampling.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Peter Maydell [Tue, 10 Jun 2014 11:06:17 +0000 (12:06 +0100)]
Merge remote-tracking branch 'remotes/kraxel/tags/pull-console-
20140610-1' into staging
console: two little bugfixes.
# gpg: Signature made Tue 10 Jun 2014 12:01:07 BST using RSA key ID
D3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>"
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>"
* remotes/kraxel/tags/pull-console-
20140610-1:
console: fix -vga none -sdl crash
console: kill MAX_CONSOLES, alloc consoles dynamically
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Gerd Hoffmann [Mon, 2 Jun 2014 12:07:18 +0000 (14:07 +0200)]
console: fix -vga none -sdl crash
Call get_alloc_displaystate() for proper initialization
instead of allocating with g_new().
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Gerd Hoffmann [Mon, 26 May 2014 08:36:35 +0000 (10:36 +0200)]
console: kill MAX_CONSOLES, alloc consoles dynamically
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Peter Maydell [Tue, 10 Jun 2014 09:59:26 +0000 (10:59 +0100)]
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-
20140610' into staging
Several patches for s390:
- bugfixes: A fix for a long-standing bug in the css code as well as
a fixup for the recent I/O adapter support.
- Exploitation of the userspace cmma enablement/reset interface, if
it is present.
- Some debuggability improvements by logging unmanageable conditions.
- virtio-ccw finally gets migration support for its structures.
- Some cleanup as to how floating interrupts are injected.
# gpg: Signature made Tue 10 Jun 2014 08:57:56 BST using RSA key ID
C6F02FAF
# gpg: Can't check signature: public key not found
* remotes/cohuck/tags/s390x-
20140610:
s390x/kvm: inject via flic
s390x: cleanup interrupt injection
s390x/kvm: add alternative injection interface
s390x: consolidate floating interrupts
s390/virtio-ccw: migration support
s390x/kvm: Log unmanageable program interruptions
s390x/kvm: Log unmanageable external interruptions
s390x/kvm: enable/reset cmma via vm attributes
s390x/kvm: make flic play well with old kernels
s390x/css: handle emw correctly for tsch
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Cornelia Huck [Wed, 12 Mar 2014 11:40:31 +0000 (12:40 +0100)]
s390x/kvm: inject via flic
Try to inject floating interrupts via the flic if it is available.
This allows us to inject the full range of floating interrupts.
Reviewed-by: Jens Freimann <jfrei@linux.vnet.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Cornelia Huck [Tue, 11 Mar 2014 12:19:43 +0000 (13:19 +0100)]
s390x: cleanup interrupt injection
Remove the need for a cpu to inject a floating interrupt on kvm.
Acked-by: Thomas Huth <thuth@linux.vnet.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Cornelia Huck [Tue, 11 Mar 2014 16:10:07 +0000 (17:10 +0100)]
s390x/kvm: add alternative injection interface
Add kvm_s390_{vcpu,floating}_interrupt, which offer the possibility
to inject interrupts with larger payloads (when a kvm backend becomes
available).
Moreover, kvm_s390_floating_interrupt() does no longer have the bogus
requirement for a vcpu.
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Cornelia Huck [Tue, 11 Mar 2014 12:52:06 +0000 (13:52 +0100)]
s390x: consolidate floating interrupts
Move the injection code for all floating interrupts to interrupt.c
and add a comment.
Also get rid of the #ifdef CONFIG_KVM for the service interrupt.
Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Jens Freimann [Tue, 11 Feb 2014 12:29:44 +0000 (13:29 +0100)]
s390/virtio-ccw: migration support
This patch adds live migration support for virtio-ccw devices.
It's not done with vmstate because virtio itself is not yet ported
to vmstate either.
Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Thomas Huth [Wed, 7 May 2014 07:45:21 +0000 (09:45 +0200)]
s390x/kvm: Log unmanageable program interruptions
The kernel only drops to userspace if an endless program interrupt loop
has been detected. Let's print an error message in this case to inform
the user about the crash and stop the affected CPU with a panic event,
just like it is already done for the external interruption loop detection.
Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>
Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com>
Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Thomas Huth [Thu, 20 Mar 2014 20:49:18 +0000 (21:49 +0100)]
s390x/kvm: Log unmanageable external interruptions
Interception code 0x14 only drops to userspace when an unmanageable
external interruption interception occured (e.g. if the External New
PSW does not disable external interruptions). Instead of bailing out
via the default handler, it is better to inform the user with a
proper error message that also includes the bad PSW, and to stop
the affected CPU with a panic event instead.
Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>
Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com>
Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com>
Acked-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Dominik Dingel [Fri, 11 Apr 2014 11:47:40 +0000 (13:47 +0200)]
s390x/kvm: enable/reset cmma via vm attributes
Exploit the new api for userspace-controlled cmma. If supported, enable
cmma during kvm initialization and register a reset handler for cmma,
which is also called directly from the load IPL code.
The reset functionality is needed to reset the cmma state of the guest
pages, e.g. if a system reset is triggered via qemu monitor; otherwise
this could result in data corruption.
A guest triggered reboot may now lead to multiple cmma resets; this is
OK, however, as this is slowpath anyway and the simplest way to achieve
the intended effects.
Signed-off-by: Dominik Dingel <dingel@linux.vnet.ibm.com>
Acked-by: Christian Borntraeger <borntraeger@de.ibm.com>
Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Cornelia Huck [Wed, 28 May 2014 12:15:57 +0000 (14:15 +0200)]
s390x/kvm: make flic play well with old kernels
If we run with an old kernel that does not support KVM_CAP_IRQ_ROUTING,
we don't have to do anything in the ->register_io_adapter and
->io_adapter_map callbacks and therefore should return 0 instead of
-ENOSYS (just as the non-kvm flic does).
This fixes using adapter interrupts when running under an older kernel,
which broke with "s390x: add I/O adapter registration".
Reported-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Cornelia Huck [Tue, 27 May 2014 10:40:44 +0000 (12:40 +0200)]
s390x/css: handle emw correctly for tsch
We should not try to store the emw portion of the irb if extended
measurements are not applicable. In particular, we should not surprise
the guest by storing a larger irb if it did not enable extended
measurements.
Cc: qemu-stable@nongnu.org
Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com>
Tested-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Peter Maydell [Mon, 9 Jun 2014 16:04:13 +0000 (17:04 +0100)]
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-
20140609-1' into staging
----------------------------------------------------------------
target-arm queue:
* support -bios option in vexpress boards
* register the Cortex-A57 impdef system registers
* fix handling of UXN bit in ARMv8 page tables
* complete support of crypto insns in A32/T32
* implement CRC and crypto insns in A64
* fix bugs in generic timer control register
----------------------------------------------------------------
# gpg: Signature made Mon 09 Jun 2014 16:08:26 BST using RSA key ID
14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
* remotes/pmaydell/tags/pull-target-arm-
20140609-1:
target-arm: Delete unused iwmmxt_msadb helper
target-arm: Fix errors in writes to generic timer control registers
target-arm: A64: Implement two-register SHA instructions
target-arm: A64: Implement 3-register SHA instructions
target-arm: A64: Implement AES instructions
target-arm: A32/T32: Mask CRC value in calling code, not helper
target-arm: A64: Implement CRC instructions
target-arm: VFPv4 implies half-precision extension
target-arm: Clean up handling of ARMv8 optional feature bits
target-arm: Remove unnecessary setting of feature bits
target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64
target-arm: A64: Use PMULL feature bit for PMULL
target-arm: add support for v8 VMULL.P64 instruction
target-arm: Allow 3reg_wide undefreq to encode more bad size options
target-arm: add support for v8 SHA1 and SHA256 instructions
target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables
target-arm: Prepare cpreg writefns/readfns for EL3/SecExt
target-arm/cpu64.c: Actually register Cortex-A57 impdef registers
vexpress: Add support for the -bios flag to provide firmware
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Mon, 9 Jun 2014 15:25:34 +0000 (16:25 +0100)]
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging
Tracing pull request
# gpg: Signature made Mon 09 Jun 2014 14:44:18 BST using RSA key ID
81AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>"
# gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>"
* remotes/stefanha/tags/tracing-pull-request:
trace: Replace fprintf with error_report and print location
trace: Multi-backend tracing
trace: Replace error with warning if event is not defined
simpletrace: add support for trace record pid field
trace: add pid field to simpletrace record
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Mon, 9 Jun 2014 14:43:26 +0000 (15:43 +0100)]
target-arm: Delete unused iwmmxt_msadb helper
The iwmmxt_msadb helper and its corresponding gen function are unused;
delete them. (This function appears to have never been used right back
to the initial implementation of iwMMXt; it is identical to iwmmxt_madduq,
and is presumably an accidental remnant from the initial development.)
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1401822125-1822-1-git-send-email-peter.maydell@linaro.org
Peter Maydell [Mon, 9 Jun 2014 14:43:26 +0000 (15:43 +0100)]
target-arm: Fix errors in writes to generic timer control registers
The code for handling writes to the generic timer control registers
had several bugs:
* ISTATUS (bit 2) is read-only but we forced it to zero on any write
* the check for "was IMASK (bit 1) toggled?" incorrectly used '&' where
it should be '^'
* the handling of IMASK was inverted: we should set the IRQ if
ISTATUS is set and IMASK is clear, not if both are set
The combination of these bugs meant that when running a Linux guest
that uses the generic timers we would fairly quickly end up either
forgetting that the timer output should be asserted, or failing to
set the IRQ when the timer was unmasked. The result is that the guest
never gets any more timer interrupts.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1401803208-1281-1-git-send-email-peter.maydell@linaro.org
Cc: qemu-stable@nongnu.org
Peter Maydell [Mon, 9 Jun 2014 14:43:26 +0000 (15:43 +0100)]
target-arm: A64: Implement two-register SHA instructions
Implement the two-register SHA instruction group from the optional
Crypto Extensions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1401458125-27977-10-git-send-email-peter.maydell@linaro.org
Peter Maydell [Mon, 9 Jun 2014 14:43:26 +0000 (15:43 +0100)]
target-arm: A64: Implement 3-register SHA instructions
Implement the 3-register SHA instruction group from the optional
Crypto Extensions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1401458125-27977-9-git-send-email-peter.maydell@linaro.org
Peter Maydell [Mon, 9 Jun 2014 14:43:25 +0000 (15:43 +0100)]
target-arm: A64: Implement AES instructions
Implement the AES instructions from the optional Crypto Extensions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1401458125-27977-8-git-send-email-peter.maydell@linaro.org
Peter Maydell [Mon, 9 Jun 2014 14:43:25 +0000 (15:43 +0100)]
target-arm: A32/T32: Mask CRC value in calling code, not helper
Bring the 32-bit CRC helper functions into line with the A64 ones,
by masking the high bytes of the value in the calling code rather
than the helper. This is more efficient since we can determine the
mask at translation time.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1401458125-27977-7-git-send-email-peter.maydell@linaro.org
Peter Maydell [Mon, 9 Jun 2014 14:43:25 +0000 (15:43 +0100)]
target-arm: A64: Implement CRC instructions
Implement the optional A64 CRC instructions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1401458125-27977-6-git-send-email-peter.maydell@linaro.org
Peter Maydell [Mon, 9 Jun 2014 14:43:25 +0000 (15:43 +0100)]
target-arm: VFPv4 implies half-precision extension
VFPv4 implies the presence of the half-precision floating point
extension (which is optional in VFPv3). Add this implied rule
to arm_cpu_realizefn() and remove some no-longer-needed explicit
setting of the bit in initfns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1401458125-27977-5-git-send-email-peter.maydell@linaro.org
Peter Maydell [Mon, 9 Jun 2014 14:43:24 +0000 (15:43 +0100)]
target-arm: Clean up handling of ARMv8 optional feature bits
CRC and crypto are both optional v8 extensions, so FEATURE_V8
should not imply them. Instead we should set these bits in the
initfns for the 32-bit and 64-bit "cpu any" and for the Cortex-A57.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1401458125-27977-4-git-send-email-peter.maydell@linaro.org
Peter Maydell [Mon, 9 Jun 2014 14:43:24 +0000 (15:43 +0100)]
target-arm: Remove unnecessary setting of feature bits
FEATURE_V8 implies both FEATURE_V7MP and FEATURE_ARM_DIV, so
we don't need to set them explicitly in initfns which set the
V8 feature bit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1401458125-27977-3-git-send-email-peter.maydell@linaro.org
Peter Maydell [Mon, 9 Jun 2014 14:43:24 +0000 (15:43 +0100)]
target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64
The arm_any_initfn() is used only for the 32-bit linux-user "cpu any",
so it only gets called in builds where TARGET_AARCH64 is not defined.
Remove the unreachable line which sets ARM_FEATURE_AARCH64.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1401458125-27977-2-git-send-email-peter.maydell@linaro.org
Peter Maydell [Mon, 9 Jun 2014 14:43:24 +0000 (15:43 +0100)]
target-arm: A64: Use PMULL feature bit for PMULL
Now that we have a separate ARM_FEATURE_V8_PMULL bit, use it for
the A64 PMULL, not the AES feature bit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Mon, 9 Jun 2014 14:43:23 +0000 (15:43 +0100)]
target-arm: add support for v8 VMULL.P64 instruction
Add support for the VMULL.P64 polynomial 64x64 to 128 bit multiplication
instruction in the A32/T32 instruction sets; this is part of the v8
Crypto Extensions.
To do this we have to move the neon_pmull_64_{lo,hi} helpers from
helper-a64.c into neon_helper.c so they can be used by the AArch32
translator.
Inspired-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1401386724-26529-4-git-send-email-peter.maydell@linaro.org
Peter Maydell [Mon, 9 Jun 2014 14:43:23 +0000 (15:43 +0100)]
target-arm: Allow 3reg_wide undefreq to encode more bad size options
The current undefreq field in the neon_3reg_wide handling allows us
to encode "UNDEF if size != 0" and "UNDEF if size == 0". This is
no longer sufficient with the advent of 64-bit polynomial VMULL,
which means we want to UNDEF if size == 1. Change the undefreq
encoding to use separate bits for all of "UNDEF if size == 0",
"UNDEF if size == 1" and "UNDEF if size == 2".
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1401386724-26529-3-git-send-email-peter.maydell@linaro.org
Ard Biesheuvel [Mon, 9 Jun 2014 14:43:23 +0000 (15:43 +0100)]
target-arm: add support for v8 SHA1 and SHA256 instructions
This adds support for the SHA1 and SHA256 instructions that are available
on some v8 implementations of Aarch32.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1401386724-26529-2-git-send-email-peter.maydell@linaro.org
[PMM:
* rebase
* fix bad indent
* add a missing UNDEF check for Q!=1 in the 3-reg SHA1/SHA256 case
* use g_assert_not_reached()
* don't re-extract bit 6 for the 2-reg-misc encodings
* set the ELF HWCAP2 bits for the new features
]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Ian Campbell [Mon, 9 Jun 2014 14:43:23 +0000 (15:43 +0100)]
target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables
In v8 page tables bit 54 in the PTE is UXN in the EL0/EL1 translation regimes
and XN elsewhere. In v7 the bit is always XN. Since we only emulate EL0/EL1 we
can just treat this bit as UXN whenever we are in v8 mode.
Also correctly extract the upper attributes from the PTE entry, the v8 version
tried to avoid extracting the CONTIG bit and ended up with the upper bits being
off-by-one. Instead behave the same as v7 and extract (but ignore) the CONTIG
bit.
This fixes "Bad mode in Synchronous Abort handler detected, code 0x8400000f"
seen when modprobing modules under Linux.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Claudio Fontana <claudio.fontana@huawei.com>
Cc: Rob Herring <robherring2@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Fabian Aggeler [Mon, 9 Jun 2014 14:43:22 +0000 (15:43 +0100)]
target-arm: Prepare cpreg writefns/readfns for EL3/SecExt
This patch changes some readfns/writefns to use raw_write
and raw_read functions, which use the fieldoffset specified
in ARMCPRegInfo instead of directly accessing the field.
This will simplify patches for EL3 & Security Extensions.
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Message-id:
1401962428-14749-1-git-send-email-aggelerf@ethz.ch
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Mon, 9 Jun 2014 14:43:22 +0000 (15:43 +0100)]
target-arm/cpu64.c: Actually register Cortex-A57 impdef registers
cpu64.c contains a reginfo list for the impdef registers on
the Cortex-A57; however we forgot to actually call define_arm_cp_regs(),
so it was sitting there doing nothing. Remedy this omission.
Message-id:
1401226259-23121-1-git-send-email-peter.maydell@linaro.org
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Tested-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Grant Likely [Mon, 9 Jun 2014 14:43:22 +0000 (15:43 +0100)]
vexpress: Add support for the -bios flag to provide firmware
Right now to run firmware inside the QEMU VExpress model requires
padding out the firmware image to the size of the virtual flash and
passing it in via the -pflash argument. If the firmware image is passed
without padding, then QEMU will fail. Also, when passed as a -pflash
argument, QEMU treats the file as persistent storage and will modify the
file.
The -bios flag provides the semantics that we want for providing a
firmware image. This patch maps the contents of the -bios file into the
address space at the boot flash location.
Tested with the vexpress-a15 model and the Tianocore port.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Tested-by: Roy Franz <roy.franz@linaro.org>
[PMM: folded long line, removed stray \n from error message,
use correct variable for printing image name, exit(1) rather than 0]
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Mon, 9 Jun 2014 14:00:21 +0000 (15:00 +0100)]
Merge remote-tracking branch 'remotes/stefanha/tags/net-pull-request' into staging
Net patches
# gpg: Signature made Mon 09 Jun 2014 14:41:34 BST using RSA key ID
81AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>"
# gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>"
* remotes/stefanha/tags/net-pull-request:
e1000: remove broken support for 82573L
tests: e1000: test additional device IDs
e1000: allow command-line selection of card model
vmxnet3: fix msix vectors unuse
net: xilinx_ethlite: Fix Rx-pong interrupt
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alexey Kardashevskiy [Mon, 2 Jun 2014 06:34:10 +0000 (16:34 +1000)]
trace: Replace fprintf with error_report and print location
This replaces fprintf(stderr) with error_report.
This moves local variables to the beginning of the function to comply
with QEMU's coding style.
Suggested-by: Lluís Vilanova <vilanova@ac.upc.edu>
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Lluís Vilanova [Tue, 27 May 2014 13:02:14 +0000 (15:02 +0200)]
trace: Multi-backend tracing
Adds support to compile QEMU with multiple tracing backends at the same time.
For example, you can compile QEMU with:
$ ./configure --enable-trace-backends=ftrace,dtrace
Where 'ftrace' can be handy for having an in-flight record of events, and 'dtrace' can be later used to extract more information from the system.
This patch allows having both available without recompiling QEMU.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Alexey Kardashevskiy [Wed, 21 May 2014 08:16:01 +0000 (18:16 +1000)]
trace: Replace error with warning if event is not defined
At the moment QEMU exits if trace point is not defined which makes
a developer life harder if he has to switch between branches with
different traces implemented.
This replaces error+exit wit WARNING if the tracepoint does not exist or
not traceable.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Wed, 7 May 2014 17:24:11 +0000 (19:24 +0200)]
simpletrace: add support for trace record pid field
Extract the pid field from the trace record and print it.
Change the trace record tuple from:
(event_num, timestamp, arg1, ..., arg6)
to:
(event_num, timestamp, pid, arg1, ..., arg6)
Trace event methods now support 3 prototypes:
1. <event-name>(arg1, arg2, arg3)
2. <event-name>(timestamp, arg1, arg2, arg3)
3. <event-name>(timestamp, pid, arg1, arg2, arg3)
Existing script continue to work without changes, they only know about
prototypes 1 and 2.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Wed, 7 May 2014 17:24:10 +0000 (19:24 +0200)]
trace: add pid field to simpletrace record
It is useful to know the QEMU process ID when working with traces from
multiple VMs. Although the trace filename may contain the pid, tools
that aggregate traces or even trace globally need somewhere to record
the pid.
There is a reserved field in the trace event header struct that we can
use.
It is not necessary to bump the simpletrace file format version number
because it has already been incremented for the QEMU 2.1 release cycle
in commit "trace: [simple] Bump up log version number".
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Gabriel L. Somlo [Mon, 2 Jun 2014 13:33:29 +0000 (09:33 -0400)]
e1000: remove broken support for 82573L
Currently, e1000 support is based on the manual for the 8254xx
model series. 82573x models are documented in a separate manual
(see http://www.intel.com/content/dam/www/public/us/en/documents/manuals/pcie-gbe-controllers-open-source-manual.pdf)
and the 82573L device ID no longer works correctly on either Linux
(3.14.*) or Windows 7.
This patch removes stale code claiming to support 82573L, cleaning
up the code base for the remaining 8254xx model series.
Signed-off-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Gabriel L. Somlo [Mon, 2 Jun 2014 13:33:28 +0000 (09:33 -0400)]
tests: e1000: test additional device IDs
Update e1000-test.c to check all currently supported devices.
Suggested-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Gabriel L. Somlo [Mon, 2 Jun 2014 13:33:27 +0000 (09:33 -0400)]
e1000: allow command-line selection of card model
Allow selection of different card models from the qemu
command line, to better accomodate a wider range of guests.
Signed-off-by: Romain Dolbeau <romain@dolbeau.org>
Signed-off-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Jiri Pirko [Mon, 19 May 2014 13:47:16 +0000 (15:47 +0200)]
vmxnet3: fix msix vectors unuse
In vmxnet3_cleanup_msix(), there is called msix_vector_unuse() with
VMXNET3_MAX_INTRS. That is not correct since vector of
value VMXNET3_MAX_INTRS was never used. Also all the used vectors
are not un-used. So call vmxnet3_unuse_msix_vectors() instead which
does the correct job.
Signed-off-by: Jiri Pirko <jiri@resnulli.us>
Acked-by: Dmitry Fleytman <dmitry@daynix.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Peter Crosthwaite [Tue, 6 May 2014 04:39:38 +0000 (21:39 -0700)]
net: xilinx_ethlite: Fix Rx-pong interrupt
There is no CTRL_I bit in the pong buffer control register. The
CTRL_I bit from the ping buffer masks both ping and pong buffers.
Fix.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Peter Maydell [Mon, 9 Jun 2014 10:54:22 +0000 (11:54 +0100)]
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging
Block pull request
# gpg: Signature made Fri 06 Jun 2014 17:08:50 BST using RSA key ID
81AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>"
# gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>"
* remotes/stefanha/tags/block-pull-request: (42 commits)
qapi: Extract qapi/block.json definitions
qapi: Extract qapi/block-core.json definitions
qapi: create two block related json modules
qapi: Extract qapi/common.json definitions
sheepdog: reload only header in a case of live snapshot
sheepdog: fix vdi object update after live snapshot
rbd: Fix leaks in rbd_start_aio() error path
qemu-img: Document check exit codes
block: fix wrong order in live block migration setup
blockdev: acquire AioContext in block_set_io_throttle
throttle: add detach/attach test case
throttle: add throttle_detach/attach_aio_context()
dataplane: Support VIRTIO_BLK_T_SCSI_CMD
virtio-blk: Factor out virtio_blk_handle_scsi_req from virtio_blk_handle_scsi
virtio-blk: Allow config-wce in dataplane
block: Move declaration of bdrv_get_aio_context to block.h
raw-posix: drop raw_get_aio_fd() since it is no longer used
dataplane: implement async flush
dataplane: delete IOQueue since it is no longer used
dataplane: use the QEMU block layer for I/O
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Samuel Thibault [Wed, 14 May 2014 01:13:09 +0000 (03:13 +0200)]
slirp/arp: do not special-case bogus IP addresses
Do not special-case addresses with zero host part, as we do not
necessarily know how big it is, and the guest can fake them anyway.
Silently avoid having 0.0.0.0 as a destination, however.
Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
[Edgar: Minor change to subject]
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Peter Maydell [Sat, 7 Jun 2014 17:03:02 +0000 (18:03 +0100)]
target-cris/translate.c: Remove _t_gen_mov_TN_env and _t_gen_mov_env_TN
The wrapper functions _t_gen_mov_TN_env and _t_gen_mov_env_TN are only
used via their accompanying non-underscore macros. The check they add
on offset is thus pointless, since the compiler will complain if the
struct field passed to the macro is not part of the struct. Remove the
functions and make the macros directly expand to the appropriate
tcg_gen_{ld,st}_tl calls.
This conveniently avoids a warning due to _t_gen_mov_TN_env() being
unused.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Peter Maydell [Sat, 7 Jun 2014 17:03:01 +0000 (18:03 +0100)]
target-cris/translate.c: Remove t_gen_mov_TN_reg and t_gen_mov_reg_TN
Remove the t_gen_mov_TN_reg and t_gen_mov_reg_TN wrappers: the
latter is completely unused, and the former only used in a few
places (which are thus inconsistent with the rest of the decoder
which directly accesses cpu_R[]).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Peter Crosthwaite [Thu, 29 May 2014 09:26:12 +0000 (02:26 -0700)]
intc: xilinx_uartlite: Convert SBD::init -> instance_init
SysBusDevice::init is depracated. Convert to Object::init
as prescribed by QOM conventions.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Peter Crosthwaite [Thu, 29 May 2014 09:25:37 +0000 (02:25 -0700)]
char: xilinx_uartlite: Convert to realize()
SysBusDevice::init is depracated. Convert to Object::init and
Device::realize as prescribed by QOM conventions.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Peter Crosthwaite [Thu, 29 May 2014 09:25:03 +0000 (02:25 -0700)]
char: xilinx_uartlite: Don't reset from init
This refresh of the device state is intended to be a reset side
effect. Move it to a proper reset handler rather than do it at
init time.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Peter Crosthwaite [Thu, 29 May 2014 09:24:29 +0000 (02:24 -0700)]
net: xilinx_ethlite: Convert to realize()
SysBusDevice::init is depracated. Convert to Object::init and
Device::realize as prescribed by QOM conventions.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Peter Crosthwaite [Thu, 29 May 2014 09:23:54 +0000 (02:23 -0700)]
net: xilinx_ethlite: Don't reset from init
This zeroing-out of the rxbuf variable (ping pong state) is a reset
side effect. Extract into a proper reset.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Peter Crosthwaite [Thu, 29 May 2014 09:23:20 +0000 (02:23 -0700)]
timer: xilinx_timer: Convert to realize()
SysBusDevice::init is depracated. Convert to Object::init and
Device::realize as prescribed by QOM conventions.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Benoît Canet [Thu, 5 Jun 2014 11:45:32 +0000 (13:45 +0200)]
qapi: Extract qapi/block.json definitions
Signed-off-by: Benoit Canet <benoit@irqsave.net>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Benoît Canet [Thu, 5 Jun 2014 11:45:31 +0000 (13:45 +0200)]
qapi: Extract qapi/block-core.json definitions
Signed-off-by: Benoit Canet <benoit@irqsave.net
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Benoît Canet [Thu, 5 Jun 2014 11:45:30 +0000 (13:45 +0200)]
qapi: create two block related json modules
qapi/block-core.json contains block definitions unrelated to emulation.
qapi/block.json is a superset of the previous and contains definitions related
to emulation.
The purpose of these extractions is to be able to hook qapi/block-core.json
generated code on qemu-nbd.
Signed-off-by: Benoit Canet <benoit@irqsave.net>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Benoît Canet [Thu, 5 Jun 2014 11:45:29 +0000 (13:45 +0200)]
qapi: Extract qapi/common.json definitions
Signed-off-by: Benoit Canet <benoit@irqsave.net>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Hitoshi Mitake [Fri, 6 Jun 2014 04:35:12 +0000 (13:35 +0900)]
sheepdog: reload only header in a case of live snapshot
sheepdog driver doesn't need to read data_vdi_id[] when a live snapshot is
created.
Cc: Kevin Wolf <kwolf@redhat.com>
Cc: Stefan Hajnoczi <stefanha@redhat.com>
Cc: Liu Yuan <namei.unix@gmail.com>
Cc: MORITA Kazutaka <morita.kazutaka@lab.ntt.co.jp>
Signed-off-by: Hitoshi Mitake <mitake.hitoshi@lab.ntt.co.jp>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Hitoshi Mitake [Fri, 6 Jun 2014 04:35:11 +0000 (13:35 +0900)]
sheepdog: fix vdi object update after live snapshot
sheepdog driver should decide a write request is COW or not based on inode
object which is active when the write request is issued.
Example of wrong inode update path in the previous driver:
1. drier issues an ordinal write request to an existing object
2. user creates a snapshot of the VDI before the write request is completed
3. the respones for the request is RDONLY, because the VDI is already a snapshot
4. the driver reload an inode object of the new active VDI, then issues a write
request again
5. the second write request can be completed
6. driver decide the request is COW or not with the below conditional branch:
if (s->inode.data_vdi_id[idx] != s->inode.vdi_id) {
7. the ID of the written object and VID of the new active VDI is different, so
the driver updates data_vdi_id[idx] and writes inode object
8. the existing object cannot be seen by the new active VDI, it results object
leaking
Cc: Kevin Wolf <kwolf@redhat.com>
Cc: Stefan Hajnoczi <stefanha@redhat.com>
Cc: Liu Yuan <namei.unix@gmail.com>
Cc: MORITA Kazutaka <morita.kazutaka@lab.ntt.co.jp>
Signed-off-by: Hitoshi Mitake <mitake.hitoshi@lab.ntt.co.jp>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Kevin Wolf [Thu, 5 Jun 2014 14:19:26 +0000 (16:19 +0200)]
rbd: Fix leaks in rbd_start_aio() error path
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Benoit Canet <benoit@irqsave.net>
Reviewed-by: Josh Durgin <josh.durgin@inktank.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Peter Maydell [Thu, 5 Jun 2014 22:05:07 +0000 (23:05 +0100)]
Merge remote-tracking branch 'remotes/mcayland/qemu-sparc' into staging
* remotes/mcayland/qemu-sparc:
apb: implement IOMMU translation for PCI host bridge
apb: handle reading/writing of IOMMU control registers
apb: fix IOMMU register sizes
apb: Move IOMMU registers into a separate IOMMUState struct
tcx: move initialisation from realizefn to initfn
tcx: move initialisation from SysBusDevice class to TCX class realizefn
cg3: add extra check to prevent CG3 register array overflow
cg3: move initialisation from realizefn to initfn
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Thu, 5 Jun 2014 21:40:44 +0000 (22:40 +0100)]
Merge remote-tracking branch 'remotes/mdroth/qga-pull-2014-06-05' into staging
* remotes/mdroth/qga-pull-2014-06-05:
qga: Fix handle fd leak in acquire_privilege()
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Thu, 5 Jun 2014 20:52:37 +0000 (21:52 +0100)]
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
pc,pci,virtio,qdev fixes, tests
new tests for SMBIOS
SMBIOS fixes
pc, pci fixes
qdev patches stayed on list for a month with no review,
as I told people on KVM forum I'm merging stuch patches
if they look fine.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* remotes/mst/tags/for_upstream:
qdev: Add test of qdev_prop_check_global
qdev: Display warning about unused -global
tests: add smbios testing
tests: rename acpi-test to bios-tables-test
virtio-balloon: return empty data when no stats are available
pcie_host: Turn pcie_host_init() into an instance_init
SMBIOS: Fix type 17 field sizes
SMBIOS: Update Type 0 struct generator for machines >= 2.1
SMBIOS: Fix endian-ness when populating multi-byte fields
serial-pci: Set prog interface field of pci config to 16550 compatible
Conflicts:
include/hw/i386/pc.h
[PMM: fixed trivial conflict in pc.h]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Thu, 5 Jun 2014 20:06:13 +0000 (21:06 +0100)]
Merge remote-tracking branch 'remotes/bonzini/softmmu-smap' into staging
* remotes/bonzini/softmmu-smap: (33 commits)
target-i386: cleanup x86_cpu_get_phys_page_debug
target-i386: fix protection bits in the TLB for SMEP
target-i386: support long addresses for 4MB pages (PSE-36)
target-i386: raise page fault for reserved bits in large pages
target-i386: unify reserved bits and NX bit check
target-i386: simplify pte/vaddr calculation
target-i386: raise page fault for reserved physical address bits
target-i386: test reserved PS bit on PML4Es
target-i386: set correct error code for reserved bit access
target-i386: introduce support for 1 GB pages
target-i386: introduce do_check_protect label
target-i386: tweak handling of PG_NX_MASK
target-i386: commonize checks for PAE and non-PAE
target-i386: commonize checks for 4MB and 4KB pages
target-i386: commonize checks for 2MB and 4KB pages
target-i386: fix coding standards in x86_cpu_handle_mmu_fault
target-i386: simplify SMAP handling in MMU_KSMAP_IDX
target-i386: fix kernel accesses with SMAP and CPL = 3
target-i386: move check_io helpers to seg_helper.c
target-i386: rename KSMAP to KNOSMAP
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Mark Cave-Ayland [Wed, 28 May 2014 07:28:22 +0000 (08:28 +0100)]
apb: implement IOMMU translation for PCI host bridge
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Wed, 28 May 2014 07:28:22 +0000 (08:28 +0100)]
apb: handle reading/writing of IOMMU control registers
While the registers are documented as being 64-bit, Linux seems to access
them in two halves as 2 x 32-bit accesses. Make sure that we can correctly
handle this case.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Wed, 28 May 2014 07:28:21 +0000 (08:28 +0100)]
apb: fix IOMMU register sizes
According to the referenced documentation, the IOMMU has 3 64-bit registers
consisting of a control register, base register and flush register.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Wed, 28 May 2014 07:28:21 +0000 (08:28 +0100)]
apb: Move IOMMU registers into a separate IOMMUState struct
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Sat, 24 May 2014 11:44:53 +0000 (12:44 +0100)]
tcx: move initialisation from realizefn to initfn
Initialisation cleanup as suggested by Andreas.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
CC: Andreas Färber <afaerber@suse.de>
Mark Cave-Ayland [Sat, 24 May 2014 11:19:44 +0000 (12:19 +0100)]
tcx: move initialisation from SysBusDevice class to TCX class realizefn
This is an intermediate step to bring TCX in line with CG3.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
CC: Andreas Färber <afaerber@suse.de>
Mark Cave-Ayland [Sat, 24 May 2014 10:51:50 +0000 (11:51 +0100)]
cg3: add extra check to prevent CG3 register array overflow
The case statements in the CG3 read and write register routines have a maximum
value of CG3_REG_SIZE, so if a value were written to this offset then it
would overflow the register array.
Currently this cannot be exploited since the MemoryRegion restricts accesses
to the range 0 ... CG3_REG_SIZE - 1, but it seems worth clarifying this for
future review and/or static analysis.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
CC: Paolo Bonzini <pbonzini@redhat.com>
Mark Cave-Ayland [Sat, 24 May 2014 10:42:36 +0000 (11:42 +0100)]
cg3: move initialisation from realizefn to initfn
Initialisation cleanup as suggested by Andreas.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
CC: Andreas Färber <afaerber@suse.de>
Peter Maydell [Thu, 5 Jun 2014 19:11:50 +0000 (20:11 +0100)]
Merge remote-tracking branch 'remotes/rth/tcg-next' into staging
* remotes/rth/tcg-next:
TCG: Fix tcg_gen_extr_i64_tl for 32bit
tcg: Remove TCG_TARGET_HAS_new_ldst
tci: Convert to new ldst opcodes
tcg-i386: Fix win64 qemu store
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Thu, 5 Jun 2014 18:16:28 +0000 (19:16 +0100)]
Merge remote-tracking branch 'remotes/kvm/uq/master' into staging
* remotes/kvm/uq/master:
kvm: Fix eax for cpuid leaf 0x40000000
kvmclock: Ensure proper env->tsc value for kvmclock_current_nsec calculation
kvm: Enable -cpu option to hide KVM
kvm: Ensure negative return value on kvm_init() error handling path
target-i386: set CC_OP to CC_OP_EFLAGS in cpu_load_eflags
target-i386: get CPL from SS.DPL
target-i386: rework CPL checks during task switch, preparing for next patch
target-i386: fix segment flags for SMM and VM86 mode
target-i386: Fix vm86 mode regression introduced in
fd460606fd6f.
kvm_stat: allow choosing between tracepoints and old stats
kvmclock: Ensure time in migration never goes backward
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Thu, 5 Jun 2014 17:58:53 +0000 (18:58 +0100)]
Merge remote-tracking branch 'remotes/kraxel/tags/pull-input-10' into staging
updates for docs/multiseat.txt
input: add support for kbd delays
# gpg: Signature made Wed 04 Jun 2014 08:22:39 BST using RSA key ID
D3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>"
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>"
* remotes/kraxel/tags/pull-input-10:
docs/multiseat.txt: add note about spice
docs/multiseat.txt: gtk joined the party
docs/multiseat.txt: use autoseat
input/vnc: use kbd delays in press_key
input/curses: add kbd delay between keydown and keyup events
input: use kbd delays for send_key monitor command
input: add support for kbd delays
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Don Slutz [Mon, 5 May 2014 18:03:07 +0000 (14:03 -0400)]
qdev: Add test of qdev_prop_check_global
This will generate a warning from "make check":
...
GTESTER tests/test-qdev-global-props
Warning: "-global dynamic-prop-type-bad.prop3=103" not used
GTESTER tests/check-qom-interface
...
If the warning is not generated, the test will fail.
Signed-off-by: Don Slutz <dslutz@verizon.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Don Slutz [Mon, 5 May 2014 18:03:06 +0000 (14:03 -0400)]
qdev: Display warning about unused -global
This can help a user understand why -global was ignored.
For example: with "-vga cirrus"; "-global vga.vgamem_mb=16" is just
ignored when "-global cirrus-vga.vgamem_mb=16" is not.
This is currently clear when the wrong property is provided:
out/x86_64-softmmu/qemu-system-x86_64 -global cirrus-vga.vram_size_mb=16 -monitor pty -vga cirrus
char device redirected to /dev/pts/20 (label compat_monitor0)
qemu-system-x86_64: Property '.vram_size_mb' not found
Aborted (core dumped)
vs
out/x86_64-softmmu/qemu-system-x86_64 -global vga.vram_size_mb=16 -monitor pty -vga cirrus
char device redirected to /dev/pts/20 (label compat_monitor0)
VNC server running on `::1:5900'
^Cqemu: terminating on signal 2
Signed-off-by: Don Slutz <dslutz@verizon.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Paolo Bonzini [Tue, 27 May 2014 12:58:47 +0000 (14:58 +0200)]
target-i386: cleanup x86_cpu_get_phys_page_debug
Make the code a bit more similar to x86_cpu_handle_mmu_fault.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 27 May 2014 11:24:54 +0000 (13:24 +0200)]
target-i386: fix protection bits in the TLB for SMEP
User pages must be marked as non-executable when running under SMEP;
otherwise, fetching the page first and then calling it will fail.
With this patch, all SMEP testcases in kvm-unit-tests now pass.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 27 May 2014 10:31:28 +0000 (12:31 +0200)]
target-i386: support long addresses for 4MB pages (PSE-36)
4MB pages can use 40-bit addresses by putting the higher 8 bits in bits
20-13 of the PDE. Bit 21 is reserved.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 27 May 2014 11:03:17 +0000 (13:03 +0200)]
target-i386: raise page fault for reserved bits in large pages
In large pages, bit 12 is for PAT, but bits starting at 13 are reserved.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 27 May 2014 11:58:46 +0000 (13:58 +0200)]
target-i386: unify reserved bits and NX bit check
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 27 May 2014 12:44:49 +0000 (14:44 +0200)]
target-i386: simplify pte/vaddr calculation
They can moved to after the dirty bit processing, and unified between
CR0.PG=1 and CR0.PG=0.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 27 May 2014 10:58:36 +0000 (12:58 +0200)]
target-i386: raise page fault for reserved physical address bits
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 27 May 2014 10:39:23 +0000 (12:39 +0200)]
target-i386: test reserved PS bit on PML4Es
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 27 May 2014 10:16:08 +0000 (12:16 +0200)]
target-i386: set correct error code for reserved bit access
The correct error code is 9 (present, reserved), not 8.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Fri, 4 Apr 2014 06:12:28 +0000 (08:12 +0200)]
target-i386: introduce support for 1 GB pages
Given the simplifications to the code in the previous patches, this
is now very simple to do.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Fri, 4 Apr 2014 06:11:48 +0000 (08:11 +0200)]
target-i386: introduce do_check_protect label
This will help adding 1GB page support in the next patch.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Fri, 4 Apr 2014 06:04:18 +0000 (08:04 +0200)]
target-i386: tweak handling of PG_NX_MASK
Remove the tail of the PAE case, so that we can use "goto" in the
next patch to jump to the protection checks.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Fri, 4 Apr 2014 06:00:40 +0000 (08:00 +0200)]
target-i386: commonize checks for PAE and non-PAE
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Fri, 4 Apr 2014 05:57:02 +0000 (07:57 +0200)]
target-i386: commonize checks for 4MB and 4KB pages
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>