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Mandeep Singh Grang [Sat, 2 Mar 2019 00:14:10 +0000 (00:14 +0000)]
[llvm] Fix typo: 's/analsyis/analysis/' [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355246
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Daniel Sanders [Sat, 2 Mar 2019 00:12:57 +0000 (00:12 +0000)]
[tblgen] Track CodeInit origins when possible
Summary:
Add an SMLoc to CodeInit that records the source line it originated from.
This allows tablegen to point precisely at portions of code when reporting
errors within the CodeInit. For example, in the upcoming GlobalISel
combiner, it can report undefined expansions and point at the instance of
the expansion. This is achieved using something like:
SMLoc::getFromPointer(SMLoc::getPointer() +
(StringRef - CodeInit::getValue()))
The location is lost when producing a CodeInit by string concatenation so
a fallback SMLoc is required (e.g. the Record::getLoc()) but that's pretty
rare for CodeInits.
There's a reasonable case for extending tracking of a couple other Init
objects, for example StringInit's are often parsed and it would be good to
point inside the string when reporting errors about that. However, location
tracking also harms de-duplication. This is fine for CodeInit where there's
only a few hundred of them (~160 for X86) and it may be worth it for
StringInit (~86k up to ~1.9M for roughly 15MB increase for X86).
However the origin tracking would be a _terrible_ idea for IntInit, BitInit,
and UnsetInit. I haven't measured either of those three but BitInit would
most likely be on the order of increasing the current 2 BitInit values up
to billions.
Reviewers: volkan, aditya_nandakumar, bogner, paquette, aemerson
Reviewed By: paquette
Subscribers: javed.absar, kristof.beyls, dexonsmith, llvm-commits, kristina
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58141
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355245
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Caroline Tice [Fri, 1 Mar 2019 23:51:54 +0000 (23:51 +0000)]
llvm-dwarfdump: Add new variable, parameter and inlining statistics; also function source location statistics.
Add statistics for abstract origins, function, variable and parameter
locations; break the 'variable' counts down into variables and
parameters. Also update call site counting to check for
DW_AT_call_{file,line} in addition to DW_TAG_call_site.
Differential revision: https://reviews.llvm.org/D58849
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355243
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Paul Robinson [Fri, 1 Mar 2019 22:28:13 +0000 (22:28 +0000)]
Try to fix Windows bots after r355226.
Windows has two path separator characters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355235
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Jonas Devlieghere [Fri, 1 Mar 2019 22:14:24 +0000 (22:14 +0000)]
[DWARFFormValue] Cleanup DWARFFormValue interface. (2/2) (NFC)
Continues the work started in r354941. Changes (all but one) uses of the
extractValue to static createFromData.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355233
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Craig Topper [Fri, 1 Mar 2019 21:02:40 +0000 (21:02 +0000)]
[X86] Remove IntrArgMemOnly from target specific gather/scatter intrinsics
IntrArgMemOnly implies that only memory pointed to by pointer typed arguments will be accessed. But these intrinsics allow you to pass null to the pointer argument and put the full address into the index argument. Other passes won't be able to understand this.
A colleague found that ISPC was creating gathers like this and then dead store elimination removed some stores because it didn't understand what the gather was doing since the pointer argument was null.
Differential Revision: https://reviews.llvm.org/D58805
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355228
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Craig Topper [Fri, 1 Mar 2019 21:02:34 +0000 (21:02 +0000)]
[X86] Add test case for D58805. NFC
This demonstrates dead store elimination removing a store that may alias a gather that uses null as its base.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355227
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Paul Robinson [Fri, 1 Mar 2019 20:58:04 +0000 (20:58 +0000)]
[DWARF] Make -g with empty assembler source work better.
This was sometimes causing clang or llvm-mc to crash, and in other
cases could emit a bogus DWARF line-table header. I did an interim
patch in r352541; this patch should be a cleaner and more complete
fix, and retains the test.
Addresses PR40538.
Differential Revision: https://reviews.llvm.org/D58750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355226
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Craig Topper [Fri, 1 Mar 2019 20:18:38 +0000 (20:18 +0000)]
[TableGen][SelectionDAG][X86] Add specific isel matchers for immAllZerosV/immAllOnesV. Remove bitcasts from X86 patterns that are no longer necessary.
Previously we had build_vector PatFrags that called ISD::isBuildVectorAllZeros/Ones. Internally the ISD::isBuildVectorAllZeros/Ones look through bitcasts, but we aren't able to take advantage of that in isel. Instead of we have to canonicalize the types of the all zeros/ones build_vectors and insert bitcasts. Then we have to pattern match those exact bitcasts.
By emitting specific matchers for these 2 nodes, we can make isel look through any bitcasts without needing to explicitly match them. We should also be able to remove the canonicalization to vXi32 from lowering, but I've left that for a follow up.
This removes something like 40,000 bytes from the X86 isel table.
Differential Revision: https://reviews.llvm.org/D58595
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355224
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Nikita Popov [Fri, 1 Mar 2019 20:07:04 +0000 (20:07 +0000)]
[ValueTracking] Known bits support for unsigned saturating add/sub
We have two sources of known bits:
1. For adds leading ones of either operand are preserved. For sub
leading zeros of LHS and leading ones of RHS become leading zeros in
the result.
2. The saturating math is a select between add/sub and an all-ones/
zero value. As such we can carry out the add/sub known bits
calculation, and only preseve the known one/zero bits respectively.
Differential Revision: https://reviews.llvm.org/D58329
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355223
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Philip Reames [Fri, 1 Mar 2019 19:50:36 +0000 (19:50 +0000)]
[InstCombine] Extend saturating idempotent atomicrmw transform to FP
I'm assuming that the nan propogation logic for InstructonSimplify's handling of fadd and fsub is correct, and applying the same to atomicrmw.
Differential Revision: https://reviews.llvm.org/D58836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355222
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Sanjay Patel [Fri, 1 Mar 2019 19:42:40 +0000 (19:42 +0000)]
[InstCombine] move add after umin/umax
In the motivating cases from PR14613:
https://bugs.llvm.org/show_bug.cgi?id=14613
...moving the add enables us to narrow the
min/max which eliminates zext/trunc which
enables signficantly better vectorization.
But that bug is still not completely fixed.
https://rise4fun.com/Alive/5KQ
Name: umax
Pre: C1 u>= C0
%a = add nuw i8 %x, C0
%cond = icmp ugt i8 %a, C1
%r = select i1 %cond, i8 %a, i8 C1
=>
%c2 = icmp ugt i8 %x, C1-C0
%u2 = select i1 %c2, i8 %x, i8 C1-C0
%r = add nuw i8 %u2, C0
Name: umin
Pre: C1 u>= C0
%a = add nuw i32 %x, C0
%cond = icmp ult i32 %a, C1
%r = select i1 %cond, i32 %a, i32 C1
=>
%c2 = icmp ult i32 %x, C1-C0
%u2 = select i1 %c2, i32 %x, i32 C1-C0
%r = add nuw i32 %u2, C0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355221
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Sanjay Patel [Fri, 1 Mar 2019 19:42:34 +0000 (19:42 +0000)]
[InstCombine] add tests for umin/umax narrowing (PR14613); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355220
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Vlad Tsyrklevich [Fri, 1 Mar 2019 18:58:22 +0000 (18:58 +0000)]
Revert "[MIPS GlobalISel] Fix mul operands"
This reverts commit r355178, it is causing ASan failures on the
sanitizer bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355219
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Peter Collingbourne [Fri, 1 Mar 2019 18:53:41 +0000 (18:53 +0000)]
ELF: Change FileSize back to a uint64_t.
This lets us detect file size overflows when creating a 64-bit binary on
a 32-bit machine.
Differential Revision: https://reviews.llvm.org/D58840
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355218
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Philip Reames [Fri, 1 Mar 2019 18:45:05 +0000 (18:45 +0000)]
[LICM] Infer proper alignment from loads during scalar promotion
This patch fixes an issue where we would compute an unnecessarily small alignment during scalar promotion when no store is not to be guaranteed to execute, but we've proven load speculation safety. Since speculating a load requires proving the existing alignment is valid at the new location (see Loads.cpp), we can use the alignment fact from the load.
For non-atomics, this is a performance problem. For atomics, this is a correctness issue, though an *incredibly* rare one to see in practice. For atomics, we might not be able to lower an improperly aligned load or store (i.e. i32 align 1). If such an instruction makes it all the way to codegen, we *may* fail to codegen the operation, or we may simply generate a slow call to a library function. The part that makes this super hard to see in practice is that the memory location actually *is* well aligned, and instcombine knows that. So, to see a failure, you have to have a) hit the bug in LICM, b) somehow hit a depth limit in InstCombine/ValueTracking to avoid fixing the alignment, and c) then have generated an instruction which fails codegen rather than simply emitting a slow libcall. All around, pretty hard to hit.
Differential Revision: https://reviews.llvm.org/D58809
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355217
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Rong Xu [Fri, 1 Mar 2019 18:36:24 +0000 (18:36 +0000)]
[PGO] Remove the default parameter in ProfileSummary API. NFC
Remove the default parameter in setProfileSummary() and getSummary().
This is a follow-up of r355131.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355216
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Philip Reames [Fri, 1 Mar 2019 18:24:05 +0000 (18:24 +0000)]
[Tests] More missing atomicrmw combines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355215
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Philip Reames [Fri, 1 Mar 2019 18:10:37 +0000 (18:10 +0000)]
[Tests] Add tests for missed optimizations of saturating and idempotent FP atomicrmws
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355212
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Philip Reames [Fri, 1 Mar 2019 18:00:07 +0000 (18:00 +0000)]
[InstCombine] Extend "idempotent" atomicrmw optimizations to floating point
An idempotent atomicrmw is one that does not change memory in the process of execution. We have already added handling for the various integer operations; this patch extends the same handling to floating point operations which were recently added to IR.
Note: At the moment, we canonicalize idempotent fsub to fadd when ordering requirements prevent us from using a load. As discussed in the review, I will be replacing this with canonicalizing both floating point ops to integer ops in the near future.
Differential Revision: https://reviews.llvm.org/D58251
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355210
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Thomas Lively [Fri, 1 Mar 2019 17:43:55 +0000 (17:43 +0000)]
Revert "[WebAssembly] Lower SIMD shifts since they are fixed in V8"
They weren't fixed in V8. Oops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355208
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Matt Davis [Fri, 1 Mar 2019 17:31:32 +0000 (17:31 +0000)]
[llvm-readobj] Display section names for STT_SECTION symbols.
Summary:
This patch will obtain the section name for symbols that refer to a section. Prior to this patch the Name field for STT_SECTIONs was blank, now it is populated.
Before:
```
Symbol table '.symtab' contains 6 entries:
Num: Value Size Type Bind Vis Ndx Name
0:
0000000000000000 0 NOTYPE LOCAL DEFAULT UND
1:
0000000000000000 0 SECTION LOCAL DEFAULT 1
2:
0000000000000000 0 SECTION LOCAL DEFAULT 3
3:
0000000000000000 0 SECTION LOCAL DEFAULT 4
4:
0000000000000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_
5:
0000000000000000 0 TLS GLOBAL DEFAULT UND sym
```
With this patch:
```
Symbol table '.symtab' contains 6 entries:
Num: Value Size Type Bind Vis Ndx Name
0:
0000000000000000 0 NOTYPE LOCAL DEFAULT UND
1:
0000000000000000 0 SECTION LOCAL DEFAULT 1 .text
2:
0000000000000000 0 SECTION LOCAL DEFAULT 3 .data
3:
0000000000000000 0 SECTION LOCAL DEFAULT 4 .bss
4:
0000000000000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_
5:
0000000000000000 0 TLS GLOBAL DEFAULT UND sym
```
This fixes PR40788
Reviewers: jhenderson, rupprecht, espindola
Reviewed By: rupprecht
Subscribers: emaste, javed.absar, arichardson, MaskRay, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58796
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355207
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Sanjay Patel [Fri, 1 Mar 2019 17:29:10 +0000 (17:29 +0000)]
[InstCombine] add tests for add+umin/umax canonicalization; NFC
Fixing this should solve the biggest part of the vector problems seen in:
https://bugs.llvm.org/show_bug.cgi?id=14613
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355206
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Jonas Hahnfeld [Fri, 1 Mar 2019 17:15:21 +0000 (17:15 +0000)]
Hide two unused debugging methods, NFCI.
GCC correctly moans that PlainCFGBuilder::isExternalDef(llvm::Value*) and
StackSafetyDataFlowAnalysis::verifyFixedPoint() are defined but not used
in Release builds. Hide them behind 'ifndef NDEBUG'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355205
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Manman Ren [Fri, 1 Mar 2019 15:25:24 +0000 (15:25 +0000)]
Try to fix NetBSD buildbot breakage introduced in D57463.
By including the header file in the source.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355202
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Oliver Stannard [Fri, 1 Mar 2019 14:20:28 +0000 (14:20 +0000)]
[ARM] Fix FP16 stack loads/stores for Thumb2 with frame pointer
The new addressing mode added for the v8.2A FP16 instructions uses bit 8 of the
immediate to encode the sign of the offset, like the other FP loads/stores, so
need to be treated the same way.
Differential revision: https://reviews.llvm.org/D58816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355201
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Oliver Stannard [Fri, 1 Mar 2019 13:58:25 +0000 (13:58 +0000)]
[ARM] Consider undefined-on-NaN conditions in checkVSELConstraints
This function was not checking for the condition code variants which are
undefined if either input is NaN, so we were missing selection of the VSEL
instruction in some cases when using -fno-honor-nans or -ffast-math.
Differential revision: https://reviews.llvm.org/D58812
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355199
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Simon Pilgrim [Fri, 1 Mar 2019 13:13:40 +0000 (13:13 +0000)]
[X86] Regenerate legalize test files
Noticed while getting update_mir_test_checks.py to work on python3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355198
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Simon Pilgrim [Fri, 1 Mar 2019 12:08:50 +0000 (12:08 +0000)]
[Thumb] Add some integer abs testcases for different typesizes.
Committed on behalf of @ikulagin (Ivan Kulagin)
Differential Revision: https://reviews.llvm.org/D52138
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355197
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George Rimar [Fri, 1 Mar 2019 10:18:16 +0000 (10:18 +0000)]
[yaml2obj] - Allow setting custom sh_info for RawContentSection sections.
This is for tweaking SHT_SYMTAB sections.
Their sh_info contains the (number of symbols + 1) usually.
But for creating invalid inputs for test cases it would be convenient
to allow explicitly override this field from YAML.
Differential revision: https://reviews.llvm.org/D58779
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355193
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Alexey Lapshin [Fri, 1 Mar 2019 10:15:18 +0000 (10:15 +0000)]
Attempt to fix buildbot after r354972 [#2]. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355192
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Diana Picus [Fri, 1 Mar 2019 10:12:28 +0000 (10:12 +0000)]
[ARM GlobalISel] Support G_CTLZ for Thumb2
Same as ARM mode but with different opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355191
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Diana Picus [Fri, 1 Mar 2019 10:01:22 +0000 (10:01 +0000)]
[ARM GlobalISel] Check target flags in test. NFCI
There was a time when we couldn't dump target-specific flags such as
arm-sbrel etc, so the tests didn't check for them. We can now be more
specific in our tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355189
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Nicola Zaghen [Fri, 1 Mar 2019 09:46:29 +0000 (09:46 +0000)]
[Tablegen] Add support for the !mul operator.
This is a small addition to arithmetic operations that improves
expressiveness of the language.
Differential Revision: https://reviews.llvm.org/D58775
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355187
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Oliver Stannard [Fri, 1 Mar 2019 09:26:21 +0000 (09:26 +0000)]
[ARM] Add armv8a triple to test check updaters
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355186
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Igor Kudrin [Fri, 1 Mar 2019 09:22:42 +0000 (09:22 +0000)]
[CommandLine] Allow grouping options which can have values.
This patch allows all forms of values for options to be used at the end
of a group. With the fix, it is possible to follow the way GNU binutils
tools handle grouping options better. For example, the -j option can be
used with objdump in any of the following ways:
$ objdump -d -j .text a.o
$ objdump -d -j.text a.o
$ objdump -dj .text a.o
$ objdump -dj.text a.o
Differential Revision: https://reviews.llvm.org/D58711
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355185
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Igor Kudrin [Fri, 1 Mar 2019 09:20:56 +0000 (09:20 +0000)]
[CommandLine] Do not crash if an option has both ValueRequired and Grouping.
If an option, which requires a value, has a `cl::Grouping` formatting
modifier, it works well as far as it is used at the end of a group,
or as a separate argument. However, if the option appears accidentally
in the middle of a group, the program just crashes. This patch prints
an error message instead.
Differential Revision: https://reviews.llvm.org/D58499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355184
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James Henderson [Fri, 1 Mar 2019 09:12:38 +0000 (09:12 +0000)]
[llvm-readobj]Add test showing behaviour of thin archive member path printing
This was a test requested in https://reviews.llvm.org/D58677.
Reviewed by: rupprecht, grimar, Higuoxing
Differential Revision: https://reviews.llvm.org/D5877
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355183
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Stanislav Mekhanoshin [Fri, 1 Mar 2019 07:59:17 +0000 (07:59 +0000)]
[AMDGPU] Mark ds instructions as meybeAtomic
These were not recognized as potential atomics by memory legalizer.
The test was working not because legalizer did a right thing, but
because it has skipped all these instructions. When I have fixed
DS desciption test started to fail because region address has
changed from 4 to 2 a while ago.
Differential Revision: https://reviews.llvm.org/D58802
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355179
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Petar Avramovic [Fri, 1 Mar 2019 07:35:57 +0000 (07:35 +0000)]
[MIPS GlobalISel] Fix mul operands
Unsigned mul high for MIPS32 is selected into two PseudoInstructions:
PseudoMULTu and PseudoMFHI that use accumulator register class ACC64 for
some of its operands. Registers in this class have appropriate hi and lo
register as subregisters: $lo0 and $hi0 are subregisters of $ac0 etc.
mul instruction implicit-defs $lo0 and $hi0 according to MipsInstrInfo.td.
In functions where mul and PseudoMULTu are present fastRegisterAllocator
will "run out of registers during register allocation" because
'calcSpillCost' for $ac0 will return spillImpossible because subregisters
$lo0 and $hi0 of $ac0 are reserved by mul instruction above. A solution is
to mark implicit-defs of $lo0 and $hi0 as dead in mul instruction.
Differential Revision: https://reviews.llvm.org/D58715
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355178
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Petar Avramovic [Fri, 1 Mar 2019 07:25:44 +0000 (07:25 +0000)]
[MIPS GlobalISel] Select G_UMULH
Legalize G_UMULO and select G_UMULH for MIPS32.
Differential Revision: https://reviews.llvm.org/D58714
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355177
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Fangrui Song [Fri, 1 Mar 2019 05:27:01 +0000 (05:27 +0000)]
[ConstantHoisting] Call cleanup() in ConstantHoistingPass::runImpl to avoid dangling elements in ConstIntInfoVec for new PM
Summary:
ConstIntInfoVec contains elements extracted from the previous function.
In new PM, releaseMemory() is not called and the dangling elements can
cause segfault in findConstantInsertionPoint.
Rename releaseMemory() to cleanup() to deliver the idea that it is
mandatory and call cleanup() in ConstantHoistingPass::runImpl to fix
this.
Reviewers: ormris, zzheng, dmgreen, wmi
Reviewed By: ormris, wmi
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58589
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355174
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Craig Topper [Fri, 1 Mar 2019 02:19:26 +0000 (02:19 +0000)]
[Subtarget] Remove static global constructor call from the tablegened subtarget feature tables
Subtarget features are stored in a std::bitset that has been subclassed. There is a special constructor to allow the tablegen files to provide a list of bits to initialize the std::bitset to. This constructor isn't constexpr and std::bitset doesn't support many constexpr operations either. This results in a static global constructor being used to initialize the feature bitsets in these files at startup.
To fix this I've introduced a new FeatureBitArray class that holds three 64-bit values representing the initial bit values and taught tablegen to emit hex constants for them based on the feature enum values. This makes the tablegen files less readable than they were before. I can add the list of features back as a comment if we think that's important.
I've added a method to convert from this class into the std::bitset subclass we had before. I considered making the new FeatureBitArray class just implement the std::bitset interface we need instead, but thought I'd see how others felts about that first.
I've simplified the interfaces to SetImpliedBits and ClearImpliedBits a little minimize the number of times we need to convert to the bitset.
This removes about 27K from my local release+asserts build of llc.
Differential Revision: https://reviews.llvm.org/D58520
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355167
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Thomas Lively [Fri, 1 Mar 2019 01:38:54 +0000 (01:38 +0000)]
[WebAssembly] Lower SIMD shifts since they are fixed in V8
Reviewers: sbc100
Subscribers: dschuff, jgravelle-google, hiraditya, aheejin, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58800
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355163
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Tom Stellard [Fri, 1 Mar 2019 00:50:26 +0000 (00:50 +0000)]
AMDGPU/GlobalISel: Implement select for G_INSERT
Re-commit r344310.
Reviewers: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D53116
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355159
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Thomas Lively [Fri, 1 Mar 2019 00:12:13 +0000 (00:12 +0000)]
[WebAssembly] Fix crash when @llvm.global_dtors is external
Reviewers: aheejin
Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355157
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Tom Stellard [Thu, 28 Feb 2019 23:37:48 +0000 (23:37 +0000)]
AMDGPU/GlobalISel: Implement select for G_EXTRACT
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D49714
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355156
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Joerg Sonnenberger [Thu, 28 Feb 2019 23:33:09 +0000 (23:33 +0000)]
[PPC] Secure PLT only has meaning for PIC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355154
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Reid Kleckner [Thu, 28 Feb 2019 22:54:30 +0000 (22:54 +0000)]
[sancov] Instrument reachable blocks that end in unreachable
Summary:
These sorts of blocks often contain calls to noreturn functions, like
longjmp, throw, or trap. If they don't end the program, they are
"interesting" from the perspective of sanitizer coverage, so we should
instrument them. This was discussed in https://reviews.llvm.org/D57982.
Reviewers: kcc, vitalybuka
Subscribers: llvm-commits, craig.topper, efriedma, morehouse, hiraditya
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355152
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Peter Collingbourne [Thu, 28 Feb 2019 22:42:55 +0000 (22:42 +0000)]
llvm-readobj: Try the DWARF CFI dumper on all machines.
There's no reason to limit the DWARF CFI dumper to EM_386 and EM_X86_64;
ELF files could contain DWARF CFI on almost any platform (even 32-bit ARM;
NetBSD uses DWARF CFI on that platform). So start using the DWARF CFI dumper
unconditionally so that we can dump .eh_frame sections on the remaining ELF
platforms as well as in NetBSD binaries.
Differential Revision: https://reviews.llvm.org/D58761
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355151
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Adrian Prantl [Thu, 28 Feb 2019 22:26:00 +0000 (22:26 +0000)]
Update testcase since llvm-dwarfdump got more accurate in r355148.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355150
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Adrian Prantl [Thu, 28 Feb 2019 22:12:32 +0000 (22:12 +0000)]
dsymutil support for DW_OP_convert
Add support for cloning DWARF expressions that contain base type DIE
references in dsymutil.
<rdar://problem/
48167812>
Differential Revision: https://reviews.llvm.org/D58534
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355148
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Peter Collingbourne [Thu, 28 Feb 2019 22:12:09 +0000 (22:12 +0000)]
gn build: Merge r355133.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355147
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Nico Weber [Thu, 28 Feb 2019 22:08:18 +0000 (22:08 +0000)]
gn build: Merge r355035
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355146
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Nico Weber [Thu, 28 Feb 2019 22:07:37 +0000 (22:07 +0000)]
gn build: Merge r355024
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355145
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Manman Ren [Thu, 28 Feb 2019 20:48:19 +0000 (20:48 +0000)]
Trying to fix bot breakage due to symbols not defined for WINDOWS!
Follow up to r355133
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355139
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Eli Friedman [Thu, 28 Feb 2019 20:38:45 +0000 (20:38 +0000)]
[AArch64] [Windows] Don't skip constructing UnwindHelp.
In certain cases, the first non-frame-setup instruction in a function is
a branch. For example, it could be a cbz on an argument. Make sure we
correctly allocate the UnwindHelp, and find an appropriate register to
use to initialize it.
Fixes https://bugs.llvm.org/show_bug.cgi?id=40184
Differential Revision: https://reviews.llvm.org/D58752
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355136
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Eli Friedman [Thu, 28 Feb 2019 20:33:22 +0000 (20:33 +0000)]
[AArch64] [Windows] Fix llvm-readobj -unwind output with many epilogs.
The number of epilog scopes may not fit into a uint8_t.
Fixes https://bugs.llvm.org/show_bug.cgi?id=40855
Differential Revision: https://reviews.llvm.org/D58693
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355135
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Abderrazek Zaafrani [Thu, 28 Feb 2019 20:21:46 +0000 (20:21 +0000)]
[AArch64] Improve FP16 vector convert from short instructions.
https://reviews.llvm.org/D58563
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355134
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Manman Ren [Thu, 28 Feb 2019 20:13:38 +0000 (20:13 +0000)]
Add a module pass for order file instrumentation
The basic idea of the pass is to use a circular buffer to log the execution ordering of the functions. We only log the function when it is first executed. We use a 8-byte hash to log the function symbol name.
In this pass, we add three global variables:
(1) an order file buffer: a circular buffer at its own llvm section.
(2) a bitmap for each module: one byte for each function to say if the function is already executed.
(3) a global index to the order file buffer.
At the function prologue, if the function has not been executed (by checking the bitmap), log the function hash, then atomically increase the index.
Differential Revision: https://reviews.llvm.org/D57463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355133
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Rong Xu [Thu, 28 Feb 2019 19:55:07 +0000 (19:55 +0000)]
[PGO] Context sensitive PGO (part 2)
Part 2 of CSPGO changes (mostly related to ProfileSummary).
Note that I use a default parameter in setProfileSummary() and getSummary().
This is to break the dependency in clang. I will make the parameter explicit
after changing clang in a separated patch.
Differential Revision: https://reviews.llvm.org/D54175
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355131
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Sanjay Patel [Thu, 28 Feb 2019 19:47:04 +0000 (19:47 +0000)]
[x86] scalarize extract element 0 of FP math
This is another step towards ensuring that we produce the optimal code for reductions,
but there are other potential benefits as seen in the tests diffs:
1. Memory loads may get scalarized resulting in more efficient code.
2. Memory stores may get scalarized resulting in more efficient code.
3. Complex ops like fdiv/sqrt get scalarized which may be faster instructions depending on uarch.
4. Even simple ops like addss/subss/mulss/roundss may result in faster operation/less frequency throttling when scalarized depending on uarch.
The TODO comment suggests 1 or more follow-ups for opcodes that can currently result in regressions.
Differential Revision: https://reviews.llvm.org/D58282
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355130
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Jiong Wang [Thu, 28 Feb 2019 19:22:34 +0000 (19:22 +0000)]
bpf: disassembler support for XADD under sub-register mode
Like the other load/store instructions, "w" register is preferred when
disassembling BPF_STX | BPF_W | BPF_XADD.
v1 -> v2:
- Updated testcase insn-unit.s (Yonghong)
Acked-by: Yonghong Song <yhs@fb.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355127
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Jiong Wang [Thu, 28 Feb 2019 19:21:28 +0000 (19:21 +0000)]
bpf: enable sub-register code-gen for XADD
Support sub-register code-gen for XADD is like supporting any other Load
and Store patterns.
No new instruction is introduced.
lock *(u32 *)(r1 + 0) += w2
has exactly the same underlying insn as:
lock *(u32 *)(r1 + 0) += r2
BPF_W width modifier has guaranteed they behave the same at runtime. This
patch merely teaches BPF back-end that BPF_W width modifier could work
GPR32 register class and that's all needed for sub-register code-gen
support for XADD.
test/CodeGen/BPF/xadd.ll updated to include sub-register code-gen tests.
A new testcase test/CodeGen/BPF/xadd_legal.ll is added to make sure the
legal case could pass on all code-gen modes. It could also test dead Def
check on GPR32. If there is no proper handling like what has been done
inside BPFMIChecking.cpp:hasLivingDefs, then this testcase will fail.
Acked-by: Yonghong Song <yhs@fb.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355126
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Jiong Wang [Thu, 28 Feb 2019 19:20:26 +0000 (19:20 +0000)]
bpf: improve dead Defs check for XADD
BPF XADD semantics require all Defs of XADD are dead, meaning any result of
XADD insn is not used.
However, BPF backend hasn't enabled sub-register liveness track, so when
the source and destination operands of XADD are GPR32, there is no
sub-register dead info. If we rely on the generic
MachineInstr::allDefsAreDead, then we will raise false alarm on GPR32 Def.
This was fine as there was no sub-register code-gen support for XADD which
will be added by the next patch.
To support GPR32 Def, ideally we could just enable sub-registr liveness
track on BPF backend, then allDefsAreDead could work on GPR32 Def. This
requires implementing TargetSubtargetInfo::enableSubRegLiveness on BPF.
However, sub-register liveness tracking module inside LLVM is actually
designed for the situation where one register could be split into more
than one sub-registers for which case each sub-register could have their
own liveness and kill one of them doesn't kill others. So, tracking
liveness for each make sense.
For BPF, each 64-bit register could only have one 32-bit sub-register. This
is exactly the case which LLVM think brings no benefits for doing
sub-register tracking, because the live range of sub-register must always
equal to its parent register, therefore liveness tracking is disabled even
the back-end has implemented enableSubRegLiveness. The detailed information
is at r232695:
Author: Matthias Braun <matze@braunis.de>
Date: Thu Mar 19 00:21:58 2015 +0000
Do not track subregister liveness when it brings no benefits
Hence, for BPF, we enhance MachineInstr::allDefsAreDead. Given the solo
sub-register always has the same liveness as its parent register, LLVM is
already attaching a implicit 64-bit register Def whenever the there is
a sub-register Def. The liveness of the implicit 64-bit Def is available.
For example, for "lock *(u32 *)(r0 + 4) += w9", the MachineOperand info
could be:
$w9 = XADDW32 killed $r0, 4, $w9(tied-def 0),
implicit killed $r9, implicit-def dead $r9
Even though w9 is not marked as Dead, the parent register r9 is marked as
Dead correctly, and it is safe to use such information or our purpose.
v1 -> v2:
- Simplified code logic inside hasLiveDefs. (Yonghong)
Acked-by: Yonghong Song <yhs@fb.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355124
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Serge Guelton [Thu, 28 Feb 2019 19:16:17 +0000 (19:16 +0000)]
Add Support for Creating and Deleting Unicode Files and Directories in Lit
This enables lit to work with unicode file names via mkdir, rm, and redirection.
Lit still uses utf-8 internally, but converts to utf-16 on Windows, or just utf-8
bytes on everything else.
Committed on behalf of Jason Mittertreiner
Differential Revision: https://reviews.llvm.org/D56754
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355122
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Sanjay Patel [Thu, 28 Feb 2019 19:05:26 +0000 (19:05 +0000)]
[InstCombine] fold adds of constants separated by sext/zext
This is part of a transform that may be done in the backend:
D13757
...but it should always be beneficial to fold this sooner in IR
for all targets.
https://rise4fun.com/Alive/vaiW
Name: sext add nsw
%add = add nsw i8 %i, C0
%ext = sext i8 %add to i32
%r = add i32 %ext, C1
=>
%s = sext i8 %i to i32
%r = add i32 %s, sext(C0)+C1
Name: zext add nuw
%add = add nuw i8 %i, C0
%ext = zext i8 %add to i16
%r = add i16 %ext, C1
=>
%s = zext i8 %i to i16
%r = add i16 %s, zext(C0)+C1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355118
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Craig Topper [Thu, 28 Feb 2019 18:50:16 +0000 (18:50 +0000)]
[X86] Add test case that was supposed to go with r355116.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355117
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Craig Topper [Thu, 28 Feb 2019 18:49:29 +0000 (18:49 +0000)]
[X86] Don't peek through bitcasts before checking ISD::isBuildVectorOfConstantSDNodes in combineTruncatedArithmetic
We don't have any combines that can look through a bitcast to truncate a build vector of constants. So the truncate will stick around and give us something like this pattern (binop (trunc X), (trunc (bitcast (build_vector)))) which has two truncates in it. Which will be reversed by hoistLogicOpWithSameOpcodeHands in the generic DAG combiner. Thus causing an infinite loop.
Even if we had a combine for (truncate (bitcast (build_vector))), I think it would need to be implemented in getNode otherwise DAG combiner visit ordering would probably still visit the binop first and reverse it. Or combineTruncatedArithmetic would need to do its own constant folding.
Differential Revision: https://reviews.llvm.org/D58705
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355116
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Amara Emerson [Thu, 28 Feb 2019 18:47:29 +0000 (18:47 +0000)]
Revert "[AArch64][GlobalISel] Add support for 64 bit vector shuffle using TBL1."
Seems to break some neon intrinsics tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355115
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Jonas Devlieghere [Thu, 28 Feb 2019 18:46:04 +0000 (18:46 +0000)]
[dsymutil] Use rfind for paths with parentheses
Dsymutil gets library member information is through the ambiguous
/path/to/archive.a(member.o). The current logic we use would get
confused by additional parentheses. Using rfind mitigates this issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355114
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Thomas Lively [Thu, 28 Feb 2019 18:39:08 +0000 (18:39 +0000)]
[WebAssembly] Remove uses of ThreadModel
Summary:
In the clang UI, replaces -mthread-model posix with -matomics as the
source of truth on threading. In the backend, replaces
-thread-model=posix with the atomics target feature, which is now
collected on the WebAssemblyTargetMachine along with all other used
features. These collected features will also be used to emit the
target features section in the future.
The default configuration for the backend is thread-model=posix and no
atomics, which was previously an invalid configuration. This change
makes the default valid because the thread model is ignored.
A side effect of this change is that objects are never emitted with
passive segments. It will instead be up to the linker to decide
whether sections should be active or passive based on whether atomics
are used in the final link.
Reviewers: aheejin, sbc100, dschuff
Subscribers: mehdi_amini, jgravelle-google, hiraditya, sunfish, steven_wu, dexonsmith, rupprecht, jfb, jdoerfert, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D58742
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355112
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Philip Reames [Thu, 28 Feb 2019 18:17:51 +0000 (18:17 +0000)]
[Tests] Strengthen LICM test corpus to show alignment striping. (part 2)
This should have been part of r355110, but my brain isn't quite awake yet, despite the coffee. Per the original submit comment... Doing scalar promotion w/o being able to prove the alignment of the hoisted load or sunk store is a bug. Update tests to actually show the alignment so that impact of the patch which fixes this can be seen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355111
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Philip Reames [Thu, 28 Feb 2019 18:08:04 +0000 (18:08 +0000)]
[Tests] Strengthen LICM test corpus to show alignment striping
Doing scalar promotion w/o being able to prove the alignment of the hoisted load or sunk store is a bug. Update tests to actually show the alignment so that impact of the patch which fixes this can be seen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355110
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Nikita Popov [Thu, 28 Feb 2019 18:04:20 +0000 (18:04 +0000)]
[ValueTracking] More accurate unsigned sub overflow detection
Second part of D58593.
Compute precise overflow conditions based on all known bits, rather
than just the sign bits. Unsigned a - b overflows iff a < b, and we
can determine whether this always/never happens based on the minimal
and maximal values achievable for a and b subject to the known bits
constraint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355109
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Tom Stellard [Thu, 28 Feb 2019 17:31:59 +0000 (17:31 +0000)]
llvm-config: Include -stdlib= in --cxxflags
Summary:
This was removed in r349068, but it is needed when llvm is compiled
using the non-default c++ standard library on a platform.
Reviewers: sylvestre.ledru, infinity0, mgorny, cuviper
Reviewed By: sylvestre.ledru
Subscribers: jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D57859
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355107
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Chijun Sima [Thu, 28 Feb 2019 16:47:18 +0000 (16:47 +0000)]
Make MergeBlockIntoPredecessor conformant to the precondition of calling DTU.applyUpdates
Summary:
It is mentioned in the document of DTU that "It is illegal to submit any update that has already been submitted, i.e., you are supposed not to insert an existent edge or delete a nonexistent edge." It is dangerous to violet this rule because DomTree and PostDomTree occasionally crash on this scenario.
This patch fixes `MergeBlockIntoPredecessor`, making it conformant to this precondition.
Reviewers: kuhar, brzycki, chandlerc
Reviewed By: brzycki
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58444
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355105
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Amara Emerson [Thu, 28 Feb 2019 16:43:11 +0000 (16:43 +0000)]
[AArch64][GlobalISel] Add support for 64 bit vector shuffle using TBL1.
This extends the existing support for shufflevector to handle cases like
<2 x float>, which we can implement by concating the vectors and using a TBL1.
Differential Revision: https://reviews.llvm.org/D58684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355104
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Kadir Cetinkaya [Thu, 28 Feb 2019 15:55:11 +0000 (15:55 +0000)]
[Target][ARM] Add a usage for SrcSz to unbreak build-bots without assertions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355101
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Bjorn Pettersson [Thu, 28 Feb 2019 15:45:29 +0000 (15:45 +0000)]
Add support for computing "zext of value" in KnownBits. NFCI
Summary:
The description of KnownBits::zext() and
KnownBits::zextOrTrunc() has confusingly been telling
that the operation is equivalent to zero extending the
value we're tracking. That has not been true, instead
the user has been forced to explicitly set the extended
bits as known zero afterwards.
This patch adds a second argument to KnownBits::zext()
and KnownBits::zextOrTrunc() to control if the extended
bits should be considered as known zero or as unknown.
Reviewers: craig.topper, RKSimon
Reviewed By: RKSimon
Subscribers: javed.absar, hiraditya, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58650
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355099
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Stefan Pintilie [Thu, 28 Feb 2019 12:40:28 +0000 (12:40 +0000)]
[PowerPC] Removed STATISTIC that was causing build errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355087
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Stefan Pintilie [Thu, 28 Feb 2019 12:23:28 +0000 (12:23 +0000)]
[PowerPC] Move the stack pointer update instruction later in the prologue and earlier in the epilogue.
Move the stdu instruction in the prologue and epilogue.
This should provide a small performance boost in functions that are able to do
this. I've kept this change rather conservative at the moment and functions
with frame pointers or base pointers will not try to move the stack pointer
update.
Differential Revision: https://reviews.llvm.org/D42590
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355085
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Simon Pilgrim [Thu, 28 Feb 2019 11:39:52 +0000 (11:39 +0000)]
[X86][AVX] Remove superfluous insert_subvector(zero, bitcast(x)) -> bitcast(insert_subvector(zero, x)) fold
This is caught by other existing bitcast folds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355084
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Diana Picus [Thu, 28 Feb 2019 11:13:05 +0000 (11:13 +0000)]
[ARM GlobalISel] Make arm_i32imm an IntImmLeaf
This gets rid of some duplication in the TableGen definition, but it
forces us to keep both a pointer and a reference to the subtarget in the
ARMInstructionSelector. That is pretty ugly but it might be a reasonable
trade-off, since the TableGen descriptions should outlive the code in
the selector (or in the worst case we can update to use just the
reference when we get rid of DAGISel).
Differential Revision: https://reviews.llvm.org/D58031
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355083
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Dmitri Gribenko [Thu, 28 Feb 2019 10:58:13 +0000 (10:58 +0000)]
Fixed typos in a test: s/CEHCK/CHECK/
Reviewers: ilya-biryukov, serge-sans-paille
Subscribers: delcypher, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58613
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355080
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Dmitri Gribenko [Thu, 28 Feb 2019 10:56:39 +0000 (10:56 +0000)]
Fixed a typo in the test s/CEHCK/CHECK/
Summary:
Turns out the test was not correct, I had to adjust the test to work. I
also added CHECK-LABELs for better error messages from FileCheck while
I'm here.
Reviewers: jsji
Subscribers: nemanjai, eraman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58614
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355079
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Simon Pilgrim [Thu, 28 Feb 2019 10:53:58 +0000 (10:53 +0000)]
[X86][AVX] Fold vf64 concat_vectors(movddup(x),movddup(x)) -> broadcast(x)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355078
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Diana Picus [Thu, 28 Feb 2019 10:42:47 +0000 (10:42 +0000)]
[ARM GlobalISel] Support global variables for Thumb2
Add the same level of support as for ARM mode (i.e. still no TLS
support).
In most cases, it is sufficient to replace the opcodes with the
t2-equivalent, but there are some idiosyncrasies that I decided to
preserve because I don't understand the full implications:
* For ARM we use LDRi12 to load from constant pools, but for Thumb we
use t2LDRpci (I'm not sure if the ideal would be to use t2LDRi12 for
Thumb as well, or to use LDRcp for ARM).
* For Thumb we don't have an equivalent for MOV|LDRLIT_ga_pcrel_ldr, so
we have to generate MOV|LDRLIT_ga_pcrel plus a load from GOT.
The tests are in separate files because they're hard enough to read even
without doubling the number of checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355077
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George Rimar [Thu, 28 Feb 2019 08:21:50 +0000 (08:21 +0000)]
[llvm-objdump] - Improve the error message for "removing a section that is used by relocation" case.
This refines/improves the error message introduced in D58625
Differential revision: https://reviews.llvm.org/D58709
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355074
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George Rimar [Thu, 28 Feb 2019 08:15:59 +0000 (08:15 +0000)]
[llvm-readobj] - Fix the invalid dumping of the dynamic sections without terminating DT_NULL entry.
This is https://bugs.llvm.org/show_bug.cgi?id=40861,
Previously llvm-readobj would print the DT_NULL sometimes
for the dynamic section that has no terminator entry.
The logic of printDynamicTable was a bit overcomplicated.
I rewrote it slightly to fix the issue and commented.
Differential revision: https://reviews.llvm.org/D58716
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355073
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Nikita Popov [Thu, 28 Feb 2019 08:11:20 +0000 (08:11 +0000)]
[ValueTracking] More accurate unsigned add overflow detection
Part of D58593.
Compute precise overflow conditions based on all known bits, rather
than just the sign bits. Unsigned a + b overflows iff a > ~b, and we
can determine whether this always/never happens based on the minimal
and maximal values achievable for a and ~b subject to the known bits
constraint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355072
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Craig Topper [Thu, 28 Feb 2019 07:21:26 +0000 (07:21 +0000)]
[X86] Use PreprocessISelDAG to convert vector sra/srl/shl to the X86 specific variable shift ISD opcodes.
These allows use to use the same set of isel patterns for sra/srl/shl which are undefined for out of range shifts and intrinsic shifts which aren't undefined.
Doing this late allows DAG combine to have every opportunity to optimize the sra/srl/shl nodes.
This removes about 7000 bytes from the isel table and simplies the td files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355071
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Fangrui Song [Thu, 28 Feb 2019 05:16:01 +0000 (05:16 +0000)]
[Dominators] Avoid potentially quadratic std::is_permutation
Summary:
If the two sequences are not equal, std::is_permutation may be O(N^2)
and indeed the case in libstdc++ and libc++. Use SmallPtrSet to prevent
pessimizing cases. On my machine, SmallPtrSet starts to outperform
std::is_permutation when there are 16 elements.
Reviewers: kuhar
Reviewed By: kuhar
Subscribers: kristina, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355070
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Philip Reames [Thu, 28 Feb 2019 04:07:23 +0000 (04:07 +0000)]
[SelectionDAG] Strengthen assertions about usage of AtomicSDNodes
In D57601, I described the expectations around usage of AtomicSDNode and LoadSDNode/StoreSDNode w.r.t. atomic and volatiles. This patch simply embeds those expectations in assertions so that they can't be accidentally weakened.
Note: The reason only AtomicSDNodes of ATOMIC_LOAD and ATOMIC_STORE opcode are currently checked is that AMDGPU has an intrinsic which gets lowered to an ATOMIC_LOAD_FADD w/o a corresponding atomic MMO. This is suspicious, and I've brought it to the attention of the relevant developers. Once resolved, I'll strengthen that assertion.
Note 2: If this breaks your out-of-tree backend, go read the update instructions associated w/the previously mentioned patch. This will assert on (a subset of) things you need to update per those instructions.
Differential Revision: https://reviews.llvm.org/D58738
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355069
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Richard Trieu [Thu, 28 Feb 2019 04:00:55 +0000 (04:00 +0000)]
Fix IR/Analysis layering issue with OptBisect
OptBisect is in IR due to LLVMContext using it. However, it uses IR units from
Analysis as well. This change moves getDescription functions from OptBisect
to their respective IR units. Generating names for IR units will now be up
to the callers, keeping the Analysis IR units in Analysis. To prevent
unnecessary string generation, isEnabled function is added so that callers know
when the description needs to be generated.
Differential Revision: https://reviews.llvm.org/D58406
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355068
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Alexandre Ganea [Thu, 28 Feb 2019 03:42:07 +0000 (03:42 +0000)]
Fix SupportTests.exe/AllocationTests/MappedMemoryTest.AllocAndReleaseHuge when the machine doesn't have large pages enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355067
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Alexandre Ganea [Thu, 28 Feb 2019 03:03:07 +0000 (03:03 +0000)]
Fix non-Windows platforms build break introduced by r355065. Fixes:
In file included from /home/buildbots/ppc64le-lld-multistage-test/ppc64le-lld-multistage-test/llvm/lib/Support/Memory.cpp:14:
/home/buildbots/ppc64le-lld-multistage-test/ppc64le-lld-multistage-test/llvm/include/llvm/Support/Memory.h:38:14: error: private field 'Flags' is not used [-Werror,-Wunused-private-field]
unsigned Flags = 0;
^
1 error generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355066
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Alexandre Ganea [Thu, 28 Feb 2019 02:47:34 +0000 (02:47 +0000)]
[Memory] Add basic support for large/huge memory pages
This patch introduces Memory::MF_HUGE_HINT which indicates that allocateMappedMemory() shall return a pointer to a large memory page.
However the flag is a hint because we're not guaranteed in any way that we will get back a large memory page. There are several restrictions:
- Large/huge memory pages aren't enabled by default on modern OSes (Windows 10 and Linux at least), and should be manually enabled/reserved.
- Once enabled, it should be kept in mind that large pages are physical only, they can't be swapped.
- Memory fragmentation can affect the availability of large pages, especially after running the OS for a long time and/or running along many other applications.
Memory::allocateMappedMemory() will fallback to 4KB pages if it can't allocate 2MB large pages (if Memory::MF_HUGE_HINT is provided)
Currently, Memory::MF_HUGE_HINT only works on Windows. The hint will be ignored on Linux, 4KB pages will always be returned.
Differential Revision: https://reviews.llvm.org/D58718
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355065
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Eric Christopher [Thu, 28 Feb 2019 01:11:12 +0000 (01:11 +0000)]
Temporarily revert "ArgumentPromotion should copy all metadata to new Function" and the dependent patch "Refine ArgPromotion metadata handling" as they're causing segfaults in argument promotion.
This reverts commits r354032 and r353537.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355060
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Craig Topper [Thu, 28 Feb 2019 01:00:31 +0000 (01:00 +0000)]
[X86] Use X86::LAST_VALID_COND instead of assuming X86::COND_S is the last encoding. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355059
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