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Thomas Preud'homme [Wed, 19 Jun 2019 23:47:24 +0000 (23:47 +0000)]
[FileCheck] Stop qualifying expressions as numeric
Summary:
Stop referring to "numeric expression", using simply the term
"expression" instead. Likewise for numeric operation since operations
are only used in numeric expressions.
Reviewers: jhenderson, jdenny, probinson, arichardson
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63500
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363901
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Thomas Preud'homme [Wed, 19 Jun 2019 23:47:10 +0000 (23:47 +0000)]
FileCheck: Return parse error w/ Error & Expected
Summary:
Make use of Error and Expected to bubble up diagnostics and force
checking of errors in the callers.
Reviewers: jhenderson, jdenny, probinson, arichardson
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63125
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363900
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Matt Arsenault [Wed, 19 Jun 2019 23:37:43 +0000 (23:37 +0000)]
AMDGPU: Undo sub x, c canonicalization for v2i16
Should avoid regression from D62341
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363899
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Matt Arsenault [Wed, 19 Jun 2019 22:37:08 +0000 (22:37 +0000)]
AMDGPU: Add baseline test for vector sub x, c canonicalization
This will catch regressions from D62341, and show improvements from a
future patch to fix them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363888
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Simon Pilgrim [Wed, 19 Jun 2019 22:14:24 +0000 (22:14 +0000)]
[DAGCombine] Use ConstantSDNode::getAPIntValue() instead of getZExtValue().
Use getAPIntValue() in a few more places. Most of the time getZExtValue() is fine, but occasionally there's fuzzed code or someone decides to create i65536 or something.....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363887
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Simon Atanasyan [Wed, 19 Jun 2019 22:08:06 +0000 (22:08 +0000)]
[mips] Mark the `lwupc` instruction as MIPS64 R6 only
The "The MIPS64 Instruction Set Reference Manual" [1] states that
the `lwupc` is MIPS64 Release 6 only. It should not be supported
for 32-bit CPUs.
[1] https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS64BIS-AFP-6.06.pdf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363886
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Simon Atanasyan [Wed, 19 Jun 2019 22:07:46 +0000 (22:07 +0000)]
[mips] Add (GPR|PTR)_64 predicates to PseudoReturn64 and PseudoIndirectHazardBranch64
This patch is one of a series of patches. The goal is to make P5600
scheduler model complete and turn on the `CompleteModel` flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363885
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Philip Reames [Wed, 19 Jun 2019 22:05:47 +0000 (22:05 +0000)]
[Util] Add a helper script for converting -print-before-all output into a file based equivelent
Simple little utility which takes a opt logfile generated with "opt -print-before-all -print-module-scope -o /dev/null <args> 2&>1", and splits into a series of individual "chunk-X.ll" files. The intended purpose is to help automate one step in failure reduction.
The imagined workflow is:
New crasher bug reported against clang or other frontend
Frontend run with -emit-llvm equivalent and manually confirmed that opt -O2 <emit.ll> crashes
Run this splitter script
Manually map pass name to invocation command (next on the to automate list)
Run bugpoint on last chunk file + manual command
I chose to dump every chunk rather than only the last since miscompile debugging frequently requires either manual step by step reduction, or cross feeding IR into different compiler versions. Not an immediate target, but there may be applications.
Differential Revision: https://reviews.llvm.org/D63461
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363884
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Philip Reames [Wed, 19 Jun 2019 21:58:25 +0000 (21:58 +0000)]
LFTR for multiple exit loops
Teach IndVarSimply's LinearFunctionTestReplace transform to handle multiple exit loops. LFTR does two key things 1) it rewrites (all) exit tests in terms of a common IV potentially eliminating one in the process and 2) it moves any offset/indexing/f(i) style logic out of the loop.
This turns out to actually be pretty easy to implement. SCEV already has all the information we need to know what the backedge taken count is for each individual exit. (We use that when computing the BE taken count for the loop as a whole.) We basically just need to iterate through the exiting blocks and apply the existing logic with the exit specific BE taken count. (The previously landed NFC makes this super obvious.)
I chose to go ahead and apply this to all loop exits instead of only latch exits as originally proposed. After reviewing other passes, the only case I could find where LFTR form was harmful was LoopPredication. I've fixed the latch case, and guards aren't LFTRed anyways. We'll have some more work to do on the way towards widenable_conditions, but that's easily deferred.
I do want to note that I added one bit after the review. When running tests, I saw a new failure (no idea why didn't see previously) which pointed out LFTR can rewrite a constant condition back to a loop varying one. This was theoretically possible with a single exit, but the zero case covered it in practice. With multiple exits, we saw this happening in practice for the eliminate-comparison.ll test case because we'd compute a ExitCount for one of the exits which was guaranteed to never actually be reached. Since LFTR ran after simplifyAndExtend, we'd immediately turn around and undo the simplication work we'd just done. The solution seemed obvious, so I didn't bother with another round of review.
Differential Revision: https://reviews.llvm.org/D62625
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363883
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Philip Reames [Wed, 19 Jun 2019 21:39:07 +0000 (21:39 +0000)]
[Tests] Autogen a test so that future changes are understandable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363882
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Alina Sbirlea [Wed, 19 Jun 2019 21:33:09 +0000 (21:33 +0000)]
[MemorySSA] Cleanup trivial phis.
Summary:
This is unfortunately needed for correctness, if we are to extend the tolerance of the update API to the way simple loop unswitch is doing cloning.
In simple loop unswitch (as opposed to loop unswitch), not all blocks are cloned. This can create unreachable cloned blocks (no predecessor), which are later cleaned up.
In MemorySSA, the APIs for supporting these kind of updates (clone + update exit blocks), make certain assumption on the integrity of the CFG. When cloning, if something was not cloned, it's values in MemorySSA default to LiveOnEntry. When updating exit blocks, it is safe to assume that we can first insert phis in the blocks merging two clones, then add additional phis in the IDF of the blocks that received phis. This no longer holds true if one of the clones being merged comes from an unreachable block. We'd conservatively need to add all phis before filling in their incoming definitions. In practice this restriction can be relaxed if we clean up trivial phis after the first round of insertion.
Reviewers: george.burgess.iv
Subscribers: jlebar, Prazek, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363880
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Alina Sbirlea [Wed, 19 Jun 2019 21:17:31 +0000 (21:17 +0000)]
[MemorySSA] Use GraphDiff info when computing IDF.
Summary:
When computing IDF for insert updates, ensure we use the snapshot CFG offered by GraphDiff.
Caught by D63389.
Reviewers: kuhar, george.burgess.iv
Subscribers: jlebar, Prazek, llvm-commits, Szelethus
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63443
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363879
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Philip Reames [Wed, 19 Jun 2019 20:45:57 +0000 (20:45 +0000)]
[LFTR] Stylistic cleanup as suggested in last review comment of D62939 [NFC]
(Resumbit of r363292 which was reverted along w/an earlier patch)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363877
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Matt Arsenault [Wed, 19 Jun 2019 20:44:15 +0000 (20:44 +0000)]
AMDGPU: Fix folding immediate into readfirstlane through reg_sequence
The def instruction for the vreg may not match, because it may be
folding through a reg_sequence. The assert was overly conservative and
not necessary. It's not actually important if DefMI really defined the
register, because the fold that will be done cares about the def of
the value that will be folded.
For some reason copies aren't making it through the reg_sequence,
although they should.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363876
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Philip Reames [Wed, 19 Jun 2019 20:41:28 +0000 (20:41 +0000)]
[LFTR] Rename variable to minimize confusion [NFC]
(Recommit of r363293 which was reverted when a dependent patch was.)
As pointed out by Nikita in D62625, BackedgeTakenCount is generally used to refer to the backedge taken count of the loop. A conditional backedge taken count - one which only applies if a particular exit is taken - is called a ExitCount in SCEV code, so be consistent here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363875
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Peter Collingbourne [Wed, 19 Jun 2019 20:40:03 +0000 (20:40 +0000)]
hwasan: Shrink outlined checks by 1 instruction.
Turns out that we can save an instruction by folding the right shift into
the compare.
Differential Revision: https://reviews.llvm.org/D63568
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363874
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Matt Arsenault [Wed, 19 Jun 2019 19:55:27 +0000 (19:55 +0000)]
Reapply "AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsics"
This reapplies r363678, using the correct chain for the CopyToReg for
v0. glueCopyToM0 counterintuitively changes the operands of the
original node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363870
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Yuanfang Chen [Wed, 19 Jun 2019 19:31:07 +0000 (19:31 +0000)]
[llvm-readobj] Match GNU output for DT_RPATH and DT_RUNPATH when dumping dynamic symbol table.
Reviewers: jhenderson, grimar, MaskRay, rupprecht, espindola
Subscribers: emaste, nemanjai, arichardson, kbarton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63347
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363868
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Philip Reames [Wed, 19 Jun 2019 19:23:19 +0000 (19:23 +0000)]
[SCEV] Revise a method description to match actual behavior [NFC]
Reword the ScalarEvolution::getExitCount comment in the same terminology as used by getBackedgeTakenCount since they're equivelent for single exit loops. Also, strengthen the comment to indicate exiting on the exact iteration specified is guaranteed. Several transforms implicitly rely on this; and the actual implementation checks for it (via dominating latch checks). So, spell out the guarantee in the comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363867
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Peter Collingbourne [Wed, 19 Jun 2019 19:11:23 +0000 (19:11 +0000)]
gn build: Merge r363757.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363865
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Peter Collingbourne [Wed, 19 Jun 2019 19:11:14 +0000 (19:11 +0000)]
gn build: Merge r363848.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363864
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Peter Collingbourne [Wed, 19 Jun 2019 19:11:05 +0000 (19:11 +0000)]
gn build: Merge r363846.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363863
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Peter Collingbourne [Wed, 19 Jun 2019 19:10:56 +0000 (19:10 +0000)]
gn build: Merge r363794.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363862
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Peter Collingbourne [Wed, 19 Jun 2019 19:10:47 +0000 (19:10 +0000)]
gn build: Merge r363680.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363861
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Peter Collingbourne [Wed, 19 Jun 2019 19:10:38 +0000 (19:10 +0000)]
gn build: Merge r363712.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363860
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Yuanfang Chen [Wed, 19 Jun 2019 18:44:29 +0000 (18:44 +0000)]
[llvm-objdump] Remove unnecessary indentation when dumping ELF data.
Reviewers: MaskRay, jhenderson, rupprecht
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63393
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363858
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Simon Pilgrim [Wed, 19 Jun 2019 18:34:58 +0000 (18:34 +0000)]
[TargetLowering] SimplifyDemandedBits - add ANY_EXTEND_VECTOR_INREG support
Move 'lowest' demanded elt -> bitcast fold out of ZERO_EXTEND_VECTOR_INREG into ANY_EXTEND_VECTOR_INREG case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363856
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Volkan Keles [Wed, 19 Jun 2019 18:15:45 +0000 (18:15 +0000)]
Fix GlobalISel MachineVerifier tests. NFC.
These test were failing when building llvm with
`-DLLVM_DEFAULT_TARGET_TRIPLE=''`. Add `-march` to the
run line to fix the issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363854
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Sanjay Patel [Wed, 19 Jun 2019 18:13:47 +0000 (18:13 +0000)]
[x86] avoid vector load narrowing with extracted store uses (PR42305)
This is an exception to the rule that we should prefer xmm ops to ymm ops.
As shown in PR42305:
https://bugs.llvm.org/show_bug.cgi?id=42305
...the store folding opportunity with vextractf128 may result in better
perf by reducing the instruction count.
Differential Revision: https://reviews.llvm.org/D63517
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363853
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Sanjay Patel [Wed, 19 Jun 2019 18:06:59 +0000 (18:06 +0000)]
[x86] add test for unaligned 32-byte load/store splitting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363852
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Jordan Rupprecht [Wed, 19 Jun 2019 18:03:36 +0000 (18:03 +0000)]
[test] Fix TargetParserTest runtime.
r363780 fixes extreme memory growth by using a new std::vector every loop iteration, but causes runtime to go up (and occasionally timeout in certain situations) because of constructor cost every loop iteration. Fix this by moving the constructor back out, but clearing contents in the loop.
Also apply this to the AArch64 features test case, which seems to use the same pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363851
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Simon Pilgrim [Wed, 19 Jun 2019 18:00:24 +0000 (18:00 +0000)]
[TargetLowering] SimplifyDemandedBits ZERO_EXTEND_VECTOR_INREG -> ANY_EXTEND_VECTOR_INREG
Simplify ZERO_EXTEND_VECTOR_INREG if the extended bits are not required.
Matches what we already do for ZERO_EXTEND.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363850
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Simon Pilgrim [Wed, 19 Jun 2019 17:42:37 +0000 (17:42 +0000)]
[X86][SSE] combineToExtendVectorInReg - add ANY_EXTEND support TODO. NFCI.
So I don't forget - there's a load of yak shaving to do first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363847
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Huihui Zhang [Wed, 19 Jun 2019 17:31:39 +0000 (17:31 +0000)]
[InstCombine] Fold icmp eq/ne (and %x, signbit), 0 -> %x s>=/s< 0 earlier
Summary:
To generate simplified IR, make sure fold
```
(X & signbit) ==/!= 0) -> X s>=/s< 0;
```
is scheduled before fold
```
((X << Y) & C) == 0 -> (X & (C >> Y)) == 0.
```
https://rise4fun.com/Alive/fbdh
Reviewers: lebedev.ri, efriedma, spatel, craig.topper
Reviewed By: lebedev.ri
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363845
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Sanjay Patel [Wed, 19 Jun 2019 17:23:29 +0000 (17:23 +0000)]
[InstSimplify] add a phi test with 1 incoming value; NFC
D63489 proposes to change this behavior, but there's no
direct -instsimplify test to verify that the transform exists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363842
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Simon Pilgrim [Wed, 19 Jun 2019 17:21:15 +0000 (17:21 +0000)]
[X86][SSE] Combine shuffles to ANY_EXTEND/ANY_EXTEND_VECTOR_INREG.
We already do this for ZERO_EXTEND/ZERO_EXTEND_VECTOR_INREG - this just extends the pattern matcher to recognize cases where we don't need the zeros in the extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363841
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Evandro Menezes [Wed, 19 Jun 2019 16:59:34 +0000 (16:59 +0000)]
[AArch64] Improve jump tables testing (NFC)
Improve testing of the minimum and maximum sizes of jump tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363839
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Simon Tatham [Wed, 19 Jun 2019 16:43:53 +0000 (16:43 +0000)]
[ARM] Add MVE vector bit-operations (register inputs).
This includes all the obvious bitwise operations (AND, OR, BIC, ORN,
MVN) in register-to-register forms, and the immediate forms of
AND/OR/BIC/ORN; byte-order reverse instructions; and the VMOVs that
access a single lane of a vector.
Some of those VMOVs (specifically, the ones that access a 32-bit lane)
share an encoding with existing instructions that were disassembled as
accessing half of a d-register (e.g. `vmov.32 r0, d1[0]`), but in
8.1-M they're now written as accessing a quarter of a q-register (e.g.
`vmov.32 r0, q0[2]`). The older syntax is still accepted by the
assembler.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62673
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363838
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Evandro Menezes [Wed, 19 Jun 2019 16:35:30 +0000 (16:35 +0000)]
[AArch64] Improve jump tables testing (NFC)
Improve testing of the minimum and maximum sizes of jump tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363837
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Cameron McInally [Wed, 19 Jun 2019 16:35:15 +0000 (16:35 +0000)]
[NFC][IR] Move CreateFNegFMF(...) next to CreateFNeg(...).
This is now in line with the other Create*FMF(...) functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363836
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James Henderson [Wed, 19 Jun 2019 16:31:59 +0000 (16:31 +0000)]
[test][llvm-dwarfdump] Remove pointless CHECK-NOT lines
The original line was there from when this test was added, but it is
checking for a switch that doesn't exist, so really has no purpose, at
least any more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363833
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Evandro Menezes [Wed, 19 Jun 2019 16:12:12 +0000 (16:12 +0000)]
[AVR] Change limit type to match the argument type (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363832
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Evandro Menezes [Wed, 19 Jun 2019 16:12:01 +0000 (16:12 +0000)]
[Hexagon] Change limit type to match the argument type (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363831
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Andrea Di Biagio [Wed, 19 Jun 2019 16:10:58 +0000 (16:10 +0000)]
[llvm-mca][docs] clarify how the quality of the perf report is affected by the quality of the scheduling models.
Differential Revision: https://reviews.llvm.org/D63556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363830
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Hubert Tong [Wed, 19 Jun 2019 16:04:24 +0000 (16:04 +0000)]
[NFC][llvm-objcopy] Fix overly restrictive od output check
The check against the output of `od` in the affected tests expect a
specific input offset format. They also expect a specific offset value,
not consistent with the EXAMPLE section for `od` in POSIX.1-2017
Chapter 4, while using the `-j` option. In particular, the example shows
that the input offset begins at 0 following the bytes skipped.
This patch adjusts the matching of the input offset to be more generic.
In order to avoid false matches, it restricts the number of bytes to be
formatted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363829
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Hubert Tong [Wed, 19 Jun 2019 16:02:54 +0000 (16:02 +0000)]
[NFC][LSR] Avoid undefined grep in pr2570.ll
greater-than-sign is not a BRE special character.
POSIX.1-2017 XBD Section 9.3.2 indicates that the interpretation of `\>`
is undefined. This patch replaces the pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363828
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Stefan Granitz [Wed, 19 Jun 2019 15:25:32 +0000 (15:25 +0000)]
Specify log level for CMake messages (less stderr)
Summary:
Specify message levels in CMake. Prefer STATUS (stdout).
As the default message mode (i.e. level) is NOTICE in CMake, more then necessary messages get printed to stderr. Some tools, noticably ccmake treat this as an error and require additional confirmation and re-running CMake's configuration step.
This commit specifies a mode (either STATUS or WARNING or FATAL_ERROR) instead of the default.
* I used `csearch -f 'llvm-project/.+(CMakeLists\.txt|cmake)' -l 'message\("'` to find all locations.
* Reviewers were chosen by the most common authors of specific files. If there are more suitable reviewers for these CMake changes, please let me know.
Patch by: Christoph Siedentop
Reviewers: zturner, beanz, xiaobai, kbobyrev, lebedev.ri, sgraenitz
Reviewed By: sgraenitz
Subscribers: mgorny, lebedev.ri, #sanitizers, lldb-commits, llvm-commits
Tags: #sanitizers, #lldb, #llvm
Differential Revision: https://reviews.llvm.org/D63370
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363821
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Simon Pilgrim [Wed, 19 Jun 2019 15:18:24 +0000 (15:18 +0000)]
[X86] getExtendInVec - take a ISD::*_EXTEND opcode instead of a IsSigned bool flag. NFCI.
Prep work to support ANY_EXTEND/ANY_EXTEND_VECTOR_INREG without needing another flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363818
91177308-0d34-0410-b5e6-
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Cameron McInally [Wed, 19 Jun 2019 15:11:41 +0000 (15:11 +0000)]
[DFSan] Add UnaryOperator visitor to DataFlowSanitizer
Differential Revision: https://reviews.llvm.org/D62815
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363814
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Cameron McInally [Wed, 19 Jun 2019 14:59:14 +0000 (14:59 +0000)]
[Reassociate] Handle unary FNeg in the Reassociate pass
Differential Revision: https://reviews.llvm.org/D63445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363813
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 19 Jun 2019 14:54:02 +0000 (14:54 +0000)]
[X86] Add *_EXTEND -> *_EXTEND_VECTOR_INREG opcode conversion helper. NFCI.
Given a *_EXTEND or *_EXTEND_VECTOR_INREG opcode, convert it to *_EXTEND_VECTOR_INREG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363812
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Bjorn Pettersson [Wed, 19 Jun 2019 14:28:03 +0000 (14:28 +0000)]
[ConstantFolding] Add constant folding for smul.fix and smul.fix.sat
Summary:
This patch teaches ConstantFolding to constant fold
both scalar and vector variants of llvm.smul.fix and
llvm.smul.fix.sat.
As described in the LangRef rounding is unspecified for
these instrinsics. If the result cannot be represented
exactly the default behavior in ConstantFolding is to
round down towards negative infinity. If a target has a
preferred rounding that is different some kind of target
hook would be needed (same strategy as used by the
SelectionDAG legalizer).
Reviewers: nikic, leonardchan, RKSimon
Reviewed By: leonardchan
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63385
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363811
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Bjorn Pettersson [Wed, 19 Jun 2019 14:27:51 +0000 (14:27 +0000)]
[ConstantFolding] Refactor ConstantFoldScalarCall. NFC
This patch splits ConstantFoldScalarCall into several
functions.
Benefits:
- Reduces indentation levels and avoids long if-statements.
- Makes it easier to add support for > 3 operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363810
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Simon Pilgrim [Wed, 19 Jun 2019 14:25:27 +0000 (14:25 +0000)]
[X86] Merge extract_subvector(*_EXTEND) and extract_subvector(*_EXTEND_VECTOR_INREG) handling. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363808
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Ulrich Weigand [Wed, 19 Jun 2019 14:20:00 +0000 (14:20 +0000)]
[SystemZ] Support vector load/store alignment hints
Vector load/store instructions support an optional alignment field
that the compiler can use to provide known alignment info to the
hardware. If the field is used (and the information is correct),
the hardware may be able (on some models) to perform faster memory
accesses than otherwise.
This patch adds support for alignment hints in the assembler and
disassembler, and fills in known alignment during codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363806
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 19 Jun 2019 13:58:02 +0000 (13:58 +0000)]
[TargetLowering] SimplifyDemandedBits SIGN_EXTEND_VECTOR_INREG -> ANY/ZERO_EXTEND_VECTOR_INREG
Simplify SIGN_EXTEND_VECTOR_INREG if the extended bits are not required/known zero.
Matches what we already do for SIGN_EXTEND.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363802
91177308-0d34-0410-b5e6-
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Fangrui Song [Wed, 19 Jun 2019 13:51:29 +0000 (13:51 +0000)]
[llvm-dwarfdump] --gdb-index: fix uninitialized TuListOffset
The test only checks the existence of the `Types CU list` line.
Unfortunately I can't make a better test because
{gcc,clang} -fuse-ld={lld,gold} --gdb-index do not give me a non-empty types CU list.
Reviewed By: ikudrin
Differential Revision: https://reviews.llvm.org/D63537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363800
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Simon Pilgrim [Wed, 19 Jun 2019 13:00:54 +0000 (13:00 +0000)]
Revert rL363678 : AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsics
There may or may not be additional work to handle this correctly on
SI/CI.
........
Breaks EXPENSIVE_CHECKS buildbots - http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/78/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363797
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David Bolvansky [Wed, 19 Jun 2019 12:59:37 +0000 (12:59 +0000)]
[NFC] Added tests for D63534
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363796
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David Bolvansky [Wed, 19 Jun 2019 12:55:39 +0000 (12:55 +0000)]
[NFC] Added tests for cttz(abs(x)) -> cttz(x) fold
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363795
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Simon Pilgrim [Wed, 19 Jun 2019 12:41:37 +0000 (12:41 +0000)]
[DAGCombiner] Support (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2)) non-uniform folds.
Use matchBinaryPredicate instead of isConstOrConstSplat to let us handle non-uniform shift cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363793
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Simon Pilgrim [Wed, 19 Jun 2019 12:25:29 +0000 (12:25 +0000)]
[DAGCombiner] Support (shl (ext (shl x, c1)), c2) -> 0 non-uniform folds.
Use matchBinaryPredicate instead of isConstOrConstSplat to let us handle non-uniform shift cases.
This requires us to tweak matchBinaryPredicate to allow it to (optionally) handle constants with different type widths.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363792
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Simon Pilgrim [Wed, 19 Jun 2019 11:36:01 +0000 (11:36 +0000)]
[X86] Add non-uniform (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2)) test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363791
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Simon Pilgrim [Wed, 19 Jun 2019 11:31:26 +0000 (11:31 +0000)]
[DAGCombiner] visitSHL - pull out repeated shift amount VT. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363789
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 19 Jun 2019 11:17:48 +0000 (11:17 +0000)]
[DAGCombine] Fix (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2)) comment. NFCI.
We pre-extend, not post.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363787
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Orlando Cazalet-Hyams [Wed, 19 Jun 2019 10:50:47 +0000 (10:50 +0000)]
[DebugInfo@O2][LoopVectorize] pr39024: Vectorized code linenos step through loop even after completion
Summary:
Bug: https://bugs.llvm.org/show_bug.cgi?id=39024
The bug reports that a vectorized loop is stepped through 4 times and each step through the loop seemed to show a different path. I found two problems here:
A) An incorrect line number on a preheader block (for.body.preheader) instruction causes a step into the loop before it begins.
B) Instructions in the middle block have different line numbers which give the impression of another iteration.
In this patch I give all of the middle block instructions the line number of the scalar loop latch terminator branch. This seems to provide the smoothest debugging experience because the vectorized loops will always end on this line before dropping into the scalar loop. To solve problem A I have altered llvm::SplitBlockPredecessors to accommodate loop header blocks.
I have set up a separate review D61933 for a fix which is required for this patch.
Reviewers: samsonov, vsk, aprantl, probinson, anemet, hfinkel, jmorse
Reviewed By: hfinkel, jmorse
Subscribers: jmorse, javed.absar, eraman, kcc, bjope, jmellorcrummey, hfinkel, gbedwell, hiraditya, zzheng, llvm-commits
Tags: #llvm, #debug-info
Differential Revision: https://reviews.llvm.org/D60831
llvm-svn: 363046
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363786
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Jay Foad [Wed, 19 Jun 2019 10:28:48 +0000 (10:28 +0000)]
[ConstantFolding] Fix assertion failure on non-power-of-two vector load.
Summary:
The test case does an (out of bounds) load from a global constant with
type <3 x float>. InstSimplify tried to turn this into an integer load
of the whole alloc size of the vector, which is 128 bits due to
alignment padding, and then bitcast this to <3 x vector> which failed
an assertion due to the type size mismatch.
The fix is to do an integer load of the normal size of the vector, with
no alignment padding.
Reviewers: tpr, arsenm, majnemer, dstuttard
Reviewed By: arsenm
Subscribers: hfinkel, wdng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63375
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363784
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Lewis Revill [Wed, 19 Jun 2019 10:27:24 +0000 (10:27 +0000)]
[RISCV] Allow parsing immediates that use tilde & exclaim
This patch allows immediates (and CSR alias immediates) which start with
a tilde token or an exclaim (!) token to be parsed as intended.
Differential Revision: https://reviews.llvm.org/D57320
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363783
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Lewis Revill [Wed, 19 Jun 2019 10:11:13 +0000 (10:11 +0000)]
[RISCV] Fix failure to parse parenthesized immediates
Since the parser attempts to parse an operand as a register with
parentheses before parsing it as an immediate, immediates in
parentheses should not be parsed by parseRegister. However in the case
where the immediate does not start with an identifier, the LParen is not
unlexed and so the RParen causes an unexpected token error.
This patch adds the missing UnLex, and modifies the existing UnLex to
not use a buffered token, as it should always be unlexing an LParen.
Differential Revision: https://reviews.llvm.org/D57319
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363782
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Clement Courbet [Wed, 19 Jun 2019 10:00:36 +0000 (10:00 +0000)]
Fix r363773: Update Barcelona MCA tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363781
91177308-0d34-0410-b5e6-
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Hans Wennborg [Wed, 19 Jun 2019 09:46:37 +0000 (09:46 +0000)]
Make TargetParserTest.ARMExtensionFeatures not run out of memory on 32-bit (PR42316)
The test still probably shouldn't run this loop 17 million times, but at
least now it won't run out of memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363780
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George Rimar [Wed, 19 Jun 2019 08:57:38 +0000 (08:57 +0000)]
[yaml2obj/obj2yaml] - Make RawContentSection::Info Optional<>
This allows to customize this field for "implicit" sections properly.
Differential revision: https://reviews.llvm.org/D63487
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363777
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Roman Lebedev [Wed, 19 Jun 2019 08:53:34 +0000 (08:53 +0000)]
[NFC][X86][MCA] Barcelona: add load/store/load-store-throughput tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363775
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Roman Lebedev [Wed, 19 Jun 2019 08:53:28 +0000 (08:53 +0000)]
[NFC][X86][MCA] BdVer2: add load-store-throughput test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363774
91177308-0d34-0410-b5e6-
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Clement Courbet [Wed, 19 Jun 2019 08:44:31 +0000 (08:44 +0000)]
[X86] Add missing properties on llvm.x86.sse.{st,ld}mxcsr
Summary:
llvm.x86.sse.stmxcsr only writes to memory.
llvm.x86.sse.ldmxcsr only reads from memory, and might generate an FPE.
Reviewers: craig.topper, RKSimon
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363773
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Lewis Revill [Wed, 19 Jun 2019 08:40:59 +0000 (08:40 +0000)]
[RISCV] Add lowering of global TLS addresses
This patch adds lowering for global TLS addresses for the TLS models of
InitialExec, GlobalDynamic, LocalExec and LocalDynamic.
LocalExec support required using a 4-operand add instruction, which uses
the fourth operand to express a relocation on the symbol. The necessary
fixup is emitted when the instruction is emitted.
Differential Revision: https://reviews.llvm.org/D55305
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363771
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Hans Wennborg [Wed, 19 Jun 2019 07:39:53 +0000 (07:39 +0000)]
vs integration: bump version nbr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363769
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Hans Wennborg [Wed, 19 Jun 2019 07:37:53 +0000 (07:37 +0000)]
Revert r359557 "vs integration: vs2019 support"
Turns out this worked on my machine because I still had VS2017 installed, but
it didn't actually work in general.
Since the extension is unmaintained and MS is doing their own LLVM toolset
integration for VS2019, let's just revert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363768
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Yuanfang Chen [Wed, 19 Jun 2019 05:40:24 +0000 (05:40 +0000)]
Test commit access
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363763
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Alex Bradbury [Wed, 19 Jun 2019 03:18:48 +0000 (03:18 +0000)]
[RISCV] Fix test after r363757
r363757 renamed ExpandISelPseudo to FinalizeISel, so the RUN line in
select-optimize-multiple.mir needed updating to refer to finalize-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363762
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Chen Zheng [Wed, 19 Jun 2019 01:26:31 +0000 (01:26 +0000)]
[NFC] move some hardware loop checking code to a common place for other using.
Differential Revision: https://reviews.llvm.org/D63478
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363758
91177308-0d34-0410-b5e6-
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Matt Arsenault [Wed, 19 Jun 2019 00:25:39 +0000 (00:25 +0000)]
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
This allows targets to make more decisions about reserved registers
after isel. For example, now it should be certain there are calls or
stack objects in the frame or not, which could have been introduced by
legalization.
Patch by Matthias Braun
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363757
91177308-0d34-0410-b5e6-
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Thomas Lively [Wed, 19 Jun 2019 00:02:13 +0000 (00:02 +0000)]
[WebAssembly] Optimize ISel for SIMD Boolean reductions
Summary:
Converting the result *.{all,any}_true to a bool at the source level
generates LLVM IR that compares the result to 0. This check is
redundant since these instructions already return either 0 or 1 and
therefore conform to the BooleanContents setting for WebAssembly. This
CL adds patterns to detect and remove such redundant operations on the
result of Boolean reductions.
Reviewers: dschuff, aheejin
Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63529
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363756
91177308-0d34-0410-b5e6-
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Daniel Sanders [Tue, 18 Jun 2019 23:34:46 +0000 (23:34 +0000)]
Re-commit r363744: [tblgen][disasm] Allow multiple encodings to disassemble to the same instruction
It seems macOS lets you have ArrayRef<const X> even though this is apparently
forbidden by the language standard (Thanks MSVC++ for the clear error message).
Removed the problematic const's to fix this.
(It also seems I'm not receiving buildbot emails anymore and I'm trying to find
out why. In the mean time I'll be polling lab.llvm.org to hopefully see if/when
failures occur)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363753
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Erik Pilkington [Tue, 18 Jun 2019 23:34:09 +0000 (23:34 +0000)]
[demangle] Special case clang's creative mangling of __uuidof expressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363752
91177308-0d34-0410-b5e6-
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Evandro Menezes [Tue, 18 Jun 2019 23:31:10 +0000 (23:31 +0000)]
[test] Change comment wording (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363751
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Jordan Rupprecht [Tue, 18 Jun 2019 22:21:31 +0000 (22:21 +0000)]
Revert [tblgen][disasm] Allow multiple encodings to disassemble to the same instruction
This reverts r363744 (git commit
9b2252123d1e79d2b3594097a9d9cc60072b83d9)
This breaks many buildbots, e.g. http://lab.llvm.org:8011/builders/clang-atom-d525-fedora-rel/builds/203/steps/build%20stage%201/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363747
91177308-0d34-0410-b5e6-
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Michael Trent [Tue, 18 Jun 2019 22:20:10 +0000 (22:20 +0000)]
Print dylib load kind (weak, reexport, etc) in llvm-objdump -m -dylibs-used
Summary:
Historically llvm-objdump prints the path to a dylib as well as the
dylib's compatibility version and current version number. This change
extends this information by adding the kind of dylib load: weak,
reexport, etc.
rdar://
51383512
Reviewers: pete, lhames
Reviewed By: pete
Subscribers: rupprecht, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363746
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Amara Emerson [Tue, 18 Jun 2019 22:08:40 +0000 (22:08 +0000)]
[GlobalISel][Localizer] Remove redundant set lookup.
After changing the algorithm to only process the entry block we never revisit
a processed instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363745
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Daniel Sanders [Tue, 18 Jun 2019 21:56:04 +0000 (21:56 +0000)]
[tblgen][disasm] Allow multiple encodings to disassemble to the same instruction
Summary:
Add an AdditionalEncoding class which can be used to define additional encodings
for a given instruction. This causes the disassembler to add an additional
encoding to its matching tables that map to the specified instruction.
Usage:
def ADD1 : Instruction {
bits<8> Reg;
bits<32> Inst;
let Size = 4;
let Inst{0-7} = Reg;
let Inst{8-14} = 0;
let Inst{15} = 1; // Continuation bit
let Inst{16-31} = 0;
...
}
def : AdditionalEncoding<ADD1> {
bits<8> Reg;
bits<16> Inst; // You can also have bits<32> and it will still be a 16-bit encoding
let Size = 2;
let Inst{0-3} = 0;
let Inst{4-7} = Reg;
let Inst{8-15} = 0;
...
}
with those definitions, llvm-mc will successfully disassemble both of these:
0x01 0x00
0x10 0x80 0x00 0x00
to:
ADD1 r1
Depends on D52366
Reviewers: bogner, charukcs
Reviewed By: bogner
Subscribers: nlguillemot, nhaehnle, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D52369
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363744
91177308-0d34-0410-b5e6-
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Michael Liao [Tue, 18 Jun 2019 21:41:13 +0000 (21:41 +0000)]
Recommit [SROA] Enhance SROA to handle `addrspacecast`ed allocas
[SROA] Enhance SROA to handle `addrspacecast`ed allocas
- Fix typo in original change
- Add additional handling to ensure all return pointers are properly
casted.
Summary:
- After `addrspacecast` is allowed to be eliminated in SROA, the
adjusting of storage pointer (from `alloca) needs to handle the
potential different address spaces between the storage pointer (from
alloca) and the pointer being used.
Reviewers: arsenm
Subscribers: wdng, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63501
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363743
91177308-0d34-0410-b5e6-
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Matt Arsenault [Tue, 18 Jun 2019 21:32:51 +0000 (21:32 +0000)]
InstCombine: Pre-commit test for reassociating nuw
D39417
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363741
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Huihui Zhang [Tue, 18 Jun 2019 20:55:09 +0000 (20:55 +0000)]
[ARM] Comply with rules on ARMv8-A thumb mode partial deprecation of IT.
Summary:
When identifing instructions that can be folded into a MOVCC instruction,
checking for a predicate operand is not enough, also need to check for
thumb2 function, with restrict-IT, is the machine instruction eligible for
ARMv8 IT or not.
Notes in ARMv8-A Architecture Reference Manual, section "Partial deprecation of IT"
https://usermanual.wiki/Pdf/ARM20Architecture20Reference20ManualARMv8.
1667877052.pdf
"ARMv8-A deprecates some uses of the T32 IT instruction. All uses of IT that apply to
instructions other than a single subsequent 16-bit instruction from a restricted set
are deprecated, as are explicit references to the PC within that single 16-bit
instruction. This permits the non-deprecated forms of IT and subsequent instructions
to be treated as a single 32-bit conditional instruction."
Reviewers: efriedma, lebedev.ri, t.p.northover, jmolloy, aemerson, compnerd, stoklund, ostannard
Reviewed By: ostannard
Subscribers: ostannard, javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363739
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Sam Elliott [Tue, 18 Jun 2019 20:38:08 +0000 (20:38 +0000)]
[RISCV] Prevent re-ordering some adds after shifts
Summary:
DAGCombine will normally turn a `(shl (add x, c1), c2)` into `(add (shl x, c2), c1 << c2)`, where `c1` and `c2` are constants. This can be prevented by a callback in TargetLowering.
On RISC-V, materialising the constant `c1 << c2` can be more expensive than materialising `c1`, because materialising the former may take more instructions, and may use a register, where materialising the latter would not.
This patch implements the hook in RISCVTargetLowering to prevent this transform, in the cases where:
- `c1` fits into the immediate field in an `addi` instruction.
- `c1` takes fewer instructions to materialise than `c1 << c2`.
In future, DAGCombine could do the check to see whether `c1` fits into an add immediate, which might simplify more targets hooks than just RISC-V.
Reviewers: asb, luismarques, efriedma
Reviewed By: asb
Subscribers: xbolva00, lebedev.ri, craig.topper, lewis-revill, Jim, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363736
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Jinsong Ji [Tue, 18 Jun 2019 20:24:49 +0000 (20:24 +0000)]
[MachinePipeliner][NFC] Do resource tracking log only when requested.
In most cases we don't need to do resource tracking debug,
so leave them off by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363733
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Sanjay Patel [Tue, 18 Jun 2019 20:13:35 +0000 (20:13 +0000)]
[x86] add another test for load splitting with extracted stores (PR42305); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363732
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Adrian Prantl [Tue, 18 Jun 2019 20:09:09 +0000 (20:09 +0000)]
Add debug location verification for !llvm.loop attachments.
This patch teaches the Verifier how to detect broken !llvm.loop
attachments as discussed in https://reviews.llvm.org/D60831. This
allows LLVM to warn and strip out the broken debug info before
attempting an LTO compilation with input generated by LLVM predating
https://reviews.llvm.org/rL361149.
rdar://problem/
51631158
Differential Revision: https://reviews.llvm.org/D63499
[Re-applies r363725 without changes after fixing a broken testcase.]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363731
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Adrian Prantl [Tue, 18 Jun 2019 20:07:53 +0000 (20:07 +0000)]
Fix broken debug info in in an !llvm.loop attachment in this testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363730
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Stanislav Mekhanoshin [Tue, 18 Jun 2019 20:00:24 +0000 (20:00 +0000)]
[AMDGPU] gfx10 wave32 patterns
Differential Revision: https://reviews.llvm.org/D63511
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363729
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Adrian Prantl [Tue, 18 Jun 2019 19:54:17 +0000 (19:54 +0000)]
Revert Add debug location verification for !llvm.loop attachments.
This reverts r363725 (git commit
8ff822d61dacf5a9466755eedafd3eeb54abc00d)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363728
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