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Simon Pilgrim [Mon, 30 Apr 2018 16:51:13 +0000 (16:51 +0000)]
[X86][Atom] Remove unnecessary x87 load/move instrw overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331198
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Tom Stellard [Mon, 30 Apr 2018 16:28:02 +0000 (16:28 +0000)]
AMDGPU: Remove some dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331196
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Andrea Di Biagio [Mon, 30 Apr 2018 15:55:04 +0000 (15:55 +0000)]
[llvm-mca] Correctly handle zero-latency stores that consume pipeline resources.
This fixes PR37293.
We can have scheduling classes with no write latency entries, that still consume
processor resources. We don't want to treat those instructions as zero-latency
instructions; they still have to be issued to the underlying pipelines, so they
still consume resource cycles.
This is likely to be a regression which I have accidentally introduced at
revision 330807. Now, if an instruction has a non-empty set of write processor
resources, we conservatively treat it as a normal (i.e. non zero-latency)
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331193
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Ulrich Weigand [Mon, 30 Apr 2018 15:52:28 +0000 (15:52 +0000)]
[SystemZ] Refactor some VT casts in DAG match patterns
In patterns where we need to specify a result VT, prefer
[(set (tr.vt tr.op:$V1), (operator ...))]
over
[(set tr.op:$V1, (tr.vt (operator ...)))]
This is NFC now, but simplifies some future changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331192
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Ulrich Weigand [Mon, 30 Apr 2018 15:49:27 +0000 (15:49 +0000)]
[SystemZ] Improve handling of Select pseudo-instructions
If we have LOCR instructions, select them directly from SelectionDAG
instead of first going through a pseudo instruction and then using
the custom inserter to emit the LOCR.
Provide Select pseudo-instructions for VR32/VR64 if we have vector
instructions, to avoid having to go through the first 16 FPRs
unnecessarily.
If we do not have LOCFHR, prefer using LOCR followed by a move
over a conditional branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331191
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Nico Weber [Mon, 30 Apr 2018 15:26:01 +0000 (15:26 +0000)]
IWYU for llvm-config.h, removals. Also see r331184.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331190
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Simon Pilgrim [Mon, 30 Apr 2018 15:18:33 +0000 (15:18 +0000)]
[X86] Drop unnecessary VPORrm InstrRW override in SkylakeServer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331188
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Simon Pilgrim [Mon, 30 Apr 2018 15:17:16 +0000 (15:17 +0000)]
[X86] Fix SkylakeServer typo in WritePSADBW class - it only uses 1 resource.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331187
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Tom Stellard [Mon, 30 Apr 2018 15:15:23 +0000 (15:15 +0000)]
AMDGPU/GlobalISel: Don't try to lower geometry shaders
Summary: The AMDGPU_GS calling convention is not supported yet.
Reviewers: arsenm, nhaehnle
Reviewed By: nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D46041
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331186
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Nico Weber [Mon, 30 Apr 2018 14:59:11 +0000 (14:59 +0000)]
IWYU for llvm-config.h in llvm, additions.
See r331124 for how I made a list of files missing the include.
I then ran this Python script:
for f in open('filelist.txt'):
f = f.strip()
fl = open(f).readlines()
found = False
for i in xrange(len(fl)):
p = '#include "llvm/'
if not fl[i].startswith(p):
continue
if fl[i][len(p):] > 'Config':
fl.insert(i, '#include "llvm/Config/llvm-config.h"\n')
found = True
break
if not found:
print 'not found', f
else:
open(f, 'w').write(''.join(fl))
and then looked through everything with `svn diff | diffstat -l | xargs -n 1000 gvim -p`
and tried to fix include ordering and whatnot.
No intended behavior change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331184
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Bjorn Pettersson [Mon, 30 Apr 2018 14:37:46 +0000 (14:37 +0000)]
[BranchFolding] Salvage DBG_VALUE instructions from empty blocks
Summary:
This patch will introduce copying of DBG_VALUE instructions
from an otherwise empty basic block to predecessor/successor
blocks in case the empty block is eliminated/bypassed. It
is currently only done in one identified situation in the
BranchFolding pass, before optimizing on empty block.
It can be seen as a light variant of the propagation done
by the LiveDebugValues pass, which unfortunately is executed
after the BranchFolding pass.
We only propagate (copy) DBG_VALUE instructions in a limited
number of situations:
a) If the empty BB is the only predecessor of a successor
we can copy the DBG_VALUE instruction to the beginning of
the successor (because the DBG_VALUE instruction is always
part of the flow between the blocks).
b) If the empty BB is the only successor of a predecessor
we can copy the DBG_VALUE instruction to the end of the
predecessor (because the DBG_VALUE instruction is always
part of the flow between the blocks). In this case we add
the DBG_VALUE just before the first terminator (assuming
that the terminators do not impact the DBG_VALUE).
A future solution, to handle more situations, could perhaps
be to run the LiveDebugValues pass before branch folding?
This fix is related to PR37234. It is expected to resolve
the problem seen, when applied together with the fix in
SelectionDAG from here: https://reviews.llvm.org/D46129
Reviewers: #debug-info, aprantl, rnk
Reviewed By: #debug-info, aprantl
Subscribers: ormris, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D46184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331183
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Bjorn Pettersson [Mon, 30 Apr 2018 14:37:39 +0000 (14:37 +0000)]
[SelectionDAG] Improve selection of DBG_VALUE using a PHI node result
Summary:
When building the selection DAG at ISel all PHI nodes are
selected and lowered to Machine Instruction PHI nodes before
we start to create any SDNodes. So there are no SDNodes for
values produced by the PHI nodes.
In the past when selecting a dbg.value intrinsic that uses
the value produced by a PHI node we have been handling such
dbg.value intrinsics as "dangling debug info". I.e. we have
not created a SDDbgValue node directly, because there is
no existing SDNode for the PHI result, instead we deferred
the creationg of a SDDbgValue until we found the first use
of the PHI result.
The old solution had a couple of flaws. The position of the
selected DBG_VALUE instruction would end up quite late in a
basic block, and for example not directly after the PHI node
as in the LLVM IR input. And in case there were no use at all
in the basic block the dbg.value could be dropped completely.
This patch introduces a new VREG kind of SDDbgValue nodes.
It is similar to a SDNODE kind of node, but it refers directly
to a virtual register and not a SDNode. When we do selection
for a dbg.value that is using the result of a PHI node we
can do a lookup of the virtual register directly (as it already
is determined for the PHI node) and create a SDDbgValue node
immediately instead of delaying the selection until we find a
use.
This should fix a problem with losing debug info at ISel
as seen in PR37234 (https://bugs.llvm.org/show_bug.cgi?id=37234).
It does not resolve PR37234 completely, because the debug info
is dropped later on in the BranchFolder (see D46184).
Reviewers: #debug-info, aprantl
Reviewed By: #debug-info, aprantl
Subscribers: rnk, gbedwell, aprantl, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D46129
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331182
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Gabor Buella [Mon, 30 Apr 2018 14:21:28 +0000 (14:21 +0000)]
NFC, Avoid a warning on pointer casting in PassPlugin.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331179
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Simon Dardis [Mon, 30 Apr 2018 14:03:35 +0000 (14:03 +0000)]
Revert "[mips] Fix the predicates of jump and branch and link instructions"
That commit broke one of the LLD builders, reverting while I investigate.
This patch reverts r331175.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331178
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Simon Dardis [Mon, 30 Apr 2018 13:37:42 +0000 (13:37 +0000)]
[mips] Fix the predicates of jump and branch and link instructions
Reviewers: smaksimovic, atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D46114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331175
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Florian Hahn [Mon, 30 Apr 2018 13:28:08 +0000 (13:28 +0000)]
[LV] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).
This patch updates some code responsible the skip debug info to use
BasicBlock::instructionsWithoutDebug. I think this makes things
slightly simpler and more direct.
Reviewers: mkuper, rengolin, dcaballe, aprantl, vsk
Reviewed By: rengolin
Differential Revision: https://reviews.llvm.org/D46254
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331174
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Benjamin Kramer [Mon, 30 Apr 2018 12:48:45 +0000 (12:48 +0000)]
[bindings] Fix dibuilder go bindings after r331114.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331171
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Andrea Di Biagio [Mon, 30 Apr 2018 12:13:04 +0000 (12:13 +0000)]
[llvm-mca] Regenerate test Atom/resources-sse3.s. NFC
Before this change, it wrongly specified -mcpu=slm instead of -mcpu=atom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331170
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Andrea Di Biagio [Mon, 30 Apr 2018 12:05:34 +0000 (12:05 +0000)]
[llvm-mca] Support for in-order CPU for -instruction-tables testing.
Added Intel Atom tests to verify that the tool correctly generates instruction
tables even if the CPU is in-order.
Fixes PR37282.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331169
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Simon Pilgrim [Mon, 30 Apr 2018 10:46:35 +0000 (10:46 +0000)]
[X86] Fix typo in skylake-avx512 model for PMAXSD/PMINSD instructions
The PMAXSD/PMINSD instregexs had been written as PMAX(C?)SD - looks like this was a search+replace error when matching float MAXSD/MINSD commutative instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331167
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Gabor Buella [Mon, 30 Apr 2018 10:18:11 +0000 (10:18 +0000)]
NFC - Typo fixes lib/VMCore -> lib/IR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331166
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Simon Dardis [Mon, 30 Apr 2018 09:44:44 +0000 (09:44 +0000)]
[mips] Fix microMIPS loads and stores.
Previously these instructions were unselectable and instead were generated
through the instruction mapping tables.
Reviewers: atanasyan, smaksimovic, abeserminji
Differential Revision: https://reviews.llvm.org/D46055
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331165
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Sander de Smalen [Mon, 30 Apr 2018 07:24:38 +0000 (07:24 +0000)]
[AArch64][SVE] Asm: Improve diagnostics for gather loads.
This patch extends the 'isSVEVectorRegWithShiftExtend' function to
improve diagnostics for SVE's gather load (scalar + vector) addressing
modes. Instead of always suggesting the 'unscaled' addressing mode,
the use of DiagnosticPredicate enables a more specific error message
in the context where the scaling is incorrect. For example:
ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
^
shift amount should be '1'
Instead of suggesting the packed, unscaled addressing mode:
expected 'z[0..31].d, (uxtw|sxtw)'
the assembler now suggests using the proper scaling:
expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D46124
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331162
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Craig Topper [Mon, 30 Apr 2018 06:21:24 +0000 (06:21 +0000)]
[X86] Add a Requires<[In64BitMode]> to FARJMP64
Otherwise we can try to assemble it in 32-bit mode and throw an assert in the encoder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331161
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Craig Topper [Mon, 30 Apr 2018 06:21:23 +0000 (06:21 +0000)]
[X86] Hide another instruction from the assembly matcher table to avoid a duplicate entry. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331160
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Craig Topper [Mon, 30 Apr 2018 06:21:22 +0000 (06:21 +0000)]
[X86] Remove some InstAliases aren't needed because a MnemonicAlias makes them unreachable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331159
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Craig Topper [Mon, 30 Apr 2018 06:21:21 +0000 (06:21 +0000)]
[X86] Remove some instructions from the Intel assembly matcher table as there are equivalent mode aware InstAliases that conflict.
The instructions have predicates of Not64BitMode, but there are identical strings in InstAliases that have Mode32Bit and Mode16Bit. But the ordering is uncontrolled and the less specific Not64BitMode was ordered first.
This patch hides the Not64BitMode from the table so there is no conflict anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331158
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Craig Topper [Mon, 30 Apr 2018 06:21:19 +0000 (06:21 +0000)]
[X86] Use a MnemonicAlias instead of an InstAlias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331157
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Craig Topper [Mon, 30 Apr 2018 01:53:12 +0000 (01:53 +0000)]
[X86] Remove support for accepting 'fnstsw %eax' and 'fnstsw %al'.
I assume this was done because gas accepted it at one point, but current versions of gas don't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331154
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Craig Topper [Mon, 30 Apr 2018 01:53:10 +0000 (01:53 +0000)]
[X86] Mark some more InstAliases as 'att' syntax only.
These aliases are used to default the memory forms of call and jmp to the size of the operating mode. This doesn't work for Intel syntax. We have a different hack in the AsmParser code itself to force a size on unsized memory operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331153
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Nico Weber [Mon, 30 Apr 2018 00:08:06 +0000 (00:08 +0000)]
Remove a dead #ifdef.
Unix/Threading.inc should never be included on _WIN32. See also
https://reviews.llvm.org/D30526#
1082292
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331151
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Craig Topper [Sun, 29 Apr 2018 22:55:54 +0000 (22:55 +0000)]
[X86] Make 64-bit sysret/sysexit not ambiguous in Intel assembly syntax.
This also makes it default to the 32-bit non REX.W version in 64-bit mode. This seems to be more consistent with gas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331149
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Simon Pilgrim [Sun, 29 Apr 2018 18:18:51 +0000 (18:18 +0000)]
[X86] Remove unnecessary BT InstRW overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331147
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Sander de Smalen [Sun, 29 Apr 2018 18:18:21 +0000 (18:18 +0000)]
[AArch64][AsmParser] NFC: Cleanup of addOperands functions
Most of the add<operandname>Operands() functions are the same
and can be replaced by using a single 'RenderMethod' in
the AArch64InstrFormats.td file. Since many of the scaled
immediates (with different scaling/bits) are the same, most of
these can reuse the same AsmOperandClass.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: samparker
Differential Revision: https://reviews.llvm.org/D46122
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331146
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Sander de Smalen [Sun, 29 Apr 2018 17:33:38 +0000 (17:33 +0000)]
[AArch64][SVE] Asm: Support for gather LD1/LDFF1 (vector + imm) load instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46120
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331145
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Simon Pilgrim [Sun, 29 Apr 2018 15:45:31 +0000 (15:45 +0000)]
[llvm-mca][X86] Add BT resource tests to all models
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331144
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Simon Pilgrim [Sun, 29 Apr 2018 15:33:15 +0000 (15:33 +0000)]
[X86] Merge more instregex single matches to reduce InstrRW compile time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331143
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Simon Pilgrim [Sun, 29 Apr 2018 14:16:17 +0000 (14:16 +0000)]
[X86] Remove unnecessary add/adc+sub/sbb InstRW overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331142
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Simon Pilgrim [Sun, 29 Apr 2018 11:03:25 +0000 (11:03 +0000)]
[llvm-mca][X86] Add add/adc + sub/sbb resource tests to all models
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331140
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Hideki Saito [Sun, 29 Apr 2018 07:26:18 +0000 (07:26 +0000)]
[NFC][LV][LoopUtil] Move LoopVectorizationLegality to its own file
Summary:
This is a follow up to D45420 (included here since it is still under review and this change is dependent on that) and D45072 (committed).
Actual change for this patch is LoopVectorize* and cmakefile. All others are all from D45420.
LoopVectorizationLegality is an analysis and thus really belongs to Analysis tree. It is modular enough and it is reusable enough ---- we can further improve those aspects once uses outside of LV picks up.
Hopefully, this will make it easier for people familiar with vectorization theory, but not necessarily LV itself to contribute, by lowering the volume of code they should deal with. We probably should start adding some code in LV to check its own capability (i.e., vectorization is legal but LV is not ready to handle it) and then bail out.
Reviewers: rengolin, fhahn, hfinkel, mkuper, aemerson, mssimpso, dcaballe, sguggill
Reviewed By: rengolin, dcaballe
Subscribers: egarcia, rogfer01, mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D45552
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331139
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Craig Topper [Sun, 29 Apr 2018 06:24:09 +0000 (06:24 +0000)]
[X86] Add suffixes to the LGDT/LIDT/SGDT/SIDT mnemonics in Intel syntax. Add aliases based on 16/32-bit mode to choose the default.
This allows the instruction selection to follow mode in Intel syntax. And allows a suffix to be used to change size.
This matches gas behavior from what I could tell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331138
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Craig Topper [Sun, 29 Apr 2018 04:50:53 +0000 (04:50 +0000)]
[X86] Remove SLDT64m instruction.
It doesn't really exist. The instruction always writes 16-bits of memory. Putting a REX.w on it won't change anything.
While I was touching the encoding tests to remove it, I added some other missing register form test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331135
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Craig Topper [Sun, 29 Apr 2018 04:06:02 +0000 (04:06 +0000)]
[X86] Remove unnecessary InstAliases. NFCI
These used to disambiguate MOV16ms/MOV16sm from other size instructions that no longer exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331134
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whitequark [Sun, 29 Apr 2018 02:01:34 +0000 (02:01 +0000)]
[LLVM-C] Eliminate an unused variable in a test.
This was introduced in r331123 and broke -Werror bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331132
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Rafael Espindola [Sun, 29 Apr 2018 01:13:57 +0000 (01:13 +0000)]
Update my email address and description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331131
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Craig Topper [Sun, 29 Apr 2018 00:53:10 +0000 (00:53 +0000)]
[X86] Use getX86SubSuperRegister in addGR32orGR64Operands in the AsmParser instead of duplicating its functionality. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331128
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Nico Weber [Sun, 29 Apr 2018 00:45:03 +0000 (00:45 +0000)]
s/LLVM_ON_WIN32/_WIN32/, llvm
LLVM_ON_WIN32 is set exactly with MSVC and MinGW (but not Cygwin) in
HandleLLVMOptions.cmake, which is where _WIN32 defined too. Just use the
default macro instead of a reinvented one.
See thread "Replacing LLVM_ON_WIN32 with just _WIN32" on llvm-dev and cfe-dev.
No intended behavior change.
This moves over all uses of the macro, but doesn't remove the definition
of it in (llvm-)config.h yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331127
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Robert Widmann [Sat, 28 Apr 2018 22:32:07 +0000 (22:32 +0000)]
[LLVM-C] Add DIBuilder bindings to create import declarations
Summary: Add bindings to create import declarations for modules, functions, types, and other entities. This wraps the conveniences available in the existing DIBuilder API, but these seem C++-specific.
Reviewers: whitequark, harlanhaskins, deadalnix
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46167
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331123
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Craig Topper [Sat, 28 Apr 2018 18:46:11 +0000 (18:46 +0000)]
[X86] Restrict many of the InstAliases to either to only att or intel syntax. NFCI
Many of these aliases exist to give one syntax or the other a slightly different mnemonic and the other variant gets a duplicate of its normal mnemonic
This patch restricts a lot of these to only one variant so we don't get the duplication.
This removes a lot of duplicate entries from the matcher table. It also reduces the number of warnings printed when you enable the ambiguous match warning in tablegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331117
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Simon Pilgrim [Sat, 28 Apr 2018 18:45:16 +0000 (18:45 +0000)]
[X86] Remove unnecessary rotate-carry folded InstRW overrides.
Merge some remaining instregex entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331116
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Daniel Sanders [Sat, 28 Apr 2018 18:14:50 +0000 (18:14 +0000)]
[globalisel][legalizerinfo] Introduce dedicated extending loads and add lowerings for them
Summary:
Previously, a extending load was represented at (G_*EXT (G_LOAD x)).
This had a few drawbacks:
* G_LOAD had to be legal for all sizes you could extend from, even if
registers didn't naturally hold those sizes.
* All sizes you could extend from had to be allocatable just in case the
extend went missing (e.g. by optimization).
* At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we
improve optimization of extends and truncates, this legality requirement
would spread without considerable care w.r.t when certain combines were
permitted.
* The SelectionDAG importer required some ugly and fragile pattern
rewriting to translate patterns into this style.
This patch begins changing the representation to:
* (G_[SZ]EXTLOAD x)
* (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits()
which resolves these issues by allowing targets to work entirely in their
native register sizes, and by having a more direct translation from
SelectionDAG patterns.
This patch introduces the new generic instructions and new variation on
G_LOAD and adds lowering for them to convert back to the existing
representations.
Depends on D45466
Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, aemerson, javed.absar
Reviewed By: aemerson
Subscribers: aemerson, kristof.beyls, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D45540
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331115
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Robert Widmann [Sat, 28 Apr 2018 18:13:39 +0000 (18:13 +0000)]
[LLVM-C] Miscellaneous Cleanups in DIBuilder Bindings
Summary:
* rL328953 does not include bindings for LLVMDIBuilderCreateClassType and LLVMDIBuilderCreateBitFieldMemberType despite declaring their prototypes. Provide these bindings now.
* Switch to more precise types with specific numeric limits matching the DIBuilder's C++ API.
Reviewers: harlanhaskins, whitequark, deadalnix
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46168
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331114
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Roman Lebedev [Sat, 28 Apr 2018 15:45:07 +0000 (15:45 +0000)]
[InstCombine] Canonicalize variable mask in masked merge
Summary:
Masked merge has a pattern of: `((x ^ y) & M) ^ y`.
But, there is no difference between `((x ^ y) & M) ^ y` and `((x ^ y) & ~M) ^ x`,
We should canonicalize the pattern to non-inverted mask.
https://rise4fun.com/Alive/Yol
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45664
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331112
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Roman Lebedev [Sat, 28 Apr 2018 15:45:00 +0000 (15:45 +0000)]
[InstCombine][NFC] Add tests for variable mask canonicalization in masked merge
Summary:
Masked merge has a pattern of: `((x ^ y) & M) ^ y`.
But, there is no difference between `((x ^ y) & M) ^ y` and `((x ^ y) & ~M) ^ x`,
We should canonicalize the pattern to non-inverted mask.
Differential Revision: https://reviews.llvm.org/D45663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331111
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Simon Pilgrim [Sat, 28 Apr 2018 15:32:19 +0000 (15:32 +0000)]
[X86] Remove unnecessary shift/rotate folded InstRW overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331110
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sat, 28 Apr 2018 15:18:49 +0000 (15:18 +0000)]
[llvm-mca][X86] Add double shift resource tests to all relevant models
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331109
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Simon Pilgrim [Sat, 28 Apr 2018 14:56:18 +0000 (14:56 +0000)]
[llvm-mca][X86] Add shift/rotate resource tests to all relevant models
I intend to add further instruction tests to the resources-x86_64.s test file as required, but this initial commit is to help remove a load of unnecessary InstRW overrides in a future patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331108
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Simon Pilgrim [Sat, 28 Apr 2018 14:08:51 +0000 (14:08 +0000)]
[X86][SSE] Stop hard coding some instruction scheduler classes.
Make these arguments to the multiclass to allow easier specialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331107
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Simon Pilgrim [Sat, 28 Apr 2018 14:06:28 +0000 (14:06 +0000)]
[X86][HW] Cleanup Haswell model. NFCI.
Moved LAHF/SAHF to instrs instead of instregex.
Removed some unnecessary instregex entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331106
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Craig Topper [Sat, 28 Apr 2018 06:58:27 +0000 (06:58 +0000)]
[X86] Remove mayLoad flag from BNDMK/BNDCL/BNDCN/BNDCU.
The instruction documentation specifically says that these instruction don't access memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331105
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Craig Topper [Sat, 28 Apr 2018 06:58:26 +0000 (06:58 +0000)]
[X86] Change memory operand of BNDMK/BNDCL/BNDCU/BNDCN/BNDST to anymem.
These instruction don't use their memory operands as normal memory operands. They're just used as addresses. They don't have a size because they aren't directly representing a load or store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331104
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Serguei Katkov [Sat, 28 Apr 2018 06:41:35 +0000 (06:41 +0000)]
[SCEV] Touch the unsused stats variables for product build.
This is a fix by elimination compiler warnings considered as errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331103
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Craig Topper [Sat, 28 Apr 2018 06:02:40 +0000 (06:02 +0000)]
[X86] Remove REX.W from 64-bit mode BND instructions.
As far as I can tell from the docs, the instructions are automatically 64-bit in 64-bit mode. We don't need REX.W.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331102
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Craig Topper [Sat, 28 Apr 2018 06:02:39 +0000 (06:02 +0000)]
[X86] Rename BNDMOV instructions and hide redundant instruction encoding from the assembler.
Favor the 0x1a encoding for register/register move to match gas.
The instructions used RM and MR in their name along with rr/rm/mr at the end. To make more consistent with other instructions remove the RM/MR and use rr/rm/mr/rr_REV.
Hide the _REV encoding from the assembler but leave it for the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331101
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Max Kazantsev [Sat, 28 Apr 2018 04:38:21 +0000 (04:38 +0000)]
[NFC] Add some tests that demonstrate unrecognized three-way comparison patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331100
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Serguei Katkov [Sat, 28 Apr 2018 03:53:36 +0000 (03:53 +0000)]
[SCEV] Reduce the number of invocation to non trivial getExact function
The invocation of getExact in ScalarEvolution::getBackedgeTakenInfo is used
only for getting statistic and for assert.
Even if statistics is disabled, the code related to it will be eliminated
the invocation to getExact itself will not be eliminated
because it may have side-effects like creation of new SCEVs.
So do invocation only when we collect statistics or executes asserts.
Reviewers: mkazantsev, sanjoy, javed.absar
Reviewed By: javed.absar
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46178
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331099
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Jessica Paquette [Fri, 27 Apr 2018 23:36:35 +0000 (23:36 +0000)]
[MachineOutliner] Add defs to calls + don't track liveness on outlined functions
This commit makes it so that if you outline a def of some register, then the
call instruction created by the outliner actually reflects that the register
is defined by the call. It also makes it so that outlined functions don't
have the TracksLiveness property.
Outlined calls shouldn't break liveness assumptions that someone might make.
This also un-XFAILs the noredzone test, and updates the calls test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331095
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Philip Reames [Fri, 27 Apr 2018 23:15:56 +0000 (23:15 +0000)]
[LoopGuardWidening] Make PostDomTree optional
The effect of doing so is not disrupting the LoopPassManager when mixing this pass with other loop passes. This should help locality of access substaintially and avoids the cost of computing PostDom.
The assumption here is that the full GuardWidening (which does use PostDom) is run as a canonicalization before loop opts and that this version is just catching cases exposed by other loop passes. (i.e. LoopPredication, IndVarSimplify, LoopUnswitch, etc..)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331094
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Heejin Ahn [Fri, 27 Apr 2018 22:23:11 +0000 (22:23 +0000)]
[DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisor
Summary:
D42479 (rL329525) enabled SDIV combine for pow2 non-splat vector
dividers. But when there is a 1 in a vector, the instruction sequence to
be generated involves shifting a value by the number of its bit widths,
which is undefined
(https://github.com/llvm-mirror/llvm/blob/
c64f4dbfe31e509f9c1092b951e524b056245af8/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L6000-L6006).
Especially, in architectures that do not support vector instructions,
each of element in a vector will be computed separately using scalar
operations, and then the resulting value will be undef for '1' values
in a vector.
(All 1's vector is fine; only vectors mixed with 1 and others will be
affected.)
Reviewers: RKSimon, jgravelle-google
Subscribers: jfb, dschuff, sbc100, jgravelle-google, llvm-commits
Differential Revision: https://reviews.llvm.org/D46161
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331092
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Craig Topper [Fri, 27 Apr 2018 22:15:33 +0000 (22:15 +0000)]
[X86] Make the STTNI flag intrinsics use the flags from pcmpestrm/pcmpistrm if the mask instrinsics are also used in the same basic block.
Summary:
Previously the flag intrinsics always used the index instructions even if a mask instruction also exists.
To fix fix this I've created a single ISD node type that returns index, mask, and flags. The SelectionDAG CSE process will merge all flavors of intrinsics with the same inputs to a s ingle node. Then during isel we just have to look at which results are used to know what instruction to generate. If both mask and index are used we'll need to emit two instructions. But for all other cases we can emit a single instruction.
Since I had to do manual isel anyway, I've removed the pseudo instructions and custom inserter code that was working around tablegen limitations with multiple implicit defs.
I've also renamed the recently added sse42.ll test case to sttni.ll since it focuses on that subset of the sse4.2 instructions.
Reviewers: chandlerc, RKSimon, spatel
Reviewed By: chandlerc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46202
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331091
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Adrian Prantl [Fri, 27 Apr 2018 22:05:31 +0000 (22:05 +0000)]
Fix a bug that prevents global variables from having a DW_OP_deref.
For local variables the first DW_OP_deref is consumed by turning the
location kind into a memeory location, but that only makes sense for
values that are in a register to begin with, which cannot happen for
global variables that are attached to a symbol.
rdar://problem/
39741860
This reapplies r330970 after fixing an uncovered bug in r331086 and
working around the situation caused by it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331090
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Reid Kleckner [Fri, 27 Apr 2018 21:51:25 +0000 (21:51 +0000)]
[FastISel] Actually enable local value sinking by default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331088
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Reid Kleckner [Fri, 27 Apr 2018 21:48:51 +0000 (21:48 +0000)]
[FastISel] Fix local value sinking algorithmic complexity
Now local value sinking only scans and numbers instructions added
between the current flush point and the last flush point. This ensures
that ISel is overall linear in the size of the BB.
Fixes PR37010 and re-enables local value sinking by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331087
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Adrian Prantl [Fri, 27 Apr 2018 21:41:36 +0000 (21:41 +0000)]
Fix a bug in GlobalOpt's handling of DIExpressions.
This patch adds support for fragment expressions
TryToShrinkGlobalToBoolean() which were previously just dropped.
Thanks to Reid Kleckner for providing me a reproducer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331086
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Roman Lebedev [Fri, 27 Apr 2018 21:23:20 +0000 (21:23 +0000)]
[PatternMatch] Stabilize the matching order of commutative matchers
Summary:
Currently, we
1. match `LHS` matcher to the `first` operand of binary operator,
2. and then match `RHS` matcher to the `second` operand of binary operator.
If that does not match, we swap the `LHS` and `RHS` matchers:
1. match `RHS` matcher to the `first` operand of binary operator,
2. and then match `LHS` matcher to the `second` operand of binary operator.
This works ok.
But it complicates writing of commutative matchers, where one would like to match
(`m_Value()`) the value on one side, and use (`m_Specific()`) it on the other side.
This is additionally complicated by the fact that `m_Specific()` stores the `Value *`,
not `Value **`, so it won't work at all out of the box.
The last problem is trivially solved by adding a new `m_c_Specific()` that stores the
`Value **`, not `Value *`. I'm choosing to add a new matcher, not change the existing
one because i guess all the current users are ok with existing behavior,
and this additional pointer indirection may have performance drawbacks.
Also, i'm storing pointer, not reference, because for some mysterious-to-me reason
it did not work with the reference.
The first one appears trivial, too.
Currently, we
1. match `LHS` matcher to the `first` operand of binary operator,
2. and then match `RHS` matcher to the `second` operand of binary operator.
If that does not match, we swap the ~~`LHS` and `RHS` matchers~~ **operands**:
1. match ~~`RHS`~~ **`LHS`** matcher to the ~~`first`~~ **`second`** operand of binary operator,
2. and then match ~~`LHS`~~ **`RHS`** matcher to the ~~`second`~ **`first`** operand of binary operator.
Surprisingly, `$ ninja check-llvm` still passes with this.
But i expect the bots will disagree..
The motivational unittest is included.
I'd like to use this in D45664.
Reviewers: spatel, craig.topper, arsenm, RKSimon
Reviewed By: craig.topper
Subscribers: xbolva00, wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D45828
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331085
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Simon Pilgrim [Fri, 27 Apr 2018 21:14:19 +0000 (21:14 +0000)]
[X86] Merge some x87 instruction instregex single matches. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331084
91177308-0d34-0410-b5e6-
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Sanjay Patel [Fri, 27 Apr 2018 21:14:15 +0000 (21:14 +0000)]
[Reassociate] add a test with debug info; NFC
As suggested in D45842
(although still not sure if we're going to advance that),
we must invalidate references to instructions that have
been recycled (operands were changed, so result is different).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331083
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Daniel Sanders [Fri, 27 Apr 2018 21:03:27 +0000 (21:03 +0000)]
Attempt to fix remaining build failures after r331071 by changing the tuple to a struct
Some of the bots were failing in a different way to the others. These were
unable to compare tuples. Fix this by changing to a struct, thereby avoiding
the quirks of tuples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331081
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Philip Reames [Fri, 27 Apr 2018 20:58:30 +0000 (20:58 +0000)]
[LICM] Reduce nesting with an early return [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331080
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Philip Reames [Fri, 27 Apr 2018 20:44:01 +0000 (20:44 +0000)]
[MustExecute/LICM] Special case first instruction in throwing header
We currently have a hard to solve analysis problem around the order of instructions within a potentially throwing block. We can't cheaply determine whether a given instruction is before the first potential throw in the block. While we're working on that in the background, special case the first instruction within the header.
why this particular special case? Well, headers are guaranteed to execute if the loop does, and it turns out we tend to produce this form in practice.
In a follow on patch, I tend to extend LICM with an alternate approach which works for any instruction in the header before the first throw, but this is the best I can come up with other users of the analysis (such as store promotion.)
Note: I can't show the difference in the analysis result since we're ORing in the expensive instruction walk used by SCEV. Using the full walk is not suitable for a general solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331079
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Vlad Tsyrklevich [Fri, 27 Apr 2018 20:32:34 +0000 (20:32 +0000)]
ELFObjectWriter: Allow one unique symver per symbol
Summary:
Only allow a single unique .symver alias per symbol. This matches the
behavior of gas. I noticed that we ignored multiple mismatched symver
directives looking at https://reviews.llvm.org/D45798
Reviewers: pcc, tejohnson, espindola
Reviewed By: pcc
Subscribers: emaste, arichardson, llvm-commits, kcc
Differential Revision: https://reviews.llvm.org/D45845
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331078
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Daniel Neilson [Fri, 27 Apr 2018 20:29:18 +0000 (20:29 +0000)]
[LV] Common duplicate vector load/store address calculation (NFC)
Summary:
Commoning some obviously copy/paste code in
InnerLoopVectorizer::vectorizeMemoryInstruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331076
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Daniel Sanders [Fri, 27 Apr 2018 20:17:44 +0000 (20:17 +0000)]
Attempt to fix build failure after r331071 using std::make_tuple
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331074
91177308-0d34-0410-b5e6-
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Jun Bum Lim [Fri, 27 Apr 2018 19:59:20 +0000 (19:59 +0000)]
[PostRASink] extend the live-in check for all aliased registers
Extend the live-in check for all aliased registers so that we can
allow sinking Copy instructions when only implicit def is in successor's
live-in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331072
91177308-0d34-0410-b5e6-
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Daniel Sanders [Fri, 27 Apr 2018 19:48:53 +0000 (19:48 +0000)]
[globalisel][legalizerinfo] Add support for legalization based on the MachineMemOperand
Summary:
Currently only the memory size is supported but others can be added as
needed.
narrowScalar for G_LOAD and G_STORE now correctly update the
MachineMemOperand and will refuse to legalize atomics since those need more
careful expansions to maintain atomicity.
Reviewers: ab, aditya_nandakumar, bogner, rtereshin, aemerson, javed.absar
Reviewed By: aemerson
Subscribers: aemerson, rovka, kristof.beyls, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D45466
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331071
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Paul Semel [Fri, 27 Apr 2018 19:16:27 +0000 (19:16 +0000)]
[llvm-objcopy] Add --weaken-symbol (-W) option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331070
91177308-0d34-0410-b5e6-
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Paul Semel [Fri, 27 Apr 2018 19:09:44 +0000 (19:09 +0000)]
[llvm-objcopy] Add --globalize-symbol option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331068
91177308-0d34-0410-b5e6-
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Jun Bum Lim [Fri, 27 Apr 2018 18:44:37 +0000 (18:44 +0000)]
[CodeGen] Use RegUnits to track register aliases (NFC)
Summary: Use RegUnits to track register aliases in PostRASink and AArch64LoadStoreOptimizer.
Reviewers: thegameg, mcrosier, gberry, qcolombet, sebpop, MatzeB, t.p.northover, javed.absar
Reviewed By: thegameg, sebpop
Subscribers: javed.absar, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331066
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Simon Pilgrim [Fri, 27 Apr 2018 18:19:48 +0000 (18:19 +0000)]
[X86] Split WriteFBlend/WriteFVarBlend/WriteFVarShuffle into XMM and YMM/ZMM scheduler classes
This removes all the WriteFBlend/WriteFVarBlend InstRW overrides - some WriteFVarShuffle remain to be fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331065
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Mark Searles [Fri, 27 Apr 2018 17:59:15 +0000 (17:59 +0000)]
[AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained.
Differential Revision: https://reviews.llvm.org/D46154
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331062
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Philip Reames [Fri, 27 Apr 2018 17:41:37 +0000 (17:41 +0000)]
[GuardWidening] Add some clarifying comments about heuristics [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331061
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Philip Reames [Fri, 27 Apr 2018 17:29:10 +0000 (17:29 +0000)]
[LoopGuardWidening] Split out a loop pass version of GuardWidening
The idea is to have a pass which performs the same transformation as GuardWidening, but can be run within a loop pass manager without disrupting the pass manager structure. As demonstrated by the test case, this doesn't quite get there because of issues with post dom, but it gives a good step in the right direction. the motivation is purely to reduce compile time since we can now preserve locality during the loop walk.
This patch only includes a legacy pass. A follow up will add a new style pass as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331060
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Sanjay Patel [Fri, 27 Apr 2018 16:33:35 +0000 (16:33 +0000)]
[docs] add fp-cast-overflow-workaround options to release notes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331059
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Nirav Dave [Fri, 27 Apr 2018 16:16:06 +0000 (16:16 +0000)]
[MC] Undo spurious commit added into r331052.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331055
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Simon Pilgrim [Fri, 27 Apr 2018 16:11:57 +0000 (16:11 +0000)]
[X86] Split WriteFHadd into XMM and YMM/ZMM scheduler classes
This removes all the HADD/HSUB PS/PD InstRW overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331054
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Nirav Dave [Fri, 27 Apr 2018 16:11:24 +0000 (16:11 +0000)]
[MC] Provide default value for IsResolved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331052
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Simon Pilgrim [Fri, 27 Apr 2018 15:50:33 +0000 (15:50 +0000)]
[X86][AVX] Split WriteFLogic into XMM and YMM/ZMM scheduler classes
This removes all the AND/ANDN/OR/XOR PS/PD InstRW overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331051
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Simon Dardis [Fri, 27 Apr 2018 15:49:49 +0000 (15:49 +0000)]
[mips] Analyze and provide selection patterns microMIPSR6 branches
These branches were previously unanalyzable and unselectable. Add them and
recognize how to generate their inverses.
Reviewers: smaksimovic, atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D46113
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331050
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Nirav Dave [Fri, 27 Apr 2018 15:45:54 +0000 (15:45 +0000)]
[MC] Modify MCAsmStreamer to always build MCAssembler. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331048
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Nirav Dave [Fri, 27 Apr 2018 15:45:27 +0000 (15:45 +0000)]
[MC] Allow MCAssembler to be constructed without all subcomponents. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331047
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