OSDN Git Service
Lang Hames [Fri, 9 Jan 2015 18:55:42 +0000 (18:55 +0000)]
Recommit r224935 with a fix for the ObjC++/AArch64 bug that that revision
introduced.
A test case for the bug was already committed in r225385.
Patch by Rafael Espindola.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225534
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Duncan P. N. Exon Smith [Fri, 9 Jan 2015 17:53:27 +0000 (17:53 +0000)]
Revert "Bitcode: Move the DEBUG_LOC record to DEBUG_LOC_OLD"
This reverts commit r225498 (but leaves r225499, which was a worthy
cleanup).
My plan was to change `DEBUG_LOC` to store the `MDNode` directly rather
than its operands (patch was to go out this morning), but on reflection
it's not clear that it's strictly better. (I had missed that the
current code is unlikely to emit the `MDNode` at all.)
Conflicts:
lib/Bitcode/Reader/BitcodeReader.cpp (due to r225499)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225531
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Daniel Sanders [Fri, 9 Jan 2015 17:21:30 +0000 (17:21 +0000)]
[mips] Add support for accessing $gp as a named register.
Summary:
Mips Linux uses $gp to hold a pointer to thread info structure and accesses it
with a named register. This makes this work for LLVM.
The N32 ABI doesn't quite work yet since the frontend generates incorrect IR
for this case. It neglects to truncate the 64-bit GPR to a 32-bit value before
converting to a pointer. Given correct IR (as in the testcase in this patch),
it works correctly.
Reviewers: sstankovic, vmedic, atanasyan
Reviewed By: atanasyan
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D6893
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225529
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Sanjay Patel [Fri, 9 Jan 2015 17:11:51 +0000 (17:11 +0000)]
fix typos; remove names from comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225528
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Sanjay Patel [Fri, 9 Jan 2015 16:47:20 +0000 (16:47 +0000)]
remove names from comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225526
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Sanjay Patel [Fri, 9 Jan 2015 16:35:37 +0000 (16:35 +0000)]
fix typos; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225525
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Sanjay Patel [Fri, 9 Jan 2015 16:29:50 +0000 (16:29 +0000)]
fix typo; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225524
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Sanjay Patel [Fri, 9 Jan 2015 16:28:15 +0000 (16:28 +0000)]
more efficient use of a dyn_cast; no functional change intended
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225523
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Hal Finkel [Fri, 9 Jan 2015 15:51:16 +0000 (15:51 +0000)]
[PowerPC] Enable late partial unrolling on the POWER7
The P7 benefits from not have really-small loops so that we either have
multiple dispatch groups in the loop and/or the ability to form more-full
dispatch groups during scheduling. Setting the partial unrolling threshold to
44 seems good, empirically, for the P7. Compared to using no late partial
unrolling, this yields the following test-suite speedups:
SingleSource/Benchmarks/Adobe-C++/simple_types_constant_folding
-66.3253% +/- 24.1975%
SingleSource/Benchmarks/Misc-C++/oopack_v1p8
-44.0169% +/- 29.4881%
SingleSource/Benchmarks/Misc/pi
-27.8351% +/- 12.2712%
SingleSource/Benchmarks/Stanford/Bubblesort
-30.9898% +/- 22.4647%
I've speculatively added a similar setting for the P8. Also, I've noticed that
the unroller does not quite calculate the unrolling factor correctly for really
tiny loops because it neglects to account for the fact that not every loop body
replicant contains an ending branch and counter increment. I'll fix that later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225522
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Toma Tabacu [Fri, 9 Jan 2015 15:00:30 +0000 (15:00 +0000)]
[mips] Add comment which explains why we need to change the assembler options before and after inline asm blocks. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225521
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Suyog Sarda [Fri, 9 Jan 2015 10:23:48 +0000 (10:23 +0000)]
Assumption that "VectorizedValue" will always be an Instruction is not correct.
It can be a constant or a vector argument.
ex :
define i32 @hadd(<4 x i32> %a) #0 {
entry:
%vecext = extractelement <4 x i32> %a, i32 0
%vecext1 = extractelement <4 x i32> %a, i32 1
%add = add i32 %vecext, %vecext1
%vecext2 = extractelement <4 x i32> %a, i32 2
%add3 = add i32 %add, %vecext2
%vecext4 = extractelement <4 x i32> %a, i32 3
%add5 = add i32 %add3, %vecext4
ret i32 %add5
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225517
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Saleem Abdulrasool [Fri, 9 Jan 2015 06:57:24 +0000 (06:57 +0000)]
ARM: add support for R_ARM_ABS16
Add support for R_ARM_ABS16 relocation mapping. Addresses PR22156.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225510
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Saleem Abdulrasool [Fri, 9 Jan 2015 06:57:18 +0000 (06:57 +0000)]
test: add additional test for SVN r225507
Add an additional test case to ensure that we generate the relocation even if
the thumb target is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225509
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Saleem Abdulrasool [Fri, 9 Jan 2015 05:59:12 +0000 (05:59 +0000)]
ARM: add support for R_ARM_ABS8 relocations
Add support for R_ARM_ABS8 relocation. Addresses PR22126.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225507
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Matthias Braun [Fri, 9 Jan 2015 03:01:31 +0000 (03:01 +0000)]
RegisterCoalescer: Fix removeCopyByCommutingDef with subreg liveness
The code that eliminated additional coalescable copies in
removeCopyByCommutingDef() used MergeValueNumberInto() which internally
may merge A into B or B into A. In this case A and B had different Def
points, so we have to reset ValNo.Def to the intended one after merging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225503
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Matthias Braun [Fri, 9 Jan 2015 03:01:28 +0000 (03:01 +0000)]
RegisterCoalescer: Some cleanup in removeCopyByCommutingDef(), NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225502
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Matthias Braun [Fri, 9 Jan 2015 03:01:26 +0000 (03:01 +0000)]
RegisterCoalescer: No need to set kill flags, they are recompute later anyway
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225501
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Matthias Braun [Fri, 9 Jan 2015 03:01:23 +0000 (03:01 +0000)]
RegisterCoalescer: Turn some impossible conditions into asserts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225500
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Duncan P. N. Exon Smith [Fri, 9 Jan 2015 02:51:45 +0000 (02:51 +0000)]
Bitcode: Share logic for last instruction, NFC
Share logic for getting the last instruction emitted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225499
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Duncan P. N. Exon Smith [Fri, 9 Jan 2015 02:48:48 +0000 (02:48 +0000)]
Bitcode: Move the DEBUG_LOC record to DEBUG_LOC_OLD
Prepare to simplify the `DebugLoc` record.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225498
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Hal Finkel [Fri, 9 Jan 2015 02:03:11 +0000 (02:03 +0000)]
[PowerPC] Add a flag for experimenting with subreg liveness tracking
This cannot yet be enabled by default, it causes ~50 miscompiles in the test
suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225497
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Hal Finkel [Fri, 9 Jan 2015 01:34:30 +0000 (01:34 +0000)]
[PowerPC] Fold [sz]ext with fp_to_int lowering where possible
On modern cores with lfiw[az]x, we can fold a sign or zero extension from i32
to i64 into the load necessary for an i64 -> fp conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225493
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Hal Finkel [Fri, 9 Jan 2015 01:29:29 +0000 (01:29 +0000)]
[DAGCombine] Remainder of fix to r225380 (More FMA folding opportunities)
As pointed out by Aditya (and Owen), when we elide an FP extend to form an FMA,
we need to extend the incoming operands so that the resulting node will really
be legal. This is currently enabled only for PowerPC, and it happens to work
there regardless, but this should fix the functionality for everyone else
should anyone else wish to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225492
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Chandler Carruth [Fri, 9 Jan 2015 01:24:36 +0000 (01:24 +0000)]
[x86] Add a flag to control the vector shuffle legality predicates that
complements the new vector shuffle lowering code path. This flag,
naturally, is *off* because we've not tested or evaluated the results of
this at all. However, the flag will make it much easier to evaluate
whether we can be this aggressive and whether there are missing vector
shuffle lowering optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225491
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Chandler Carruth [Fri, 9 Jan 2015 00:48:47 +0000 (00:48 +0000)]
Cleaup ValueHandle to no longer keep a PointerIntPair for the Value*.
This was used previously for metadata but is no longer needed there. Not
doing this simplifies ValueHandle and will make it easier to fix things
like AssertingVH's DenseMapInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225487
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Hal Finkel [Fri, 9 Jan 2015 00:45:54 +0000 (00:45 +0000)]
Partial fix to r225380 (More FMA folding opportunities)
As pointed out by Aditya (and Owen), there are two things wrong with this code.
First, it adds patterns which elide FP extends when forming FMAs, and that might
not be profitable on all targets (it belongs behind the pre-existing
aggressive-FMA-formation flag). This is fixed by this change.
Second, the resulting nodes might have operands of different types (the
extensions need to be re-added). That will be fixed in the follow-up commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225485
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Philip Reames [Fri, 9 Jan 2015 00:26:45 +0000 (00:26 +0000)]
[REFACTOR] Push logic from MemDepPrinter into getNonLocalPointerDependency
Previously, MemDepPrinter handled volatile and unordered accesses without involving MemoryDependencyAnalysis. By making a slight tweak to the documented interface - which is respected by both callers - we can move this responsibility to MDA for the benefit of any future callers. This is basically just cleanup.
In the future, we may decide to extend MDA's non local dependency analysis to return useful results for ordered or volatile loads. I believe (but have not really checked in detail) that local dependency analyis does get useful results for ordered, but not volatile, loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225483
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Hans Wennborg [Fri, 9 Jan 2015 00:21:26 +0000 (00:21 +0000)]
ReleaseNotes.rst: these are for 3.6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225482
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Philip Reames [Fri, 9 Jan 2015 00:04:22 +0000 (00:04 +0000)]
[Refactor] Have getNonLocalPointerDependency take the query instruction
Previously, MemoryDependenceAnalysis::getNonLocalPointerDependency was taking a list of properties about the instruction being queried. Since I'm about to need one more property to be passed down through the infrastructure - I need to know a query instruction is non-volatile in an inner helper - fix the interface once and for all.
I also added some assertions and behaviour clarifications around volatile and ordered field accesses. At the moment, this is mostly to document expected behaviour. The only non-standard instructions which can currently reach this are atomic, but unordered, loads and stores. Neither ordered or volatile accesses can reach here.
The call in GVN is protected by an isSimple check when it first considers the load. The calls in MemDepPrinter are protected by isUnordered checks. Both utilities also check isVolatile for loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225481
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Duncan P. N. Exon Smith [Thu, 8 Jan 2015 23:50:26 +0000 (23:50 +0000)]
LangRef: Add usage points for distinct MDNodes
Omission pointed out by Sean Silva!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225479
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Duncan P. N. Exon Smith [Thu, 8 Jan 2015 22:43:19 +0000 (22:43 +0000)]
IR: Drop TODO now that PR22111 is finished
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225477
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Duncan P. N. Exon Smith [Thu, 8 Jan 2015 22:42:30 +0000 (22:42 +0000)]
Utils: Keep distinct MDNodes distinct in MapMetadata()
Create new copies of distinct `MDNode`s instead of following the
uniquing `MDNode` logic.
Just like self-references (or other cycles), `MapMetadata()` creates a
new node. In practice most calls use `RF_NoModuleLevelChanges`, in
which case nothing is duplicated anyway.
Part of PR22111.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225476
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Duncan P. N. Exon Smith [Thu, 8 Jan 2015 22:38:29 +0000 (22:38 +0000)]
IR: Add 'distinct' MDNodes to bitcode and assembly
Propagate whether `MDNode`s are 'distinct' through the other types of IR
(assembly and bitcode). This adds the `distinct` keyword to assembly.
Currently, no one actually calls `MDNode::getDistinct()`, so these nodes
only get created for:
- self-references, which are never uniqued, and
- nodes whose operands are replaced that hit a uniquing collision.
The concept of distinct nodes is still not quite first-class, since
distinct-ness doesn't yet survive across `MapMetadata()`.
Part of PR22111.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225474
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Sanjay Patel [Thu, 8 Jan 2015 22:36:56 +0000 (22:36 +0000)]
remove function names from comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225473
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Hal Finkel [Thu, 8 Jan 2015 22:11:49 +0000 (22:11 +0000)]
[PowerPC] Mark all instructions as non-cheap for MachineLICM
MachineLICM uses a callback named hasLowDefLatency to determine if an
instruction def operand has a 'low' latency. If all relevant operands have a
'low' latency, the instruction is considered too cheap to hoist out of loops
even in low-register-pressure situations. On PowerPC cores, both the embedded
cores and the others, there is no reason to believe that this is a good choice:
all instructions have a cost inside a loop, and hoisting them when not limited
by register pressure is a reasonable default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225471
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Hal Finkel [Thu, 8 Jan 2015 22:10:48 +0000 (22:10 +0000)]
[MachineLICM] A command-line option to hoist even cheap instructions
Add a command-line option to enable hoisting even cheap instructions (in
low-register-pressure situations). This is turned off by default, but has
proved useful for testing purposes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225470
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Duncan P. N. Exon Smith [Thu, 8 Jan 2015 21:07:55 +0000 (21:07 +0000)]
CodeGen: Use handy new-fangled post-increment, NFC
Drive-by cleanup; I noticed this when reviewing the patch that became
r225466.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225468
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Akira Hatanaka [Thu, 8 Jan 2015 20:44:50 +0000 (20:44 +0000)]
[ARM] Fix a bug in constant island pass that was triggering an assertion.
The assert was being triggered when the distance between a constant pool entry
and its user exceeded the maximally allowed distance after thumb2 branch
shortening. A padding was inserted after a thumb2 branch instruction was shrunk,
which caused the user to be out of range. This is wrong as the padding should
have been inserted by the layout algorithm so that the distance between two
instructions doesn't grow later during thumb2 instruction optimization.
This commit fixes the code in ARMConstantIslands::createNewWater to call
computeBlockSize and set BasicBlock::Unalign when a branch instruction is
inserted to create new water after a basic block. A non-zero Unalign causes
the worst-case padding to be inserted when adjustBBOffsetsAfter is called to
recompute the basic block offsets.
rdar://problem/
19130476
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225467
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Duncan P. N. Exon Smith [Thu, 8 Jan 2015 20:44:33 +0000 (20:44 +0000)]
CodeGen: Use range-based for loops, NFC
Patch by Ramkumar Ramachandra!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225466
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Matt Arsenault [Thu, 8 Jan 2015 20:09:34 +0000 (20:09 +0000)]
Fix fcmp + fabs instcombines when using the intrinsic
This was only handling the libcall. This is another example
of why only the intrinsic should ever be used when it exists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225465
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Eric Christopher [Thu, 8 Jan 2015 19:07:01 +0000 (19:07 +0000)]
The Kaleidoscope tutorial should be using "mcjit" for the library,
"jit" doesn't exist anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225462
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Lang Hames [Thu, 8 Jan 2015 18:52:15 +0000 (18:52 +0000)]
[MCJIT] Remove a few redundant MCJIT tests, and drop the extraneous datalayout
strings from the copies that remain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225460
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Eric Christopher [Thu, 8 Jan 2015 18:18:57 +0000 (18:18 +0000)]
Make the TargetMachine in MipsSubtarget a reference rather
than a pointer to make unifying code a bit easier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225459
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Eric Christopher [Thu, 8 Jan 2015 18:18:54 +0000 (18:18 +0000)]
Update include - this class doesn't use the target machine, but
only the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225458
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Eric Christopher [Thu, 8 Jan 2015 18:18:53 +0000 (18:18 +0000)]
Fix a couple of odd formatting issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225457
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Eric Christopher [Thu, 8 Jan 2015 18:18:50 +0000 (18:18 +0000)]
This routine is in InstrInfo, there's no need to access it again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225456
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Ahmed Bougacha [Thu, 8 Jan 2015 17:49:48 +0000 (17:49 +0000)]
[X86] Reflow comment. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225455
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Rafael Espindola [Thu, 8 Jan 2015 16:25:01 +0000 (16:25 +0000)]
clang-format. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225454
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Rafael Espindola [Thu, 8 Jan 2015 16:11:18 +0000 (16:11 +0000)]
Make this test a bit stricter.
It now checks for the end of the line or the opening '{'.
While at it, remove empty comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225451
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Justin Hibbits [Thu, 8 Jan 2015 15:47:19 +0000 (15:47 +0000)]
Add saving and restoring of r30 to the prologue and epilogue, respectively
Summary: The PIC additions didn't update the prologue and epilogue code to save and restore r30 (PIC base register). This does that.
Test Plan: Tests updated.
Reviewers: hfinkel
Reviewed By: hfinkel
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D6876
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225450
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Rafael Espindola [Thu, 8 Jan 2015 15:39:50 +0000 (15:39 +0000)]
Explicitly handle LinkOnceODRAutoHideLinkage. NFC. We already have a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225449
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Rafael Espindola [Thu, 8 Jan 2015 15:36:32 +0000 (15:36 +0000)]
Update naming style and clang-format. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225448
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Kristof Beyls [Thu, 8 Jan 2015 15:09:14 +0000 (15:09 +0000)]
Fix large stack alignment codegen for ARM and Thumb2 targets
This partially fixes PR13007 (ARM CodeGen fails with large stack
alignment): for ARM and Thumb2 targets, but not for Thumb1, as it
seems stack alignment for Thumb1 targets hasn't been supported at
all.
Producing an aligned stack pointer is done by zero-ing out the lower
bits of the stack pointer. The BIC instruction was used for this.
However, the immediate field of the BIC instruction only allows to
encode an immediate that can zero out up to a maximum of the 8 lower
bits. When a larger alignment is requested, a BIC instruction cannot
be used; llvm was silently producing incorrect code in this case.
This commit fixes code generation for large stack aligments by
using the BFC instruction instead, when the BFC instruction is
available. When not, it uses 2 instructions: a right shift,
followed by a left shift to zero out the lower bits.
The lowering of ARM::Int_eh_sjlj_dispatchsetup still has code
that unconditionally uses BIC to realign the stack pointer, so it
very likely has the same problem. However, I wasn't able to
produce a test case for that. This commit adds an assert so that
the compiler will fail the assert instead of silently generating
wrong code if this is ever reached.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225446
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Tom Stellard [Thu, 8 Jan 2015 15:08:17 +0000 (15:08 +0000)]
R600/SI: Remove SIISelLowering::legalizeOperands()
Its functionality has been replaced by calling
SIInstrInfo::legalizeOperands() from
SIISelLowering::AdjstInstrPostInstrSelection() and running the
SIFoldOperands and SIShrinkInstructions passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225445
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Elena Demikhovsky [Thu, 8 Jan 2015 12:29:19 +0000 (12:29 +0000)]
Masked Load/Store - fixed a bug in type legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225441
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Michael Kuperstein [Thu, 8 Jan 2015 12:05:02 +0000 (12:05 +0000)]
Fix a think-o in the test for r225438.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225440
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Michael Kuperstein [Thu, 8 Jan 2015 11:59:43 +0000 (11:59 +0000)]
Fix include ordering, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225439
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Michael Kuperstein [Thu, 8 Jan 2015 11:50:58 +0000 (11:50 +0000)]
[X86] Don't try to generate direct calls to TLS globals
The call lowering assumes that if the callee is a global, we want to emit a direct call.
This is correct for regular globals, but not for TLS ones.
Differential Revision: http://reviews.llvm.org/D6862
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225438
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Michael Kuperstein [Thu, 8 Jan 2015 11:04:38 +0000 (11:04 +0000)]
Move SPAdj logic from PEI into the targets (NFC)
PEI tries to keep track of how much starting or ending a call sequence adjusts the stack pointer by, so that it can resolve frame-index references. Currently, it takes a very simplistic view of how SP adjustments are done - both FrameStartOpcode and FrameDestroyOpcode adjust it exactly by the amount written in its first argument.
This view is in fact incorrect for some targets (e.g. due to stack re-alignment, or because it may want to adjust the stack pointer in multiple steps). However, that doesn't cause breakage, because most targets (the only in-tree exception appears to be 32-bit ARM) rely on being able to simplify the call frame pseudo-instructions earlier, so this code is never hit.
Moving the computation into TargetInstrInfo allows targets to override the way the adjustment is computed if they need to have a non-zero SPAdj.
Differential Revision: http://reviews.llvm.org/D6863
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225437
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Craig Topper [Thu, 8 Jan 2015 07:57:27 +0000 (07:57 +0000)]
Fix test case I missed in r225432.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225434
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Craig Topper [Thu, 8 Jan 2015 07:41:30 +0000 (07:41 +0000)]
[X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the LEA variants in Intel syntax. The memory operand is inherently unsized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225432
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Adrian Prantl [Thu, 8 Jan 2015 02:02:00 +0000 (02:02 +0000)]
Revert "Reapply: Teach SROA how to update debug info for fragmented variables."
This reverts commit r225379 while investigating an assertion failure reported
by Alexey.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225424
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Quentin Colombet [Thu, 8 Jan 2015 01:16:39 +0000 (01:16 +0000)]
[RegAllocGreedy] Introduce a late pass to repair broken hints.
A broken hint is a copy where both ends are assigned different colors. When a
variable gets evicted in the neighborhood of such copies, it is likely we can
reconcile some of them.
** Context **
Copies are inserted during the register allocation via splitting. These split
points are required to relax the constraints on the allocation problem. When
such a point is inserted, both ends of the copy would not share the same color
with respect to the current allocation problem. When variables get evicted,
the allocation problem becomes different and some split point may not be
required anymore. However, the related variables may already have been colored.
This usually shows up in the assembly with pattern like this:
def A
...
save A to B
def A
use A
restore A from B
...
use B
Whereas we could simply have done:
def B
...
def A
use A
...
use B
** Proposed Solution **
A variable having a broken hint is marked for late recoloring if and only if
selecting a register for it evict another variable. Indeed, if no eviction
happens this is pointless to look for recoloring opportunities as it means the
situation was the same as the initial allocation problem where we had to break
the hint.
Finally, when everything has been allocated, we look for recoloring
opportunities for all the identified candidates.
The recoloring is performed very late to rely on accurate copy cost (all
involved variables are allocated).
The recoloring is simple unlike the last change recoloring. It propagates the
color of the broken hint to all its copy-related variables. If the color is
available for them, the recoloring uses it, otherwise it gives up on that hint
even if a more complex coloring would have worked.
The recoloring happens only if it is profitable. The profitability is evaluated
using the expected frequency of the copies of the currently recolored variable
with a) its current color and b) with the target color. If a) is greater or
equal than b), then it is profitable and the recoloring happen.
** Example **
Consider the following example:
BB1:
a =
b =
BB2:
...
= b
= a
Let us assume b gets split:
BB1:
a =
b =
BB2:
c = b
...
d = c
= d
= a
Because of how the allocation work, b, c, and d may be assigned different
colors. Now, if a gets evicted to make room for c, assuming b and d were
assigned to something different than a.
We end up with:
BB1:
a =
st a, SpillSlot
b =
BB2:
c = b
...
d = c
= d
e = ld SpillSlot
= e
This is likely that we can assign the same register for b, c, and d,
getting rid of 2 copies.
** Performances **
Both ARM64 and x86_64 show performance improvements of up to 3% for the
llvm-testsuite + externals with Os and O3. There are a few regressions too that
comes from the (in)accuracy of the block frequency estimate.
<rdar://problem/
18312047>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225422
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Ahmed Bougacha [Thu, 8 Jan 2015 00:51:32 +0000 (00:51 +0000)]
[SelectionDAG] Allow targets to specify legality of extloads' result
type (in addition to the memory type).
The *LoadExt* legalization handling used to only have one type, the
memory type. This forced users to assume that as long as the extload
for the memory type was declared legal, and the result type was legal,
the whole extload was legal.
However, this isn't always the case. For instance, on X86, with AVX,
this is legal:
v4i32 load, zext from v4i8
but this isn't:
v4i64 load, zext from v4i8
Whereas v4i64 is (arguably) legal, even without AVX2.
Note that the same thing was done a while ago for truncstores (r46140),
but I assume no one needed it yet for extloads, so here we go.
Calls to getLoadExtAction were changed to add the value type, found
manually in the surrounding code.
Calls to setLoadExtAction were mechanically changed, by wrapping the
call in a loop, to match previous behavior. The loop iterates over
the MVT subrange corresponding to the memory type (FP vectors, etc...).
I also pulled neighboring setTruncStoreActions into some of the loops;
those shouldn't make a difference, as the additional types are illegal.
(e.g., i128->i1 truncstores on PPC.)
No functional change intended.
Differential Revision: http://reviews.llvm.org/D6532
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225421
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Nick Lewycky [Thu, 8 Jan 2015 00:47:03 +0000 (00:47 +0000)]
Remove empty statement. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225420
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Matthias Braun [Thu, 8 Jan 2015 00:33:48 +0000 (00:33 +0000)]
X86: VZeroUpperInserter: shortcut should not trigger if we have any function live-ins.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225419
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Kevin Enderby [Thu, 8 Jan 2015 00:25:24 +0000 (00:25 +0000)]
Run clang-format on tools/llvm-objdump/MachODump.cpp again as some of my
previous changes got in with incorrect formatting. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225417
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Matthias Braun [Thu, 8 Jan 2015 00:21:23 +0000 (00:21 +0000)]
RegisterCoalescer: Do not remove IMPLICIT_DEFS if they are required for subranges.
The register coalescer used to remove implicit_defs when they are
covered by the main range anyway. With subreg liveness tracking we can't
do that anymore in places where the IMPLICIT_DEF is required as begin of
a subregister liverange.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225416
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Matthias Braun [Wed, 7 Jan 2015 23:58:38 +0000 (23:58 +0000)]
RegisterCoalescer: Fix valuesIdentical() in some subrange merge cases.
I got confused and assumed SrcIdx/DstIdx of the CoalescerPair is a
subregister index in SrcReg/DstReg, but they are actually subregister
indices of the coalesced register that get you back to SrcReg/DstReg
when applied.
Fixed the bug, improved comments and simplified code accordingly.
Testcase by Tom Stellard!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225415
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Matthias Braun [Wed, 7 Jan 2015 23:35:11 +0000 (23:35 +0000)]
LiveInterval: Implement feedback by Quentin Colombet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225413
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Philip Reames [Wed, 7 Jan 2015 22:48:01 +0000 (22:48 +0000)]
[GC] improve testing around gc.relocate and fix a test
Patch by: Ramkumar Ramachandra <artagnon@gmail.com>
"This patch started out as an exploration of gc.relocate, and an attempt
to write a simple test in call-lowering. I then noticed that the
arguments of gc.relocate were not checked fully, so I went in and fixed
a few things. Finally, the most important outcome of this patch is that
my new error handling code caught a bug in a callsite in
stackmap-format."
Differential Revision: http://reviews.llvm.org/D6824
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225412
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Ahmed Bougacha [Wed, 7 Jan 2015 22:47:46 +0000 (22:47 +0000)]
[CodeGen] Add MVT::isValid to replace manual validity checks. NFC.
Now that we have MVT::FIRST_VALUETYPE (r225362), we can provide a method
checking that the MVT is valid, that is, it's in
[FIRST_VALUETYPE, LAST_VALUETYPE[.
This commit also uses it in a few asserts, that would previously accept
invalid MVTs, such as the default constructed -1. In that case,
the code following those asserts would do an out-of-bounds array access.
Using MVT::isValid, those assertions fail as expected when passed
invalid MVTs.
It feels clunky to have such a validity checking function, but it's
at least better than the alternative of broken manual checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225411
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Tom Stellard [Wed, 7 Jan 2015 22:44:19 +0000 (22:44 +0000)]
R600/SI: Commute instructions to enable more folding opportunities
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225410
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Duncan P. N. Exon Smith [Wed, 7 Jan 2015 22:24:46 +0000 (22:24 +0000)]
IR: Add MDNode::getDistinct()
Allow distinct `MDNode`s to be explicitly created. There's no way (yet)
of representing their distinctness in assembly/bitcode, however, so this
still isn't first-class.
Part of PR22111.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225406
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Tom Stellard [Wed, 7 Jan 2015 22:18:27 +0000 (22:18 +0000)]
R600/SI: Only fold immediates that have one use
Folding the same immediate into multiple instruction will increase
program size, which can hurt performance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225405
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Sean Silva [Wed, 7 Jan 2015 22:07:33 +0000 (22:07 +0000)]
Test commit.
Hopefully this one won't kill the git mirror...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225404
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Duncan P. N. Exon Smith [Wed, 7 Jan 2015 21:35:38 +0000 (21:35 +0000)]
IR: Add MDNode::isDistinct()
Add API to indicate whether an `MDNode` is distinct. A distinct node is
not stored in the MDNode uniquing tables, and will never be returned by
`MDNode::get()`.
Although distinct nodes are only currently created by uniquing
collisions (when operands change), PR22111 will allow these nodes to be
explicitly created.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225401
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Sean Silva [Wed, 7 Jan 2015 21:35:14 +0000 (21:35 +0000)]
[LangRef] PR22118: Hyphen is allowed in IR identifiers.
E.g. %-foo and %fo-o.
Thanks to eagle-eyed reporter Tomas Brukner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225400
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Adrian Prantl [Wed, 7 Jan 2015 21:35:13 +0000 (21:35 +0000)]
Update a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225399
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Duncan P. N. Exon Smith [Wed, 7 Jan 2015 21:32:27 +0000 (21:32 +0000)]
Linker: Don't use MDNode::replaceOperandWith()
`MDNode::replaceOperandWith()` changes all instances of metadata. Stop
using it when linking module flags, since (due to uniquing) the flag
values could be used by other metadata.
Instead, use new API `NamedMDNode::setOperand()` to update the reference
directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225397
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Alexey Samsonov [Wed, 7 Jan 2015 21:27:26 +0000 (21:27 +0000)]
XFAIL several MCJIT EH tests under ASan and MSan bootstrap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225393
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Ahmed Bougacha [Wed, 7 Jan 2015 21:27:10 +0000 (21:27 +0000)]
[CodeGen] Use MVT iterator_ranges in legality loops. NFC intended.
A few loops do trickier things than just iterating on an MVT subset,
so I'll leave them be for now.
Follow-up of r225387.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225392
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Ahmed Bougacha [Wed, 7 Jan 2015 21:15:38 +0000 (21:15 +0000)]
[CodeGen] Add iterator_range for the MVT::SimpleValueType enum.
This commit adds a simple iterator over that enum, and a few
functions to create iterator ranges over the most common types.
Differential Revision: http://reviews.llvm.org/D6537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225387
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Alexey Samsonov [Wed, 7 Jan 2015 21:13:30 +0000 (21:13 +0000)]
Fix uninitialized memory read in llvm-dsymutil for the second time.
This was already fixed by r224481, but apparently was accidentally
reverted in r225207.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225386
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Rafael Espindola [Wed, 7 Jan 2015 21:10:25 +0000 (21:10 +0000)]
Add a test that would have found the issue in r224935.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225385
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Chandler Carruth [Wed, 7 Jan 2015 21:08:54 +0000 (21:08 +0000)]
[git] Mark the llgo directory in the LLVM gitignore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225384
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Kevin Enderby [Wed, 7 Jan 2015 21:02:18 +0000 (21:02 +0000)]
Slightly refactor things for llvm-objdump and the -macho option so it can be used with
options other than just -disassemble so that universal files can be used with other
options combined with -arch options.
No functional change to existing options and use. One test case added for the
additional functionality with a universal file an a -arch option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225383
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Tom Stellard [Wed, 7 Jan 2015 20:59:25 +0000 (20:59 +0000)]
R600/SI: Remove VReg_32 register class
Use VGPR_32 register class instead. These two register classes were
identical and having separate classes was causing
SIInstrInfo::isLegalOperands() to be overly conservative in some cases.
This change is necessary to prevent future paches from missing a folding
opportunity in fneg-fabs.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225382
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Olivier Sallenave [Wed, 7 Jan 2015 20:54:17 +0000 (20:54 +0000)]
More FMA folding opportunities.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225380
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Adrian Prantl [Wed, 7 Jan 2015 20:52:22 +0000 (20:52 +0000)]
Reapply: Teach SROA how to update debug info for fragmented variables.
The two buildbot failures were addressed in LLVM r225378 and CFE r225359.
This rapplies commit 225272 without modifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225379
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Adrian Prantl [Wed, 7 Jan 2015 20:48:58 +0000 (20:48 +0000)]
Debug info: Allow aggregate types to be described by constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225378
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Colin LeMahieu [Wed, 7 Jan 2015 20:43:38 +0000 (20:43 +0000)]
[Hexagon] Fix 225372 USR register is not fully complete. Removing Uses = [USR] maintains existing functionality to old instructions without encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225377
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Colin LeMahieu [Wed, 7 Jan 2015 20:28:57 +0000 (20:28 +0000)]
[Hexagon] Adding floating point classification and creation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225374
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Tom Stellard [Wed, 7 Jan 2015 20:27:25 +0000 (20:27 +0000)]
R600/SI: Add a V_MOV_B64 pseudo instruction
This is used to simplify the SIFoldOperands pass and make it easier to
fold immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225373
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Colin LeMahieu [Wed, 7 Jan 2015 20:24:09 +0000 (20:24 +0000)]
[Hexagon] Adding encodings for v5 floating point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225372
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Colin LeMahieu [Wed, 7 Jan 2015 20:07:28 +0000 (20:07 +0000)]
[Hexagon] Adding encoding for popcount, fastcorner, dword asr with rounding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225371
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Tom Stellard [Wed, 7 Jan 2015 19:56:17 +0000 (19:56 +0000)]
R600/SI: Teach SIFoldOperands to split 64-bit constants when folding
This allows folding of sequences like:
s[0:1] = s_mov_b64 4
v_add_i32 v0, s0, v0
v_addc_u32 v1, s1, v1
into
v_add_i32 v0, 4, v0
v_add_i32 v1, 0, v1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225369
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Olivier Sallenave [Wed, 7 Jan 2015 19:45:17 +0000 (19:45 +0000)]
Test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225368
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Ahmed Bougacha [Wed, 7 Jan 2015 19:38:50 +0000 (19:38 +0000)]
[X86] Fix 512->256 typo in comments. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225367
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Philip Reames [Wed, 7 Jan 2015 19:13:28 +0000 (19:13 +0000)]
Add a missing file from 225365
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225366
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